1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2009 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2009 Red Hat Inc. 4254885Sdumbbell * 5254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 6254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 7254885Sdumbbell * to deal in the Software without restriction, including without limitation 8254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 10254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 11254885Sdumbbell * 12254885Sdumbbell * The above copyright notice and this permission notice shall be included in 13254885Sdumbbell * all copies or substantial portions of the Software. 14254885Sdumbbell * 15254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 22254885Sdumbbell * 23254885Sdumbbell * Authors: Dave Airlie 24254885Sdumbbell * Alex Deucher 25254885Sdumbbell * Jerome Glisse 26254885Sdumbbell */ 27254885Sdumbbell#ifndef R600D_H 28254885Sdumbbell#define R600D_H 29254885Sdumbbell 30254885Sdumbbell#include <sys/cdefs.h> 31254885Sdumbbell__FBSDID("$FreeBSD: releng/10.3/sys/dev/drm2/radeon/r600d.h 282199 2015-04-28 19:35:05Z dumbbell $"); 32254885Sdumbbell 33254885Sdumbbell#define CP_PACKET2 0x80000000 34254885Sdumbbell#define PACKET2_PAD_SHIFT 0 35254885Sdumbbell#define PACKET2_PAD_MASK (0x3fffffff << 0) 36254885Sdumbbell 37254885Sdumbbell#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 38254885Sdumbbell 39254885Sdumbbell#define R6XX_MAX_SH_GPRS 256 40254885Sdumbbell#define R6XX_MAX_TEMP_GPRS 16 41254885Sdumbbell#define R6XX_MAX_SH_THREADS 256 42254885Sdumbbell#define R6XX_MAX_SH_STACK_ENTRIES 4096 43254885Sdumbbell#define R6XX_MAX_BACKENDS 8 44254885Sdumbbell#define R6XX_MAX_BACKENDS_MASK 0xff 45254885Sdumbbell#define R6XX_MAX_SIMDS 8 46254885Sdumbbell#define R6XX_MAX_SIMDS_MASK 0xff 47254885Sdumbbell#define R6XX_MAX_PIPES 8 48254885Sdumbbell#define R6XX_MAX_PIPES_MASK 0xff 49254885Sdumbbell 50254885Sdumbbell/* PTE flags */ 51282199Sdumbbell/* 52282199Sdumbbell * FIXME Linux<->FreeBSD: PTE_VALID is already defined on PowerPC on FreeBSD. 53282199Sdumbbell * Fortunately, it's never used in the Radeon driver. 54282199Sdumbbell */ 55282199Sdumbbell/* 56254885Sdumbbell#define PTE_VALID (1 << 0) 57254885Sdumbbell#define PTE_SYSTEM (1 << 1) 58254885Sdumbbell#define PTE_SNOOPED (1 << 2) 59254885Sdumbbell#define PTE_READABLE (1 << 5) 60254885Sdumbbell#define PTE_WRITEABLE (1 << 6) 61282199Sdumbbell*/ 62254885Sdumbbell 63254885Sdumbbell/* tiling bits */ 64254885Sdumbbell#define ARRAY_LINEAR_GENERAL 0x00000000 65254885Sdumbbell#define ARRAY_LINEAR_ALIGNED 0x00000001 66254885Sdumbbell#define ARRAY_1D_TILED_THIN1 0x00000002 67254885Sdumbbell#define ARRAY_2D_TILED_THIN1 0x00000004 68254885Sdumbbell 69254885Sdumbbell/* Registers */ 70254885Sdumbbell#define ARB_POP 0x2418 71254885Sdumbbell#define ENABLE_TC128 (1 << 30) 72254885Sdumbbell#define ARB_GDEC_RD_CNTL 0x246C 73254885Sdumbbell 74254885Sdumbbell#define CC_GC_SHADER_PIPE_CONFIG 0x8950 75254885Sdumbbell#define CC_RB_BACKEND_DISABLE 0x98F4 76254885Sdumbbell#define BACKEND_DISABLE(x) ((x) << 16) 77254885Sdumbbell 78254885Sdumbbell#define R_028808_CB_COLOR_CONTROL 0x28808 79254885Sdumbbell#define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) 80254885Sdumbbell#define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) 81254885Sdumbbell#define C_028808_SPECIAL_OP 0xFFFFFF8F 82254885Sdumbbell#define V_028808_SPECIAL_NORMAL 0x00 83254885Sdumbbell#define V_028808_SPECIAL_DISABLE 0x01 84254885Sdumbbell#define V_028808_SPECIAL_RESOLVE_BOX 0x07 85254885Sdumbbell 86254885Sdumbbell#define CB_COLOR0_BASE 0x28040 87254885Sdumbbell#define CB_COLOR1_BASE 0x28044 88254885Sdumbbell#define CB_COLOR2_BASE 0x28048 89254885Sdumbbell#define CB_COLOR3_BASE 0x2804C 90254885Sdumbbell#define CB_COLOR4_BASE 0x28050 91254885Sdumbbell#define CB_COLOR5_BASE 0x28054 92254885Sdumbbell#define CB_COLOR6_BASE 0x28058 93254885Sdumbbell#define CB_COLOR7_BASE 0x2805C 94254885Sdumbbell#define CB_COLOR7_FRAG 0x280FC 95254885Sdumbbell 96254885Sdumbbell#define CB_COLOR0_SIZE 0x28060 97254885Sdumbbell#define CB_COLOR0_VIEW 0x28080 98254885Sdumbbell#define R_028080_CB_COLOR0_VIEW 0x028080 99254885Sdumbbell#define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) 100254885Sdumbbell#define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) 101254885Sdumbbell#define C_028080_SLICE_START 0xFFFFF800 102254885Sdumbbell#define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) 103254885Sdumbbell#define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 104254885Sdumbbell#define C_028080_SLICE_MAX 0xFF001FFF 105254885Sdumbbell#define R_028084_CB_COLOR1_VIEW 0x028084 106254885Sdumbbell#define R_028088_CB_COLOR2_VIEW 0x028088 107254885Sdumbbell#define R_02808C_CB_COLOR3_VIEW 0x02808C 108254885Sdumbbell#define R_028090_CB_COLOR4_VIEW 0x028090 109254885Sdumbbell#define R_028094_CB_COLOR5_VIEW 0x028094 110254885Sdumbbell#define R_028098_CB_COLOR6_VIEW 0x028098 111254885Sdumbbell#define R_02809C_CB_COLOR7_VIEW 0x02809C 112254885Sdumbbell#define R_028100_CB_COLOR0_MASK 0x028100 113254885Sdumbbell#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) 114254885Sdumbbell#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) 115254885Sdumbbell#define C_028100_CMASK_BLOCK_MAX 0xFFFFF000 116254885Sdumbbell#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) 117254885Sdumbbell#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF) 118254885Sdumbbell#define C_028100_FMASK_TILE_MAX 0x00000FFF 119254885Sdumbbell#define R_028104_CB_COLOR1_MASK 0x028104 120254885Sdumbbell#define R_028108_CB_COLOR2_MASK 0x028108 121254885Sdumbbell#define R_02810C_CB_COLOR3_MASK 0x02810C 122254885Sdumbbell#define R_028110_CB_COLOR4_MASK 0x028110 123254885Sdumbbell#define R_028114_CB_COLOR5_MASK 0x028114 124254885Sdumbbell#define R_028118_CB_COLOR6_MASK 0x028118 125254885Sdumbbell#define R_02811C_CB_COLOR7_MASK 0x02811C 126254885Sdumbbell#define CB_COLOR0_INFO 0x280a0 127254885Sdumbbell# define CB_FORMAT(x) ((x) << 2) 128254885Sdumbbell# define CB_ARRAY_MODE(x) ((x) << 8) 129254885Sdumbbell# define CB_SOURCE_FORMAT(x) ((x) << 27) 130254885Sdumbbell# define CB_SF_EXPORT_FULL 0 131254885Sdumbbell# define CB_SF_EXPORT_NORM 1 132254885Sdumbbell#define CB_COLOR0_TILE 0x280c0 133254885Sdumbbell#define CB_COLOR0_FRAG 0x280e0 134254885Sdumbbell#define CB_COLOR0_MASK 0x28100 135254885Sdumbbell 136254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_0 0x28940 137254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_1 0x28944 138254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_2 0x28948 139254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_3 0x2894c 140254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_4 0x28950 141254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_5 0x28954 142254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_6 0x28958 143254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_7 0x2895c 144254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_8 0x28960 145254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_9 0x28964 146254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_10 0x28968 147254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_11 0x2896c 148254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_12 0x28970 149254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_13 0x28974 150254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_14 0x28978 151254885Sdumbbell#define SQ_ALU_CONST_CACHE_PS_15 0x2897c 152254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_0 0x28980 153254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_1 0x28984 154254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_2 0x28988 155254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_3 0x2898c 156254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_4 0x28990 157254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_5 0x28994 158254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_6 0x28998 159254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_7 0x2899c 160254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_8 0x289a0 161254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_9 0x289a4 162254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_10 0x289a8 163254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_11 0x289ac 164254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_12 0x289b0 165254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_13 0x289b4 166254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_14 0x289b8 167254885Sdumbbell#define SQ_ALU_CONST_CACHE_VS_15 0x289bc 168254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_0 0x289c0 169254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_1 0x289c4 170254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_2 0x289c8 171254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_3 0x289cc 172254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_4 0x289d0 173254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_5 0x289d4 174254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_6 0x289d8 175254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_7 0x289dc 176254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_8 0x289e0 177254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_9 0x289e4 178254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_10 0x289e8 179254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_11 0x289ec 180254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_12 0x289f0 181254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_13 0x289f4 182254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_14 0x289f8 183254885Sdumbbell#define SQ_ALU_CONST_CACHE_GS_15 0x289fc 184254885Sdumbbell 185254885Sdumbbell#define CONFIG_MEMSIZE 0x5428 186254885Sdumbbell#define CONFIG_CNTL 0x5424 187254885Sdumbbell#define CP_STALLED_STAT1 0x8674 188254885Sdumbbell#define CP_STALLED_STAT2 0x8678 189254885Sdumbbell#define CP_BUSY_STAT 0x867C 190254885Sdumbbell#define CP_STAT 0x8680 191254885Sdumbbell#define CP_COHER_BASE 0x85F8 192254885Sdumbbell#define CP_DEBUG 0xC1FC 193254885Sdumbbell#define R_0086D8_CP_ME_CNTL 0x86D8 194254885Sdumbbell#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) 195254885Sdumbbell#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) 196254885Sdumbbell#define CP_ME_RAM_DATA 0xC160 197254885Sdumbbell#define CP_ME_RAM_RADDR 0xC158 198254885Sdumbbell#define CP_ME_RAM_WADDR 0xC15C 199254885Sdumbbell#define CP_MEQ_THRESHOLDS 0x8764 200254885Sdumbbell#define MEQ_END(x) ((x) << 16) 201254885Sdumbbell#define ROQ_END(x) ((x) << 24) 202254885Sdumbbell#define CP_PERFMON_CNTL 0x87FC 203254885Sdumbbell#define CP_PFP_UCODE_ADDR 0xC150 204254885Sdumbbell#define CP_PFP_UCODE_DATA 0xC154 205254885Sdumbbell#define CP_QUEUE_THRESHOLDS 0x8760 206254885Sdumbbell#define ROQ_IB1_START(x) ((x) << 0) 207254885Sdumbbell#define ROQ_IB2_START(x) ((x) << 8) 208254885Sdumbbell#define CP_RB_BASE 0xC100 209254885Sdumbbell#define CP_RB_CNTL 0xC104 210254885Sdumbbell#define RB_BUFSZ(x) ((x) << 0) 211254885Sdumbbell#define RB_BLKSZ(x) ((x) << 8) 212254885Sdumbbell#define RB_NO_UPDATE (1 << 27) 213261455Seadler#define RB_RPTR_WR_ENA (1U << 31) 214254885Sdumbbell#define BUF_SWAP_32BIT (2 << 16) 215254885Sdumbbell#define CP_RB_RPTR 0x8700 216254885Sdumbbell#define CP_RB_RPTR_ADDR 0xC10C 217254885Sdumbbell#define RB_RPTR_SWAP(x) ((x) << 0) 218254885Sdumbbell#define CP_RB_RPTR_ADDR_HI 0xC110 219254885Sdumbbell#define CP_RB_RPTR_WR 0xC108 220254885Sdumbbell#define CP_RB_WPTR 0xC114 221254885Sdumbbell#define CP_RB_WPTR_ADDR 0xC118 222254885Sdumbbell#define CP_RB_WPTR_ADDR_HI 0xC11C 223254885Sdumbbell#define CP_RB_WPTR_DELAY 0x8704 224254885Sdumbbell#define CP_ROQ_IB1_STAT 0x8784 225254885Sdumbbell#define CP_ROQ_IB2_STAT 0x8788 226254885Sdumbbell#define CP_SEM_WAIT_TIMER 0x85BC 227254885Sdumbbell 228254885Sdumbbell#define DB_DEBUG 0x9830 229261455Seadler#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31) 230254885Sdumbbell#define DB_DEPTH_BASE 0x2800C 231254885Sdumbbell#define DB_HTILE_DATA_BASE 0x28014 232254885Sdumbbell#define DB_HTILE_SURFACE 0x28D24 233254885Sdumbbell#define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) 234254885Sdumbbell#define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 235254885Sdumbbell#define C_028D24_HTILE_WIDTH 0xFFFFFFFE 236254885Sdumbbell#define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 237254885Sdumbbell#define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 238254885Sdumbbell#define C_028D24_HTILE_HEIGHT 0xFFFFFFFD 239254885Sdumbbell#define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) 240254885Sdumbbell#define DB_WATERMARKS 0x9838 241254885Sdumbbell#define DEPTH_FREE(x) ((x) << 0) 242254885Sdumbbell#define DEPTH_FLUSH(x) ((x) << 5) 243254885Sdumbbell#define DEPTH_PENDING_FREE(x) ((x) << 15) 244254885Sdumbbell#define DEPTH_CACHELINE_FREE(x) ((x) << 20) 245254885Sdumbbell 246254885Sdumbbell#define DCP_TILING_CONFIG 0x6CA0 247254885Sdumbbell#define PIPE_TILING(x) ((x) << 1) 248254885Sdumbbell#define BANK_TILING(x) ((x) << 4) 249254885Sdumbbell#define GROUP_SIZE(x) ((x) << 6) 250254885Sdumbbell#define ROW_TILING(x) ((x) << 8) 251254885Sdumbbell#define BANK_SWAPS(x) ((x) << 11) 252254885Sdumbbell#define SAMPLE_SPLIT(x) ((x) << 14) 253254885Sdumbbell#define BACKEND_MAP(x) ((x) << 16) 254254885Sdumbbell 255254885Sdumbbell#define GB_TILING_CONFIG 0x98F0 256254885Sdumbbell#define PIPE_TILING__SHIFT 1 257254885Sdumbbell#define PIPE_TILING__MASK 0x0000000e 258254885Sdumbbell 259254885Sdumbbell#define GC_USER_SHADER_PIPE_CONFIG 0x8954 260254885Sdumbbell#define INACTIVE_QD_PIPES(x) ((x) << 8) 261254885Sdumbbell#define INACTIVE_QD_PIPES_MASK 0x0000FF00 262254885Sdumbbell#define INACTIVE_SIMDS(x) ((x) << 16) 263254885Sdumbbell#define INACTIVE_SIMDS_MASK 0x00FF0000 264254885Sdumbbell 265254885Sdumbbell#define SQ_CONFIG 0x8c00 266254885Sdumbbell# define VC_ENABLE (1 << 0) 267254885Sdumbbell# define EXPORT_SRC_C (1 << 1) 268254885Sdumbbell# define DX9_CONSTS (1 << 2) 269254885Sdumbbell# define ALU_INST_PREFER_VECTOR (1 << 3) 270254885Sdumbbell# define DX10_CLAMP (1 << 4) 271254885Sdumbbell# define CLAUSE_SEQ_PRIO(x) ((x) << 8) 272254885Sdumbbell# define PS_PRIO(x) ((x) << 24) 273254885Sdumbbell# define VS_PRIO(x) ((x) << 26) 274254885Sdumbbell# define GS_PRIO(x) ((x) << 28) 275254885Sdumbbell# define ES_PRIO(x) ((x) << 30) 276254885Sdumbbell#define SQ_GPR_RESOURCE_MGMT_1 0x8c04 277254885Sdumbbell# define NUM_PS_GPRS(x) ((x) << 0) 278254885Sdumbbell# define NUM_VS_GPRS(x) ((x) << 16) 279254885Sdumbbell# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 280254885Sdumbbell#define SQ_GPR_RESOURCE_MGMT_2 0x8c08 281254885Sdumbbell# define NUM_GS_GPRS(x) ((x) << 0) 282254885Sdumbbell# define NUM_ES_GPRS(x) ((x) << 16) 283254885Sdumbbell#define SQ_THREAD_RESOURCE_MGMT 0x8c0c 284254885Sdumbbell# define NUM_PS_THREADS(x) ((x) << 0) 285254885Sdumbbell# define NUM_VS_THREADS(x) ((x) << 8) 286254885Sdumbbell# define NUM_GS_THREADS(x) ((x) << 16) 287254885Sdumbbell# define NUM_ES_THREADS(x) ((x) << 24) 288254885Sdumbbell#define SQ_STACK_RESOURCE_MGMT_1 0x8c10 289254885Sdumbbell# define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 290254885Sdumbbell# define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 291254885Sdumbbell#define SQ_STACK_RESOURCE_MGMT_2 0x8c14 292254885Sdumbbell# define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 293254885Sdumbbell# define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 294254885Sdumbbell#define SQ_ESGS_RING_BASE 0x8c40 295254885Sdumbbell#define SQ_GSVS_RING_BASE 0x8c48 296254885Sdumbbell#define SQ_ESTMP_RING_BASE 0x8c50 297254885Sdumbbell#define SQ_GSTMP_RING_BASE 0x8c58 298254885Sdumbbell#define SQ_VSTMP_RING_BASE 0x8c60 299254885Sdumbbell#define SQ_PSTMP_RING_BASE 0x8c68 300254885Sdumbbell#define SQ_FBUF_RING_BASE 0x8c70 301254885Sdumbbell#define SQ_REDUC_RING_BASE 0x8c78 302254885Sdumbbell 303254885Sdumbbell#define GRBM_CNTL 0x8000 304254885Sdumbbell# define GRBM_READ_TIMEOUT(x) ((x) << 0) 305254885Sdumbbell#define GRBM_STATUS 0x8010 306254885Sdumbbell#define CMDFIFO_AVAIL_MASK 0x0000001F 307254885Sdumbbell#define GUI_ACTIVE (1<<31) 308254885Sdumbbell#define GRBM_STATUS2 0x8014 309254885Sdumbbell#define GRBM_SOFT_RESET 0x8020 310254885Sdumbbell#define SOFT_RESET_CP (1<<0) 311254885Sdumbbell 312254885Sdumbbell#define CG_THERMAL_STATUS 0x7F4 313254885Sdumbbell#define ASIC_T(x) ((x) << 0) 314254885Sdumbbell#define ASIC_T_MASK 0x1FF 315254885Sdumbbell#define ASIC_T_SHIFT 0 316254885Sdumbbell 317254885Sdumbbell#define HDP_HOST_PATH_CNTL 0x2C00 318254885Sdumbbell#define HDP_NONSURFACE_BASE 0x2C04 319254885Sdumbbell#define HDP_NONSURFACE_INFO 0x2C08 320254885Sdumbbell#define HDP_NONSURFACE_SIZE 0x2C0C 321254885Sdumbbell#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 322254885Sdumbbell#define HDP_TILING_CONFIG 0x2F3C 323254885Sdumbbell#define HDP_DEBUG1 0x2F34 324254885Sdumbbell 325254885Sdumbbell#define MC_VM_AGP_TOP 0x2184 326254885Sdumbbell#define MC_VM_AGP_BOT 0x2188 327254885Sdumbbell#define MC_VM_AGP_BASE 0x218C 328254885Sdumbbell#define MC_VM_FB_LOCATION 0x2180 329254885Sdumbbell#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C 330254885Sdumbbell#define ENABLE_L1_TLB (1 << 0) 331254885Sdumbbell#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 332254885Sdumbbell#define ENABLE_L1_STRICT_ORDERING (1 << 2) 333254885Sdumbbell#define SYSTEM_ACCESS_MODE_MASK 0x000000C0 334254885Sdumbbell#define SYSTEM_ACCESS_MODE_SHIFT 6 335254885Sdumbbell#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 336254885Sdumbbell#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 337254885Sdumbbell#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 338254885Sdumbbell#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 339254885Sdumbbell#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 340254885Sdumbbell#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 341254885Sdumbbell#define ENABLE_SEMAPHORE_MODE (1 << 10) 342254885Sdumbbell#define ENABLE_WAIT_L2_QUERY (1 << 11) 343254885Sdumbbell#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) 344254885Sdumbbell#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 345254885Sdumbbell#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 346254885Sdumbbell#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) 347254885Sdumbbell#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 348254885Sdumbbell#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 349254885Sdumbbell#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 350254885Sdumbbell#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC 351254885Sdumbbell#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 352254885Sdumbbell#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 353254885Sdumbbell#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C 354254885Sdumbbell#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 355254885Sdumbbell#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 356254885Sdumbbell#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 357254885Sdumbbell#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 358254885Sdumbbell#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 359254885Sdumbbell#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C 360254885Sdumbbell#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 361254885Sdumbbell#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 362254885Sdumbbell#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 363254885Sdumbbell#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 364254885Sdumbbell#define LOGICAL_PAGE_NUMBER_SHIFT 0 365254885Sdumbbell#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 366254885Sdumbbell#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 367254885Sdumbbell 368254885Sdumbbell#define PA_CL_ENHANCE 0x8A14 369254885Sdumbbell#define CLIP_VTX_REORDER_ENA (1 << 0) 370254885Sdumbbell#define NUM_CLIP_SEQ(x) ((x) << 1) 371254885Sdumbbell#define PA_SC_AA_CONFIG 0x28C04 372254885Sdumbbell#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 373254885Sdumbbell#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 374254885Sdumbbell#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 375254885Sdumbbell#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C 376254885Sdumbbell#define S0_X(x) ((x) << 0) 377254885Sdumbbell#define S0_Y(x) ((x) << 4) 378254885Sdumbbell#define S1_X(x) ((x) << 8) 379254885Sdumbbell#define S1_Y(x) ((x) << 12) 380254885Sdumbbell#define S2_X(x) ((x) << 16) 381254885Sdumbbell#define S2_Y(x) ((x) << 20) 382254885Sdumbbell#define S3_X(x) ((x) << 24) 383254885Sdumbbell#define S3_Y(x) ((x) << 28) 384254885Sdumbbell#define S4_X(x) ((x) << 0) 385254885Sdumbbell#define S4_Y(x) ((x) << 4) 386254885Sdumbbell#define S5_X(x) ((x) << 8) 387254885Sdumbbell#define S5_Y(x) ((x) << 12) 388254885Sdumbbell#define S6_X(x) ((x) << 16) 389254885Sdumbbell#define S6_Y(x) ((x) << 20) 390254885Sdumbbell#define S7_X(x) ((x) << 24) 391254885Sdumbbell#define S7_Y(x) ((x) << 28) 392254885Sdumbbell#define PA_SC_CLIPRECT_RULE 0x2820c 393254885Sdumbbell#define PA_SC_ENHANCE 0x8BF0 394254885Sdumbbell#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 395254885Sdumbbell#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 396254885Sdumbbell#define PA_SC_LINE_STIPPLE 0x28A0C 397254885Sdumbbell#define PA_SC_LINE_STIPPLE_STATE 0x8B10 398254885Sdumbbell#define PA_SC_MODE_CNTL 0x28A4C 399254885Sdumbbell#define PA_SC_MULTI_CHIP_CNTL 0x8B20 400254885Sdumbbell 401254885Sdumbbell#define PA_SC_SCREEN_SCISSOR_TL 0x28030 402254885Sdumbbell#define PA_SC_GENERIC_SCISSOR_TL 0x28240 403254885Sdumbbell#define PA_SC_WINDOW_SCISSOR_TL 0x28204 404254885Sdumbbell 405254885Sdumbbell#define PCIE_PORT_INDEX 0x0038 406254885Sdumbbell#define PCIE_PORT_DATA 0x003C 407254885Sdumbbell 408254885Sdumbbell#define CHMAP 0x2004 409254885Sdumbbell#define NOOFCHAN_SHIFT 12 410254885Sdumbbell#define NOOFCHAN_MASK 0x00003000 411254885Sdumbbell 412254885Sdumbbell#define RAMCFG 0x2408 413254885Sdumbbell#define NOOFBANK_SHIFT 0 414254885Sdumbbell#define NOOFBANK_MASK 0x00000001 415254885Sdumbbell#define NOOFRANK_SHIFT 1 416254885Sdumbbell#define NOOFRANK_MASK 0x00000002 417254885Sdumbbell#define NOOFROWS_SHIFT 2 418254885Sdumbbell#define NOOFROWS_MASK 0x0000001C 419254885Sdumbbell#define NOOFCOLS_SHIFT 5 420254885Sdumbbell#define NOOFCOLS_MASK 0x00000060 421254885Sdumbbell#define CHANSIZE_SHIFT 7 422254885Sdumbbell#define CHANSIZE_MASK 0x00000080 423254885Sdumbbell#define BURSTLENGTH_SHIFT 8 424254885Sdumbbell#define BURSTLENGTH_MASK 0x00000100 425254885Sdumbbell#define CHANSIZE_OVERRIDE (1 << 10) 426254885Sdumbbell 427254885Sdumbbell#define SCRATCH_REG0 0x8500 428254885Sdumbbell#define SCRATCH_REG1 0x8504 429254885Sdumbbell#define SCRATCH_REG2 0x8508 430254885Sdumbbell#define SCRATCH_REG3 0x850C 431254885Sdumbbell#define SCRATCH_REG4 0x8510 432254885Sdumbbell#define SCRATCH_REG5 0x8514 433254885Sdumbbell#define SCRATCH_REG6 0x8518 434254885Sdumbbell#define SCRATCH_REG7 0x851C 435254885Sdumbbell#define SCRATCH_UMSK 0x8540 436254885Sdumbbell#define SCRATCH_ADDR 0x8544 437254885Sdumbbell 438254885Sdumbbell#define SPI_CONFIG_CNTL 0x9100 439254885Sdumbbell#define GPR_WRITE_PRIORITY(x) ((x) << 0) 440254885Sdumbbell#define DISABLE_INTERP_1 (1 << 5) 441254885Sdumbbell#define SPI_CONFIG_CNTL_1 0x913C 442254885Sdumbbell#define VTX_DONE_DELAY(x) ((x) << 0) 443254885Sdumbbell#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 444254885Sdumbbell#define SPI_INPUT_Z 0x286D8 445254885Sdumbbell#define SPI_PS_IN_CONTROL_0 0x286CC 446254885Sdumbbell#define NUM_INTERP(x) ((x)<<0) 447254885Sdumbbell#define POSITION_ENA (1<<8) 448254885Sdumbbell#define POSITION_CENTROID (1<<9) 449254885Sdumbbell#define POSITION_ADDR(x) ((x)<<10) 450254885Sdumbbell#define PARAM_GEN(x) ((x)<<15) 451254885Sdumbbell#define PARAM_GEN_ADDR(x) ((x)<<19) 452254885Sdumbbell#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 453254885Sdumbbell#define PERSP_GRADIENT_ENA (1<<28) 454254885Sdumbbell#define LINEAR_GRADIENT_ENA (1<<29) 455254885Sdumbbell#define POSITION_SAMPLE (1<<30) 456254885Sdumbbell#define BARYC_AT_SAMPLE_ENA (1<<31) 457254885Sdumbbell#define SPI_PS_IN_CONTROL_1 0x286D0 458254885Sdumbbell#define GEN_INDEX_PIX (1<<0) 459254885Sdumbbell#define GEN_INDEX_PIX_ADDR(x) ((x)<<1) 460254885Sdumbbell#define FRONT_FACE_ENA (1<<8) 461254885Sdumbbell#define FRONT_FACE_CHAN(x) ((x)<<9) 462254885Sdumbbell#define FRONT_FACE_ALL_BITS (1<<11) 463254885Sdumbbell#define FRONT_FACE_ADDR(x) ((x)<<12) 464254885Sdumbbell#define FOG_ADDR(x) ((x)<<17) 465254885Sdumbbell#define FIXED_PT_POSITION_ENA (1<<24) 466254885Sdumbbell#define FIXED_PT_POSITION_ADDR(x) ((x)<<25) 467254885Sdumbbell 468254885Sdumbbell#define SQ_MS_FIFO_SIZES 0x8CF0 469254885Sdumbbell#define CACHE_FIFO_SIZE(x) ((x) << 0) 470254885Sdumbbell#define FETCH_FIFO_HIWATER(x) ((x) << 8) 471254885Sdumbbell#define DONE_FIFO_HIWATER(x) ((x) << 16) 472254885Sdumbbell#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 473254885Sdumbbell#define SQ_PGM_START_ES 0x28880 474254885Sdumbbell#define SQ_PGM_START_FS 0x28894 475254885Sdumbbell#define SQ_PGM_START_GS 0x2886C 476254885Sdumbbell#define SQ_PGM_START_PS 0x28840 477254885Sdumbbell#define SQ_PGM_RESOURCES_PS 0x28850 478254885Sdumbbell#define SQ_PGM_EXPORTS_PS 0x28854 479254885Sdumbbell#define SQ_PGM_CF_OFFSET_PS 0x288cc 480254885Sdumbbell#define SQ_PGM_START_VS 0x28858 481254885Sdumbbell#define SQ_PGM_RESOURCES_VS 0x28868 482254885Sdumbbell#define SQ_PGM_CF_OFFSET_VS 0x288d0 483254885Sdumbbell 484254885Sdumbbell#define SQ_VTX_CONSTANT_WORD0_0 0x30000 485254885Sdumbbell#define SQ_VTX_CONSTANT_WORD1_0 0x30004 486254885Sdumbbell#define SQ_VTX_CONSTANT_WORD2_0 0x30008 487254885Sdumbbell# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 488254885Sdumbbell# define SQ_VTXC_STRIDE(x) ((x) << 8) 489254885Sdumbbell# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 490254885Sdumbbell# define SQ_ENDIAN_NONE 0 491254885Sdumbbell# define SQ_ENDIAN_8IN16 1 492254885Sdumbbell# define SQ_ENDIAN_8IN32 2 493254885Sdumbbell#define SQ_VTX_CONSTANT_WORD3_0 0x3000c 494254885Sdumbbell#define SQ_VTX_CONSTANT_WORD6_0 0x38018 495254885Sdumbbell#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) 496254885Sdumbbell#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) 497254885Sdumbbell#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 498254885Sdumbbell#define SQ_TEX_VTX_INVALID_BUFFER 0x1 499254885Sdumbbell#define SQ_TEX_VTX_VALID_TEXTURE 0x2 500254885Sdumbbell#define SQ_TEX_VTX_VALID_BUFFER 0x3 501254885Sdumbbell 502254885Sdumbbell 503254885Sdumbbell#define SX_MISC 0x28350 504254885Sdumbbell#define SX_MEMORY_EXPORT_BASE 0x9010 505254885Sdumbbell#define SX_DEBUG_1 0x9054 506254885Sdumbbell#define SMX_EVENT_RELEASE (1 << 0) 507254885Sdumbbell#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 508254885Sdumbbell 509254885Sdumbbell#define TA_CNTL_AUX 0x9508 510254885Sdumbbell#define DISABLE_CUBE_WRAP (1 << 0) 511254885Sdumbbell#define DISABLE_CUBE_ANISO (1 << 1) 512254885Sdumbbell#define SYNC_GRADIENT (1 << 24) 513254885Sdumbbell#define SYNC_WALKER (1 << 25) 514254885Sdumbbell#define SYNC_ALIGNER (1 << 26) 515254885Sdumbbell#define BILINEAR_PRECISION_6_BIT (0 << 31) 516261455Seadler#define BILINEAR_PRECISION_8_BIT (1U << 31) 517254885Sdumbbell 518254885Sdumbbell#define TC_CNTL 0x9608 519254885Sdumbbell#define TC_L2_SIZE(x) ((x)<<5) 520254885Sdumbbell#define L2_DISABLE_LATE_HIT (1<<9) 521254885Sdumbbell 522254885Sdumbbell#define VC_ENHANCE 0x9714 523254885Sdumbbell 524254885Sdumbbell#define VGT_CACHE_INVALIDATION 0x88C4 525254885Sdumbbell#define CACHE_INVALIDATION(x) ((x)<<0) 526254885Sdumbbell#define VC_ONLY 0 527254885Sdumbbell#define TC_ONLY 1 528254885Sdumbbell#define VC_AND_TC 2 529254885Sdumbbell#define VGT_DMA_BASE 0x287E8 530254885Sdumbbell#define VGT_DMA_BASE_HI 0x287E4 531254885Sdumbbell#define VGT_ES_PER_GS 0x88CC 532254885Sdumbbell#define VGT_GS_PER_ES 0x88C8 533254885Sdumbbell#define VGT_GS_PER_VS 0x88E8 534254885Sdumbbell#define VGT_GS_VERTEX_REUSE 0x88D4 535254885Sdumbbell#define VGT_PRIMITIVE_TYPE 0x8958 536254885Sdumbbell#define VGT_NUM_INSTANCES 0x8974 537254885Sdumbbell#define VGT_OUT_DEALLOC_CNTL 0x28C5C 538254885Sdumbbell#define DEALLOC_DIST_MASK 0x0000007F 539254885Sdumbbell#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 540254885Sdumbbell#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 541254885Sdumbbell#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 542254885Sdumbbell#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c 543254885Sdumbbell#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 544254885Sdumbbell#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 545254885Sdumbbell#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c 546254885Sdumbbell#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 547254885Sdumbbell#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 548254885Sdumbbell#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 549254885Sdumbbell#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 550254885Sdumbbell#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 551254885Sdumbbell#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC 552254885Sdumbbell#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC 553254885Sdumbbell#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC 554254885Sdumbbell#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C 555254885Sdumbbell#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 556254885Sdumbbell#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 557254885Sdumbbell#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 558254885Sdumbbell#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 559254885Sdumbbell 560254885Sdumbbell#define VGT_STRMOUT_EN 0x28AB0 561254885Sdumbbell#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 562254885Sdumbbell#define VTX_REUSE_DEPTH_MASK 0x000000FF 563254885Sdumbbell#define VGT_EVENT_INITIATOR 0x28a90 564254885Sdumbbell# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 565254885Sdumbbell# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 566254885Sdumbbell 567254885Sdumbbell#define VM_CONTEXT0_CNTL 0x1410 568254885Sdumbbell#define ENABLE_CONTEXT (1 << 0) 569254885Sdumbbell#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 570254885Sdumbbell#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 571254885Sdumbbell#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 572254885Sdumbbell#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 573254885Sdumbbell#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 574254885Sdumbbell#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 575254885Sdumbbell#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 576254885Sdumbbell#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 577254885Sdumbbell#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 578254885Sdumbbell#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 579254885Sdumbbell#define RESPONSE_TYPE_MASK 0x000000F0 580254885Sdumbbell#define RESPONSE_TYPE_SHIFT 4 581254885Sdumbbell#define VM_L2_CNTL 0x1400 582254885Sdumbbell#define ENABLE_L2_CACHE (1 << 0) 583254885Sdumbbell#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 584254885Sdumbbell#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 585254885Sdumbbell#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) 586254885Sdumbbell#define VM_L2_CNTL2 0x1404 587254885Sdumbbell#define INVALIDATE_ALL_L1_TLBS (1 << 0) 588254885Sdumbbell#define INVALIDATE_L2_CACHE (1 << 1) 589254885Sdumbbell#define VM_L2_CNTL3 0x1408 590254885Sdumbbell#define BANK_SELECT_0(x) (((x) & 0x1f) << 0) 591254885Sdumbbell#define BANK_SELECT_1(x) (((x) & 0x1f) << 5) 592254885Sdumbbell#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) 593254885Sdumbbell#define VM_L2_STATUS 0x140C 594254885Sdumbbell#define L2_BUSY (1 << 0) 595254885Sdumbbell 596254885Sdumbbell#define WAIT_UNTIL 0x8040 597254885Sdumbbell#define WAIT_2D_IDLE_bit (1 << 14) 598254885Sdumbbell#define WAIT_3D_IDLE_bit (1 << 15) 599254885Sdumbbell#define WAIT_2D_IDLECLEAN_bit (1 << 16) 600254885Sdumbbell#define WAIT_3D_IDLECLEAN_bit (1 << 17) 601254885Sdumbbell 602254885Sdumbbell/* async DMA */ 603254885Sdumbbell#define DMA_TILING_CONFIG 0x3ec4 604254885Sdumbbell#define DMA_CONFIG 0x3e4c 605254885Sdumbbell 606254885Sdumbbell#define DMA_RB_CNTL 0xd000 607254885Sdumbbell# define DMA_RB_ENABLE (1 << 0) 608254885Sdumbbell# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 609254885Sdumbbell# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 610254885Sdumbbell# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 611254885Sdumbbell# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 612254885Sdumbbell# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 613254885Sdumbbell#define DMA_RB_BASE 0xd004 614254885Sdumbbell#define DMA_RB_RPTR 0xd008 615254885Sdumbbell#define DMA_RB_WPTR 0xd00c 616254885Sdumbbell 617254885Sdumbbell#define DMA_RB_RPTR_ADDR_HI 0xd01c 618254885Sdumbbell#define DMA_RB_RPTR_ADDR_LO 0xd020 619254885Sdumbbell 620254885Sdumbbell#define DMA_IB_CNTL 0xd024 621254885Sdumbbell# define DMA_IB_ENABLE (1 << 0) 622254885Sdumbbell# define DMA_IB_SWAP_ENABLE (1 << 4) 623254885Sdumbbell#define DMA_IB_RPTR 0xd028 624254885Sdumbbell#define DMA_CNTL 0xd02c 625254885Sdumbbell# define TRAP_ENABLE (1 << 0) 626254885Sdumbbell# define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 627254885Sdumbbell# define SEM_WAIT_INT_ENABLE (1 << 2) 628254885Sdumbbell# define DATA_SWAP_ENABLE (1 << 3) 629254885Sdumbbell# define FENCE_SWAP_ENABLE (1 << 4) 630254885Sdumbbell# define CTXEMPTY_INT_ENABLE (1 << 28) 631254885Sdumbbell#define DMA_STATUS_REG 0xd034 632254885Sdumbbell# define DMA_IDLE (1 << 0) 633254885Sdumbbell#define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 634254885Sdumbbell#define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 635254885Sdumbbell#define DMA_MODE 0xd0bc 636254885Sdumbbell 637254885Sdumbbell/* async DMA packets */ 638254885Sdumbbell#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 639254885Sdumbbell (((t) & 0x1) << 23) | \ 640254885Sdumbbell (((s) & 0x1) << 22) | \ 641254885Sdumbbell (((n) & 0xFFFF) << 0)) 642254885Sdumbbell/* async DMA Packet types */ 643254885Sdumbbell#define DMA_PACKET_WRITE 0x2 644254885Sdumbbell#define DMA_PACKET_COPY 0x3 645254885Sdumbbell#define DMA_PACKET_INDIRECT_BUFFER 0x4 646254885Sdumbbell#define DMA_PACKET_SEMAPHORE 0x5 647254885Sdumbbell#define DMA_PACKET_FENCE 0x6 648254885Sdumbbell#define DMA_PACKET_TRAP 0x7 649254885Sdumbbell#define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */ 650254885Sdumbbell#define DMA_PACKET_NOP 0xf 651254885Sdumbbell 652254885Sdumbbell#define IH_RB_CNTL 0x3e00 653254885Sdumbbell# define IH_RB_ENABLE (1 << 0) 654254885Sdumbbell# define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 655254885Sdumbbell# define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 656254885Sdumbbell# define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 657254885Sdumbbell# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 658254885Sdumbbell# define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 659261455Seadler# define IH_WPTR_OVERFLOW_CLEAR (1U << 31) 660254885Sdumbbell#define IH_RB_BASE 0x3e04 661254885Sdumbbell#define IH_RB_RPTR 0x3e08 662254885Sdumbbell#define IH_RB_WPTR 0x3e0c 663254885Sdumbbell# define RB_OVERFLOW (1 << 0) 664254885Sdumbbell# define WPTR_OFFSET_MASK 0x3fffc 665254885Sdumbbell#define IH_RB_WPTR_ADDR_HI 0x3e10 666254885Sdumbbell#define IH_RB_WPTR_ADDR_LO 0x3e14 667254885Sdumbbell#define IH_CNTL 0x3e18 668254885Sdumbbell# define ENABLE_INTR (1 << 0) 669254885Sdumbbell# define IH_MC_SWAP(x) ((x) << 1) 670254885Sdumbbell# define IH_MC_SWAP_NONE 0 671254885Sdumbbell# define IH_MC_SWAP_16BIT 1 672254885Sdumbbell# define IH_MC_SWAP_32BIT 2 673254885Sdumbbell# define IH_MC_SWAP_64BIT 3 674254885Sdumbbell# define RPTR_REARM (1 << 4) 675254885Sdumbbell# define MC_WRREQ_CREDIT(x) ((x) << 15) 676254885Sdumbbell# define MC_WR_CLEAN_CNT(x) ((x) << 20) 677254885Sdumbbell 678254885Sdumbbell#define RLC_CNTL 0x3f00 679254885Sdumbbell# define RLC_ENABLE (1 << 0) 680254885Sdumbbell#define RLC_HB_BASE 0x3f10 681254885Sdumbbell#define RLC_HB_CNTL 0x3f0c 682254885Sdumbbell#define RLC_HB_RPTR 0x3f20 683254885Sdumbbell#define RLC_HB_WPTR 0x3f1c 684254885Sdumbbell#define RLC_HB_WPTR_LSB_ADDR 0x3f14 685254885Sdumbbell#define RLC_HB_WPTR_MSB_ADDR 0x3f18 686254885Sdumbbell#define RLC_GPU_CLOCK_COUNT_LSB 0x3f38 687254885Sdumbbell#define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c 688254885Sdumbbell#define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40 689254885Sdumbbell#define RLC_MC_CNTL 0x3f44 690254885Sdumbbell#define RLC_UCODE_CNTL 0x3f48 691254885Sdumbbell#define RLC_UCODE_ADDR 0x3f2c 692254885Sdumbbell#define RLC_UCODE_DATA 0x3f30 693254885Sdumbbell 694254885Sdumbbell/* new for TN */ 695254885Sdumbbell#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10 696254885Sdumbbell#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 697254885Sdumbbell 698254885Sdumbbell#define SRBM_SOFT_RESET 0xe60 699254885Sdumbbell# define SOFT_RESET_DMA (1 << 12) 700254885Sdumbbell# define SOFT_RESET_RLC (1 << 13) 701254885Sdumbbell# define RV770_SOFT_RESET_DMA (1 << 20) 702254885Sdumbbell 703254885Sdumbbell#define CP_INT_CNTL 0xc124 704254885Sdumbbell# define CNTX_BUSY_INT_ENABLE (1 << 19) 705254885Sdumbbell# define CNTX_EMPTY_INT_ENABLE (1 << 20) 706254885Sdumbbell# define SCRATCH_INT_ENABLE (1 << 25) 707254885Sdumbbell# define TIME_STAMP_INT_ENABLE (1 << 26) 708254885Sdumbbell# define IB2_INT_ENABLE (1 << 29) 709254885Sdumbbell# define IB1_INT_ENABLE (1 << 30) 710261455Seadler# define RB_INT_ENABLE (1U << 31) 711254885Sdumbbell#define CP_INT_STATUS 0xc128 712254885Sdumbbell# define SCRATCH_INT_STAT (1 << 25) 713254885Sdumbbell# define TIME_STAMP_INT_STAT (1 << 26) 714254885Sdumbbell# define IB2_INT_STAT (1 << 29) 715254885Sdumbbell# define IB1_INT_STAT (1 << 30) 716261455Seadler# define RB_INT_STAT (1U << 31) 717254885Sdumbbell 718254885Sdumbbell#define GRBM_INT_CNTL 0x8060 719254885Sdumbbell# define RDERR_INT_ENABLE (1 << 0) 720254885Sdumbbell# define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) 721254885Sdumbbell# define GUI_IDLE_INT_ENABLE (1 << 19) 722254885Sdumbbell 723254885Sdumbbell#define INTERRUPT_CNTL 0x5468 724254885Sdumbbell# define IH_DUMMY_RD_OVERRIDE (1 << 0) 725254885Sdumbbell# define IH_DUMMY_RD_EN (1 << 1) 726254885Sdumbbell# define IH_REQ_NONSNOOP_EN (1 << 3) 727254885Sdumbbell# define GEN_IH_INT_EN (1 << 8) 728254885Sdumbbell#define INTERRUPT_CNTL2 0x546c 729254885Sdumbbell 730254885Sdumbbell#define D1MODE_VBLANK_STATUS 0x6534 731254885Sdumbbell#define D2MODE_VBLANK_STATUS 0x6d34 732254885Sdumbbell# define DxMODE_VBLANK_OCCURRED (1 << 0) 733254885Sdumbbell# define DxMODE_VBLANK_ACK (1 << 4) 734254885Sdumbbell# define DxMODE_VBLANK_STAT (1 << 12) 735254885Sdumbbell# define DxMODE_VBLANK_INTERRUPT (1 << 16) 736254885Sdumbbell# define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) 737254885Sdumbbell#define D1MODE_VLINE_STATUS 0x653c 738254885Sdumbbell#define D2MODE_VLINE_STATUS 0x6d3c 739254885Sdumbbell# define DxMODE_VLINE_OCCURRED (1 << 0) 740254885Sdumbbell# define DxMODE_VLINE_ACK (1 << 4) 741254885Sdumbbell# define DxMODE_VLINE_STAT (1 << 12) 742254885Sdumbbell# define DxMODE_VLINE_INTERRUPT (1 << 16) 743254885Sdumbbell# define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) 744254885Sdumbbell#define DxMODE_INT_MASK 0x6540 745254885Sdumbbell# define D1MODE_VBLANK_INT_MASK (1 << 0) 746254885Sdumbbell# define D1MODE_VLINE_INT_MASK (1 << 4) 747254885Sdumbbell# define D2MODE_VBLANK_INT_MASK (1 << 8) 748254885Sdumbbell# define D2MODE_VLINE_INT_MASK (1 << 12) 749254885Sdumbbell#define DCE3_DISP_INTERRUPT_STATUS 0x7ddc 750254885Sdumbbell# define DC_HPD1_INTERRUPT (1 << 18) 751254885Sdumbbell# define DC_HPD2_INTERRUPT (1 << 19) 752254885Sdumbbell#define DISP_INTERRUPT_STATUS 0x7edc 753254885Sdumbbell# define LB_D1_VLINE_INTERRUPT (1 << 2) 754254885Sdumbbell# define LB_D2_VLINE_INTERRUPT (1 << 3) 755254885Sdumbbell# define LB_D1_VBLANK_INTERRUPT (1 << 4) 756254885Sdumbbell# define LB_D2_VBLANK_INTERRUPT (1 << 5) 757254885Sdumbbell# define DACA_AUTODETECT_INTERRUPT (1 << 16) 758254885Sdumbbell# define DACB_AUTODETECT_INTERRUPT (1 << 17) 759254885Sdumbbell# define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) 760254885Sdumbbell# define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) 761254885Sdumbbell# define DC_I2C_SW_DONE_INTERRUPT (1 << 20) 762254885Sdumbbell# define DC_I2C_HW_DONE_INTERRUPT (1 << 21) 763254885Sdumbbell#define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 764254885Sdumbbell#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 765254885Sdumbbell# define DC_HPD4_INTERRUPT (1 << 14) 766254885Sdumbbell# define DC_HPD4_RX_INTERRUPT (1 << 15) 767254885Sdumbbell# define DC_HPD3_INTERRUPT (1 << 28) 768254885Sdumbbell# define DC_HPD1_RX_INTERRUPT (1 << 29) 769254885Sdumbbell# define DC_HPD2_RX_INTERRUPT (1 << 30) 770254885Sdumbbell#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec 771254885Sdumbbell# define DC_HPD3_RX_INTERRUPT (1 << 0) 772254885Sdumbbell# define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) 773254885Sdumbbell# define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) 774254885Sdumbbell# define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) 775254885Sdumbbell# define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) 776254885Sdumbbell# define AUX1_SW_DONE_INTERRUPT (1 << 5) 777254885Sdumbbell# define AUX1_LS_DONE_INTERRUPT (1 << 6) 778254885Sdumbbell# define AUX2_SW_DONE_INTERRUPT (1 << 7) 779254885Sdumbbell# define AUX2_LS_DONE_INTERRUPT (1 << 8) 780254885Sdumbbell# define AUX3_SW_DONE_INTERRUPT (1 << 9) 781254885Sdumbbell# define AUX3_LS_DONE_INTERRUPT (1 << 10) 782254885Sdumbbell# define AUX4_SW_DONE_INTERRUPT (1 << 11) 783254885Sdumbbell# define AUX4_LS_DONE_INTERRUPT (1 << 12) 784254885Sdumbbell# define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) 785254885Sdumbbell# define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) 786254885Sdumbbell/* DCE 3.2 */ 787254885Sdumbbell# define AUX5_SW_DONE_INTERRUPT (1 << 15) 788254885Sdumbbell# define AUX5_LS_DONE_INTERRUPT (1 << 16) 789254885Sdumbbell# define AUX6_SW_DONE_INTERRUPT (1 << 17) 790254885Sdumbbell# define AUX6_LS_DONE_INTERRUPT (1 << 18) 791254885Sdumbbell# define DC_HPD5_INTERRUPT (1 << 19) 792254885Sdumbbell# define DC_HPD5_RX_INTERRUPT (1 << 20) 793254885Sdumbbell# define DC_HPD6_INTERRUPT (1 << 21) 794254885Sdumbbell# define DC_HPD6_RX_INTERRUPT (1 << 22) 795254885Sdumbbell 796254885Sdumbbell#define DACA_AUTO_DETECT_CONTROL 0x7828 797254885Sdumbbell#define DACB_AUTO_DETECT_CONTROL 0x7a28 798254885Sdumbbell#define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 799254885Sdumbbell#define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 800254885Sdumbbell# define DACx_AUTODETECT_MODE(x) ((x) << 0) 801254885Sdumbbell# define DACx_AUTODETECT_MODE_NONE 0 802254885Sdumbbell# define DACx_AUTODETECT_MODE_CONNECT 1 803254885Sdumbbell# define DACx_AUTODETECT_MODE_DISCONNECT 2 804254885Sdumbbell# define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) 805254885Sdumbbell/* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ 806254885Sdumbbell# define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) 807254885Sdumbbell 808254885Sdumbbell#define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 809254885Sdumbbell#define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 810254885Sdumbbell#define DACA_AUTODETECT_INT_CONTROL 0x7838 811254885Sdumbbell#define DACB_AUTODETECT_INT_CONTROL 0x7a38 812254885Sdumbbell# define DACx_AUTODETECT_ACK (1 << 0) 813254885Sdumbbell# define DACx_AUTODETECT_INT_ENABLE (1 << 16) 814254885Sdumbbell 815254885Sdumbbell#define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 816254885Sdumbbell#define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 817254885Sdumbbell#define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 818254885Sdumbbell# define DC_HOT_PLUG_DETECTx_EN (1 << 0) 819254885Sdumbbell 820254885Sdumbbell#define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 821254885Sdumbbell#define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 822254885Sdumbbell#define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 823254885Sdumbbell# define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) 824254885Sdumbbell# define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) 825254885Sdumbbell 826254885Sdumbbell/* DCE 3.0 */ 827254885Sdumbbell#define DC_HPD1_INT_STATUS 0x7d00 828254885Sdumbbell#define DC_HPD2_INT_STATUS 0x7d0c 829254885Sdumbbell#define DC_HPD3_INT_STATUS 0x7d18 830254885Sdumbbell#define DC_HPD4_INT_STATUS 0x7d24 831254885Sdumbbell/* DCE 3.2 */ 832254885Sdumbbell#define DC_HPD5_INT_STATUS 0x7dc0 833254885Sdumbbell#define DC_HPD6_INT_STATUS 0x7df4 834254885Sdumbbell# define DC_HPDx_INT_STATUS (1 << 0) 835254885Sdumbbell# define DC_HPDx_SENSE (1 << 1) 836254885Sdumbbell# define DC_HPDx_RX_INT_STATUS (1 << 8) 837254885Sdumbbell 838254885Sdumbbell#define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 839254885Sdumbbell#define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 840254885Sdumbbell#define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c 841254885Sdumbbell# define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) 842254885Sdumbbell# define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) 843254885Sdumbbell# define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) 844254885Sdumbbell/* DCE 3.0 */ 845254885Sdumbbell#define DC_HPD1_INT_CONTROL 0x7d04 846254885Sdumbbell#define DC_HPD2_INT_CONTROL 0x7d10 847254885Sdumbbell#define DC_HPD3_INT_CONTROL 0x7d1c 848254885Sdumbbell#define DC_HPD4_INT_CONTROL 0x7d28 849254885Sdumbbell/* DCE 3.2 */ 850254885Sdumbbell#define DC_HPD5_INT_CONTROL 0x7dc4 851254885Sdumbbell#define DC_HPD6_INT_CONTROL 0x7df8 852254885Sdumbbell# define DC_HPDx_INT_ACK (1 << 0) 853254885Sdumbbell# define DC_HPDx_INT_POLARITY (1 << 8) 854254885Sdumbbell# define DC_HPDx_INT_EN (1 << 16) 855254885Sdumbbell# define DC_HPDx_RX_INT_ACK (1 << 20) 856254885Sdumbbell# define DC_HPDx_RX_INT_EN (1 << 24) 857254885Sdumbbell 858254885Sdumbbell/* DCE 3.0 */ 859254885Sdumbbell#define DC_HPD1_CONTROL 0x7d08 860254885Sdumbbell#define DC_HPD2_CONTROL 0x7d14 861254885Sdumbbell#define DC_HPD3_CONTROL 0x7d20 862254885Sdumbbell#define DC_HPD4_CONTROL 0x7d2c 863254885Sdumbbell/* DCE 3.2 */ 864254885Sdumbbell#define DC_HPD5_CONTROL 0x7dc8 865254885Sdumbbell#define DC_HPD6_CONTROL 0x7dfc 866254885Sdumbbell# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 867254885Sdumbbell# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 868254885Sdumbbell/* DCE 3.2 */ 869254885Sdumbbell# define DC_HPDx_EN (1 << 28) 870254885Sdumbbell 871254885Sdumbbell#define D1GRPH_INTERRUPT_STATUS 0x6158 872254885Sdumbbell#define D2GRPH_INTERRUPT_STATUS 0x6958 873254885Sdumbbell# define DxGRPH_PFLIP_INT_OCCURRED (1 << 0) 874254885Sdumbbell# define DxGRPH_PFLIP_INT_CLEAR (1 << 8) 875254885Sdumbbell#define D1GRPH_INTERRUPT_CONTROL 0x615c 876254885Sdumbbell#define D2GRPH_INTERRUPT_CONTROL 0x695c 877254885Sdumbbell# define DxGRPH_PFLIP_INT_MASK (1 << 0) 878254885Sdumbbell# define DxGRPH_PFLIP_INT_TYPE (1 << 8) 879254885Sdumbbell 880254885Sdumbbell/* PCIE link stuff */ 881254885Sdumbbell#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 882254885Sdumbbell# define LC_POINT_7_PLUS_EN (1 << 6) 883254885Sdumbbell#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 884254885Sdumbbell# define LC_LINK_WIDTH_SHIFT 0 885254885Sdumbbell# define LC_LINK_WIDTH_MASK 0x7 886254885Sdumbbell# define LC_LINK_WIDTH_X0 0 887254885Sdumbbell# define LC_LINK_WIDTH_X1 1 888254885Sdumbbell# define LC_LINK_WIDTH_X2 2 889254885Sdumbbell# define LC_LINK_WIDTH_X4 3 890254885Sdumbbell# define LC_LINK_WIDTH_X8 4 891254885Sdumbbell# define LC_LINK_WIDTH_X16 6 892254885Sdumbbell# define LC_LINK_WIDTH_RD_SHIFT 4 893254885Sdumbbell# define LC_LINK_WIDTH_RD_MASK 0x70 894254885Sdumbbell# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 895254885Sdumbbell# define LC_RECONFIG_NOW (1 << 8) 896254885Sdumbbell# define LC_RENEGOTIATION_SUPPORT (1 << 9) 897254885Sdumbbell# define LC_RENEGOTIATE_EN (1 << 10) 898254885Sdumbbell# define LC_SHORT_RECONFIG_EN (1 << 11) 899254885Sdumbbell# define LC_UPCONFIGURE_SUPPORT (1 << 12) 900254885Sdumbbell# define LC_UPCONFIGURE_DIS (1 << 13) 901254885Sdumbbell#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 902254885Sdumbbell# define LC_GEN2_EN_STRAP (1 << 0) 903254885Sdumbbell# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 904254885Sdumbbell# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 905254885Sdumbbell# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 906254885Sdumbbell# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 907254885Sdumbbell# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 908254885Sdumbbell# define LC_CURRENT_DATA_RATE (1 << 11) 909254885Sdumbbell# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 910254885Sdumbbell# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 911254885Sdumbbell# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 912254885Sdumbbell# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 913254885Sdumbbell#define MM_CFGREGS_CNTL 0x544c 914254885Sdumbbell# define MM_WR_TO_CFG_EN (1 << 3) 915254885Sdumbbell#define LINK_CNTL2 0x88 /* F0 */ 916254885Sdumbbell# define TARGET_LINK_SPEED_MASK (0xf << 0) 917254885Sdumbbell# define SELECTABLE_DEEMPHASIS (1 << 6) 918254885Sdumbbell 919254885Sdumbbell/* Audio clocks */ 920254885Sdumbbell#define DCCG_AUDIO_DTO0_PHASE 0x0514 921254885Sdumbbell#define DCCG_AUDIO_DTO0_MODULE 0x0518 922254885Sdumbbell#define DCCG_AUDIO_DTO0_LOAD 0x051c 923261455Seadler# define DTO_LOAD (1U << 31) 924254885Sdumbbell#define DCCG_AUDIO_DTO0_CNTL 0x0520 925254885Sdumbbell 926254885Sdumbbell#define DCCG_AUDIO_DTO1_PHASE 0x0524 927254885Sdumbbell#define DCCG_AUDIO_DTO1_MODULE 0x0528 928254885Sdumbbell#define DCCG_AUDIO_DTO1_LOAD 0x052c 929254885Sdumbbell#define DCCG_AUDIO_DTO1_CNTL 0x0530 930254885Sdumbbell 931254885Sdumbbell#define DCCG_AUDIO_DTO_SELECT 0x0534 932254885Sdumbbell 933254885Sdumbbell/* digital blocks */ 934254885Sdumbbell#define TMDSA_CNTL 0x7880 935254885Sdumbbell# define TMDSA_HDMI_EN (1 << 2) 936254885Sdumbbell#define LVTMA_CNTL 0x7a80 937254885Sdumbbell# define LVTMA_HDMI_EN (1 << 2) 938254885Sdumbbell#define DDIA_CNTL 0x7200 939254885Sdumbbell# define DDIA_HDMI_EN (1 << 2) 940254885Sdumbbell#define DIG0_CNTL 0x75a0 941254885Sdumbbell# define DIG_MODE(x) (((x) & 7) << 8) 942254885Sdumbbell# define DIG_MODE_DP 0 943254885Sdumbbell# define DIG_MODE_LVDS 1 944254885Sdumbbell# define DIG_MODE_TMDS_DVI 2 945254885Sdumbbell# define DIG_MODE_TMDS_HDMI 3 946254885Sdumbbell# define DIG_MODE_SDVO 4 947254885Sdumbbell#define DIG1_CNTL 0x79a0 948254885Sdumbbell 949254885Sdumbbell/* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one 950254885Sdumbbell * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly 951254885Sdumbbell * different due to the new DIG blocks, but also have 2 instances. 952254885Sdumbbell * DCE 3.0 HDMI blocks are part of each DIG encoder. 953254885Sdumbbell */ 954254885Sdumbbell 955254885Sdumbbell/* rs6xx/rs740/r6xx/dce3 */ 956254885Sdumbbell#define HDMI0_CONTROL 0x7400 957254885Sdumbbell/* rs6xx/rs740/r6xx */ 958254885Sdumbbell# define HDMI0_ENABLE (1 << 0) 959254885Sdumbbell# define HDMI0_STREAM(x) (((x) & 3) << 2) 960254885Sdumbbell# define HDMI0_STREAM_TMDSA 0 961254885Sdumbbell# define HDMI0_STREAM_LVTMA 1 962254885Sdumbbell# define HDMI0_STREAM_DVOA 2 963254885Sdumbbell# define HDMI0_STREAM_DDIA 3 964254885Sdumbbell/* rs6xx/r6xx/dce3 */ 965254885Sdumbbell# define HDMI0_ERROR_ACK (1 << 8) 966254885Sdumbbell# define HDMI0_ERROR_MASK (1 << 9) 967254885Sdumbbell#define HDMI0_STATUS 0x7404 968254885Sdumbbell# define HDMI0_ACTIVE_AVMUTE (1 << 0) 969254885Sdumbbell# define HDMI0_AUDIO_ENABLE (1 << 4) 970254885Sdumbbell# define HDMI0_AZ_FORMAT_WTRIG (1 << 28) 971254885Sdumbbell# define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29) 972254885Sdumbbell#define HDMI0_AUDIO_PACKET_CONTROL 0x7408 973254885Sdumbbell# define HDMI0_AUDIO_SAMPLE_SEND (1 << 0) 974254885Sdumbbell# define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 975254885Sdumbbell# define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8) 976254885Sdumbbell# define HDMI0_AUDIO_TEST_EN (1 << 12) 977254885Sdumbbell# define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 978254885Sdumbbell# define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24) 979254885Sdumbbell# define HDMI0_60958_CS_UPDATE (1 << 26) 980254885Sdumbbell# define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28) 981254885Sdumbbell# define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) 982254885Sdumbbell#define HDMI0_AUDIO_CRC_CONTROL 0x740c 983254885Sdumbbell# define HDMI0_AUDIO_CRC_EN (1 << 0) 984254885Sdumbbell#define HDMI0_VBI_PACKET_CONTROL 0x7410 985254885Sdumbbell# define HDMI0_NULL_SEND (1 << 0) 986254885Sdumbbell# define HDMI0_GC_SEND (1 << 4) 987254885Sdumbbell# define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 988254885Sdumbbell#define HDMI0_INFOFRAME_CONTROL0 0x7414 989254885Sdumbbell# define HDMI0_AVI_INFO_SEND (1 << 0) 990254885Sdumbbell# define HDMI0_AVI_INFO_CONT (1 << 1) 991254885Sdumbbell# define HDMI0_AUDIO_INFO_SEND (1 << 4) 992254885Sdumbbell# define HDMI0_AUDIO_INFO_CONT (1 << 5) 993254885Sdumbbell# define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */ 994254885Sdumbbell# define HDMI0_AUDIO_INFO_UPDATE (1 << 7) 995254885Sdumbbell# define HDMI0_MPEG_INFO_SEND (1 << 8) 996254885Sdumbbell# define HDMI0_MPEG_INFO_CONT (1 << 9) 997254885Sdumbbell# define HDMI0_MPEG_INFO_UPDATE (1 << 10) 998254885Sdumbbell#define HDMI0_INFOFRAME_CONTROL1 0x7418 999254885Sdumbbell# define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 1000254885Sdumbbell# define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 1001254885Sdumbbell# define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 1002254885Sdumbbell#define HDMI0_GENERIC_PACKET_CONTROL 0x741c 1003254885Sdumbbell# define HDMI0_GENERIC0_SEND (1 << 0) 1004254885Sdumbbell# define HDMI0_GENERIC0_CONT (1 << 1) 1005254885Sdumbbell# define HDMI0_GENERIC0_UPDATE (1 << 2) 1006254885Sdumbbell# define HDMI0_GENERIC1_SEND (1 << 4) 1007254885Sdumbbell# define HDMI0_GENERIC1_CONT (1 << 5) 1008254885Sdumbbell# define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 1009254885Sdumbbell# define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 1010254885Sdumbbell#define HDMI0_GC 0x7428 1011254885Sdumbbell# define HDMI0_GC_AVMUTE (1 << 0) 1012254885Sdumbbell#define HDMI0_AVI_INFO0 0x7454 1013254885Sdumbbell# define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1014254885Sdumbbell# define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8) 1015254885Sdumbbell# define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10) 1016254885Sdumbbell# define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12) 1017254885Sdumbbell# define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13) 1018254885Sdumbbell# define HDMI0_AVI_INFO_Y_RGB 0 1019254885Sdumbbell# define HDMI0_AVI_INFO_Y_YCBCR422 1 1020254885Sdumbbell# define HDMI0_AVI_INFO_Y_YCBCR444 2 1021254885Sdumbbell# define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 1022254885Sdumbbell# define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16) 1023254885Sdumbbell# define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20) 1024254885Sdumbbell# define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22) 1025254885Sdumbbell# define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 1026254885Sdumbbell# define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24) 1027254885Sdumbbell# define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 1028254885Sdumbbell#define HDMI0_AVI_INFO1 0x7458 1029254885Sdumbbell# define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 1030254885Sdumbbell# define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 1031254885Sdumbbell# define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 1032254885Sdumbbell#define HDMI0_AVI_INFO2 0x745c 1033254885Sdumbbell# define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 1034254885Sdumbbell# define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 1035254885Sdumbbell#define HDMI0_AVI_INFO3 0x7460 1036254885Sdumbbell# define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 1037254885Sdumbbell# define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24) 1038254885Sdumbbell#define HDMI0_MPEG_INFO0 0x7464 1039254885Sdumbbell# define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1040254885Sdumbbell# define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 1041254885Sdumbbell# define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 1042254885Sdumbbell# define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 1043254885Sdumbbell#define HDMI0_MPEG_INFO1 0x7468 1044254885Sdumbbell# define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 1045254885Sdumbbell# define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8) 1046254885Sdumbbell# define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12) 1047254885Sdumbbell#define HDMI0_GENERIC0_HDR 0x746c 1048254885Sdumbbell#define HDMI0_GENERIC0_0 0x7470 1049254885Sdumbbell#define HDMI0_GENERIC0_1 0x7474 1050254885Sdumbbell#define HDMI0_GENERIC0_2 0x7478 1051254885Sdumbbell#define HDMI0_GENERIC0_3 0x747c 1052254885Sdumbbell#define HDMI0_GENERIC0_4 0x7480 1053254885Sdumbbell#define HDMI0_GENERIC0_5 0x7484 1054254885Sdumbbell#define HDMI0_GENERIC0_6 0x7488 1055254885Sdumbbell#define HDMI0_GENERIC1_HDR 0x748c 1056254885Sdumbbell#define HDMI0_GENERIC1_0 0x7490 1057254885Sdumbbell#define HDMI0_GENERIC1_1 0x7494 1058254885Sdumbbell#define HDMI0_GENERIC1_2 0x7498 1059254885Sdumbbell#define HDMI0_GENERIC1_3 0x749c 1060254885Sdumbbell#define HDMI0_GENERIC1_4 0x74a0 1061254885Sdumbbell#define HDMI0_GENERIC1_5 0x74a4 1062254885Sdumbbell#define HDMI0_GENERIC1_6 0x74a8 1063254885Sdumbbell#define HDMI0_ACR_32_0 0x74ac 1064254885Sdumbbell# define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 1065254885Sdumbbell#define HDMI0_ACR_32_1 0x74b0 1066254885Sdumbbell# define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0) 1067254885Sdumbbell#define HDMI0_ACR_44_0 0x74b4 1068254885Sdumbbell# define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 1069254885Sdumbbell#define HDMI0_ACR_44_1 0x74b8 1070254885Sdumbbell# define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0) 1071254885Sdumbbell#define HDMI0_ACR_48_0 0x74bc 1072254885Sdumbbell# define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 1073254885Sdumbbell#define HDMI0_ACR_48_1 0x74c0 1074254885Sdumbbell# define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0) 1075254885Sdumbbell#define HDMI0_ACR_STATUS_0 0x74c4 1076254885Sdumbbell#define HDMI0_ACR_STATUS_1 0x74c8 1077254885Sdumbbell#define HDMI0_AUDIO_INFO0 0x74cc 1078254885Sdumbbell# define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1079254885Sdumbbell# define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8) 1080254885Sdumbbell#define HDMI0_AUDIO_INFO1 0x74d0 1081254885Sdumbbell# define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 1082254885Sdumbbell# define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 1083254885Sdumbbell# define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 1084254885Sdumbbell# define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 1085254885Sdumbbell#define HDMI0_60958_0 0x74d4 1086254885Sdumbbell# define HDMI0_60958_CS_A(x) (((x) & 1) << 0) 1087254885Sdumbbell# define HDMI0_60958_CS_B(x) (((x) & 1) << 1) 1088254885Sdumbbell# define HDMI0_60958_CS_C(x) (((x) & 1) << 2) 1089254885Sdumbbell# define HDMI0_60958_CS_D(x) (((x) & 3) << 3) 1090254885Sdumbbell# define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6) 1091254885Sdumbbell# define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 1092254885Sdumbbell# define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 1093254885Sdumbbell# define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 1094254885Sdumbbell# define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 1095254885Sdumbbell# define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 1096254885Sdumbbell#define HDMI0_60958_1 0x74d8 1097254885Sdumbbell# define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 1098254885Sdumbbell# define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 1099254885Sdumbbell# define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16) 1100254885Sdumbbell# define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18) 1101254885Sdumbbell# define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 1102254885Sdumbbell#define HDMI0_ACR_PACKET_CONTROL 0x74dc 1103254885Sdumbbell# define HDMI0_ACR_SEND (1 << 0) 1104254885Sdumbbell# define HDMI0_ACR_CONT (1 << 1) 1105254885Sdumbbell# define HDMI0_ACR_SELECT(x) (((x) & 3) << 4) 1106254885Sdumbbell# define HDMI0_ACR_HW 0 1107254885Sdumbbell# define HDMI0_ACR_32 1 1108254885Sdumbbell# define HDMI0_ACR_44 2 1109254885Sdumbbell# define HDMI0_ACR_48 3 1110254885Sdumbbell# define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 1111254885Sdumbbell# define HDMI0_ACR_AUTO_SEND (1 << 12) 1112254885Sdumbbell#define HDMI0_RAMP_CONTROL0 0x74e0 1113254885Sdumbbell# define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 1114254885Sdumbbell#define HDMI0_RAMP_CONTROL1 0x74e4 1115254885Sdumbbell# define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 1116254885Sdumbbell#define HDMI0_RAMP_CONTROL2 0x74e8 1117254885Sdumbbell# define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 1118254885Sdumbbell#define HDMI0_RAMP_CONTROL3 0x74ec 1119254885Sdumbbell# define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 1120254885Sdumbbell/* HDMI0_60958_2 is r7xx only */ 1121254885Sdumbbell#define HDMI0_60958_2 0x74f0 1122254885Sdumbbell# define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 1123254885Sdumbbell# define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 1124254885Sdumbbell# define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 1125254885Sdumbbell# define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 1126254885Sdumbbell# define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 1127254885Sdumbbell# define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 1128254885Sdumbbell/* r6xx only; second instance starts at 0x7700 */ 1129254885Sdumbbell#define HDMI1_CONTROL 0x7700 1130254885Sdumbbell#define HDMI1_STATUS 0x7704 1131254885Sdumbbell#define HDMI1_AUDIO_PACKET_CONTROL 0x7708 1132254885Sdumbbell/* DCE3; second instance starts at 0x7800 NOT 0x7700 */ 1133254885Sdumbbell#define DCE3_HDMI1_CONTROL 0x7800 1134254885Sdumbbell#define DCE3_HDMI1_STATUS 0x7804 1135254885Sdumbbell#define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808 1136254885Sdumbbell/* DCE3.2 (for interrupts) */ 1137254885Sdumbbell#define AFMT_STATUS 0x7600 1138254885Sdumbbell# define AFMT_AUDIO_ENABLE (1 << 4) 1139254885Sdumbbell# define AFMT_AZ_FORMAT_WTRIG (1 << 28) 1140254885Sdumbbell# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 1141254885Sdumbbell# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 1142254885Sdumbbell#define AFMT_AUDIO_PACKET_CONTROL 0x7604 1143254885Sdumbbell# define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 1144254885Sdumbbell# define AFMT_AUDIO_TEST_EN (1 << 12) 1145254885Sdumbbell# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 1146254885Sdumbbell# define AFMT_60958_CS_UPDATE (1 << 26) 1147254885Sdumbbell# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 1148254885Sdumbbell# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 1149254885Sdumbbell# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 1150254885Sdumbbell# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 1151254885Sdumbbell 1152254885Sdumbbell/* 1153254885Sdumbbell * PM4 1154254885Sdumbbell */ 1155254885Sdumbbell#define PACKET_TYPE0 0 1156254885Sdumbbell#define PACKET_TYPE1 1 1157254885Sdumbbell#define PACKET_TYPE2 2 1158254885Sdumbbell#define PACKET_TYPE3 3 1159254885Sdumbbell 1160254885Sdumbbell#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 1161254885Sdumbbell#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 1162254885Sdumbbell#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 1163254885Sdumbbell#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 1164254885Sdumbbell#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 1165254885Sdumbbell (((reg) >> 2) & 0xFFFF) | \ 1166254885Sdumbbell ((n) & 0x3FFF) << 16) 1167254885Sdumbbell#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1168254885Sdumbbell (((op) & 0xFF) << 8) | \ 1169254885Sdumbbell ((n) & 0x3FFF) << 16) 1170254885Sdumbbell 1171254885Sdumbbell/* Packet 3 types */ 1172254885Sdumbbell#define PACKET3_NOP 0x10 1173254885Sdumbbell#define PACKET3_INDIRECT_BUFFER_END 0x17 1174254885Sdumbbell#define PACKET3_SET_PREDICATION 0x20 1175254885Sdumbbell#define PACKET3_REG_RMW 0x21 1176254885Sdumbbell#define PACKET3_COND_EXEC 0x22 1177254885Sdumbbell#define PACKET3_PRED_EXEC 0x23 1178254885Sdumbbell#define PACKET3_START_3D_CMDBUF 0x24 1179254885Sdumbbell#define PACKET3_DRAW_INDEX_2 0x27 1180254885Sdumbbell#define PACKET3_CONTEXT_CONTROL 0x28 1181254885Sdumbbell#define PACKET3_DRAW_INDEX_IMMD_BE 0x29 1182254885Sdumbbell#define PACKET3_INDEX_TYPE 0x2A 1183254885Sdumbbell#define PACKET3_DRAW_INDEX 0x2B 1184254885Sdumbbell#define PACKET3_DRAW_INDEX_AUTO 0x2D 1185254885Sdumbbell#define PACKET3_DRAW_INDEX_IMMD 0x2E 1186254885Sdumbbell#define PACKET3_NUM_INSTANCES 0x2F 1187254885Sdumbbell#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1188254885Sdumbbell#define PACKET3_INDIRECT_BUFFER_MP 0x38 1189254885Sdumbbell#define PACKET3_MEM_SEMAPHORE 0x39 1190254885Sdumbbell# define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 1191254885Sdumbbell# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 1192254885Sdumbbell# define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1193254885Sdumbbell#define PACKET3_MPEG_INDEX 0x3A 1194254885Sdumbbell#define PACKET3_COPY_DW 0x3B 1195254885Sdumbbell#define PACKET3_WAIT_REG_MEM 0x3C 1196254885Sdumbbell#define PACKET3_MEM_WRITE 0x3D 1197254885Sdumbbell#define PACKET3_INDIRECT_BUFFER 0x32 1198254885Sdumbbell#define PACKET3_CP_DMA 0x41 1199254885Sdumbbell/* 1. header 1200254885Sdumbbell * 2. SRC_ADDR_LO [31:0] 1201254885Sdumbbell * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0] 1202254885Sdumbbell * 4. DST_ADDR_LO [31:0] 1203254885Sdumbbell * 5. DST_ADDR_HI [7:0] 1204254885Sdumbbell * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1205254885Sdumbbell */ 1206261455Seadler# define PACKET3_CP_DMA_CP_SYNC (1U << 31) 1207254885Sdumbbell/* COMMAND */ 1208254885Sdumbbell# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1209254885Sdumbbell /* 0 - none 1210254885Sdumbbell * 1 - 8 in 16 1211254885Sdumbbell * 2 - 8 in 32 1212254885Sdumbbell * 3 - 8 in 64 1213254885Sdumbbell */ 1214254885Sdumbbell# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1215254885Sdumbbell /* 0 - none 1216254885Sdumbbell * 1 - 8 in 16 1217254885Sdumbbell * 2 - 8 in 32 1218254885Sdumbbell * 3 - 8 in 64 1219254885Sdumbbell */ 1220254885Sdumbbell# define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1221254885Sdumbbell /* 0 - memory 1222254885Sdumbbell * 1 - register 1223254885Sdumbbell */ 1224254885Sdumbbell# define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1225254885Sdumbbell /* 0 - memory 1226254885Sdumbbell * 1 - register 1227254885Sdumbbell */ 1228254885Sdumbbell# define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1229254885Sdumbbell# define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1230254885Sdumbbell#define PACKET3_SURFACE_SYNC 0x43 1231254885Sdumbbell# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1232254885Sdumbbell# define PACKET3_TC_ACTION_ENA (1 << 23) 1233254885Sdumbbell# define PACKET3_VC_ACTION_ENA (1 << 24) 1234254885Sdumbbell# define PACKET3_CB_ACTION_ENA (1 << 25) 1235254885Sdumbbell# define PACKET3_DB_ACTION_ENA (1 << 26) 1236254885Sdumbbell# define PACKET3_SH_ACTION_ENA (1 << 27) 1237254885Sdumbbell# define PACKET3_SMX_ACTION_ENA (1 << 28) 1238254885Sdumbbell#define PACKET3_ME_INITIALIZE 0x44 1239254885Sdumbbell#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1240254885Sdumbbell#define PACKET3_COND_WRITE 0x45 1241254885Sdumbbell#define PACKET3_EVENT_WRITE 0x46 1242254885Sdumbbell#define EVENT_TYPE(x) ((x) << 0) 1243254885Sdumbbell#define EVENT_INDEX(x) ((x) << 8) 1244254885Sdumbbell /* 0 - any non-TS event 1245254885Sdumbbell * 1 - ZPASS_DONE 1246254885Sdumbbell * 2 - SAMPLE_PIPELINESTAT 1247254885Sdumbbell * 3 - SAMPLE_STREAMOUTSTAT* 1248254885Sdumbbell * 4 - *S_PARTIAL_FLUSH 1249254885Sdumbbell * 5 - TS events 1250254885Sdumbbell */ 1251254885Sdumbbell#define PACKET3_EVENT_WRITE_EOP 0x47 1252254885Sdumbbell#define DATA_SEL(x) ((x) << 29) 1253254885Sdumbbell /* 0 - discard 1254254885Sdumbbell * 1 - send low 32bit data 1255254885Sdumbbell * 2 - send 64bit data 1256254885Sdumbbell * 3 - send 64bit counter value 1257254885Sdumbbell */ 1258254885Sdumbbell#define INT_SEL(x) ((x) << 24) 1259254885Sdumbbell /* 0 - none 1260254885Sdumbbell * 1 - interrupt only (DATA_SEL = 0) 1261254885Sdumbbell * 2 - interrupt when data write is confirmed 1262254885Sdumbbell */ 1263254885Sdumbbell#define PACKET3_ONE_REG_WRITE 0x57 1264254885Sdumbbell#define PACKET3_SET_CONFIG_REG 0x68 1265254885Sdumbbell#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 1266254885Sdumbbell#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1267254885Sdumbbell#define PACKET3_SET_CONTEXT_REG 0x69 1268254885Sdumbbell#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 1269254885Sdumbbell#define PACKET3_SET_CONTEXT_REG_END 0x00029000 1270254885Sdumbbell#define PACKET3_SET_ALU_CONST 0x6A 1271254885Sdumbbell#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 1272254885Sdumbbell#define PACKET3_SET_ALU_CONST_END 0x00032000 1273254885Sdumbbell#define PACKET3_SET_BOOL_CONST 0x6B 1274254885Sdumbbell#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 1275254885Sdumbbell#define PACKET3_SET_BOOL_CONST_END 0x00040000 1276254885Sdumbbell#define PACKET3_SET_LOOP_CONST 0x6C 1277254885Sdumbbell#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 1278254885Sdumbbell#define PACKET3_SET_LOOP_CONST_END 0x0003e380 1279254885Sdumbbell#define PACKET3_SET_RESOURCE 0x6D 1280254885Sdumbbell#define PACKET3_SET_RESOURCE_OFFSET 0x00038000 1281254885Sdumbbell#define PACKET3_SET_RESOURCE_END 0x0003c000 1282254885Sdumbbell#define PACKET3_SET_SAMPLER 0x6E 1283254885Sdumbbell#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 1284254885Sdumbbell#define PACKET3_SET_SAMPLER_END 0x0003cff0 1285254885Sdumbbell#define PACKET3_SET_CTL_CONST 0x6F 1286254885Sdumbbell#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 1287254885Sdumbbell#define PACKET3_SET_CTL_CONST_END 0x0003e200 1288254885Sdumbbell#define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */ 1289254885Sdumbbell#define PACKET3_SURFACE_BASE_UPDATE 0x73 1290254885Sdumbbell 1291254885Sdumbbell 1292254885Sdumbbell#define R_008020_GRBM_SOFT_RESET 0x8020 1293254885Sdumbbell#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) 1294254885Sdumbbell#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) 1295254885Sdumbbell#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) 1296254885Sdumbbell#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) 1297254885Sdumbbell#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) 1298254885Sdumbbell#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) 1299254885Sdumbbell#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) 1300254885Sdumbbell#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) 1301254885Sdumbbell#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) 1302254885Sdumbbell#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) 1303254885Sdumbbell#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) 1304254885Sdumbbell#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) 1305254885Sdumbbell#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) 1306254885Sdumbbell#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) 1307254885Sdumbbell#define R_008010_GRBM_STATUS 0x8010 1308254885Sdumbbell#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) 1309254885Sdumbbell#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) 1310254885Sdumbbell#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) 1311254885Sdumbbell#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) 1312254885Sdumbbell#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) 1313254885Sdumbbell#define S_008010_VC_BUSY(x) (((x) & 1) << 11) 1314254885Sdumbbell#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) 1315254885Sdumbbell#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) 1316254885Sdumbbell#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) 1317254885Sdumbbell#define S_008010_VGT_BUSY(x) (((x) & 1) << 17) 1318254885Sdumbbell#define S_008010_TA03_BUSY(x) (((x) & 1) << 18) 1319254885Sdumbbell#define S_008010_TC_BUSY(x) (((x) & 1) << 19) 1320254885Sdumbbell#define S_008010_SX_BUSY(x) (((x) & 1) << 20) 1321254885Sdumbbell#define S_008010_SH_BUSY(x) (((x) & 1) << 21) 1322254885Sdumbbell#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) 1323254885Sdumbbell#define S_008010_SMX_BUSY(x) (((x) & 1) << 23) 1324254885Sdumbbell#define S_008010_SC_BUSY(x) (((x) & 1) << 24) 1325254885Sdumbbell#define S_008010_PA_BUSY(x) (((x) & 1) << 25) 1326254885Sdumbbell#define S_008010_DB03_BUSY(x) (((x) & 1) << 26) 1327254885Sdumbbell#define S_008010_CR_BUSY(x) (((x) & 1) << 27) 1328254885Sdumbbell#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) 1329254885Sdumbbell#define S_008010_CP_BUSY(x) (((x) & 1) << 29) 1330254885Sdumbbell#define S_008010_CB03_BUSY(x) (((x) & 1) << 30) 1331254885Sdumbbell#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) 1332254885Sdumbbell#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) 1333254885Sdumbbell#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) 1334254885Sdumbbell#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) 1335254885Sdumbbell#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) 1336254885Sdumbbell#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) 1337254885Sdumbbell#define G_008010_VC_BUSY(x) (((x) >> 11) & 1) 1338254885Sdumbbell#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) 1339254885Sdumbbell#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) 1340254885Sdumbbell#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) 1341254885Sdumbbell#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) 1342254885Sdumbbell#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) 1343254885Sdumbbell#define G_008010_TC_BUSY(x) (((x) >> 19) & 1) 1344254885Sdumbbell#define G_008010_SX_BUSY(x) (((x) >> 20) & 1) 1345254885Sdumbbell#define G_008010_SH_BUSY(x) (((x) >> 21) & 1) 1346254885Sdumbbell#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) 1347254885Sdumbbell#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) 1348254885Sdumbbell#define G_008010_SC_BUSY(x) (((x) >> 24) & 1) 1349254885Sdumbbell#define G_008010_PA_BUSY(x) (((x) >> 25) & 1) 1350254885Sdumbbell#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) 1351254885Sdumbbell#define G_008010_CR_BUSY(x) (((x) >> 27) & 1) 1352254885Sdumbbell#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) 1353254885Sdumbbell#define G_008010_CP_BUSY(x) (((x) >> 29) & 1) 1354254885Sdumbbell#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) 1355254885Sdumbbell#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) 1356254885Sdumbbell#define R_008014_GRBM_STATUS2 0x8014 1357254885Sdumbbell#define S_008014_CR_CLEAN(x) (((x) & 1) << 0) 1358254885Sdumbbell#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) 1359254885Sdumbbell#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) 1360254885Sdumbbell#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) 1361254885Sdumbbell#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) 1362254885Sdumbbell#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) 1363254885Sdumbbell#define S_008014_TA0_BUSY(x) (((x) & 1) << 12) 1364254885Sdumbbell#define S_008014_TA1_BUSY(x) (((x) & 1) << 13) 1365254885Sdumbbell#define S_008014_TA2_BUSY(x) (((x) & 1) << 14) 1366254885Sdumbbell#define S_008014_TA3_BUSY(x) (((x) & 1) << 15) 1367254885Sdumbbell#define S_008014_DB0_BUSY(x) (((x) & 1) << 16) 1368254885Sdumbbell#define S_008014_DB1_BUSY(x) (((x) & 1) << 17) 1369254885Sdumbbell#define S_008014_DB2_BUSY(x) (((x) & 1) << 18) 1370254885Sdumbbell#define S_008014_DB3_BUSY(x) (((x) & 1) << 19) 1371254885Sdumbbell#define S_008014_CB0_BUSY(x) (((x) & 1) << 20) 1372254885Sdumbbell#define S_008014_CB1_BUSY(x) (((x) & 1) << 21) 1373254885Sdumbbell#define S_008014_CB2_BUSY(x) (((x) & 1) << 22) 1374254885Sdumbbell#define S_008014_CB3_BUSY(x) (((x) & 1) << 23) 1375254885Sdumbbell#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) 1376254885Sdumbbell#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) 1377254885Sdumbbell#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) 1378254885Sdumbbell#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) 1379254885Sdumbbell#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) 1380254885Sdumbbell#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) 1381254885Sdumbbell#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) 1382254885Sdumbbell#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) 1383254885Sdumbbell#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) 1384254885Sdumbbell#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) 1385254885Sdumbbell#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) 1386254885Sdumbbell#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) 1387254885Sdumbbell#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) 1388254885Sdumbbell#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) 1389254885Sdumbbell#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) 1390254885Sdumbbell#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) 1391254885Sdumbbell#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) 1392254885Sdumbbell#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) 1393254885Sdumbbell#define R_000E50_SRBM_STATUS 0x0E50 1394254885Sdumbbell#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) 1395254885Sdumbbell#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) 1396254885Sdumbbell#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) 1397254885Sdumbbell#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) 1398254885Sdumbbell#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) 1399254885Sdumbbell#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) 1400254885Sdumbbell#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) 1401254885Sdumbbell#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) 1402254885Sdumbbell#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) 1403254885Sdumbbell#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) 1404254885Sdumbbell#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) 1405254885Sdumbbell#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) 1406254885Sdumbbell#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) 1407254885Sdumbbell#define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) 1408254885Sdumbbell#define R_000E60_SRBM_SOFT_RESET 0x0E60 1409254885Sdumbbell#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) 1410254885Sdumbbell#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) 1411254885Sdumbbell#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) 1412254885Sdumbbell#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) 1413254885Sdumbbell#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) 1414254885Sdumbbell#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) 1415254885Sdumbbell#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) 1416254885Sdumbbell#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) 1417254885Sdumbbell#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) 1418254885Sdumbbell#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) 1419254885Sdumbbell#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) 1420254885Sdumbbell#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) 1421254885Sdumbbell#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) 1422254885Sdumbbell#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 1423254885Sdumbbell 1424254885Sdumbbell#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 1425254885Sdumbbell 1426254885Sdumbbell#define R_028C04_PA_SC_AA_CONFIG 0x028C04 1427254885Sdumbbell#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) 1428254885Sdumbbell#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) 1429254885Sdumbbell#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC 1430254885Sdumbbell#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) 1431254885Sdumbbell#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) 1432254885Sdumbbell#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF 1433254885Sdumbbell#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) 1434254885Sdumbbell#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) 1435254885Sdumbbell#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF 1436254885Sdumbbell#define R_0280E0_CB_COLOR0_FRAG 0x0280E0 1437254885Sdumbbell#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1438254885Sdumbbell#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1439254885Sdumbbell#define C_0280E0_BASE_256B 0x00000000 1440254885Sdumbbell#define R_0280E4_CB_COLOR1_FRAG 0x0280E4 1441254885Sdumbbell#define R_0280E8_CB_COLOR2_FRAG 0x0280E8 1442254885Sdumbbell#define R_0280EC_CB_COLOR3_FRAG 0x0280EC 1443254885Sdumbbell#define R_0280F0_CB_COLOR4_FRAG 0x0280F0 1444254885Sdumbbell#define R_0280F4_CB_COLOR5_FRAG 0x0280F4 1445254885Sdumbbell#define R_0280F8_CB_COLOR6_FRAG 0x0280F8 1446254885Sdumbbell#define R_0280FC_CB_COLOR7_FRAG 0x0280FC 1447254885Sdumbbell#define R_0280C0_CB_COLOR0_TILE 0x0280C0 1448254885Sdumbbell#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1449254885Sdumbbell#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1450254885Sdumbbell#define C_0280C0_BASE_256B 0x00000000 1451254885Sdumbbell#define R_0280C4_CB_COLOR1_TILE 0x0280C4 1452254885Sdumbbell#define R_0280C8_CB_COLOR2_TILE 0x0280C8 1453254885Sdumbbell#define R_0280CC_CB_COLOR3_TILE 0x0280CC 1454254885Sdumbbell#define R_0280D0_CB_COLOR4_TILE 0x0280D0 1455254885Sdumbbell#define R_0280D4_CB_COLOR5_TILE 0x0280D4 1456254885Sdumbbell#define R_0280D8_CB_COLOR6_TILE 0x0280D8 1457254885Sdumbbell#define R_0280DC_CB_COLOR7_TILE 0x0280DC 1458254885Sdumbbell#define R_0280A0_CB_COLOR0_INFO 0x0280A0 1459254885Sdumbbell#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) 1460254885Sdumbbell#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) 1461254885Sdumbbell#define C_0280A0_ENDIAN 0xFFFFFFFC 1462254885Sdumbbell#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) 1463254885Sdumbbell#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) 1464254885Sdumbbell#define C_0280A0_FORMAT 0xFFFFFF03 1465254885Sdumbbell#define V_0280A0_COLOR_INVALID 0x00000000 1466254885Sdumbbell#define V_0280A0_COLOR_8 0x00000001 1467254885Sdumbbell#define V_0280A0_COLOR_4_4 0x00000002 1468254885Sdumbbell#define V_0280A0_COLOR_3_3_2 0x00000003 1469254885Sdumbbell#define V_0280A0_COLOR_16 0x00000005 1470254885Sdumbbell#define V_0280A0_COLOR_16_FLOAT 0x00000006 1471254885Sdumbbell#define V_0280A0_COLOR_8_8 0x00000007 1472254885Sdumbbell#define V_0280A0_COLOR_5_6_5 0x00000008 1473254885Sdumbbell#define V_0280A0_COLOR_6_5_5 0x00000009 1474254885Sdumbbell#define V_0280A0_COLOR_1_5_5_5 0x0000000A 1475254885Sdumbbell#define V_0280A0_COLOR_4_4_4_4 0x0000000B 1476254885Sdumbbell#define V_0280A0_COLOR_5_5_5_1 0x0000000C 1477254885Sdumbbell#define V_0280A0_COLOR_32 0x0000000D 1478254885Sdumbbell#define V_0280A0_COLOR_32_FLOAT 0x0000000E 1479254885Sdumbbell#define V_0280A0_COLOR_16_16 0x0000000F 1480254885Sdumbbell#define V_0280A0_COLOR_16_16_FLOAT 0x00000010 1481254885Sdumbbell#define V_0280A0_COLOR_8_24 0x00000011 1482254885Sdumbbell#define V_0280A0_COLOR_8_24_FLOAT 0x00000012 1483254885Sdumbbell#define V_0280A0_COLOR_24_8 0x00000013 1484254885Sdumbbell#define V_0280A0_COLOR_24_8_FLOAT 0x00000014 1485254885Sdumbbell#define V_0280A0_COLOR_10_11_11 0x00000015 1486254885Sdumbbell#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 1487254885Sdumbbell#define V_0280A0_COLOR_11_11_10 0x00000017 1488254885Sdumbbell#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 1489254885Sdumbbell#define V_0280A0_COLOR_2_10_10_10 0x00000019 1490254885Sdumbbell#define V_0280A0_COLOR_8_8_8_8 0x0000001A 1491254885Sdumbbell#define V_0280A0_COLOR_10_10_10_2 0x0000001B 1492254885Sdumbbell#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C 1493254885Sdumbbell#define V_0280A0_COLOR_32_32 0x0000001D 1494254885Sdumbbell#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E 1495254885Sdumbbell#define V_0280A0_COLOR_16_16_16_16 0x0000001F 1496254885Sdumbbell#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 1497254885Sdumbbell#define V_0280A0_COLOR_32_32_32_32 0x00000022 1498254885Sdumbbell#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 1499254885Sdumbbell#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) 1500254885Sdumbbell#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1501254885Sdumbbell#define C_0280A0_ARRAY_MODE 0xFFFFF0FF 1502254885Sdumbbell#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 1503254885Sdumbbell#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 1504254885Sdumbbell#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 1505254885Sdumbbell#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 1506254885Sdumbbell#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1507254885Sdumbbell#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1508254885Sdumbbell#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF 1509254885Sdumbbell#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) 1510254885Sdumbbell#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) 1511254885Sdumbbell#define C_0280A0_READ_SIZE 0xFFFF7FFF 1512254885Sdumbbell#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) 1513254885Sdumbbell#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) 1514254885Sdumbbell#define C_0280A0_COMP_SWAP 0xFFFCFFFF 1515254885Sdumbbell#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1516254885Sdumbbell#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1517254885Sdumbbell#define C_0280A0_TILE_MODE 0xFFF3FFFF 1518254885Sdumbbell#define V_0280A0_TILE_DISABLE 0 1519254885Sdumbbell#define V_0280A0_CLEAR_ENABLE 1 1520254885Sdumbbell#define V_0280A0_FRAG_ENABLE 2 1521254885Sdumbbell#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1522254885Sdumbbell#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1523254885Sdumbbell#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1524254885Sdumbbell#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) 1525254885Sdumbbell#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) 1526254885Sdumbbell#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF 1527254885Sdumbbell#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) 1528254885Sdumbbell#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) 1529254885Sdumbbell#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF 1530254885Sdumbbell#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) 1531254885Sdumbbell#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) 1532254885Sdumbbell#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF 1533254885Sdumbbell#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) 1534254885Sdumbbell#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) 1535254885Sdumbbell#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF 1536254885Sdumbbell#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) 1537254885Sdumbbell#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) 1538254885Sdumbbell#define C_0280A0_ROUND_MODE 0xFDFFFFFF 1539254885Sdumbbell#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) 1540254885Sdumbbell#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1541254885Sdumbbell#define C_0280A0_TILE_COMPACT 0xFBFFFFFF 1542254885Sdumbbell#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) 1543254885Sdumbbell#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) 1544254885Sdumbbell#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF 1545254885Sdumbbell#define R_0280A4_CB_COLOR1_INFO 0x0280A4 1546254885Sdumbbell#define R_0280A8_CB_COLOR2_INFO 0x0280A8 1547254885Sdumbbell#define R_0280AC_CB_COLOR3_INFO 0x0280AC 1548254885Sdumbbell#define R_0280B0_CB_COLOR4_INFO 0x0280B0 1549254885Sdumbbell#define R_0280B4_CB_COLOR5_INFO 0x0280B4 1550254885Sdumbbell#define R_0280B8_CB_COLOR6_INFO 0x0280B8 1551254885Sdumbbell#define R_0280BC_CB_COLOR7_INFO 0x0280BC 1552254885Sdumbbell#define R_028060_CB_COLOR0_SIZE 0x028060 1553254885Sdumbbell#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1554254885Sdumbbell#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1555254885Sdumbbell#define C_028060_PITCH_TILE_MAX 0xFFFFFC00 1556254885Sdumbbell#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1557254885Sdumbbell#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1558254885Sdumbbell#define C_028060_SLICE_TILE_MAX 0xC00003FF 1559254885Sdumbbell#define R_028064_CB_COLOR1_SIZE 0x028064 1560254885Sdumbbell#define R_028068_CB_COLOR2_SIZE 0x028068 1561254885Sdumbbell#define R_02806C_CB_COLOR3_SIZE 0x02806C 1562254885Sdumbbell#define R_028070_CB_COLOR4_SIZE 0x028070 1563254885Sdumbbell#define R_028074_CB_COLOR5_SIZE 0x028074 1564254885Sdumbbell#define R_028078_CB_COLOR6_SIZE 0x028078 1565254885Sdumbbell#define R_02807C_CB_COLOR7_SIZE 0x02807C 1566254885Sdumbbell#define R_028238_CB_TARGET_MASK 0x028238 1567254885Sdumbbell#define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) 1568254885Sdumbbell#define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) 1569254885Sdumbbell#define C_028238_TARGET0_ENABLE 0xFFFFFFF0 1570254885Sdumbbell#define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) 1571254885Sdumbbell#define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) 1572254885Sdumbbell#define C_028238_TARGET1_ENABLE 0xFFFFFF0F 1573254885Sdumbbell#define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) 1574254885Sdumbbell#define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) 1575254885Sdumbbell#define C_028238_TARGET2_ENABLE 0xFFFFF0FF 1576254885Sdumbbell#define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) 1577254885Sdumbbell#define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) 1578254885Sdumbbell#define C_028238_TARGET3_ENABLE 0xFFFF0FFF 1579254885Sdumbbell#define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) 1580254885Sdumbbell#define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) 1581254885Sdumbbell#define C_028238_TARGET4_ENABLE 0xFFF0FFFF 1582254885Sdumbbell#define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) 1583254885Sdumbbell#define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) 1584254885Sdumbbell#define C_028238_TARGET5_ENABLE 0xFF0FFFFF 1585254885Sdumbbell#define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) 1586254885Sdumbbell#define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) 1587254885Sdumbbell#define C_028238_TARGET6_ENABLE 0xF0FFFFFF 1588254885Sdumbbell#define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) 1589254885Sdumbbell#define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) 1590254885Sdumbbell#define C_028238_TARGET7_ENABLE 0x0FFFFFFF 1591254885Sdumbbell#define R_02823C_CB_SHADER_MASK 0x02823C 1592254885Sdumbbell#define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) 1593254885Sdumbbell#define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) 1594254885Sdumbbell#define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 1595254885Sdumbbell#define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) 1596254885Sdumbbell#define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) 1597254885Sdumbbell#define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F 1598254885Sdumbbell#define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) 1599254885Sdumbbell#define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) 1600254885Sdumbbell#define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF 1601254885Sdumbbell#define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) 1602254885Sdumbbell#define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) 1603254885Sdumbbell#define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF 1604254885Sdumbbell#define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) 1605254885Sdumbbell#define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) 1606254885Sdumbbell#define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF 1607254885Sdumbbell#define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) 1608254885Sdumbbell#define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) 1609254885Sdumbbell#define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF 1610254885Sdumbbell#define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) 1611254885Sdumbbell#define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) 1612254885Sdumbbell#define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF 1613254885Sdumbbell#define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) 1614254885Sdumbbell#define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) 1615254885Sdumbbell#define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF 1616254885Sdumbbell#define R_028AB0_VGT_STRMOUT_EN 0x028AB0 1617254885Sdumbbell#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) 1618254885Sdumbbell#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) 1619254885Sdumbbell#define C_028AB0_STREAMOUT 0xFFFFFFFE 1620254885Sdumbbell#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 1621254885Sdumbbell#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) 1622254885Sdumbbell#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) 1623254885Sdumbbell#define C_028B20_BUFFER_0_EN 0xFFFFFFFE 1624254885Sdumbbell#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) 1625254885Sdumbbell#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) 1626254885Sdumbbell#define C_028B20_BUFFER_1_EN 0xFFFFFFFD 1627254885Sdumbbell#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) 1628254885Sdumbbell#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) 1629254885Sdumbbell#define C_028B20_BUFFER_2_EN 0xFFFFFFFB 1630254885Sdumbbell#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) 1631254885Sdumbbell#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) 1632254885Sdumbbell#define C_028B20_BUFFER_3_EN 0xFFFFFFF7 1633254885Sdumbbell#define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1634254885Sdumbbell#define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1635254885Sdumbbell#define C_028B20_SIZE 0x00000000 1636254885Sdumbbell#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 1637254885Sdumbbell#define S_038000_DIM(x) (((x) & 0x7) << 0) 1638254885Sdumbbell#define G_038000_DIM(x) (((x) >> 0) & 0x7) 1639254885Sdumbbell#define C_038000_DIM 0xFFFFFFF8 1640254885Sdumbbell#define V_038000_SQ_TEX_DIM_1D 0x00000000 1641254885Sdumbbell#define V_038000_SQ_TEX_DIM_2D 0x00000001 1642254885Sdumbbell#define V_038000_SQ_TEX_DIM_3D 0x00000002 1643254885Sdumbbell#define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 1644254885Sdumbbell#define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1645254885Sdumbbell#define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1646254885Sdumbbell#define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 1647254885Sdumbbell#define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1648254885Sdumbbell#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) 1649254885Sdumbbell#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) 1650254885Sdumbbell#define C_038000_TILE_MODE 0xFFFFFF87 1651254885Sdumbbell#define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 1652254885Sdumbbell#define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 1653254885Sdumbbell#define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 1654254885Sdumbbell#define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 1655254885Sdumbbell#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) 1656254885Sdumbbell#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) 1657254885Sdumbbell#define C_038000_TILE_TYPE 0xFFFFFF7F 1658254885Sdumbbell#define S_038000_PITCH(x) (((x) & 0x7FF) << 8) 1659254885Sdumbbell#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) 1660254885Sdumbbell#define C_038000_PITCH 0xFFF800FF 1661254885Sdumbbell#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) 1662254885Sdumbbell#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) 1663254885Sdumbbell#define C_038000_TEX_WIDTH 0x0007FFFF 1664254885Sdumbbell#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 1665254885Sdumbbell#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) 1666254885Sdumbbell#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) 1667254885Sdumbbell#define C_038004_TEX_HEIGHT 0xFFFFE000 1668254885Sdumbbell#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) 1669254885Sdumbbell#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) 1670254885Sdumbbell#define C_038004_TEX_DEPTH 0xFC001FFF 1671254885Sdumbbell#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) 1672254885Sdumbbell#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) 1673254885Sdumbbell#define C_038004_DATA_FORMAT 0x03FFFFFF 1674254885Sdumbbell#define V_038004_COLOR_INVALID 0x00000000 1675254885Sdumbbell#define V_038004_COLOR_8 0x00000001 1676254885Sdumbbell#define V_038004_COLOR_4_4 0x00000002 1677254885Sdumbbell#define V_038004_COLOR_3_3_2 0x00000003 1678254885Sdumbbell#define V_038004_COLOR_16 0x00000005 1679254885Sdumbbell#define V_038004_COLOR_16_FLOAT 0x00000006 1680254885Sdumbbell#define V_038004_COLOR_8_8 0x00000007 1681254885Sdumbbell#define V_038004_COLOR_5_6_5 0x00000008 1682254885Sdumbbell#define V_038004_COLOR_6_5_5 0x00000009 1683254885Sdumbbell#define V_038004_COLOR_1_5_5_5 0x0000000A 1684254885Sdumbbell#define V_038004_COLOR_4_4_4_4 0x0000000B 1685254885Sdumbbell#define V_038004_COLOR_5_5_5_1 0x0000000C 1686254885Sdumbbell#define V_038004_COLOR_32 0x0000000D 1687254885Sdumbbell#define V_038004_COLOR_32_FLOAT 0x0000000E 1688254885Sdumbbell#define V_038004_COLOR_16_16 0x0000000F 1689254885Sdumbbell#define V_038004_COLOR_16_16_FLOAT 0x00000010 1690254885Sdumbbell#define V_038004_COLOR_8_24 0x00000011 1691254885Sdumbbell#define V_038004_COLOR_8_24_FLOAT 0x00000012 1692254885Sdumbbell#define V_038004_COLOR_24_8 0x00000013 1693254885Sdumbbell#define V_038004_COLOR_24_8_FLOAT 0x00000014 1694254885Sdumbbell#define V_038004_COLOR_10_11_11 0x00000015 1695254885Sdumbbell#define V_038004_COLOR_10_11_11_FLOAT 0x00000016 1696254885Sdumbbell#define V_038004_COLOR_11_11_10 0x00000017 1697254885Sdumbbell#define V_038004_COLOR_11_11_10_FLOAT 0x00000018 1698254885Sdumbbell#define V_038004_COLOR_2_10_10_10 0x00000019 1699254885Sdumbbell#define V_038004_COLOR_8_8_8_8 0x0000001A 1700254885Sdumbbell#define V_038004_COLOR_10_10_10_2 0x0000001B 1701254885Sdumbbell#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C 1702254885Sdumbbell#define V_038004_COLOR_32_32 0x0000001D 1703254885Sdumbbell#define V_038004_COLOR_32_32_FLOAT 0x0000001E 1704254885Sdumbbell#define V_038004_COLOR_16_16_16_16 0x0000001F 1705254885Sdumbbell#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 1706254885Sdumbbell#define V_038004_COLOR_32_32_32_32 0x00000022 1707254885Sdumbbell#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 1708254885Sdumbbell#define V_038004_FMT_1 0x00000025 1709254885Sdumbbell#define V_038004_FMT_GB_GR 0x00000027 1710254885Sdumbbell#define V_038004_FMT_BG_RG 0x00000028 1711254885Sdumbbell#define V_038004_FMT_32_AS_8 0x00000029 1712254885Sdumbbell#define V_038004_FMT_32_AS_8_8 0x0000002A 1713254885Sdumbbell#define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B 1714254885Sdumbbell#define V_038004_FMT_8_8_8 0x0000002C 1715254885Sdumbbell#define V_038004_FMT_16_16_16 0x0000002D 1716254885Sdumbbell#define V_038004_FMT_16_16_16_FLOAT 0x0000002E 1717254885Sdumbbell#define V_038004_FMT_32_32_32 0x0000002F 1718254885Sdumbbell#define V_038004_FMT_32_32_32_FLOAT 0x00000030 1719254885Sdumbbell#define V_038004_FMT_BC1 0x00000031 1720254885Sdumbbell#define V_038004_FMT_BC2 0x00000032 1721254885Sdumbbell#define V_038004_FMT_BC3 0x00000033 1722254885Sdumbbell#define V_038004_FMT_BC4 0x00000034 1723254885Sdumbbell#define V_038004_FMT_BC5 0x00000035 1724254885Sdumbbell#define V_038004_FMT_BC6 0x00000036 1725254885Sdumbbell#define V_038004_FMT_BC7 0x00000037 1726254885Sdumbbell#define V_038004_FMT_32_AS_32_32_32_32 0x00000038 1727254885Sdumbbell#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 1728254885Sdumbbell#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1729254885Sdumbbell#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1730254885Sdumbbell#define C_038010_FORMAT_COMP_X 0xFFFFFFFC 1731254885Sdumbbell#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 1732254885Sdumbbell#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 1733254885Sdumbbell#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 1734254885Sdumbbell#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 1735254885Sdumbbell#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 1736254885Sdumbbell#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF 1737254885Sdumbbell#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 1738254885Sdumbbell#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 1739254885Sdumbbell#define C_038010_FORMAT_COMP_W 0xFFFFFF3F 1740254885Sdumbbell#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 1741254885Sdumbbell#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 1742254885Sdumbbell#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF 1743254885Sdumbbell#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 1744254885Sdumbbell#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 1745254885Sdumbbell#define C_038010_SRF_MODE_ALL 0xFFFFFBFF 1746254885Sdumbbell#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 1747254885Sdumbbell#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 1748254885Sdumbbell#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF 1749254885Sdumbbell#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 1750254885Sdumbbell#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 1751254885Sdumbbell#define C_038010_ENDIAN_SWAP 0xFFFFCFFF 1752254885Sdumbbell#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) 1753254885Sdumbbell#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) 1754254885Sdumbbell#define C_038010_REQUEST_SIZE 0xFFFF3FFF 1755254885Sdumbbell#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) 1756254885Sdumbbell#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) 1757254885Sdumbbell#define C_038010_DST_SEL_X 0xFFF8FFFF 1758254885Sdumbbell#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) 1759254885Sdumbbell#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 1760254885Sdumbbell#define C_038010_DST_SEL_Y 0xFFC7FFFF 1761254885Sdumbbell#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) 1762254885Sdumbbell#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 1763254885Sdumbbell#define C_038010_DST_SEL_Z 0xFE3FFFFF 1764254885Sdumbbell#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) 1765254885Sdumbbell#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) 1766254885Sdumbbell#define C_038010_DST_SEL_W 0xF1FFFFFF 1767254885Sdumbbell# define SQ_SEL_X 0 1768254885Sdumbbell# define SQ_SEL_Y 1 1769254885Sdumbbell# define SQ_SEL_Z 2 1770254885Sdumbbell# define SQ_SEL_W 3 1771254885Sdumbbell# define SQ_SEL_0 4 1772254885Sdumbbell# define SQ_SEL_1 5 1773254885Sdumbbell#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) 1774254885Sdumbbell#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 1775254885Sdumbbell#define C_038010_BASE_LEVEL 0x0FFFFFFF 1776254885Sdumbbell#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 1777254885Sdumbbell#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) 1778254885Sdumbbell#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 1779254885Sdumbbell#define C_038014_LAST_LEVEL 0xFFFFFFF0 1780254885Sdumbbell#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 1781254885Sdumbbell#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 1782254885Sdumbbell#define C_038014_BASE_ARRAY 0xFFFE000F 1783254885Sdumbbell#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 1784254885Sdumbbell#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 1785254885Sdumbbell#define C_038014_LAST_ARRAY 0xC001FFFF 1786254885Sdumbbell#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 1787254885Sdumbbell#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1788254885Sdumbbell#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1789254885Sdumbbell#define C_0288A8_ITEMSIZE 0xFFFF8000 1790254885Sdumbbell#define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 1791254885Sdumbbell#define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1792254885Sdumbbell#define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1793254885Sdumbbell#define C_008C44_MEM_SIZE 0x00000000 1794254885Sdumbbell#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 1795254885Sdumbbell#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1796254885Sdumbbell#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1797254885Sdumbbell#define C_0288B0_ITEMSIZE 0xFFFF8000 1798254885Sdumbbell#define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 1799254885Sdumbbell#define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1800254885Sdumbbell#define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1801254885Sdumbbell#define C_008C54_MEM_SIZE 0x00000000 1802254885Sdumbbell#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 1803254885Sdumbbell#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1804254885Sdumbbell#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1805254885Sdumbbell#define C_0288C0_ITEMSIZE 0xFFFF8000 1806254885Sdumbbell#define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 1807254885Sdumbbell#define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1808254885Sdumbbell#define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1809254885Sdumbbell#define C_008C74_MEM_SIZE 0x00000000 1810254885Sdumbbell#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 1811254885Sdumbbell#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1812254885Sdumbbell#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1813254885Sdumbbell#define C_0288B4_ITEMSIZE 0xFFFF8000 1814254885Sdumbbell#define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C 1815254885Sdumbbell#define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1816254885Sdumbbell#define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1817254885Sdumbbell#define C_008C5C_MEM_SIZE 0x00000000 1818254885Sdumbbell#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC 1819254885Sdumbbell#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1820254885Sdumbbell#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1821254885Sdumbbell#define C_0288AC_ITEMSIZE 0xFFFF8000 1822254885Sdumbbell#define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C 1823254885Sdumbbell#define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1824254885Sdumbbell#define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1825254885Sdumbbell#define C_008C4C_MEM_SIZE 0x00000000 1826254885Sdumbbell#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC 1827254885Sdumbbell#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1828254885Sdumbbell#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1829254885Sdumbbell#define C_0288BC_ITEMSIZE 0xFFFF8000 1830254885Sdumbbell#define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C 1831254885Sdumbbell#define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1832254885Sdumbbell#define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1833254885Sdumbbell#define C_008C6C_MEM_SIZE 0x00000000 1834254885Sdumbbell#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 1835254885Sdumbbell#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1836254885Sdumbbell#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1837254885Sdumbbell#define C_0288C4_ITEMSIZE 0xFFFF8000 1838254885Sdumbbell#define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C 1839254885Sdumbbell#define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1840254885Sdumbbell#define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1841254885Sdumbbell#define C_008C7C_MEM_SIZE 0x00000000 1842254885Sdumbbell#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 1843254885Sdumbbell#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1844254885Sdumbbell#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1845254885Sdumbbell#define C_0288B8_ITEMSIZE 0xFFFF8000 1846254885Sdumbbell#define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 1847254885Sdumbbell#define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1848254885Sdumbbell#define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1849254885Sdumbbell#define C_008C64_MEM_SIZE 0x00000000 1850254885Sdumbbell#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 1851254885Sdumbbell#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1852254885Sdumbbell#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1853254885Sdumbbell#define C_0288C8_ITEMSIZE 0xFFFF8000 1854254885Sdumbbell#define R_028010_DB_DEPTH_INFO 0x028010 1855254885Sdumbbell#define S_028010_FORMAT(x) (((x) & 0x7) << 0) 1856254885Sdumbbell#define G_028010_FORMAT(x) (((x) >> 0) & 0x7) 1857254885Sdumbbell#define C_028010_FORMAT 0xFFFFFFF8 1858254885Sdumbbell#define V_028010_DEPTH_INVALID 0x00000000 1859254885Sdumbbell#define V_028010_DEPTH_16 0x00000001 1860254885Sdumbbell#define V_028010_DEPTH_X8_24 0x00000002 1861254885Sdumbbell#define V_028010_DEPTH_8_24 0x00000003 1862254885Sdumbbell#define V_028010_DEPTH_X8_24_FLOAT 0x00000004 1863254885Sdumbbell#define V_028010_DEPTH_8_24_FLOAT 0x00000005 1864254885Sdumbbell#define V_028010_DEPTH_32_FLOAT 0x00000006 1865254885Sdumbbell#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 1866254885Sdumbbell#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) 1867254885Sdumbbell#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) 1868254885Sdumbbell#define C_028010_READ_SIZE 0xFFFFFFF7 1869254885Sdumbbell#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) 1870254885Sdumbbell#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) 1871254885Sdumbbell#define C_028010_ARRAY_MODE 0xFFF87FFF 1872254885Sdumbbell#define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 1873254885Sdumbbell#define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 1874254885Sdumbbell#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) 1875254885Sdumbbell#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) 1876254885Sdumbbell#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF 1877254885Sdumbbell#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) 1878254885Sdumbbell#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1879254885Sdumbbell#define C_028010_TILE_COMPACT 0xFBFFFFFF 1880254885Sdumbbell#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1881254885Sdumbbell#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1882254885Sdumbbell#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF 1883254885Sdumbbell#define R_028000_DB_DEPTH_SIZE 0x028000 1884254885Sdumbbell#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1885254885Sdumbbell#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1886254885Sdumbbell#define C_028000_PITCH_TILE_MAX 0xFFFFFC00 1887254885Sdumbbell#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1888254885Sdumbbell#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1889254885Sdumbbell#define C_028000_SLICE_TILE_MAX 0xC00003FF 1890254885Sdumbbell#define R_028004_DB_DEPTH_VIEW 0x028004 1891254885Sdumbbell#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) 1892254885Sdumbbell#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) 1893254885Sdumbbell#define C_028004_SLICE_START 0xFFFFF800 1894254885Sdumbbell#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1895254885Sdumbbell#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1896254885Sdumbbell#define C_028004_SLICE_MAX 0xFF001FFF 1897254885Sdumbbell#define R_028800_DB_DEPTH_CONTROL 0x028800 1898254885Sdumbbell#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1899254885Sdumbbell#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1900254885Sdumbbell#define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1901254885Sdumbbell#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1902254885Sdumbbell#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1903254885Sdumbbell#define C_028800_Z_ENABLE 0xFFFFFFFD 1904254885Sdumbbell#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1905254885Sdumbbell#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1906254885Sdumbbell#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1907254885Sdumbbell#define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1908254885Sdumbbell#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1909254885Sdumbbell#define C_028800_ZFUNC 0xFFFFFF8F 1910254885Sdumbbell#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1911254885Sdumbbell#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1912254885Sdumbbell#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1913254885Sdumbbell#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1914254885Sdumbbell#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1915254885Sdumbbell#define C_028800_STENCILFUNC 0xFFFFF8FF 1916254885Sdumbbell#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1917254885Sdumbbell#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1918254885Sdumbbell#define C_028800_STENCILFAIL 0xFFFFC7FF 1919254885Sdumbbell#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1920254885Sdumbbell#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1921254885Sdumbbell#define C_028800_STENCILZPASS 0xFFFE3FFF 1922254885Sdumbbell#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1923254885Sdumbbell#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1924254885Sdumbbell#define C_028800_STENCILZFAIL 0xFFF1FFFF 1925254885Sdumbbell#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1926254885Sdumbbell#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1927254885Sdumbbell#define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1928254885Sdumbbell#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1929254885Sdumbbell#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1930254885Sdumbbell#define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1931254885Sdumbbell#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1932254885Sdumbbell#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1933254885Sdumbbell#define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1934254885Sdumbbell#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1935254885Sdumbbell#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1936254885Sdumbbell#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1937254885Sdumbbell 1938254885Sdumbbell#endif 1939