i915_drv.c revision 280369
171867Smsmith/* i915_drv.c -- Intel i915 driver -*- linux-c -*- 271867Smsmith * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com 371867Smsmith */ 471867Smsmith/*- 5167802Sjkim * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 671867Smsmith * All Rights Reserved. 771867Smsmith * 871867Smsmith * Permission is hereby granted, free of charge, to any person obtaining a 971867Smsmith * copy of this software and associated documentation files (the "Software"), 1071867Smsmith * to deal in the Software without restriction, including without limitation 1171867Smsmith * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1271867Smsmith * and/or sell copies of the Software, and to permit persons to whom the 13167802Sjkim * Software is furnished to do so, subject to the following conditions: 1471867Smsmith * 1571867Smsmith * The above copyright notice and this permission notice (including the next 1671867Smsmith * paragraph) shall be included in all copies or substantial portions of the 1771867Smsmith * Software. 1871867Smsmith * 1971867Smsmith * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 2071867Smsmith * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2171867Smsmith * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2271867Smsmith * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 2371867Smsmith * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2471867Smsmith * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2571867Smsmith * OTHER DEALINGS IN THE SOFTWARE. 2671867Smsmith * 2771867Smsmith * Authors: 2871867Smsmith * Gareth Hughes <gareth@valinux.com> 2971867Smsmith * 3071867Smsmith */ 3171867Smsmith 3271867Smsmith#include <sys/cdefs.h> 3371867Smsmith__FBSDID("$FreeBSD: stable/10/sys/dev/drm2/i915/i915_drv.c 280369 2015-03-23 13:38:33Z kib $"); 3471867Smsmith 3571867Smsmith#include <dev/drm2/drmP.h> 3671867Smsmith#include <dev/drm2/drm.h> 3771867Smsmith#include <dev/drm2/drm_mm.h> 3871867Smsmith#include <dev/drm2/i915/i915_drm.h> 3971867Smsmith#include <dev/drm2/i915/i915_drv.h> 4071867Smsmith#include <dev/drm2/drm_pciids.h> 4171867Smsmith#include <dev/drm2/i915/intel_drv.h> 4271867Smsmith 4371867Smsmith#include "fb_if.h" 4471867Smsmith 4571867Smsmith/* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */ 4671867Smsmithstatic drm_pci_id_list_t i915_pciidlist[] = { 4771867Smsmith i915_PCI_IDS 4871867Smsmith}; 4971867Smsmith 5071867Smsmithstatic const struct intel_device_info intel_i830_info = { 5171867Smsmith .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, 5271867Smsmith .has_overlay = 1, .overlay_needs_physical = 1, 5371867Smsmith}; 5471867Smsmith 5571867Smsmithstatic const struct intel_device_info intel_845g_info = { 5671867Smsmith .gen = 2, 5771867Smsmith .has_overlay = 1, .overlay_needs_physical = 1, 5871867Smsmith}; 5971867Smsmith 6071867Smsmithstatic const struct intel_device_info intel_i85x_info = { 6171867Smsmith .gen = 2, .is_i85x = 1, .is_mobile = 1, 6271867Smsmith .cursor_needs_physical = 1, 6371867Smsmith .has_overlay = 1, .overlay_needs_physical = 1, 6471867Smsmith}; 6571867Smsmith 6671867Smsmithstatic const struct intel_device_info intel_i865g_info = { 6771867Smsmith .gen = 2, 6871867Smsmith .has_overlay = 1, .overlay_needs_physical = 1, 6971867Smsmith}; 7071867Smsmith 7171867Smsmithstatic const struct intel_device_info intel_i915g_info = { 7271867Smsmith .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, 7371867Smsmith .has_overlay = 1, .overlay_needs_physical = 1, 7471867Smsmith}; 7571867Smsmithstatic const struct intel_device_info intel_i915gm_info = { 7671867Smsmith .gen = 3, .is_mobile = 1, 7771867Smsmith .cursor_needs_physical = 1, 7871867Smsmith .has_overlay = 1, .overlay_needs_physical = 1, 7971867Smsmith .supports_tv = 1, 8071867Smsmith}; 8171867Smsmithstatic const struct intel_device_info intel_i945g_info = { 8271867Smsmith .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, 8371867Smsmith .has_overlay = 1, .overlay_needs_physical = 1, 8471867Smsmith}; 8571867Smsmithstatic const struct intel_device_info intel_i945gm_info = { 8671867Smsmith .gen = 3, .is_i945gm = 1, .is_mobile = 1, 8771867Smsmith .has_hotplug = 1, .cursor_needs_physical = 1, 8871867Smsmith .has_overlay = 1, .overlay_needs_physical = 1, 8971867Smsmith .supports_tv = 1, 9071867Smsmith}; 9171867Smsmith 9271867Smsmithstatic const struct intel_device_info intel_i965g_info = { 9371867Smsmith .gen = 4, .is_broadwater = 1, 9471867Smsmith .has_hotplug = 1, 9571867Smsmith .has_overlay = 1, 9671867Smsmith}; 9771867Smsmith 9871867Smsmithstatic const struct intel_device_info intel_i965gm_info = { 9971867Smsmith .gen = 4, .is_crestline = 1, 10071867Smsmith .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, 10171867Smsmith .has_overlay = 1, 10271867Smsmith .supports_tv = 1, 10371867Smsmith}; 10471867Smsmith 10571867Smsmithstatic const struct intel_device_info intel_g33_info = { 10671867Smsmith .gen = 3, .is_g33 = 1, 10771867Smsmith .need_gfx_hws = 1, .has_hotplug = 1, 10871867Smsmith .has_overlay = 1, 10971867Smsmith}; 11071867Smsmith 11171867Smsmithstatic const struct intel_device_info intel_g45_info = { 11271867Smsmith .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, 11371867Smsmith .has_pipe_cxsr = 1, .has_hotplug = 1, 11471867Smsmith .has_bsd_ring = 1, 11571867Smsmith}; 11671867Smsmith 11771867Smsmithstatic const struct intel_device_info intel_gm45_info = { 118193251Sjkim .gen = 4, .is_g4x = 1, 119193251Sjkim .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, 12071867Smsmith .has_pipe_cxsr = 1, .has_hotplug = 1, 12177424Smsmith .supports_tv = 1, 12291116Smsmith .has_bsd_ring = 1, 12371867Smsmith}; 12471867Smsmith 125151937Sjkimstatic const struct intel_device_info intel_pineview_info = { 12671867Smsmith .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, 12771867Smsmith .need_gfx_hws = 1, .has_hotplug = 1, 12871867Smsmith .has_overlay = 1, 12971867Smsmith}; 13071867Smsmith 13171867Smsmithstatic const struct intel_device_info intel_ironlake_d_info = { 13291116Smsmith .gen = 5, 13371867Smsmith .need_gfx_hws = 1, .has_hotplug = 1, 134151937Sjkim .has_bsd_ring = 1, 13571867Smsmith .has_pch_split = 1, 13671867Smsmith}; 13771867Smsmith 13871867Smsmithstatic const struct intel_device_info intel_ironlake_m_info = { 13971867Smsmith .gen = 5, .is_mobile = 1, 140167802Sjkim .need_gfx_hws = 1, .has_hotplug = 1, 14171867Smsmith .has_fbc = 0, /* disabled due to buggy hardware */ 142167802Sjkim .has_bsd_ring = 1, 143167802Sjkim .has_pch_split = 1, 14471867Smsmith}; 14571867Smsmith 146167802Sjkimstatic const struct intel_device_info intel_sandybridge_d_info = { 14771867Smsmith .gen = 6, 148167802Sjkim .need_gfx_hws = 1, .has_hotplug = 1, 149167802Sjkim .has_bsd_ring = 1, 150167817Sjkim .has_blt_ring = 1, 151167817Sjkim .has_llc = 1, 152167802Sjkim .has_pch_split = 1, 153167802Sjkim}; 154167802Sjkim 155167802Sjkimstatic const struct intel_device_info intel_sandybridge_m_info = { 156167802Sjkim .gen = 6, .is_mobile = 1, 15771867Smsmith .need_gfx_hws = 1, .has_hotplug = 1, 15871867Smsmith .has_fbc = 1, 159167802Sjkim .has_bsd_ring = 1, 160167802Sjkim .has_blt_ring = 1, 16171867Smsmith .has_llc = 1, 162167802Sjkim .has_pch_split = 1, 163167802Sjkim}; 164167802Sjkim 165167802Sjkimstatic const struct intel_device_info intel_ivybridge_d_info = { 16671867Smsmith .is_ivybridge = 1, .gen = 7, 16771867Smsmith .need_gfx_hws = 1, .has_hotplug = 1, 16871867Smsmith .has_bsd_ring = 1, 169167802Sjkim .has_blt_ring = 1, 170167802Sjkim .has_llc = 1, 171167802Sjkim .has_pch_split = 1, 172167802Sjkim}; 17371867Smsmith 17471867Smsmithstatic const struct intel_device_info intel_ivybridge_m_info = { 17571867Smsmith .is_ivybridge = 1, .gen = 7, .is_mobile = 1, 17671867Smsmith .need_gfx_hws = 1, .has_hotplug = 1, 17771867Smsmith .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ 178167802Sjkim .has_bsd_ring = 1, 17971867Smsmith .has_blt_ring = 1, 180167802Sjkim .has_llc = 1, 181151937Sjkim .has_pch_split = 1, 18271867Smsmith}; 18371867Smsmith 18471867Smsmith#if 0 185151937Sjkimstatic const struct intel_device_info intel_valleyview_m_info = { 18671867Smsmith .gen = 7, .is_mobile = 1, 187151937Sjkim .need_gfx_hws = 1, .has_hotplug = 1, 18871867Smsmith .has_fbc = 0, 189151937Sjkim .has_bsd_ring = 1, 19071867Smsmith .has_blt_ring = 1, 191151937Sjkim .is_valleyview = 1, 19271867Smsmith}; 19371867Smsmith 19471867Smsmithstatic const struct intel_device_info intel_valleyview_d_info = { 19571867Smsmith .gen = 7, 19671867Smsmith .need_gfx_hws = 1, .has_hotplug = 1, 197167802Sjkim .has_fbc = 0, 19871867Smsmith .has_bsd_ring = 1, 199167802Sjkim .has_blt_ring = 1, 200167802Sjkim .is_valleyview = 1, 20171867Smsmith}; 20271867Smsmith#endif 203167802Sjkim 20471867Smsmithstatic const struct intel_device_info intel_haswell_d_info = { 205167802Sjkim .is_haswell = 1, .gen = 7, 20671867Smsmith .need_gfx_hws = 1, .has_hotplug = 1, 20771867Smsmith .has_bsd_ring = 1, 20871867Smsmith .has_blt_ring = 1, 20971867Smsmith .has_llc = 1, 21071867Smsmith .has_pch_split = 1, 211167802Sjkim .not_supported = 1, 212167802Sjkim}; 213167817Sjkim 214167817Sjkimstatic const struct intel_device_info intel_haswell_m_info = { 215167802Sjkim .is_haswell = 1, .gen = 7, .is_mobile = 1, 216167802Sjkim .need_gfx_hws = 1, .has_hotplug = 1, 217167802Sjkim .has_bsd_ring = 1, 218167802Sjkim .has_blt_ring = 1, 219167802Sjkim .has_llc = 1, 22071867Smsmith .has_pch_split = 1, 22171867Smsmith .not_supported = 1, 222167802Sjkim}; 223167802Sjkim 22471867Smsmith#define INTEL_VGA_DEVICE(id, info_) { \ 225167802Sjkim .device = id, \ 226167802Sjkim .info = info_, \ 227167802Sjkim} 228167802Sjkim 229167802Sjkimstatic const struct intel_gfx_device_id { 23071867Smsmith int device; 23171867Smsmith const struct intel_device_info *info; 23271867Smsmith} pciidlist[] = { /* aka */ 233167802Sjkim INTEL_VGA_DEVICE(0x3577, &intel_i830_info), 234167802Sjkim INTEL_VGA_DEVICE(0x2562, &intel_845g_info), 235167802Sjkim INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), 236167802Sjkim INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), 23771867Smsmith INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), 23871867Smsmith INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), 23971867Smsmith INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), 24071867Smsmith INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), 24171867Smsmith INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), 242167802Sjkim INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), 24387031Smsmith INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), 244167802Sjkim INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), 245151937Sjkim INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), 24671867Smsmith INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), 24787031Smsmith INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), 24871867Smsmith INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), 24971867Smsmith INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), 25071867Smsmith INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), 25171867Smsmith INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), 25271867Smsmith INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), 25387031Smsmith INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), 25487031Smsmith INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), 25587031Smsmith INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), 25687031Smsmith INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), 25771867Smsmith INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), 25871867Smsmith INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), 25971867Smsmith INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), 26071867Smsmith INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), 26187031Smsmith INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), 26277424Smsmith INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), 26371867Smsmith INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), 26477424Smsmith INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), 26577424Smsmith INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), 26677424Smsmith INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), 26771867Smsmith INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), 26877424Smsmith INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), 269167802Sjkim INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), 27091116Smsmith INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), 27191116Smsmith INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ 27271867Smsmith INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ 27371867Smsmith INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ 27471867Smsmith INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ 27599679Siwasaki INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ 27691116Smsmith INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ 27791116Smsmith INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ 27871867Smsmith INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ 27987031Smsmith INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ 28071867Smsmith INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ 28171867Smsmith INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ 28291116Smsmith INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ 28377424Smsmith INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */ 28471867Smsmith {0, 0} 28571867Smsmith}; 28671867Smsmith 28771867Smsmithstatic int i915_enable_unsupported; 28871867Smsmith 28971867Smsmithstatic int i915_drm_freeze(struct drm_device *dev) 29091116Smsmith{ 29177424Smsmith struct drm_i915_private *dev_priv; 292126372Snjl int error; 29391116Smsmith 29491116Smsmith dev_priv = dev->dev_private; 29591116Smsmith drm_kms_helper_poll_disable(dev); 29691116Smsmith 29791116Smsmith#if 0 298126372Snjl pci_save_state(dev->pdev); 29991116Smsmith#endif 30091116Smsmith 30191116Smsmith DRM_LOCK(dev); 30291116Smsmith /* If KMS is active, we do the leavevt stuff here */ 30391116Smsmith if (drm_core_check_feature(dev, DRIVER_MODESET)) { 304126372Snjl error = -i915_gem_idle(dev); 305126372Snjl if (error) { 306126372Snjl DRM_UNLOCK(dev); 307126372Snjl device_printf(dev->device, 308126372Snjl "GEM idle failed, resume might fail\n"); 309126372Snjl return (error); 310126372Snjl } 311126372Snjl drm_irq_uninstall(dev); 312126372Snjl } 313126372Snjl 314126372Snjl i915_save_state(dev); 315126372Snjl 316126372Snjl intel_opregion_fini(dev); 317126372Snjl 318126372Snjl /* Modeset on resume, not lid events */ 319126372Snjl dev_priv->modeset_on_lid = 0; 320126372Snjl DRM_UNLOCK(dev); 321126372Snjl 322126372Snjl return 0; 323151937Sjkim} 324126372Snjl 325126372Snjlstatic int 326126372Snjli915_suspend(device_t kdev) 327123315Snjl{ 328123315Snjl struct drm_device *dev; 329126372Snjl int error; 330123315Snjl 331123315Snjl dev = device_get_softc(kdev); 332167802Sjkim if (dev == NULL || dev->dev_private == NULL) { 333123315Snjl DRM_ERROR("DRM not initialized, aborting suspend.\n"); 334123315Snjl return -ENODEV; 33587031Smsmith } 33687031Smsmith 33787031Smsmith DRM_DEBUG_KMS("starting suspend\n"); 338167802Sjkim error = i915_drm_freeze(dev); 33987031Smsmith if (error) 340167802Sjkim return (error); 341151937Sjkim 34287031Smsmith error = bus_generic_suspend(kdev); 34387031Smsmith DRM_DEBUG_KMS("finished suspend %d\n", error); 34487031Smsmith return (error); 34587031Smsmith} 34687031Smsmith 34787031Smsmithstatic int i915_drm_thaw(struct drm_device *dev) 34887031Smsmith{ 34987031Smsmith struct drm_i915_private *dev_priv = dev->dev_private; 35087031Smsmith int error = 0; 35187031Smsmith 35287031Smsmith DRM_LOCK(dev); 35387031Smsmith if (drm_core_check_feature(dev, DRIVER_MODESET)) { 35487031Smsmith i915_gem_restore_gtt_mappings(dev); 35587031Smsmith } 35691116Smsmith 35787031Smsmith i915_restore_state(dev); 35899679Siwasaki intel_opregion_setup(dev); 35999679Siwasaki 36091116Smsmith /* KMS EnterVT equivalent */ 36191116Smsmith if (drm_core_check_feature(dev, DRIVER_MODESET)) { 36299679Siwasaki if (HAS_PCH_SPLIT(dev)) 36399679Siwasaki ironlake_init_pch_refclk(dev); 36487031Smsmith 36587031Smsmith dev_priv->mm.suspended = 0; 366167802Sjkim 36787031Smsmith error = i915_gem_init_hw(dev); 36891116Smsmith DRM_UNLOCK(dev); 36991116Smsmith 37091116Smsmith intel_modeset_init_hw(dev); 37187031Smsmith sx_xlock(&dev->mode_config.mutex); 372167802Sjkim drm_mode_config_reset(dev); 37391116Smsmith sx_xunlock(&dev->mode_config.mutex); 37491116Smsmith drm_irq_install(dev); 37587031Smsmith 37687031Smsmith sx_xlock(&dev->mode_config.mutex); 37791116Smsmith /* Resume the modeset for every activated CRTC */ 37891116Smsmith drm_helper_resume_force_mode(dev); 37971867Smsmith sx_xunlock(&dev->mode_config.mutex); 380128245Snjl DRM_LOCK(dev); 381128245Snjl } 382167802Sjkim 383128245Snjl intel_opregion_init(dev); 38499679Siwasaki 385128245Snjl dev_priv->modeset_on_lid = 0; 386128245Snjl 38778986Smsmith DRM_UNLOCK(dev); 388129684Snjl 389129684Snjl return error; 390167802Sjkim} 391128245Snjl 392128245Snjlstatic int 393128245Snjli915_resume(device_t kdev) 394128245Snjl{ 39587031Smsmith struct drm_device *dev; 396128245Snjl int ret; 397128245Snjl 398123315Snjl dev = device_get_softc(kdev); 399123315Snjl DRM_DEBUG_KMS("starting resume\n"); 400167802Sjkim#if 0 401123315Snjl if (pci_enable_device(dev->pdev)) 402123315Snjl return -EIO; 403123315Snjl 404123315Snjl pci_set_master(dev->pdev); 40599679Siwasaki#endif 40699679Siwasaki 407128212Snjl ret = -i915_drm_thaw(dev); 408129684Snjl if (ret != 0) 409128212Snjl return (ret); 410128212Snjl 411151937Sjkim drm_kms_helper_poll_enable(dev); 41299679Siwasaki ret = bus_generic_resume(kdev); 41399679Siwasaki DRM_DEBUG_KMS("finished resume %d\n", ret); 41499679Siwasaki return (ret); 41599679Siwasaki} 416129684Snjl 41799679Siwasakistatic int 418151937Sjkimi915_probe(device_t kdev) 419129684Snjl{ 420129684Snjl const struct intel_device_info *info; 421129684Snjl int error; 422129684Snjl 423129684Snjl error = drm_probe(kdev, i915_pciidlist); 42491116Smsmith if (error != 0) 42578986Smsmith return (error); 426151937Sjkim info = i915_get_device_id(pci_get_device(kdev)); 427151937Sjkim if (info == NULL) 42899679Siwasaki return (ENXIO); 42999679Siwasaki return (0); 43099679Siwasaki} 43199679Siwasaki 432151937Sjkimint i915_modeset; 433151937Sjkim 43482367Smsmithstatic int 43591116Smsmithi915_attach(device_t kdev) 43682367Smsmith{ 437151937Sjkim struct drm_device *dev; 438151937Sjkim 43971867Smsmith dev = device_get_softc(kdev); 44071867Smsmith if (i915_modeset == 1) 44191116Smsmith i915_driver_info.driver_features |= DRIVER_MODESET; 44282367Smsmith dev->driver = &i915_driver_info; 44391116Smsmith return (drm_attach(kdev, i915_pciidlist)); 44491116Smsmith} 44571867Smsmith 446126372Snjlstatic struct fb_info * 447126372Snjli915_fb_helper_getinfo(device_t kdev) 448126372Snjl{ 449126372Snjl struct intel_fbdev *ifbdev; 450126372Snjl drm_i915_private_t *dev_priv; 45191116Smsmith struct drm_device *dev; 45271867Smsmith struct fb_info *info; 453151937Sjkim 454151937Sjkim dev = device_get_softc(kdev); 45599679Siwasaki dev_priv = dev->dev_private; 45699679Siwasaki ifbdev = dev_priv->fbdev; 45799679Siwasaki if (ifbdev == NULL) 45899679Siwasaki return (NULL); 45982367Smsmith 460151937Sjkim info = ifbdev->helper.fbdev; 461151937Sjkim 46299679Siwasaki return (info); 46399679Siwasaki} 46499679Siwasaki 46599679Siwasakiconst struct intel_device_info * 46699679Siwasakii915_get_device_id(int device) 46791116Smsmith{ 46882367Smsmith const struct intel_gfx_device_id *did; 46991116Smsmith 47091116Smsmith for (did = &pciidlist[0]; did->device != 0; did++) { 47171867Smsmith if (did->device != device) 47291116Smsmith continue; 47371867Smsmith if (did->info->not_supported && !i915_enable_unsupported) 47499679Siwasaki return (NULL); 47580062Smsmith return (did->info); 476151937Sjkim } 477151937Sjkim return (NULL); 47899679Siwasaki} 47999679Siwasaki 48099679Siwasakistatic device_method_t i915_methods[] = { 48199679Siwasaki /* Device interface */ 48299679Siwasaki DEVMETHOD(device_probe, i915_probe), 483151937Sjkim DEVMETHOD(device_attach, i915_attach), 484151937Sjkim DEVMETHOD(device_suspend, i915_suspend), 48599679Siwasaki DEVMETHOD(device_resume, i915_resume), 48699679Siwasaki DEVMETHOD(device_detach, drm_detach), 48799679Siwasaki 48899679Siwasaki /* Framebuffer service methods */ 48999679Siwasaki DEVMETHOD(fb_getinfo, i915_fb_helper_getinfo), 49082367Smsmith 49182367Smsmith DEVMETHOD_END 49299679Siwasaki}; 493151937Sjkim 494151937Sjkimstatic driver_t i915_driver = { 495123315Snjl "drmn", 496151937Sjkim i915_methods, 497151937Sjkim sizeof(struct drm_device) 498123315Snjl}; 49999679Siwasaki 500126372Snjlextern devclass_t drm_devclass; 50199679SiwasakiDRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0, 50299679Siwasaki SI_ORDER_ANY); 50399679SiwasakiMODULE_DEPEND(i915kms, drmn, 1, 1, 1); 50482367SmsmithMODULE_DEPEND(i915kms, agp, 1, 1, 1); 505151937SjkimMODULE_DEPEND(i915kms, iicbus, 1, 1, 1); 506151937SjkimMODULE_DEPEND(i915kms, iic, 1, 1, 1); 50799679SiwasakiMODULE_DEPEND(i915kms, iicbb, 1, 1, 1); 50899679Siwasaki 50999679Siwasakiint intel_iommu_enabled = 0; 51099679SiwasakiTUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled); 51199679Siwasakiint intel_iommu_gfx_mapped = 0; 51280357SpeterTUNABLE_INT("drm.i915.intel_iommu_gfx_mapped", &intel_iommu_gfx_mapped); 51380062Smsmith 51491116Smsmithint i915_prefault_disable; 51571867SmsmithTUNABLE_INT("drm.i915.prefault_disable", &i915_prefault_disable); 516102550Siwasakiint i915_semaphores = -1; 51783174SmsmithTUNABLE_INT("drm.i915.semaphores", &i915_semaphores); 518167802Sjkimstatic int i915_try_reset = 1; 51999679SiwasakiTUNABLE_INT("drm.i915.try_reset", &i915_try_reset); 52099679Siwasakiunsigned int i915_lvds_downclock = 0; 52199679SiwasakiTUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock); 52299679Siwasakiint i915_vbt_sdvo_panel_type = -1; 52399679SiwasakiTUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type); 52491116Smsmithunsigned int i915_powersave = 1; 52582367SmsmithTUNABLE_INT("drm.i915.powersave", &i915_powersave); 52699679Siwasakiint i915_enable_fbc = 0; 52799679SiwasakiTUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc); 52871867Smsmithint i915_enable_rc6 = 0; 52971867SmsmithTUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6); 53082367Smsmithint i915_lvds_channel_mode; 531167802SjkimTUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode); 532114237Snjlint i915_panel_use_ssc = -1; 533167802SjkimTUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc); 534151937Sjkimint i915_panel_ignore_lid = 0; 53582367SmsmithTUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid); 536114237Snjlint i915_panel_invert_brightness; 537114237SnjlTUNABLE_INT("drm.i915.panel_invert_brightness", &i915_panel_invert_brightness); 538114237Snjlint i915_modeset = 1; 539114237SnjlTUNABLE_INT("drm.i915.modeset", &i915_modeset); 540114237Snjlint i915_enable_ppgtt = -1; 541114237SnjlTUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt); 542114237Snjlint i915_enable_hangcheck = 1; 543114237SnjlTUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck); 544114237SnjlTUNABLE_INT("drm.i915.enable_unsupported", &i915_enable_unsupported); 545114237Snjl 546114237Snjl#define PCI_VENDOR_INTEL 0x8086 547114237Snjl#define INTEL_PCH_DEVICE_ID_MASK 0xff00 548114237Snjl#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 549114237Snjl#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 550114237Snjl#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 551114237Snjl#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 552114237Snjl 553114237Snjlvoid intel_detect_pch(struct drm_device *dev) 554114237Snjl{ 555167802Sjkim struct drm_i915_private *dev_priv; 556114237Snjl device_t pch; 557123315Snjl uint32_t id; 558167802Sjkim 559126372Snjl dev_priv = dev->dev_private; 560126372Snjl pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA); 561126372Snjl if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) { 562126372Snjl id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK; 563114237Snjl if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { 564167802Sjkim dev_priv->pch_type = PCH_IBX; 565126372Snjl dev_priv->num_pch_pll = 2; 566126372Snjl DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); 567126372Snjl } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { 568126372Snjl dev_priv->pch_type = PCH_CPT; 569114237Snjl dev_priv->num_pch_pll = 2; 570128212Snjl DRM_DEBUG_KMS("Found CougarPoint PCH\n"); 571129684Snjl } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { 572128212Snjl /* PantherPoint is CPT compatible */ 573128212Snjl dev_priv->pch_type = PCH_CPT; 574151937Sjkim dev_priv->num_pch_pll = 2; 575126372Snjl DRM_DEBUG_KMS("Found PatherPoint PCH\n"); 576126372Snjl } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 577126372Snjl dev_priv->pch_type = PCH_LPT; 578126372Snjl dev_priv->num_pch_pll = 0; 579129684Snjl DRM_DEBUG_KMS("Found LynxPoint PCH\n"); 580114237Snjl } else 581151937Sjkim DRM_DEBUG_KMS("No PCH detected\n"); 582129684Snjl KASSERT(dev_priv->num_pch_pll <= I915_NUM_PLLS, 583129684Snjl ("num_pch_pll %d\n", dev_priv->num_pch_pll)); 584129684Snjl } else 585129684Snjl DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n"); 586129684Snjl} 587126372Snjl 588126372Snjlbool i915_semaphore_is_enabled(struct drm_device *dev) 589167802Sjkim{ 590167802Sjkim if (INTEL_INFO(dev)->gen < 6) 591114237Snjl return 0; 592114237Snjl 593114237Snjl if (i915_semaphores >= 0) 594167802Sjkim return i915_semaphores; 595114237Snjl 596114237Snjl /* Enable semaphores on SNB when IO remapping is off */ 597114237Snjl if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) 598114237Snjl return false; 599114237Snjl 600114237Snjl return 1; 601114237Snjl} 602114237Snjl 603114237Snjlvoid 604167802Sjkim__gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 605114237Snjl{ 606167802Sjkim int count; 607151937Sjkim 608114237Snjl count = 0; 60982367Smsmith while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) 61082367Smsmith DELAY(10); 61182367Smsmith 61282367Smsmith I915_WRITE_NOTRACE(FORCEWAKE, 1); 61382367Smsmith POSTING_READ(FORCEWAKE); 61482367Smsmith 61582367Smsmith count = 0; 616138287Smarks while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) 61782367Smsmith DELAY(10); 61882367Smsmith} 61982367Smsmith 62082367Smsmithvoid 62182367Smsmith__gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) 622123315Snjl{ 62382367Smsmith int count; 624123315Snjl 625123315Snjl count = 0; 626123315Snjl while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1)) 627123315Snjl DELAY(10); 628123315Snjl 629126372Snjl I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1)); 630126372Snjl POSTING_READ(FORCEWAKE_MT); 63182367Smsmith 63283174Smsmith count = 0; 633167802Sjkim while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0) 63482367Smsmith DELAY(10); 63591116Smsmith} 636126372Snjl 637126372Snjlvoid 638126372Snjlgen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 639126372Snjl{ 640126372Snjl 641126372Snjl mtx_lock(&dev_priv->gt_lock); 642126372Snjl if (dev_priv->forcewake_count++ == 0) 643123315Snjl dev_priv->display.force_wake_get(dev_priv); 644123315Snjl mtx_unlock(&dev_priv->gt_lock); 645126372Snjl} 646126372Snjl 647123315Snjlstatic void 648126372Snjlgen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) 649123315Snjl{ 650126372Snjl u32 gtfifodbg; 651126372Snjl 652126372Snjl gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); 653126372Snjl if ((gtfifodbg & GT_FIFO_CPU_ERROR_MASK) != 0) { 654126372Snjl printf("MMIO read or write has been dropped %x\n", gtfifodbg); 655126372Snjl I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); 656126372Snjl } 657126372Snjl} 658126372Snjl 659126372Snjlvoid 660126372Snjl__gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 661126372Snjl{ 662126372Snjl 663126372Snjl I915_WRITE_NOTRACE(FORCEWAKE, 0); 664126372Snjl /* The below doubles as a POSTING_READ */ 665126372Snjl gen6_gt_check_fifodbg(dev_priv); 666126372Snjl} 667126372Snjl 668126372Snjlvoid 669126372Snjl__gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) 670126372Snjl{ 671126372Snjl 672123315Snjl I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1)); 673123315Snjl /* The below doubles as a POSTING_READ */ 67487031Smsmith gen6_gt_check_fifodbg(dev_priv); 67582367Smsmith} 67691116Smsmith 67791116Smsmithvoid 67891116Smsmithgen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 67991116Smsmith{ 68082367Smsmith 68182367Smsmith mtx_lock(&dev_priv->gt_lock); 68282367Smsmith if (--dev_priv->forcewake_count == 0) 68382367Smsmith dev_priv->display.force_wake_put(dev_priv); 68491116Smsmith mtx_unlock(&dev_priv->gt_lock); 68583174Smsmith} 686126372Snjl 687126372Snjlint 688123315Snjl__gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 689123315Snjl{ 690167802Sjkim int ret = 0; 691123315Snjl 692123315Snjl if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { 693123315Snjl int loop = 500; 694126372Snjl u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 69591116Smsmith while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { 69691116Smsmith DELAY(10); 697167802Sjkim fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 69891116Smsmith } 69991116Smsmith if (loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES) { 700126372Snjl printf("%s loop\n", __func__); 70191116Smsmith ++ret; 70291116Smsmith } 703167802Sjkim dev_priv->gt_fifo_count = fifo; 70491116Smsmith } 705128212Snjl dev_priv->gt_fifo_count--; 70691116Smsmith 707128212Snjl return (ret); 708128212Snjl} 709129684Snjl 710128212Snjlvoid vlv_force_wake_get(struct drm_i915_private *dev_priv) 711128212Snjl{ 712151937Sjkim int count; 71399679Siwasaki 71499679Siwasaki count = 0; 71599679Siwasaki 71699679Siwasaki /* Already awake? */ 717129684Snjl if ((I915_READ(0x130094) & 0xa1) == 0xa1) 71882367Smsmith return; 719151937Sjkim 720129684Snjl I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff); 721129684Snjl POSTING_READ(FORCEWAKE_VLV); 722129684Snjl 723129684Snjl count = 0; 724129684Snjl while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0) 725126372Snjl DELAY(10); 726126372Snjl} 727151937Sjkim 728167802Sjkimvoid vlv_force_wake_put(struct drm_i915_private *dev_priv) 729151937Sjkim{ 730151937Sjkim I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000); 731167802Sjkim /* FIXME: confirm VLV behavior with Punit folks */ 732126372Snjl POSTING_READ(FORCEWAKE_VLV); 733123315Snjl} 734123315Snjl 735167802Sjkimstatic int 736126372Snjli8xx_do_reset(struct drm_device *dev) 737126372Snjl{ 738126372Snjl struct drm_i915_private *dev_priv = dev->dev_private; 739126372Snjl int onems; 740126372Snjl 741126372Snjl if (IS_I85X(dev)) 742126372Snjl return -ENODEV; 743126372Snjl 744126372Snjl onems = hz / 1000; 745167802Sjkim if (onems == 0) 746126372Snjl onems = 1; 747126372Snjl 74899679Siwasaki I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); 74982367Smsmith POSTING_READ(D_STATE); 750167802Sjkim 751167802Sjkim if (IS_I830(dev) || IS_845G(dev)) { 752167802Sjkim I915_WRITE(DEBUG_RESET_I830, 753 DEBUG_RESET_DISPLAY | 754 DEBUG_RESET_RENDER | 755 DEBUG_RESET_FULL); 756 POSTING_READ(DEBUG_RESET_I830); 757 pause("i8xxrst1", onems); 758 759 I915_WRITE(DEBUG_RESET_I830, 0); 760 POSTING_READ(DEBUG_RESET_I830); 761 } 762 763 pause("i8xxrst2", onems); 764 765 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); 766 POSTING_READ(D_STATE); 767 768 return 0; 769} 770 771static int 772i965_reset_complete(struct drm_device *dev) 773{ 774 u8 gdrst; 775 776 gdrst = pci_read_config(dev->device, I965_GDRST, 1); 777 return (gdrst & GRDOM_RESET_ENABLE) == 0; 778} 779 780static int 781i965_do_reset(struct drm_device *dev) 782{ 783 int ret; 784 u8 gdrst; 785 786 /* 787 * Set the domains we want to reset (GRDOM/bits 2 and 3) as 788 * well as the reset bit (GR/bit 0). Setting the GR bit 789 * triggers the reset; when done, the hardware will clear it. 790 */ 791 gdrst = pci_read_config(dev->device, I965_GDRST, 1); 792 pci_write_config(dev->device, I965_GDRST, 793 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE, 1); 794 795 ret = wait_for(i965_reset_complete(dev), 500); 796 if (ret) 797 return ret; 798 799 /* We can't reset render&media without also resetting display ... */ 800 gdrst = pci_read_config(dev->device, I965_GDRST, 1); 801 pci_write_config(dev->device, I965_GDRST, 802 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE, 1); 803 804 return wait_for(i965_reset_complete(dev), 500); 805} 806 807static int 808ironlake_do_reset(struct drm_device *dev) 809{ 810 struct drm_i915_private *dev_priv; 811 u32 gdrst; 812 int ret; 813 814 dev_priv = dev->dev_private; 815 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); 816 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 817 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); 818 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); 819 if (ret) 820 return ret; 821 822 /* We can't reset render&media without also resetting display ... */ 823 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); 824 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 825 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); 826 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); 827} 828 829static int 830gen6_do_reset(struct drm_device *dev) 831{ 832 struct drm_i915_private *dev_priv; 833 int ret; 834 835 dev_priv = dev->dev_private; 836 837 /* Hold gt_lock across reset to prevent any register access 838 * with forcewake not set correctly 839 */ 840 mtx_lock(&dev_priv->gt_lock); 841 842 /* Reset the chip */ 843 844 /* GEN6_GDRST is not in the gt power well, no need to check 845 * for fifo space for the write or forcewake the chip for 846 * the read 847 */ 848 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); 849 850 /* Spin waiting for the device to ack the reset request */ 851 ret = _intel_wait_for(dev, 852 (I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 853 500, 0, "915rst"); 854 855 /* If reset with a user forcewake, try to restore, otherwise turn it off */ 856 if (dev_priv->forcewake_count) 857 dev_priv->display.force_wake_get(dev_priv); 858 else 859 dev_priv->display.force_wake_put(dev_priv); 860 861 /* Restore fifo count */ 862 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 863 864 mtx_unlock(&dev_priv->gt_lock); 865 return (ret); 866} 867 868int 869intel_gpu_reset(struct drm_device *dev) 870{ 871 struct drm_i915_private *dev_priv = dev->dev_private; 872 int ret = -ENODEV; 873 874 switch (INTEL_INFO(dev)->gen) { 875 case 7: 876 case 6: 877 ret = gen6_do_reset(dev); 878 break; 879 case 5: 880 ret = ironlake_do_reset(dev); 881 break; 882 case 4: 883 ret = i965_do_reset(dev); 884 break; 885 case 2: 886 ret = i8xx_do_reset(dev); 887 break; 888 } 889 890 /* Also reset the gpu hangman. */ 891 if (dev_priv->stop_rings) { 892 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n"); 893 dev_priv->stop_rings = 0; 894 if (ret == -ENODEV) { 895 DRM_ERROR("Reset not implemented, but ignoring " 896 "error for simulated gpu hangs\n"); 897 ret = 0; 898 } 899 } 900 901 return ret; 902} 903 904int i915_reset(struct drm_device *dev) 905{ 906 drm_i915_private_t *dev_priv = dev->dev_private; 907 int ret; 908 909 if (!i915_try_reset) 910 return (0); 911 912 if (!sx_try_xlock(&dev->dev_struct_lock)) 913 return (-EBUSY); 914 915 dev_priv->stop_rings = 0; 916 917 i915_gem_reset(dev); 918 919 ret = -ENODEV; 920 if (time_second - dev_priv->last_gpu_reset < 5) 921 DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); 922 else 923 ret = intel_gpu_reset(dev); 924 925 dev_priv->last_gpu_reset = time_second; 926 if (ret) { 927 DRM_ERROR("Failed to reset chip.\n"); 928 DRM_UNLOCK(dev); 929 return (ret); 930 } 931 932 if (drm_core_check_feature(dev, DRIVER_MODESET) || 933 !dev_priv->mm.suspended) { 934 struct intel_ring_buffer *ring; 935 int i; 936 937 dev_priv->mm.suspended = 0; 938 939 i915_gem_init_swizzling(dev); 940 941 for_each_ring(ring, dev_priv, i) 942 ring->init(ring); 943 944 i915_gem_context_init(dev); 945 i915_gem_init_ppgtt(dev); 946 947 DRM_UNLOCK(dev); 948 949 if (drm_core_check_feature(dev, DRIVER_MODESET)) 950 intel_modeset_init_hw(dev); 951 952 DRM_LOCK(dev); 953 drm_irq_uninstall(dev); 954 DRM_UNLOCK(dev); 955 drm_irq_install(dev); 956 } else 957 DRM_UNLOCK(dev); 958 959 return (0); 960} 961 962/* We give fast paths for the really cool registers */ 963#define NEEDS_FORCE_WAKE(dev_priv, reg) \ 964 (((dev_priv)->info->gen >= 6) && \ 965 ((reg) < 0x40000) && \ 966 ((reg) != FORCEWAKE)) && \ 967 (!IS_VALLEYVIEW((dev_priv)->dev)) 968 969#define __i915_read(x, y) \ 970u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ 971 u##x val = 0; \ 972 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 973 mtx_lock(&dev_priv->gt_lock); \ 974 if (dev_priv->forcewake_count == 0) \ 975 dev_priv->display.force_wake_get(dev_priv); \ 976 val = DRM_READ##y(dev_priv->mmio_map, reg); \ 977 if (dev_priv->forcewake_count == 0) \ 978 dev_priv->display.force_wake_put(dev_priv); \ 979 mtx_unlock(&dev_priv->gt_lock); \ 980 } else { \ 981 val = DRM_READ##y(dev_priv->mmio_map, reg); \ 982 } \ 983 trace_i915_reg_rw(false, reg, val, sizeof(val)); \ 984 return val; \ 985} 986 987__i915_read(8, 8) 988__i915_read(16, 16) 989__i915_read(32, 32) 990__i915_read(64, 64) 991#undef __i915_read 992 993#define __i915_write(x, y) \ 994void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ 995 u32 __fifo_ret = 0; \ 996 trace_i915_reg_rw(true, reg, val, sizeof(val)); \ 997 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 998 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ 999 } \ 1000 DRM_WRITE##y(dev_priv->mmio_map, reg, val); \ 1001 if (__predict_false(__fifo_ret)) { \ 1002 gen6_gt_check_fifodbg(dev_priv); \ 1003 } \ 1004} 1005__i915_write(8, 8) 1006__i915_write(16, 16) 1007__i915_write(32, 32) 1008__i915_write(64, 64) 1009#undef __i915_write 1010