drm_dp_helper.h revision 254817
1294113Sbapt/* 2241675Suqs * Copyright �� 2008 Keith Packard 3241675Suqs * 4294113Sbapt * Permission to use, copy, modify, distribute, and sell this software and its 5241675Suqs * documentation for any purpose is hereby granted without fee, provided that 6241675Suqs * the above copyright notice appear in all copies and that both that copyright 7241675Suqs * notice and this permission notice appear in supporting documentation, and 8241675Suqs * that the name of the copyright holders not be used in advertising or 9241675Suqs * publicity pertaining to distribution of the software without specific, 10294113Sbapt * written prior permission. The copyright holders make no representations 11241675Suqs * about the suitability of this software for any purpose. It is provided "as 12294113Sbapt * is" without express or implied warranty. 13241675Suqs * 14241675Suqs * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15241675Suqs * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16241675Suqs * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17241675Suqs * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18241675Suqs * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19241675Suqs * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20241675Suqs * OF THIS SOFTWARE. 21241675Suqs * 22275432Sbapt * $FreeBSD: head/sys/dev/drm2/drm_dp_helper.h 254817 2013-08-24 23:38:57Z dumbbell $ 23275432Sbapt */ 24275432Sbapt 25241675Suqs#ifndef _DRM_DP_HELPER_H_ 26241675Suqs#define _DRM_DP_HELPER_H_ 27241675Suqs 28241675Suqs/* 29241675Suqs * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 30275432Sbapt * DP and DPCD versions are independent. Differences from 1.0 are not noted, 31275432Sbapt * 1.0 devices basically don't exist in the wild. 32241675Suqs * 33241675Suqs * Abbreviations, in chronological order: 34241675Suqs * 35274880Sbapt * eDP: Embedded DisplayPort version 1 36241675Suqs * DPI: DisplayPort Interoperability Guideline v1.1a 37241675Suqs * 1.2: DisplayPort 1.2 38294113Sbapt * 39241675Suqs * 1.2 formally includes both eDP and DPI definitions. 40241675Suqs */ 41294113Sbapt 42294113Sbapt#define AUX_NATIVE_WRITE 0x8 43241675Suqs#define AUX_NATIVE_READ 0x9 44241675Suqs#define AUX_I2C_WRITE 0x0 45241675Suqs#define AUX_I2C_READ 0x1 46241675Suqs#define AUX_I2C_STATUS 0x2 47241675Suqs#define AUX_I2C_MOT 0x4 48241675Suqs 49241675Suqs#define AUX_NATIVE_REPLY_ACK (0x0 << 4) 50294113Sbapt#define AUX_NATIVE_REPLY_NACK (0x1 << 4) 51241675Suqs#define AUX_NATIVE_REPLY_DEFER (0x2 << 4) 52275432Sbapt#define AUX_NATIVE_REPLY_MASK (0x3 << 4) 53241675Suqs 54241675Suqs#define AUX_I2C_REPLY_ACK (0x0 << 6) 55241675Suqs#define AUX_I2C_REPLY_NACK (0x1 << 6) 56241675Suqs#define AUX_I2C_REPLY_DEFER (0x2 << 6) 57241675Suqs#define AUX_I2C_REPLY_MASK (0x3 << 6) 58241675Suqs 59274880Sbapt/* AUX CH addresses */ 60241675Suqs/* DPCD */ 61294113Sbapt#define DP_DPCD_REV 0x000 62241675Suqs 63294113Sbapt#define DP_MAX_LINK_RATE 0x001 64241675Suqs 65294113Sbapt#define DP_MAX_LANE_COUNT 0x002 66241675Suqs# define DP_MAX_LANE_COUNT_MASK 0x1f 67241675Suqs# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ 68241675Suqs# define DP_ENHANCED_FRAME_CAP (1 << 7) 69241675Suqs 70294113Sbapt#define DP_MAX_DOWNSPREAD 0x003 71241675Suqs# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 72274880Sbapt 73279527Sbapt#define DP_NORP 0x004 74279527Sbapt 75279527Sbapt#define DP_DOWNSTREAMPORT_PRESENT 0x005 76241675Suqs# define DP_DWN_STRM_PORT_PRESENT (1 << 0) 77241675Suqs# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 78241675Suqs/* 00b = DisplayPort */ 79241675Suqs/* 01b = Analog */ 80241675Suqs/* 10b = TMDS or HDMI */ 81241675Suqs/* 11b = Other */ 82241675Suqs# define DP_FORMAT_CONVERSION (1 << 3) 83241675Suqs# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ 84241675Suqs 85241675Suqs#define DP_MAIN_LINK_CHANNEL_CODING 0x006 86274880Sbapt 87241675Suqs#define DP_DOWN_STREAM_PORT_COUNT 0x007 88241675Suqs# define DP_PORT_COUNT_MASK 0x0f 89275432Sbapt# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ 90241675Suqs# define DP_OUI_SUPPORT (1 << 7) 91294113Sbapt 92294113Sbapt#define DP_I2C_SPEED_CAP 0x00c /* DPI */ 93294113Sbapt# define DP_I2C_SPEED_1K 0x01 94294113Sbapt# define DP_I2C_SPEED_5K 0x02 95294113Sbapt# define DP_I2C_SPEED_10K 0x04 96294113Sbapt# define DP_I2C_SPEED_100K 0x08 97294113Sbapt# define DP_I2C_SPEED_400K 0x10 98294113Sbapt# define DP_I2C_SPEED_1M 0x20 99241675Suqs 100294113Sbapt#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ 101274880Sbapt#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 102241675Suqs 103241675Suqs/* Multiple stream transport */ 104241675Suqs#define DP_MSTM_CAP 0x021 /* 1.2 */ 105241675Suqs# define DP_MST_CAP (1 << 0) 106241675Suqs 107241675Suqs#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 108241675Suqs# define DP_PSR_IS_SUPPORTED 1 109241675Suqs#define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 110241675Suqs# define DP_PSR_NO_TRAIN_ON_EXIT 1 111241675Suqs# define DP_PSR_SETUP_TIME_330 (0 << 1) 112294113Sbapt# define DP_PSR_SETUP_TIME_275 (1 << 1) 113294113Sbapt# define DP_PSR_SETUP_TIME_220 (2 << 1) 114294113Sbapt# define DP_PSR_SETUP_TIME_165 (3 << 1) 115294113Sbapt# define DP_PSR_SETUP_TIME_110 (4 << 1) 116294113Sbapt# define DP_PSR_SETUP_TIME_55 (5 << 1) 117294113Sbapt# define DP_PSR_SETUP_TIME_0 (6 << 1) 118294113Sbapt# define DP_PSR_SETUP_TIME_MASK (7 << 1) 119294113Sbapt# define DP_PSR_SETUP_TIME_SHIFT 1 120294113Sbapt 121294113Sbapt/* 122241675Suqs * 0x80-0x8f describe downstream port capabilities, but there are two layouts 123294113Sbapt * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, 124241675Suqs * each port's descriptor is one byte wide. If it was set, each port's is 125241675Suqs * four bytes wide, starting with the one byte from the base info. As of 126241675Suqs * DP interop v1.1a only VGA defines additional detail. 127294113Sbapt */ 128241675Suqs 129241675Suqs/* offset 0 */ 130294113Sbapt#define DP_DOWNSTREAM_PORT_0 0x80 131241675Suqs# define DP_DS_PORT_TYPE_MASK (7 << 0) 132241675Suqs# define DP_DS_PORT_TYPE_DP 0 133241675Suqs# define DP_DS_PORT_TYPE_VGA 1 134294113Sbapt# define DP_DS_PORT_TYPE_DVI 2 135241675Suqs# define DP_DS_PORT_TYPE_HDMI 3 136241675Suqs# define DP_DS_PORT_TYPE_NON_EDID 4 137294113Sbapt# define DP_DS_PORT_HPD (1 << 3) 138241675Suqs/* offset 1 for VGA is maximum megapixels per second / 8 */ 139241675Suqs/* offset 2 */ 140241675Suqs# define DP_DS_VGA_MAX_BPC_MASK (3 << 0) 141294113Sbapt# define DP_DS_VGA_8BPC 0 142241675Suqs# define DP_DS_VGA_10BPC 1 143241675Suqs# define DP_DS_VGA_12BPC 2 144294113Sbapt# define DP_DS_VGA_16BPC 3 145241675Suqs 146241675Suqs/* link configuration */ 147274880Sbapt#define DP_LINK_BW_SET 0x100 148294113Sbapt# define DP_LINK_BW_1_62 0x06 149274880Sbapt# define DP_LINK_BW_2_7 0x0a 150274880Sbapt# define DP_LINK_BW_5_4 0x14 /* 1.2 */ 151294113Sbapt 152274880Sbapt#define DP_LANE_COUNT_SET 0x101 153275432Sbapt# define DP_LANE_COUNT_MASK 0x0f 154274880Sbapt# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 155275432Sbapt 156294113Sbapt#define DP_TRAINING_PATTERN_SET 0x102 157294113Sbapt# define DP_TRAINING_PATTERN_DISABLE 0 158274880Sbapt# define DP_TRAINING_PATTERN_1 1 159274880Sbapt# define DP_TRAINING_PATTERN_2 2 160275432Sbapt# define DP_TRAINING_PATTERN_3 3 /* 1.2 */ 161274880Sbapt# define DP_TRAINING_PATTERN_MASK 0x3 162274880Sbapt 163274880Sbapt# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) 164274880Sbapt# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) 165279527Sbapt# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) 166279527Sbapt# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) 167279527Sbapt# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) 168279527Sbapt 169279527Sbapt# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 170279527Sbapt# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 171279527Sbapt 172294113Sbapt# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 173279527Sbapt# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 174279527Sbapt# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 175279527Sbapt# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 176279527Sbapt 177279527Sbapt#define DP_TRAINING_LANE0_SET 0x103 178279527Sbapt#define DP_TRAINING_LANE1_SET 0x104 179279527Sbapt#define DP_TRAINING_LANE2_SET 0x105 180241675Suqs#define DP_TRAINING_LANE3_SET 0x106 181241675Suqs 182241675Suqs# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 183241675Suqs# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 184294113Sbapt# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 185241675Suqs# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) 186241675Suqs# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) 187241675Suqs# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) 188241675Suqs# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) 189241675Suqs 190241675Suqs# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 191241675Suqs# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) 192241675Suqs# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) 193241675Suqs# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) 194241675Suqs# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) 195241675Suqs 196241675Suqs# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 197274880Sbapt# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 198241675Suqs 199241675Suqs#define DP_DOWNSPREAD_CTRL 0x107 200241675Suqs# define DP_SPREAD_AMP_0_5 (1 << 4) 201241675Suqs# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ 202241675Suqs 203241675Suqs#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 204241675Suqs# define DP_SET_ANSI_8B10B (1 << 0) 205241675Suqs 206241675Suqs#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ 207241675Suqs/* bitmask as for DP_I2C_SPEED_CAP */ 208241675Suqs 209241675Suqs#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ 210241675Suqs 211241675Suqs#define DP_MSTM_CTRL 0x111 /* 1.2 */ 212241675Suqs# define DP_MST_EN (1 << 0) 213241675Suqs# define DP_UP_REQ_EN (1 << 1) 214241675Suqs# define DP_UPSTREAM_IS_SRC (1 << 2) 215241675Suqs 216241675Suqs#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ 217241675Suqs# define DP_PSR_ENABLE (1 << 0) 218241675Suqs# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) 219294113Sbapt# define DP_PSR_CRC_VERIFICATION (1 << 2) 220241675Suqs# define DP_PSR_FRAME_CAPTURE (1 << 3) 221241675Suqs 222241675Suqs#define DP_SINK_COUNT 0x200 223241675Suqs/* prior to 1.2 bit 7 was reserved mbz */ 224241675Suqs# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 225241675Suqs# define DP_SINK_CP_READY (1 << 6) 226274880Sbapt 227241675Suqs#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 228241675Suqs# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 229241675Suqs# define DP_AUTOMATED_TEST_REQUEST (1 << 1) 230241675Suqs# define DP_CP_IRQ (1 << 2) 231241675Suqs# define DP_SINK_SPECIFIC_IRQ (1 << 6) 232294113Sbapt 233241675Suqs#define DP_LANE0_1_STATUS 0x202 234241675Suqs#define DP_LANE2_3_STATUS 0x203 235241675Suqs# define DP_LANE_CR_DONE (1 << 0) 236241675Suqs# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 237241675Suqs# define DP_LANE_SYMBOL_LOCKED (1 << 2) 238275432Sbapt 239294113Sbapt#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 240275432Sbapt DP_LANE_CHANNEL_EQ_DONE | \ 241274880Sbapt DP_LANE_SYMBOL_LOCKED) 242294113Sbapt 243241675Suqs#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 244275432Sbapt 245294113Sbapt#define DP_INTERLANE_ALIGN_DONE (1 << 0) 246275432Sbapt#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 247274880Sbapt#define DP_LINK_STATUS_UPDATED (1 << 7) 248294113Sbapt 249241675Suqs#define DP_SINK_STATUS 0x205 250275432Sbapt 251294113Sbapt#define DP_RECEIVE_PORT_0_STATUS (1 << 0) 252275432Sbapt#define DP_RECEIVE_PORT_1_STATUS (1 << 1) 253294113Sbapt 254274880Sbapt#define DP_ADJUST_REQUEST_LANE0_1 0x206 255294113Sbapt#define DP_ADJUST_REQUEST_LANE2_3 0x207 256241675Suqs# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 257274880Sbapt# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 258294113Sbapt# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 259241675Suqs# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 260275432Sbapt# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 261275432Sbapt# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 262294113Sbapt# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 263241675Suqs# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 264275432Sbapt 265275432Sbapt#define DP_TEST_REQUEST 0x218 266241675Suqs# define DP_TEST_LINK_TRAINING (1 << 0) 267294113Sbapt# define DP_TEST_LINK_PATTERN (1 << 1) 268241675Suqs# define DP_TEST_LINK_EDID_READ (1 << 2) 269241675Suqs# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 270275432Sbapt 271275432Sbapt#define DP_TEST_LINK_RATE 0x219 272275432Sbapt# define DP_LINK_RATE_162 (0x6) 273275432Sbapt# define DP_LINK_RATE_27 (0xa) 274275432Sbapt 275275432Sbapt#define DP_TEST_LANE_COUNT 0x220 276275432Sbapt 277275432Sbapt#define DP_TEST_PATTERN 0x221 278275432Sbapt 279275432Sbapt#define DP_TEST_RESPONSE 0x260 280275432Sbapt# define DP_TEST_ACK (1 << 0) 281275432Sbapt# define DP_TEST_NAK (1 << 1) 282275432Sbapt# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 283275432Sbapt 284275432Sbapt#define DP_SOURCE_OUI 0x300 285275432Sbapt#define DP_SINK_OUI 0x400 286275432Sbapt#define DP_BRANCH_OUI 0x500 287275432Sbapt 288275432Sbapt#define DP_SET_POWER 0x600 289275432Sbapt# define DP_SET_POWER_D0 0x1 290275432Sbapt# define DP_SET_POWER_D3 0x2 291275432Sbapt 292275432Sbapt#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 293275432Sbapt# define DP_PSR_LINK_CRC_ERROR (1 << 0) 294275432Sbapt# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 295275432Sbapt 296275432Sbapt#define DP_PSR_ESI 0x2007 /* XXX 1.2? */ 297275432Sbapt# define DP_PSR_CAPS_CHANGE (1 << 0) 298275432Sbapt 299275432Sbapt#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ 300275432Sbapt# define DP_PSR_SINK_INACTIVE 0 301275432Sbapt# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 302275432Sbapt# define DP_PSR_SINK_ACTIVE_RFB 2 303275432Sbapt# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 304275432Sbapt# define DP_PSR_SINK_ACTIVE_RESYNC 4 305275432Sbapt# define DP_PSR_SINK_INTERNAL_ERROR 7 306275432Sbapt# define DP_PSR_SINK_STATE_MASK 0x07 307275432Sbapt 308275432Sbapt#define MODE_I2C_START 1 309275432Sbapt#define MODE_I2C_WRITE 2 310275432Sbapt#define MODE_I2C_READ 4 311275432Sbapt#define MODE_I2C_STOP 8 312275432Sbapt 313275432Sbaptstruct iic_dp_aux_data { 314275432Sbapt bool running; 315275432Sbapt u16 address; 316275432Sbapt void *priv; 317275432Sbapt int (*aux_ch)(device_t adapter, int mode, uint8_t write_byte, 318275432Sbapt uint8_t *read_byte); 319275432Sbapt device_t port; 320275432Sbapt}; 321275432Sbapt 322275432Sbaptint iic_dp_aux_add_bus(device_t dev, const char *name, 323275432Sbapt int (*ch)(device_t idev, int mode, uint8_t write_byte, uint8_t *read_byte), 324275432Sbapt void *priv, device_t *bus, device_t *adapter); 325275432Sbapt 326275432Sbapt 327275432Sbapt#define DP_LINK_STATUS_SIZE 6 328275432Sbaptbool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], 329275432Sbapt int lane_count); 330275432Sbaptbool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], 331275432Sbapt int lane_count); 332275432Sbaptu8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], 333275432Sbapt int lane); 334275432Sbaptu8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], 335275432Sbapt int lane); 336275432Sbapt 337275432Sbapt#define DP_RECEIVER_CAP_SIZE 0xf 338275432Sbaptvoid drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); 339275432Sbaptvoid drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); 340275432Sbapt 341275432Sbaptu8 drm_dp_link_rate_to_bw_code(int link_rate); 342294113Sbaptint drm_dp_bw_code_to_link_rate(u8 link_bw); 343294113Sbapt 344275432Sbaptstatic inline int 345275432Sbaptdrm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) 346275432Sbapt{ 347241675Suqs return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 348241675Suqs} 349241675Suqs 350241675Suqsstatic inline u8 351241675Suqsdrm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE]) 352274880Sbapt{ 353274880Sbapt return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 354274880Sbapt} 355274880Sbapt 356274880Sbapt#endif /* _DRM_DP_HELPER_H_ */ 357294113Sbapt