1235783Skib/* 2235783Skib * Copyright �� 2008 Keith Packard 3235783Skib * 4235783Skib * Permission to use, copy, modify, distribute, and sell this software and its 5235783Skib * documentation for any purpose is hereby granted without fee, provided that 6235783Skib * the above copyright notice appear in all copies and that both that copyright 7235783Skib * notice and this permission notice appear in supporting documentation, and 8235783Skib * that the name of the copyright holders not be used in advertising or 9235783Skib * publicity pertaining to distribution of the software without specific, 10235783Skib * written prior permission. The copyright holders make no representations 11235783Skib * about the suitability of this software for any purpose. It is provided "as 12235783Skib * is" without express or implied warranty. 13235783Skib * 14235783Skib * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15235783Skib * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16235783Skib * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17235783Skib * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18235783Skib * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19235783Skib * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20235783Skib * OF THIS SOFTWARE. 21235783Skib * 22235783Skib * $FreeBSD: releng/10.3/sys/dev/drm2/drm_dp_helper.h 254817 2013-08-24 23:38:57Z dumbbell $ 23235783Skib */ 24235783Skib 25235783Skib#ifndef _DRM_DP_HELPER_H_ 26235783Skib#define _DRM_DP_HELPER_H_ 27235783Skib 28254817Sdumbbell/* 29254817Sdumbbell * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 30254817Sdumbbell * DP and DPCD versions are independent. Differences from 1.0 are not noted, 31254817Sdumbbell * 1.0 devices basically don't exist in the wild. 32254817Sdumbbell * 33254817Sdumbbell * Abbreviations, in chronological order: 34254817Sdumbbell * 35254817Sdumbbell * eDP: Embedded DisplayPort version 1 36254817Sdumbbell * DPI: DisplayPort Interoperability Guideline v1.1a 37254817Sdumbbell * 1.2: DisplayPort 1.2 38254817Sdumbbell * 39254817Sdumbbell * 1.2 formally includes both eDP and DPI definitions. 40254817Sdumbbell */ 41235783Skib 42235783Skib#define AUX_NATIVE_WRITE 0x8 43235783Skib#define AUX_NATIVE_READ 0x9 44235783Skib#define AUX_I2C_WRITE 0x0 45235783Skib#define AUX_I2C_READ 0x1 46235783Skib#define AUX_I2C_STATUS 0x2 47235783Skib#define AUX_I2C_MOT 0x4 48235783Skib 49235783Skib#define AUX_NATIVE_REPLY_ACK (0x0 << 4) 50235783Skib#define AUX_NATIVE_REPLY_NACK (0x1 << 4) 51235783Skib#define AUX_NATIVE_REPLY_DEFER (0x2 << 4) 52235783Skib#define AUX_NATIVE_REPLY_MASK (0x3 << 4) 53235783Skib 54235783Skib#define AUX_I2C_REPLY_ACK (0x0 << 6) 55235783Skib#define AUX_I2C_REPLY_NACK (0x1 << 6) 56235783Skib#define AUX_I2C_REPLY_DEFER (0x2 << 6) 57235783Skib#define AUX_I2C_REPLY_MASK (0x3 << 6) 58235783Skib 59235783Skib/* AUX CH addresses */ 60235783Skib/* DPCD */ 61235783Skib#define DP_DPCD_REV 0x000 62235783Skib 63235783Skib#define DP_MAX_LINK_RATE 0x001 64235783Skib 65235783Skib#define DP_MAX_LANE_COUNT 0x002 66235783Skib# define DP_MAX_LANE_COUNT_MASK 0x1f 67254817Sdumbbell# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ 68235783Skib# define DP_ENHANCED_FRAME_CAP (1 << 7) 69235783Skib 70235783Skib#define DP_MAX_DOWNSPREAD 0x003 71235783Skib# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 72235783Skib 73235783Skib#define DP_NORP 0x004 74235783Skib 75235783Skib#define DP_DOWNSTREAMPORT_PRESENT 0x005 76235783Skib# define DP_DWN_STRM_PORT_PRESENT (1 << 0) 77235783Skib# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 78235783Skib/* 00b = DisplayPort */ 79235783Skib/* 01b = Analog */ 80235783Skib/* 10b = TMDS or HDMI */ 81235783Skib/* 11b = Other */ 82235783Skib# define DP_FORMAT_CONVERSION (1 << 3) 83254817Sdumbbell# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ 84235783Skib 85235783Skib#define DP_MAIN_LINK_CHANNEL_CODING 0x006 86235783Skib 87254817Sdumbbell#define DP_DOWN_STREAM_PORT_COUNT 0x007 88254817Sdumbbell# define DP_PORT_COUNT_MASK 0x0f 89254817Sdumbbell# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ 90254817Sdumbbell# define DP_OUI_SUPPORT (1 << 7) 91235783Skib 92254817Sdumbbell#define DP_I2C_SPEED_CAP 0x00c /* DPI */ 93254817Sdumbbell# define DP_I2C_SPEED_1K 0x01 94254817Sdumbbell# define DP_I2C_SPEED_5K 0x02 95254817Sdumbbell# define DP_I2C_SPEED_10K 0x04 96254817Sdumbbell# define DP_I2C_SPEED_100K 0x08 97254817Sdumbbell# define DP_I2C_SPEED_400K 0x10 98254817Sdumbbell# define DP_I2C_SPEED_1M 0x20 99254817Sdumbbell 100254817Sdumbbell#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ 101254817Sdumbbell#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 102254817Sdumbbell 103254817Sdumbbell/* Multiple stream transport */ 104254817Sdumbbell#define DP_MSTM_CAP 0x021 /* 1.2 */ 105254817Sdumbbell# define DP_MST_CAP (1 << 0) 106254817Sdumbbell 107254817Sdumbbell#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 108235783Skib# define DP_PSR_IS_SUPPORTED 1 109254817Sdumbbell#define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 110235783Skib# define DP_PSR_NO_TRAIN_ON_EXIT 1 111235783Skib# define DP_PSR_SETUP_TIME_330 (0 << 1) 112235783Skib# define DP_PSR_SETUP_TIME_275 (1 << 1) 113235783Skib# define DP_PSR_SETUP_TIME_220 (2 << 1) 114235783Skib# define DP_PSR_SETUP_TIME_165 (3 << 1) 115235783Skib# define DP_PSR_SETUP_TIME_110 (4 << 1) 116235783Skib# define DP_PSR_SETUP_TIME_55 (5 << 1) 117235783Skib# define DP_PSR_SETUP_TIME_0 (6 << 1) 118235783Skib# define DP_PSR_SETUP_TIME_MASK (7 << 1) 119235783Skib# define DP_PSR_SETUP_TIME_SHIFT 1 120235783Skib 121254817Sdumbbell/* 122254817Sdumbbell * 0x80-0x8f describe downstream port capabilities, but there are two layouts 123254817Sdumbbell * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, 124254817Sdumbbell * each port's descriptor is one byte wide. If it was set, each port's is 125254817Sdumbbell * four bytes wide, starting with the one byte from the base info. As of 126254817Sdumbbell * DP interop v1.1a only VGA defines additional detail. 127254817Sdumbbell */ 128254817Sdumbbell 129254817Sdumbbell/* offset 0 */ 130254817Sdumbbell#define DP_DOWNSTREAM_PORT_0 0x80 131254817Sdumbbell# define DP_DS_PORT_TYPE_MASK (7 << 0) 132254817Sdumbbell# define DP_DS_PORT_TYPE_DP 0 133254817Sdumbbell# define DP_DS_PORT_TYPE_VGA 1 134254817Sdumbbell# define DP_DS_PORT_TYPE_DVI 2 135254817Sdumbbell# define DP_DS_PORT_TYPE_HDMI 3 136254817Sdumbbell# define DP_DS_PORT_TYPE_NON_EDID 4 137254817Sdumbbell# define DP_DS_PORT_HPD (1 << 3) 138254817Sdumbbell/* offset 1 for VGA is maximum megapixels per second / 8 */ 139254817Sdumbbell/* offset 2 */ 140254817Sdumbbell# define DP_DS_VGA_MAX_BPC_MASK (3 << 0) 141254817Sdumbbell# define DP_DS_VGA_8BPC 0 142254817Sdumbbell# define DP_DS_VGA_10BPC 1 143254817Sdumbbell# define DP_DS_VGA_12BPC 2 144254817Sdumbbell# define DP_DS_VGA_16BPC 3 145254817Sdumbbell 146235783Skib/* link configuration */ 147235783Skib#define DP_LINK_BW_SET 0x100 148235783Skib# define DP_LINK_BW_1_62 0x06 149235783Skib# define DP_LINK_BW_2_7 0x0a 150254817Sdumbbell# define DP_LINK_BW_5_4 0x14 /* 1.2 */ 151235783Skib 152235783Skib#define DP_LANE_COUNT_SET 0x101 153235783Skib# define DP_LANE_COUNT_MASK 0x0f 154235783Skib# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 155235783Skib 156235783Skib#define DP_TRAINING_PATTERN_SET 0x102 157235783Skib# define DP_TRAINING_PATTERN_DISABLE 0 158235783Skib# define DP_TRAINING_PATTERN_1 1 159235783Skib# define DP_TRAINING_PATTERN_2 2 160254817Sdumbbell# define DP_TRAINING_PATTERN_3 3 /* 1.2 */ 161235783Skib# define DP_TRAINING_PATTERN_MASK 0x3 162235783Skib 163235783Skib# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) 164235783Skib# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) 165235783Skib# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) 166235783Skib# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) 167235783Skib# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) 168235783Skib 169235783Skib# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 170235783Skib# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 171235783Skib 172235783Skib# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 173235783Skib# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 174235783Skib# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 175235783Skib# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 176235783Skib 177235783Skib#define DP_TRAINING_LANE0_SET 0x103 178235783Skib#define DP_TRAINING_LANE1_SET 0x104 179235783Skib#define DP_TRAINING_LANE2_SET 0x105 180235783Skib#define DP_TRAINING_LANE3_SET 0x106 181235783Skib 182235783Skib# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 183235783Skib# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 184235783Skib# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 185235783Skib# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) 186235783Skib# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) 187235783Skib# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) 188235783Skib# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) 189235783Skib 190235783Skib# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 191235783Skib# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) 192235783Skib# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) 193235783Skib# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) 194235783Skib# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) 195235783Skib 196235783Skib# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 197235783Skib# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 198235783Skib 199235783Skib#define DP_DOWNSPREAD_CTRL 0x107 200235783Skib# define DP_SPREAD_AMP_0_5 (1 << 4) 201254817Sdumbbell# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ 202235783Skib 203235783Skib#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 204235783Skib# define DP_SET_ANSI_8B10B (1 << 0) 205235783Skib 206254817Sdumbbell#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ 207254817Sdumbbell/* bitmask as for DP_I2C_SPEED_CAP */ 208254817Sdumbbell 209254817Sdumbbell#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ 210254817Sdumbbell 211254817Sdumbbell#define DP_MSTM_CTRL 0x111 /* 1.2 */ 212254817Sdumbbell# define DP_MST_EN (1 << 0) 213254817Sdumbbell# define DP_UP_REQ_EN (1 << 1) 214254817Sdumbbell# define DP_UPSTREAM_IS_SRC (1 << 2) 215254817Sdumbbell 216254817Sdumbbell#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ 217235783Skib# define DP_PSR_ENABLE (1 << 0) 218235783Skib# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) 219235783Skib# define DP_PSR_CRC_VERIFICATION (1 << 2) 220235783Skib# define DP_PSR_FRAME_CAPTURE (1 << 3) 221235783Skib 222254817Sdumbbell#define DP_SINK_COUNT 0x200 223254817Sdumbbell/* prior to 1.2 bit 7 was reserved mbz */ 224254817Sdumbbell# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 225254817Sdumbbell# define DP_SINK_CP_READY (1 << 6) 226254817Sdumbbell 227235783Skib#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 228235783Skib# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 229235783Skib# define DP_AUTOMATED_TEST_REQUEST (1 << 1) 230235783Skib# define DP_CP_IRQ (1 << 2) 231235783Skib# define DP_SINK_SPECIFIC_IRQ (1 << 6) 232235783Skib 233235783Skib#define DP_LANE0_1_STATUS 0x202 234235783Skib#define DP_LANE2_3_STATUS 0x203 235235783Skib# define DP_LANE_CR_DONE (1 << 0) 236235783Skib# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 237235783Skib# define DP_LANE_SYMBOL_LOCKED (1 << 2) 238235783Skib 239235783Skib#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 240235783Skib DP_LANE_CHANNEL_EQ_DONE | \ 241235783Skib DP_LANE_SYMBOL_LOCKED) 242235783Skib 243235783Skib#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 244235783Skib 245235783Skib#define DP_INTERLANE_ALIGN_DONE (1 << 0) 246235783Skib#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 247235783Skib#define DP_LINK_STATUS_UPDATED (1 << 7) 248235783Skib 249235783Skib#define DP_SINK_STATUS 0x205 250235783Skib 251235783Skib#define DP_RECEIVE_PORT_0_STATUS (1 << 0) 252235783Skib#define DP_RECEIVE_PORT_1_STATUS (1 << 1) 253235783Skib 254235783Skib#define DP_ADJUST_REQUEST_LANE0_1 0x206 255235783Skib#define DP_ADJUST_REQUEST_LANE2_3 0x207 256235783Skib# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 257235783Skib# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 258235783Skib# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 259235783Skib# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 260235783Skib# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 261235783Skib# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 262235783Skib# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 263235783Skib# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 264235783Skib 265235783Skib#define DP_TEST_REQUEST 0x218 266235783Skib# define DP_TEST_LINK_TRAINING (1 << 0) 267235783Skib# define DP_TEST_LINK_PATTERN (1 << 1) 268235783Skib# define DP_TEST_LINK_EDID_READ (1 << 2) 269235783Skib# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 270235783Skib 271235783Skib#define DP_TEST_LINK_RATE 0x219 272235783Skib# define DP_LINK_RATE_162 (0x6) 273235783Skib# define DP_LINK_RATE_27 (0xa) 274235783Skib 275235783Skib#define DP_TEST_LANE_COUNT 0x220 276235783Skib 277235783Skib#define DP_TEST_PATTERN 0x221 278235783Skib 279235783Skib#define DP_TEST_RESPONSE 0x260 280235783Skib# define DP_TEST_ACK (1 << 0) 281235783Skib# define DP_TEST_NAK (1 << 1) 282235783Skib# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 283235783Skib 284254817Sdumbbell#define DP_SOURCE_OUI 0x300 285254817Sdumbbell#define DP_SINK_OUI 0x400 286254817Sdumbbell#define DP_BRANCH_OUI 0x500 287254817Sdumbbell 288235783Skib#define DP_SET_POWER 0x600 289235783Skib# define DP_SET_POWER_D0 0x1 290235783Skib# define DP_SET_POWER_D3 0x2 291235783Skib 292254817Sdumbbell#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 293235783Skib# define DP_PSR_LINK_CRC_ERROR (1 << 0) 294235783Skib# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 295235783Skib 296254817Sdumbbell#define DP_PSR_ESI 0x2007 /* XXX 1.2? */ 297235783Skib# define DP_PSR_CAPS_CHANGE (1 << 0) 298235783Skib 299254817Sdumbbell#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ 300235783Skib# define DP_PSR_SINK_INACTIVE 0 301235783Skib# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 302235783Skib# define DP_PSR_SINK_ACTIVE_RFB 2 303235783Skib# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 304235783Skib# define DP_PSR_SINK_ACTIVE_RESYNC 4 305235783Skib# define DP_PSR_SINK_INTERNAL_ERROR 7 306235783Skib# define DP_PSR_SINK_STATE_MASK 0x07 307235783Skib 308235783Skib#define MODE_I2C_START 1 309235783Skib#define MODE_I2C_WRITE 2 310235783Skib#define MODE_I2C_READ 4 311235783Skib#define MODE_I2C_STOP 8 312235783Skib 313235783Skibstruct iic_dp_aux_data { 314235783Skib bool running; 315235783Skib u16 address; 316235783Skib void *priv; 317235783Skib int (*aux_ch)(device_t adapter, int mode, uint8_t write_byte, 318235783Skib uint8_t *read_byte); 319235783Skib device_t port; 320235783Skib}; 321235783Skib 322235783Skibint iic_dp_aux_add_bus(device_t dev, const char *name, 323235783Skib int (*ch)(device_t idev, int mode, uint8_t write_byte, uint8_t *read_byte), 324235783Skib void *priv, device_t *bus, device_t *adapter); 325235783Skib 326254817Sdumbbell 327254817Sdumbbell#define DP_LINK_STATUS_SIZE 6 328254817Sdumbbellbool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE], 329254817Sdumbbell int lane_count); 330254817Sdumbbellbool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], 331254817Sdumbbell int lane_count); 332254817Sdumbbellu8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], 333254817Sdumbbell int lane); 334254817Sdumbbellu8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], 335254817Sdumbbell int lane); 336254817Sdumbbell 337254817Sdumbbell#define DP_RECEIVER_CAP_SIZE 0xf 338254817Sdumbbellvoid drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); 339254817Sdumbbellvoid drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); 340254817Sdumbbell 341254817Sdumbbellu8 drm_dp_link_rate_to_bw_code(int link_rate); 342254817Sdumbbellint drm_dp_bw_code_to_link_rate(u8 link_bw); 343254817Sdumbbell 344254817Sdumbbellstatic inline int 345254817Sdumbbelldrm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) 346254817Sdumbbell{ 347254817Sdumbbell return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 348254817Sdumbbell} 349254817Sdumbbell 350254817Sdumbbellstatic inline u8 351254817Sdumbbelldrm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE]) 352254817Sdumbbell{ 353254817Sdumbbell return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 354254817Sdumbbell} 355254817Sdumbbell 356235783Skib#endif /* _DRM_DP_HELPER_H_ */ 357