1235783Skib/** 2235783Skib * \file drm.h 3235783Skib * Header for the Direct Rendering Manager 4235783Skib * 5235783Skib * \author Rickard E. (Rik) Faith <faith@valinux.com> 6235783Skib * 7235783Skib * \par Acknowledgments: 8235783Skib * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. 9235783Skib */ 10235783Skib 11235783Skib/*- 12235783Skib * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 13235783Skib * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 14235783Skib * All rights reserved. 15235783Skib * 16235783Skib * Permission is hereby granted, free of charge, to any person obtaining a 17235783Skib * copy of this software and associated documentation files (the "Software"), 18235783Skib * to deal in the Software without restriction, including without limitation 19235783Skib * the rights to use, copy, modify, merge, publish, distribute, sublicense, 20235783Skib * and/or sell copies of the Software, and to permit persons to whom the 21235783Skib * Software is furnished to do so, subject to the following conditions: 22235783Skib * 23235783Skib * The above copyright notice and this permission notice (including the next 24235783Skib * paragraph) shall be included in all copies or substantial portions of the 25235783Skib * Software. 26235783Skib * 27235783Skib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28235783Skib * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29235783Skib * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 30235783Skib * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 31235783Skib * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 32235783Skib * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 33235783Skib * OTHER DEALINGS IN THE SOFTWARE. 34235783Skib */ 35235783Skib 36235783Skib#include <sys/cdefs.h> 37235783Skib__FBSDID("$FreeBSD: releng/10.3/sys/dev/drm2/drm.h 282199 2015-04-28 19:35:05Z dumbbell $"); 38235783Skib 39235783Skib#ifndef _DRM_H_ 40235783Skib#define _DRM_H_ 41235783Skib 42282199Sdumbbell#if defined(__linux__) 43235783Skib 44282199Sdumbbell#include <linux/types.h> 45282199Sdumbbell#include <asm/ioctl.h> 46282199Sdumbbelltypedef unsigned int drm_handle_t; 47235783Skib 48282199Sdumbbell#else /* One of the BSDs */ 49282199Sdumbbell 50235783Skib#include <sys/ioccom.h> 51282199Sdumbbell#include <sys/types.h> 52282199Sdumbbelltypedef int8_t __s8; 53282199Sdumbbelltypedef uint8_t __u8; 54282199Sdumbbelltypedef int16_t __s16; 55282199Sdumbbelltypedef uint16_t __u16; 56282199Sdumbbelltypedef int32_t __s32; 57282199Sdumbbelltypedef uint32_t __u32; 58282199Sdumbbelltypedef int64_t __s64; 59282199Sdumbbelltypedef uint64_t __u64; 60282199Sdumbbelltypedef unsigned long drm_handle_t; 61235783Skib 62282199Sdumbbell#include <dev/drm2/drm_os_freebsd.h> 63235783Skib#endif 64235783Skib 65235783Skib#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 66235783Skib#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 67235783Skib#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 68235783Skib#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 69235783Skib 70235783Skib#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 71235783Skib#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 72235783Skib#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 73235783Skib#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 74235783Skib#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 75235783Skib 76282199Sdumbbelltypedef unsigned int drm_context_t; 77235783Skibtypedef unsigned int drm_drawable_t; 78282199Sdumbbelltypedef unsigned int drm_magic_t; 79235783Skib 80235783Skib/** 81235783Skib * Cliprect. 82235783Skib * 83282199Sdumbbell * \warning: If you change this structure, make sure you change 84235783Skib * XF86DRIClipRectRec in the server as well 85235783Skib * 86235783Skib * \note KW: Actually it's illegal to change either for 87235783Skib * backwards-compatibility reasons. 88235783Skib */ 89235783Skibstruct drm_clip_rect { 90235783Skib unsigned short x1; 91235783Skib unsigned short y1; 92235783Skib unsigned short x2; 93235783Skib unsigned short y2; 94235783Skib}; 95235783Skib 96235783Skib/** 97282199Sdumbbell * Drawable information. 98282199Sdumbbell */ 99282199Sdumbbellstruct drm_drawable_info { 100282199Sdumbbell unsigned int num_rects; 101282199Sdumbbell struct drm_clip_rect *rects; 102282199Sdumbbell}; 103282199Sdumbbell 104282199Sdumbbell/** 105235783Skib * Texture region, 106235783Skib */ 107235783Skibstruct drm_tex_region { 108235783Skib unsigned char next; 109235783Skib unsigned char prev; 110235783Skib unsigned char in_use; 111235783Skib unsigned char padding; 112235783Skib unsigned int age; 113235783Skib}; 114235783Skib 115235783Skib/** 116235783Skib * Hardware lock. 117235783Skib * 118235783Skib * The lock structure is a simple cache-line aligned integer. To avoid 119235783Skib * processor bus contention on a multiprocessor system, there should not be any 120235783Skib * other data stored in the same cache line. 121235783Skib */ 122235783Skibstruct drm_hw_lock { 123235783Skib __volatile__ unsigned int lock; /**< lock variable */ 124235783Skib char padding[60]; /**< Pad to cache line */ 125235783Skib}; 126235783Skib 127235783Skib/** 128235783Skib * DRM_IOCTL_VERSION ioctl argument type. 129235783Skib * 130235783Skib * \sa drmGetVersion(). 131235783Skib */ 132235783Skibstruct drm_version { 133235783Skib int version_major; /**< Major version */ 134235783Skib int version_minor; /**< Minor version */ 135235783Skib int version_patchlevel; /**< Patch level */ 136282199Sdumbbell size_t name_len; /**< Length of name buffer */ 137282199Sdumbbell char __user *name; /**< Name of driver */ 138282199Sdumbbell size_t date_len; /**< Length of date buffer */ 139282199Sdumbbell char __user *date; /**< User-space buffer to hold date */ 140282199Sdumbbell size_t desc_len; /**< Length of desc buffer */ 141282199Sdumbbell char __user *desc; /**< User-space buffer to hold desc */ 142235783Skib}; 143235783Skib 144235783Skib/** 145235783Skib * DRM_IOCTL_GET_UNIQUE ioctl argument type. 146235783Skib * 147235783Skib * \sa drmGetBusid() and drmSetBusId(). 148235783Skib */ 149235783Skibstruct drm_unique { 150282199Sdumbbell size_t unique_len; /**< Length of unique */ 151282199Sdumbbell char __user *unique; /**< Unique name for driver instantiation */ 152235783Skib}; 153235783Skib 154235783Skibstruct drm_list { 155235783Skib int count; /**< Length of user-space structures */ 156235783Skib struct drm_version __user *version; 157235783Skib}; 158235783Skib 159235783Skibstruct drm_block { 160235783Skib int unused; 161235783Skib}; 162235783Skib 163235783Skib/** 164235783Skib * DRM_IOCTL_CONTROL ioctl argument type. 165235783Skib * 166235783Skib * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 167235783Skib */ 168235783Skibstruct drm_control { 169235783Skib enum { 170235783Skib DRM_ADD_COMMAND, 171235783Skib DRM_RM_COMMAND, 172235783Skib DRM_INST_HANDLER, 173235783Skib DRM_UNINST_HANDLER 174235783Skib } func; 175235783Skib int irq; 176235783Skib}; 177235783Skib 178235783Skib/** 179235783Skib * Type of memory to map. 180235783Skib */ 181235783Skibenum drm_map_type { 182235783Skib _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 183235783Skib _DRM_REGISTERS = 1, /**< no caching, no core dump */ 184235783Skib _DRM_SHM = 2, /**< shared, cached */ 185235783Skib _DRM_AGP = 3, /**< AGP/GART */ 186235783Skib _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 187235783Skib _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ 188282199Sdumbbell _DRM_GEM = 6, /**< GEM object */ 189235783Skib}; 190235783Skib 191235783Skib/** 192235783Skib * Memory mapping flags. 193235783Skib */ 194235783Skibenum drm_map_flags { 195235783Skib _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 196235783Skib _DRM_READ_ONLY = 0x02, 197235783Skib _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 198235783Skib _DRM_KERNEL = 0x08, /**< kernel requires access */ 199235783Skib _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 200235783Skib _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 201235783Skib _DRM_REMOVABLE = 0x40, /**< Removable mapping */ 202235783Skib _DRM_DRIVER = 0x80 /**< Managed by driver */ 203235783Skib}; 204235783Skib 205235783Skibstruct drm_ctx_priv_map { 206235783Skib unsigned int ctx_id; /**< Context requesting private mapping */ 207235783Skib void *handle; /**< Handle of map */ 208235783Skib}; 209235783Skib 210235783Skib/** 211235783Skib * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 212235783Skib * argument type. 213235783Skib * 214235783Skib * \sa drmAddMap(). 215235783Skib */ 216235783Skibstruct drm_map { 217235783Skib unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 218235783Skib unsigned long size; /**< Requested physical size (bytes) */ 219235783Skib enum drm_map_type type; /**< Type of memory to map */ 220235783Skib enum drm_map_flags flags; /**< Flags */ 221235783Skib void *handle; /**< User-space: "Handle" to pass to mmap() */ 222235783Skib /**< Kernel-space: kernel-virtual address */ 223235783Skib int mtrr; /**< MTRR slot used */ 224235783Skib /* Private data */ 225235783Skib}; 226235783Skib 227235783Skib/** 228235783Skib * DRM_IOCTL_GET_CLIENT ioctl argument type. 229235783Skib */ 230235783Skibstruct drm_client { 231235783Skib int idx; /**< Which client desired? */ 232235783Skib int auth; /**< Is client authenticated? */ 233235783Skib unsigned long pid; /**< Process ID */ 234235783Skib unsigned long uid; /**< User ID */ 235235783Skib unsigned long magic; /**< Magic */ 236235783Skib unsigned long iocs; /**< Ioctl count */ 237235783Skib}; 238235783Skib 239235783Skibenum drm_stat_type { 240235783Skib _DRM_STAT_LOCK, 241235783Skib _DRM_STAT_OPENS, 242235783Skib _DRM_STAT_CLOSES, 243235783Skib _DRM_STAT_IOCTLS, 244235783Skib _DRM_STAT_LOCKS, 245235783Skib _DRM_STAT_UNLOCKS, 246235783Skib _DRM_STAT_VALUE, /**< Generic value */ 247235783Skib _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 248235783Skib _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 249235783Skib 250235783Skib _DRM_STAT_IRQ, /**< IRQ */ 251235783Skib _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 252235783Skib _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 253235783Skib _DRM_STAT_DMA, /**< DMA */ 254235783Skib _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 255235783Skib _DRM_STAT_MISSED /**< Missed DMA opportunity */ 256235783Skib /* Add to the *END* of the list */ 257235783Skib}; 258235783Skib 259235783Skib/** 260235783Skib * DRM_IOCTL_GET_STATS ioctl argument type. 261235783Skib */ 262235783Skibstruct drm_stats { 263235783Skib unsigned long count; 264235783Skib struct { 265235783Skib unsigned long value; 266235783Skib enum drm_stat_type type; 267235783Skib } data[15]; 268235783Skib}; 269235783Skib 270235783Skib/** 271235783Skib * Hardware locking flags. 272235783Skib */ 273235783Skibenum drm_lock_flags { 274235783Skib _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 275235783Skib _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 276235783Skib _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 277235783Skib _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 278235783Skib /* These *HALT* flags aren't supported yet 279235783Skib -- they will be used to support the 280235783Skib full-screen DGA-like mode. */ 281235783Skib _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 282235783Skib _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 283235783Skib}; 284235783Skib 285235783Skib/** 286235783Skib * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 287235783Skib * 288235783Skib * \sa drmGetLock() and drmUnlock(). 289235783Skib */ 290235783Skibstruct drm_lock { 291235783Skib int context; 292235783Skib enum drm_lock_flags flags; 293235783Skib}; 294235783Skib 295235783Skib/** 296235783Skib * DMA flags 297235783Skib * 298235783Skib * \warning 299235783Skib * These values \e must match xf86drm.h. 300235783Skib * 301235783Skib * \sa drm_dma. 302235783Skib */ 303235783Skibenum drm_dma_flags { 304235783Skib /* Flags for DMA buffer dispatch */ 305235783Skib _DRM_DMA_BLOCK = 0x01, /**< 306235783Skib * Block until buffer dispatched. 307235783Skib * 308235783Skib * \note The buffer may not yet have 309235783Skib * been processed by the hardware -- 310235783Skib * getting a hardware lock with the 311235783Skib * hardware quiescent will ensure 312235783Skib * that the buffer has been 313235783Skib * processed. 314235783Skib */ 315235783Skib _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 316235783Skib _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 317235783Skib 318235783Skib /* Flags for DMA buffer request */ 319235783Skib _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 320235783Skib _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 321235783Skib _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 322235783Skib}; 323235783Skib 324235783Skib/** 325235783Skib * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 326235783Skib * 327235783Skib * \sa drmAddBufs(). 328235783Skib */ 329235783Skibstruct drm_buf_desc { 330235783Skib int count; /**< Number of buffers of this size */ 331235783Skib int size; /**< Size in bytes */ 332235783Skib int low_mark; /**< Low water mark */ 333235783Skib int high_mark; /**< High water mark */ 334235783Skib enum { 335235783Skib _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 336235783Skib _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 337282199Sdumbbell _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 338282199Sdumbbell _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ 339235783Skib _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ 340235783Skib } flags; 341235783Skib unsigned long agp_start; /**< 342235783Skib * Start address of where the AGP buffers are 343235783Skib * in the AGP aperture 344235783Skib */ 345235783Skib}; 346235783Skib 347235783Skib/** 348235783Skib * DRM_IOCTL_INFO_BUFS ioctl argument type. 349235783Skib */ 350235783Skibstruct drm_buf_info { 351282199Sdumbbell int count; /**< Entries in list */ 352282199Sdumbbell struct drm_buf_desc __user *list; 353235783Skib}; 354235783Skib 355235783Skib/** 356235783Skib * DRM_IOCTL_FREE_BUFS ioctl argument type. 357235783Skib */ 358235783Skibstruct drm_buf_free { 359235783Skib int count; 360235783Skib int __user *list; 361235783Skib}; 362235783Skib 363235783Skib/** 364235783Skib * Buffer information 365235783Skib * 366235783Skib * \sa drm_buf_map. 367235783Skib */ 368235783Skibstruct drm_buf_pub { 369235783Skib int idx; /**< Index into the master buffer list */ 370235783Skib int total; /**< Buffer size */ 371235783Skib int used; /**< Amount of buffer in use (for DMA) */ 372235783Skib void __user *address; /**< Address of buffer */ 373235783Skib}; 374235783Skib 375235783Skib/** 376235783Skib * DRM_IOCTL_MAP_BUFS ioctl argument type. 377235783Skib */ 378235783Skibstruct drm_buf_map { 379235783Skib int count; /**< Length of the buffer list */ 380235783Skib void __user *virtual; /**< Mmap'd area in user-virtual */ 381235783Skib struct drm_buf_pub __user *list; /**< Buffer information */ 382235783Skib}; 383235783Skib 384235783Skib/** 385235783Skib * DRM_IOCTL_DMA ioctl argument type. 386235783Skib * 387235783Skib * Indices here refer to the offset into the buffer list in drm_buf_get. 388235783Skib * 389235783Skib * \sa drmDMA(). 390235783Skib */ 391235783Skibstruct drm_dma { 392235783Skib int context; /**< Context handle */ 393235783Skib int send_count; /**< Number of buffers to send */ 394235783Skib int __user *send_indices; /**< List of handles to buffers */ 395235783Skib int __user *send_sizes; /**< Lengths of data to send */ 396235783Skib enum drm_dma_flags flags; /**< Flags */ 397235783Skib int request_count; /**< Number of buffers requested */ 398235783Skib int request_size; /**< Desired size for buffers */ 399282199Sdumbbell int __user *request_indices; /**< Buffer information */ 400235783Skib int __user *request_sizes; 401235783Skib int granted_count; /**< Number of buffers granted */ 402235783Skib}; 403235783Skib 404235783Skibenum drm_ctx_flags { 405235783Skib _DRM_CONTEXT_PRESERVED = 0x01, 406235783Skib _DRM_CONTEXT_2DONLY = 0x02 407235783Skib}; 408235783Skib 409235783Skib/** 410235783Skib * DRM_IOCTL_ADD_CTX ioctl argument type. 411235783Skib * 412235783Skib * \sa drmCreateContext() and drmDestroyContext(). 413235783Skib */ 414235783Skibstruct drm_ctx { 415235783Skib drm_context_t handle; 416235783Skib enum drm_ctx_flags flags; 417235783Skib}; 418235783Skib 419235783Skib/** 420235783Skib * DRM_IOCTL_RES_CTX ioctl argument type. 421235783Skib */ 422235783Skibstruct drm_ctx_res { 423235783Skib int count; 424235783Skib struct drm_ctx __user *contexts; 425235783Skib}; 426235783Skib 427235783Skib/** 428235783Skib * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 429235783Skib */ 430235783Skibstruct drm_draw { 431235783Skib drm_drawable_t handle; 432235783Skib}; 433235783Skib 434235783Skib/** 435235783Skib * DRM_IOCTL_UPDATE_DRAW ioctl argument type. 436235783Skib */ 437235783Skibtypedef enum { 438235783Skib DRM_DRAWABLE_CLIPRECTS, 439235783Skib} drm_drawable_info_type_t; 440235783Skib 441235783Skibstruct drm_update_draw { 442235783Skib drm_drawable_t handle; 443235783Skib unsigned int type; 444235783Skib unsigned int num; 445235783Skib unsigned long long data; 446235783Skib}; 447235783Skib 448235783Skib/** 449235783Skib * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 450235783Skib */ 451235783Skibstruct drm_auth { 452235783Skib drm_magic_t magic; 453235783Skib}; 454235783Skib 455235783Skib/** 456235783Skib * DRM_IOCTL_IRQ_BUSID ioctl argument type. 457235783Skib * 458235783Skib * \sa drmGetInterruptFromBusID(). 459235783Skib */ 460235783Skibstruct drm_irq_busid { 461235783Skib int irq; /**< IRQ number */ 462235783Skib int busnum; /**< bus number */ 463235783Skib int devnum; /**< device number */ 464235783Skib int funcnum; /**< function number */ 465235783Skib}; 466235783Skib 467235783Skibenum drm_vblank_seq_type { 468235783Skib _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 469235783Skib _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 470282199Sdumbbell /* bits 1-6 are reserved for high crtcs */ 471235783Skib _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, 472235783Skib _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ 473282199Sdumbbell _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ 474235783Skib _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 475235783Skib _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 476282199Sdumbbell _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ 477235783Skib}; 478235783Skib#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 479235783Skib 480235783Skib#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 481235783Skib#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ 482235783Skib _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) 483235783Skib 484235783Skibstruct drm_wait_vblank_request { 485235783Skib enum drm_vblank_seq_type type; 486235783Skib unsigned int sequence; 487235783Skib unsigned long signal; 488235783Skib}; 489235783Skib 490235783Skibstruct drm_wait_vblank_reply { 491235783Skib enum drm_vblank_seq_type type; 492235783Skib unsigned int sequence; 493235783Skib long tval_sec; 494235783Skib long tval_usec; 495235783Skib}; 496235783Skib 497235783Skib/** 498235783Skib * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 499235783Skib * 500235783Skib * \sa drmWaitVBlank(). 501235783Skib */ 502235783Skibunion drm_wait_vblank { 503235783Skib struct drm_wait_vblank_request request; 504235783Skib struct drm_wait_vblank_reply reply; 505235783Skib}; 506235783Skib 507235783Skib#define _DRM_PRE_MODESET 1 508235783Skib#define _DRM_POST_MODESET 2 509235783Skib 510235783Skib/** 511235783Skib * DRM_IOCTL_MODESET_CTL ioctl argument type 512235783Skib * 513235783Skib * \sa drmModesetCtl(). 514235783Skib */ 515235783Skibstruct drm_modeset_ctl { 516282199Sdumbbell __u32 crtc; 517282199Sdumbbell __u32 cmd; 518235783Skib}; 519235783Skib 520235783Skib/** 521235783Skib * DRM_IOCTL_AGP_ENABLE ioctl argument type. 522235783Skib * 523235783Skib * \sa drmAgpEnable(). 524235783Skib */ 525235783Skibstruct drm_agp_mode { 526235783Skib unsigned long mode; /**< AGP mode */ 527235783Skib}; 528235783Skib 529235783Skib/** 530235783Skib * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 531235783Skib * 532235783Skib * \sa drmAgpAlloc() and drmAgpFree(). 533235783Skib */ 534235783Skibstruct drm_agp_buffer { 535235783Skib unsigned long size; /**< In bytes -- will round to page boundary */ 536235783Skib unsigned long handle; /**< Used for binding / unbinding */ 537235783Skib unsigned long type; /**< Type of memory to allocate */ 538235783Skib unsigned long physical; /**< Physical used by i810 */ 539235783Skib}; 540235783Skib 541235783Skib/** 542235783Skib * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 543235783Skib * 544235783Skib * \sa drmAgpBind() and drmAgpUnbind(). 545235783Skib */ 546235783Skibstruct drm_agp_binding { 547235783Skib unsigned long handle; /**< From drm_agp_buffer */ 548235783Skib unsigned long offset; /**< In bytes -- will round to page boundary */ 549235783Skib}; 550235783Skib 551235783Skib/** 552235783Skib * DRM_IOCTL_AGP_INFO ioctl argument type. 553235783Skib * 554235783Skib * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 555235783Skib * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 556235783Skib * drmAgpVendorId() and drmAgpDeviceId(). 557235783Skib */ 558235783Skibstruct drm_agp_info { 559235783Skib int agp_version_major; 560235783Skib int agp_version_minor; 561235783Skib unsigned long mode; 562282199Sdumbbell unsigned long aperture_base; /* physical address */ 563282199Sdumbbell unsigned long aperture_size; /* bytes */ 564282199Sdumbbell unsigned long memory_allowed; /* bytes */ 565235783Skib unsigned long memory_used; 566235783Skib 567282199Sdumbbell /* PCI information */ 568235783Skib unsigned short id_vendor; 569235783Skib unsigned short id_device; 570235783Skib}; 571235783Skib 572235783Skib/** 573235783Skib * DRM_IOCTL_SG_ALLOC ioctl argument type. 574235783Skib */ 575235783Skibstruct drm_scatter_gather { 576235783Skib unsigned long size; /**< In bytes -- will round to page boundary */ 577235783Skib unsigned long handle; /**< Used for mapping / unmapping */ 578235783Skib}; 579235783Skib 580235783Skib/** 581235783Skib * DRM_IOCTL_SET_VERSION ioctl argument type. 582235783Skib */ 583235783Skibstruct drm_set_version { 584235783Skib int drm_di_major; 585235783Skib int drm_di_minor; 586235783Skib int drm_dd_major; 587235783Skib int drm_dd_minor; 588235783Skib}; 589235783Skib 590282199Sdumbbell/** DRM_IOCTL_GEM_CLOSE ioctl argument type */ 591235783Skibstruct drm_gem_close { 592235783Skib /** Handle of the object to be closed. */ 593282199Sdumbbell __u32 handle; 594282199Sdumbbell __u32 pad; 595235783Skib}; 596235783Skib 597282199Sdumbbell/** DRM_IOCTL_GEM_FLINK ioctl argument type */ 598235783Skibstruct drm_gem_flink { 599235783Skib /** Handle for the object being named */ 600282199Sdumbbell __u32 handle; 601235783Skib 602235783Skib /** Returned global name */ 603282199Sdumbbell __u32 name; 604235783Skib}; 605235783Skib 606282199Sdumbbell/** DRM_IOCTL_GEM_OPEN ioctl argument type */ 607235783Skibstruct drm_gem_open { 608235783Skib /** Name of object being opened */ 609282199Sdumbbell __u32 name; 610235783Skib 611235783Skib /** Returned handle for the object */ 612282199Sdumbbell __u32 handle; 613282199Sdumbbell 614235783Skib /** Returned size of the object */ 615282199Sdumbbell __u64 size; 616235783Skib}; 617235783Skib 618282199Sdumbbell/** DRM_IOCTL_GET_CAP ioctl argument type */ 619235783Skibstruct drm_get_cap { 620282199Sdumbbell __u64 capability; 621282199Sdumbbell __u64 value; 622235783Skib}; 623235783Skib 624282199Sdumbbell#define DRM_CLOEXEC O_CLOEXEC 625282199Sdumbbellstruct drm_prime_handle { 626282199Sdumbbell __u32 handle; 627235783Skib 628282199Sdumbbell /** Flags.. only applicable for handle->fd */ 629282199Sdumbbell __u32 flags; 630235783Skib 631282199Sdumbbell /** Returned dmabuf file descriptor */ 632282199Sdumbbell __s32 fd; 633235783Skib}; 634235783Skib 635282199Sdumbbell#include <dev/drm2/drm_mode.h> 636235783Skib 637235783Skib#define DRM_IOCTL_BASE 'd' 638235783Skib#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 639235783Skib#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 640235783Skib#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 641235783Skib#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 642235783Skib 643235783Skib#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) 644235783Skib#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) 645235783Skib#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) 646235783Skib#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) 647235783Skib#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) 648235783Skib#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) 649235783Skib#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) 650235783Skib#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) 651282199Sdumbbell#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) 652235783Skib#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) 653235783Skib#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) 654235783Skib#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) 655235783Skib#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) 656235783Skib 657235783Skib#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) 658235783Skib#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) 659235783Skib#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) 660235783Skib#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) 661235783Skib#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) 662235783Skib#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) 663235783Skib#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) 664235783Skib#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) 665235783Skib#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) 666235783Skib#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) 667235783Skib#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) 668235783Skib 669235783Skib#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) 670235783Skib 671235783Skib#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) 672282199Sdumbbell#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) 673235783Skib 674235783Skib#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) 675235783Skib#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) 676235783Skib 677235783Skib#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) 678235783Skib#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) 679235783Skib#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) 680235783Skib#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) 681235783Skib#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) 682235783Skib#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) 683235783Skib#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) 684235783Skib#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) 685235783Skib#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) 686235783Skib#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) 687235783Skib#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) 688235783Skib#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) 689235783Skib#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) 690235783Skib 691282199Sdumbbell#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) 692282199Sdumbbell#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) 693235783Skib 694235783Skib#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 695235783Skib#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 696235783Skib#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) 697235783Skib#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) 698235783Skib#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) 699235783Skib#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) 700235783Skib#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 701235783Skib#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 702235783Skib 703235783Skib#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) 704235783Skib#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 705235783Skib 706235783Skib#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 707235783Skib 708282199Sdumbbell#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) 709235783Skib 710235783Skib#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) 711235783Skib#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) 712235783Skib#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) 713235783Skib#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) 714235783Skib#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) 715235783Skib#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) 716235783Skib#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) 717235783Skib#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) 718235783Skib#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) 719235783Skib#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) 720235783Skib 721235783Skib#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) 722235783Skib#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) 723235783Skib#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) 724235783Skib#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) 725235783Skib#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) 726235783Skib#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) 727235783Skib#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) 728235783Skib#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) 729235783Skib 730282199Sdumbbell#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) 731282199Sdumbbell#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) 732282199Sdumbbell#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) 733235783Skib#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) 734282199Sdumbbell#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) 735282199Sdumbbell#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) 736235783Skib#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) 737280369Skib#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) 738280369Skib#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) 739235783Skib 740235783Skib/** 741235783Skib * Device specific ioctls should only be in their respective headers 742235783Skib * The device specific ioctl range is from 0x40 to 0x99. 743235783Skib * Generic IOCTLS restart at 0xA0. 744235783Skib * 745235783Skib * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 746235783Skib * drmCommandReadWrite(). 747235783Skib */ 748235783Skib#define DRM_COMMAND_BASE 0x40 749282199Sdumbbell#define DRM_COMMAND_END 0xA0 750235783Skib 751282199Sdumbbell/** 752282199Sdumbbell * Header for events written back to userspace on the drm fd. The 753282199Sdumbbell * type defines the type of event, the length specifies the total 754282199Sdumbbell * length of the event (including the header), and user_data is 755282199Sdumbbell * typically a 64 bit value passed with the ioctl that triggered the 756282199Sdumbbell * event. A read on the drm fd will always only return complete 757282199Sdumbbell * events, that is, if for example the read buffer is 100 bytes, and 758282199Sdumbbell * there are two 64 byte events pending, only one will be returned. 759282199Sdumbbell * 760282199Sdumbbell * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and 761282199Sdumbbell * up are chipset specific. 762282199Sdumbbell */ 763282199Sdumbbellstruct drm_event { 764282199Sdumbbell __u32 type; 765282199Sdumbbell __u32 length; 766282199Sdumbbell}; 767282199Sdumbbell 768282199Sdumbbell#define DRM_EVENT_VBLANK 0x01 769282199Sdumbbell#define DRM_EVENT_FLIP_COMPLETE 0x02 770282199Sdumbbell 771282199Sdumbbellstruct drm_event_vblank { 772282199Sdumbbell struct drm_event base; 773282199Sdumbbell __u64 user_data; 774282199Sdumbbell __u32 tv_sec; 775282199Sdumbbell __u32 tv_usec; 776282199Sdumbbell __u32 sequence; 777282199Sdumbbell __u32 reserved; 778282199Sdumbbell}; 779282199Sdumbbell 780282199Sdumbbell#define DRM_CAP_DUMB_BUFFER 0x1 781282199Sdumbbell#define DRM_CAP_VBLANK_HIGH_CRTC 0x2 782282199Sdumbbell#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 783282199Sdumbbell#define DRM_CAP_DUMB_PREFER_SHADOW 0x4 784282199Sdumbbell#define DRM_CAP_PRIME 0x5 785282199Sdumbbell#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 786282199Sdumbbell 787282199Sdumbbell#define DRM_PRIME_CAP_IMPORT 0x1 788282199Sdumbbell#define DRM_PRIME_CAP_EXPORT 0x2 789282199Sdumbbell 790235783Skib/* typedef area */ 791235783Skib#ifndef __KERNEL__ 792235783Skibtypedef struct drm_clip_rect drm_clip_rect_t; 793282199Sdumbbelltypedef struct drm_drawable_info drm_drawable_info_t; 794235783Skibtypedef struct drm_tex_region drm_tex_region_t; 795235783Skibtypedef struct drm_hw_lock drm_hw_lock_t; 796235783Skibtypedef struct drm_version drm_version_t; 797235783Skibtypedef struct drm_unique drm_unique_t; 798235783Skibtypedef struct drm_list drm_list_t; 799235783Skibtypedef struct drm_block drm_block_t; 800235783Skibtypedef struct drm_control drm_control_t; 801235783Skibtypedef enum drm_map_type drm_map_type_t; 802235783Skibtypedef enum drm_map_flags drm_map_flags_t; 803235783Skibtypedef struct drm_ctx_priv_map drm_ctx_priv_map_t; 804235783Skibtypedef struct drm_map drm_map_t; 805235783Skibtypedef struct drm_client drm_client_t; 806235783Skibtypedef enum drm_stat_type drm_stat_type_t; 807235783Skibtypedef struct drm_stats drm_stats_t; 808235783Skibtypedef enum drm_lock_flags drm_lock_flags_t; 809235783Skibtypedef struct drm_lock drm_lock_t; 810235783Skibtypedef enum drm_dma_flags drm_dma_flags_t; 811235783Skibtypedef struct drm_buf_desc drm_buf_desc_t; 812235783Skibtypedef struct drm_buf_info drm_buf_info_t; 813235783Skibtypedef struct drm_buf_free drm_buf_free_t; 814235783Skibtypedef struct drm_buf_pub drm_buf_pub_t; 815235783Skibtypedef struct drm_buf_map drm_buf_map_t; 816235783Skibtypedef struct drm_dma drm_dma_t; 817235783Skibtypedef union drm_wait_vblank drm_wait_vblank_t; 818235783Skibtypedef struct drm_agp_mode drm_agp_mode_t; 819235783Skibtypedef enum drm_ctx_flags drm_ctx_flags_t; 820235783Skibtypedef struct drm_ctx drm_ctx_t; 821235783Skibtypedef struct drm_ctx_res drm_ctx_res_t; 822235783Skibtypedef struct drm_draw drm_draw_t; 823235783Skibtypedef struct drm_update_draw drm_update_draw_t; 824235783Skibtypedef struct drm_auth drm_auth_t; 825235783Skibtypedef struct drm_irq_busid drm_irq_busid_t; 826235783Skibtypedef enum drm_vblank_seq_type drm_vblank_seq_type_t; 827282199Sdumbbell 828235783Skibtypedef struct drm_agp_buffer drm_agp_buffer_t; 829235783Skibtypedef struct drm_agp_binding drm_agp_binding_t; 830235783Skibtypedef struct drm_agp_info drm_agp_info_t; 831235783Skibtypedef struct drm_scatter_gather drm_scatter_gather_t; 832235783Skibtypedef struct drm_set_version drm_set_version_t; 833235783Skib#endif 834235783Skib 835235783Skib#endif 836