11590Srgrimes/*- 21590Srgrimes * Defines for Cronyx-Sigma adapter driver. 31590Srgrimes * 41590Srgrimes * Copyright (C) 1994-2001 Cronyx Engineering. 51590Srgrimes * Author: Serge Vakulenko, <vak@cronyx.ru> 61590Srgrimes * 71590Srgrimes * Copyright (C) 1998-2003 Cronyx Engineering. 81590Srgrimes * Author: Roman Kurakin, <rik@cronyx.ru> 91590Srgrimes * 101590Srgrimes * This software is distributed with NO WARRANTIES, not even the implied 111590Srgrimes * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 121590Srgrimes * 131590Srgrimes * Authors grant any other persons or organisations permission to use 141590Srgrimes * or modify this software as long as this message is kept with the software, 151590Srgrimes * all derivative works or modified versions. 161590Srgrimes * 171590Srgrimes * Cronyx Id: cxddk.h,v 1.1.2.1 2003/11/12 17:13:41 rik Exp $ 181590Srgrimes * $FreeBSD: releng/10.3/sys/dev/cx/cxddk.h 180132 2008-06-30 21:18:27Z rik $ 191590Srgrimes */ 201590Srgrimes 211590Srgrimes#ifndef port_t 221590Srgrimes# ifdef _M_ALPHA /* port address on Alpha under */ 231590Srgrimes# define port_t unsigned long /* Windows NT is 32 bit long */ 241590Srgrimes# else 251590Srgrimes# define port_t unsigned short /* all other architectures */ 261590Srgrimes# endif /* have 16-bit port addresses */ 271590Srgrimes#endif 281590Srgrimes 291590Srgrimes#define NBRD 3 /* the max number of installed boards */ 301590Srgrimes#define NPORT 32 /* the number of i/o ports per board */ 311590Srgrimes#define DMABUFSZ 1600 321590Srgrimes 331590Srgrimes/* 3441568Sarchie * Asynchronous channel mode ------------------------------------------------- 351590Srgrimes */ 361590Srgrimes 371590Srgrimes/* Parity */ 381590Srgrimes#define PAR_EVEN 0 /* even parity */ 391590Srgrimes#define PAR_ODD 1 /* odd parity */ 4056597Smharo 4141568Sarchie/* Parity mode */ 4256597Smharo#define PARM_NOPAR 0 /* no parity */ 431590Srgrimes#define PARM_FORCE 1 /* force parity (odd = force 1, even = 0) */ 4499112Sobrien#define PARM_NORMAL 2 /* normal parity */ 4599112Sobrien 461590Srgrimes/* Flow control transparency mode */ 471590Srgrimes#define FLOWCC_PASS 0 /* pass flow ctl chars as exceptions */ 4878158Sroam#define FLOWCC_NOTPASS 1 /* don't pass flow ctl chars to the host */ 491590Srgrimes 501590Srgrimes/* Stop bit length */ 511590Srgrimes#define STOPB_1 2 /* 1 stop bit */ 521590Srgrimes#define STOPB_15 3 /* 1.5 stop bits */ 5378158Sroam#define STOPB_2 4 /* 2 stop bits */ 541590Srgrimes 55129678Spjd/* Action on break condition */ 56132201Stjr#define BRK_INTR 0 /* generate an exception interrupt */ 57139813Spjd#define BRK_NULL 1 /* translate to a NULL character */ 581590Srgrimes#define BRK_RESERVED 2 /* reserved */ 591590Srgrimes#define BRK_DISCARD 3 /* discard character */ 601590Srgrimes 6156597Smharo/* Parity/framing error actions */ 6223693Speter#define PERR_INTR 0 /* generate an exception interrupt */ 631590Srgrimes#define PERR_NULL 1 /* translate to a NULL character */ 64227164Sed#define PERR_IGNORE 2 /* ignore error; char passed as good data */ 6578158Sroam#define PERR_DISCARD 3 /* discard error character */ 6678158Sroam#define PERR_FFNULL 5 /* translate to FF NULL char */ 6778158Sroam 6878158Sroamtypedef struct { /* async channel option register 1 */ 6978158Sroam unsigned charlen : 4; /* character length, 5..8 */ 70128772Skientzle unsigned ignpar : 1; /* ignore parity */ 7192920Simp unsigned parmode : 2; /* parity mode */ 72184656Smlaier unsigned parity : 1; /* parity */ 73184656Smlaier} cx_cor1_async_t; 74184656Smlaier 75184656Smlaiertypedef struct { /* async channel option register 2 */ 76191677Simp unsigned dsrae : 1; /* DSR automatic enable */ 771590Srgrimes unsigned ctsae : 1; /* CTS automatic enable */ 78184656Smlaier unsigned rtsao : 1; /* RTS automatic output enable */ 79184733Smlaier unsigned rlm : 1; /* remote loopback mode enable */ 80184733Smlaier unsigned zero : 1; 81191677Simp unsigned etc : 1; /* embedded transmitter cmd enable */ 82158339Smaxim unsigned ixon : 1; /* in-band XON/XOFF enable */ 831590Srgrimes unsigned ixany : 1; /* XON on any character */ 84100822Sdwmalone} cx_cor2_async_t; 851590Srgrimes 8632097Sjkhtypedef struct { /* async channel option register 3 */ 8732097Sjkh unsigned stopb : 3; /* stop bit length */ 88184733Smlaier unsigned zero : 1; 89209362Sbrian unsigned scde : 1; /* special char detection enable */ 9032097Sjkh unsigned flowct : 1; /* flow control transparency mode */ 9132097Sjkh unsigned rngde : 1; /* range detect enable */ 92228669Sjilles unsigned escde : 1; /* extended spec. char detect enable */ 93176561Skeramida} cx_cor3_async_t; 9432097Sjkh 9587216Smarkmtypedef struct { /* async channel option register 6 */ 961590Srgrimes unsigned parerr : 3; /* parity/framing error actions */ 97132201Stjr unsigned brk : 2; /* action on break condition */ 98132201Stjr unsigned inlcr : 1; /* translate NL to CR on input */ 99228669Sjilles unsigned icrnl : 1; /* translate CR to NL on input */ 100184733Smlaier unsigned igncr : 1; /* discard CR on input */ 101128772Skientzle} cx_cor6_async_t; 1021590Srgrimes 103228669Sjillestypedef struct { /* async channel option register 7 */ 104184654Smlaier unsigned ocrnl : 1; /* translate CR to NL on output */ 105209362Sbrian unsigned onlcr : 1; /* translate NL to CR on output */ 106209362Sbrian unsigned zero : 3; 107184733Smlaier unsigned fcerr : 1; /* process flow ctl err chars enable */ 108184733Smlaier unsigned lnext : 1; /* LNext option enable */ 10919120Sscrappy unsigned istrip : 1; /* strip 8-bit on input */ 11078158Sroam} cx_cor7_async_t; 111128772Skientzle 112238602Sdestypedef struct { /* async channel options */ 1131590Srgrimes cx_cor1_async_t cor1; /* channel option register 1 */ 114184733Smlaier cx_cor2_async_t cor2; /* channel option register 2 */ 115184733Smlaier cx_cor3_async_t cor3; /* option register 3 */ 116184733Smlaier cx_cor6_async_t cor6; /* channel option register 6 */ 117184733Smlaier cx_cor7_async_t cor7; /* channel option register 7 */ 118184733Smlaier unsigned char schr1; /* special character register 1 (XON) */ 119184733Smlaier unsigned char schr2; /* special character register 2 (XOFF) */ 120184733Smlaier unsigned char schr3; /* special character register 3 */ 121184733Smlaier unsigned char schr4; /* special character register 4 */ 122184733Smlaier unsigned char scrl; /* special character range low */ 123184733Smlaier unsigned char scrh; /* special character range high */ 124184733Smlaier unsigned char lnxt; /* LNext character */ 125184733Smlaier} cx_opt_async_t; 126184654Smlaier 127184654Smlaier/* 128228669Sjilles * HDLC channel mode --------------------------------------------------------- 129184654Smlaier */ 130184654Smlaier/* Address field length option */ 131184654Smlaier#define AFLO_1OCT 0 /* address field is 1 octet in length */ 132184654Smlaier#define AFLO_2OCT 1 /* address field is 2 octet in length */ 133184654Smlaier 134184654Smlaier/* Clear detect for X.21 data transfer phase */ 135228669Sjilles#define CLRDET_DISABLE 0 /* clear detect disabled */ 136184654Smlaier#define CLRDET_ENABLE 1 /* clear detect enabled */ 137184654Smlaier 138228669Sjilles/* Addressing mode */ 139184654Smlaier#define ADMODE_NOADDR 0 /* no address */ 140184654Smlaier#define ADMODE_4_1 1 /* 4 * 1 byte */ 141184654Smlaier#define ADMODE_2_2 2 /* 2 * 2 byte */ 142184654Smlaier 143184654Smlaier/* FCS append */ 144184654Smlaier#define FCS_NOTPASS 0 /* receive CRC is not passed to the host */ 145184654Smlaier#define FCS_PASS 1 /* receive CRC is passed to the host */ 146184654Smlaier 147184654Smlaier/* CRC modes */ 148184654Smlaier#define CRC_INVERT 0 /* CRC is transmitted inverted (CRC V.41) */ 149184654Smlaier#define CRC_DONT_INVERT 1 /* CRC is not transmitted inverted (CRC-16) */ 150184654Smlaier 151184654Smlaier/* Send sync pattern */ 152184654Smlaier#define SYNC_00 0 /* send 00h as pad char (NRZI encoding) */ 153184654Smlaier#define SYNC_AA 1 /* send AAh (Manchester/NRZ encoding) */ 154184654Smlaier 155184654Smlaier/* FCS preset */ 156184654Smlaier#define FCSP_ONES 0 /* FCS is preset to all ones (CRC V.41) */ 157184654Smlaier#define FCSP_ZEROS 1 /* FCS is preset to all zeros (CRC-16) */ 158184654Smlaier 159238602Sdes/* idle mode */ 160238602Sdes#define IDLE_FLAG 0 /* idle in flag */ 161238602Sdes#define IDLE_MARK 1 /* idle in mark */ 162238602Sdes 163184654Smlaier/* CRC polynomial select */ 164184654Smlaier#define POLY_V41 0 /* x^16+x^12+x^5+1 (HDLC, preset to 1) */ 165184654Smlaier#define POLY_16 1 /* x^16+x^15+x^2+1 (bisync, preset to 0) */ 166184654Smlaier 167184654Smlaiertypedef struct { /* hdlc channel option register 1 */ 168184733Smlaier unsigned ifflags : 4; /* number of inter-frame flags sent */ 169184654Smlaier unsigned admode : 2; /* addressing mode */ 170184654Smlaier unsigned clrdet : 1; /* clear detect for X.21 data transfer phase */ 171184654Smlaier unsigned aflo : 1; /* address field length option */ 172184654Smlaier} cx_cor1_hdlc_t; 173184654Smlaier 174184654Smlaiertypedef struct { /* hdlc channel option register 2 */ 175184733Smlaier unsigned dsrae : 1; /* DSR automatic enable */ 176184654Smlaier unsigned ctsae : 1; /* CTS automatic enable */ 177184654Smlaier unsigned rtsao : 1; /* RTS automatic output enable */ 178184654Smlaier unsigned zero1 : 1; 179184654Smlaier unsigned crcninv : 1; /* CRC invertion option */ 180184654Smlaier unsigned zero2 : 1; 181184654Smlaier unsigned fcsapd : 1; /* FCS append */ 182209362Sbrian unsigned zero3 : 1; 183209362Sbrian} cx_cor2_hdlc_t; 184209362Sbrian 185209362Sbriantypedef struct { /* hdlc channel option register 3 */ 186209362Sbrian unsigned padcnt : 3; /* pad character count */ 187209362Sbrian unsigned idle : 1; /* idle mode */ 188209362Sbrian unsigned nofcs : 1; /* FCS disable */ 189209362Sbrian unsigned fcspre : 1; /* FCS preset */ 190184654Smlaier unsigned syncpat : 1; /* send sync pattern */ 191184654Smlaier unsigned sndpad : 1; /* send pad characters before flag enable */ 192184654Smlaier} cx_cor3_hdlc_t; 193184654Smlaier 194184654Smlaiertypedef struct { /* hdlc channel options */ 195184654Smlaier cx_cor1_hdlc_t cor1; /* hdlc channel option register 1 */ 196184654Smlaier cx_cor2_hdlc_t cor2; /* hdlc channel option register 2 */ 1971590Srgrimes cx_cor3_hdlc_t cor3; /* hdlc channel option register 3 */ 19832097Sjkh unsigned char rfar1; /* receive frame address register 1 */ 1991590Srgrimes unsigned char rfar2; /* receive frame address register 2 */ 2001590Srgrimes unsigned char rfar3; /* receive frame address register 3 */ 2011590Srgrimes unsigned char rfar4; /* receive frame address register 4 */ 2021590Srgrimes unsigned char cpsr; /* CRC polynomial select */ 2031590Srgrimes} cx_opt_hdlc_t; 2041590Srgrimes 2051590Srgrimes/* 2061590Srgrimes * CD2400 channel state structure -------------------------------------------- 2071590Srgrimes */ 2081590Srgrimes 2091590Srgrimes/* Signal encoding */ 2101590Srgrimes#define ENCOD_NRZ 0 /* NRZ mode */ 2111590Srgrimes#define ENCOD_NRZI 1 /* NRZI mode */ 2121590Srgrimes#define ENCOD_MANCHESTER 2 /* Manchester mode */ 2131590Srgrimes 21432097Sjkh/* Clock source */ 2151590Srgrimes#define CLK_0 0 /* clock 0 */ 2161590Srgrimes#define CLK_1 1 /* clock 1 */ 217228669Sjilles#define CLK_2 2 /* clock 2 */ 218228669Sjilles#define CLK_3 3 /* clock 3 */ 2191590Srgrimes#define CLK_4 4 /* clock 4 */ 220228669Sjilles#define CLK_EXT 6 /* external clock */ 2211590Srgrimes#define CLK_RCV 7 /* receive clock */ 222184733Smlaier 223184733Smlaier/* Board type */ 224184733Smlaier#define B_SIGMA_XXX 0 /* old Sigmas */ 225227335Sed#define B_SIGMA_2X 1 /* Sigma-22 */ 226227335Sed#define B_SIGMA_800 2 /* Sigma-800 */ 227227335Sed 22832097Sjkh/* Channel type */ 2291590Srgrimes#define T_NONE 0 /* no channel */ 2301590Srgrimes#define T_ASYNC 1 /* pure asynchronous RS-232 channel */ 2311590Srgrimes#define T_SYNC_RS232 2 /* pure synchronous RS-232 channel */ 23287216Smarkm#define T_SYNC_V35 3 /* pure synchronous V.35 channel */ 2331590Srgrimes#define T_SYNC_RS449 4 /* pure synchronous RS-449 channel */ 2341590Srgrimes#define T_UNIV_RS232 5 /* sync/async RS-232 channel */ 2351590Srgrimes#define T_UNIV_RS449 6 /* sync/async RS-232/RS-449 channel */ 236184733Smlaier#define T_UNIV_V35 7 /* sync/async RS-232/V.35 channel */ 237184733Smlaier#define T_UNIV 8 /* sync/async, unknown interface */ 2381590Srgrimes 239184733Smlaier#define M_ASYNC 0 /* asynchronous mode */ 240184733Smlaier#define M_HDLC 1 /* bit-sync mode (HDLC) */ 241184733Smlaier 242184733Smlaiertypedef struct { /* channel option register 4 */ 243184733Smlaier unsigned thr : 4; /* FIFO threshold */ 244209362Sbrian unsigned zero : 1; 245209362Sbrian unsigned cts_zd : 1; /* detect 1 to 0 transition on the CTS */ 246209362Sbrian unsigned cd_zd : 1; /* detect 1 to 0 transition on the CD */ 247209362Sbrian unsigned dsr_zd : 1; /* detect 1 to 0 transition on the DSR */ 24832097Sjkh} cx_cor4_t; 249128772Skientzle 250191677Simptypedef struct { /* channel option register 5 */ 251191677Simp unsigned rx_thr : 4; /* receive flow control FIFO threshold */ 2521590Srgrimes unsigned zero : 1; 25332097Sjkh unsigned cts_od : 1; /* detect 0 to 1 transition on the CTS */ 2541590Srgrimes unsigned cd_od : 1; /* detect 0 to 1 transition on the CD */ 25532097Sjkh unsigned dsr_od : 1; /* detect 0 to 1 transition on the DSR */ 2561590Srgrimes} cx_cor5_t; 257184654Smlaier 258184654Smlaiertypedef struct { /* receive clock option register */ 259184654Smlaier unsigned clk : 3; /* receive clock source */ 260184654Smlaier unsigned encod : 2; /* signal encoding NRZ/NRZI/Manchester */ 261184654Smlaier unsigned dpll : 1; /* DPLL enable */ 262184654Smlaier unsigned zero : 1; 2631590Srgrimes unsigned tlval : 1; /* transmit line value */ 26478158Sroam} cx_rcor_t; 265184733Smlaier 266184733Smlaiertypedef struct { /* transmit clock option register */ 267184733Smlaier unsigned zero1 : 1; 268184654Smlaier unsigned llm : 1; /* local loopback mode */ 269184733Smlaier unsigned zero2 : 1; 270128772Skientzle unsigned ext1x : 1; /* external 1x clock mode */ 271209362Sbrian unsigned zero3 : 1; 272209362Sbrian unsigned clk : 3; /* transmit clock source */ 273209362Sbrian} cx_tcor_t; 274184654Smlaier 275184733Smlaiertypedef struct { 276184654Smlaier cx_cor4_t cor4; /* channel option register 4 */ 277184654Smlaier cx_cor5_t cor5; /* channel option register 5 */ 278184654Smlaier cx_rcor_t rcor; /* receive clock option register */ 279184742Smlaier cx_tcor_t tcor; /* transmit clock option register */ 280184742Smlaier} cx_chan_opt_t; 281184742Smlaier 28258601Scharniertypedef enum { /* line break mode */ 283184654Smlaier BRK_IDLE, /* normal line mode */ 284191677Simp BRK_SEND, /* start sending break */ 285191677Simp BRK_STOP, /* stop sending break */ 286191677Simp} cx_break_t; 287191677Simp 288184654Smlaier#define BUS_NORMAL 0 /* normal bus timing */ 289184654Smlaier#define BUS_FAST 1 /* fast bus timing (Sigma-22 and -800) */ 290184654Smlaier#define BUS_FAST2 2 /* fast bus timing (Sigma-800) */ 291184654Smlaier#define BUS_FAST3 3 /* fast bus timing (Sigma-800) */ 292184654Smlaier 293184654Smlaiertypedef struct { /* board options */ 294184654Smlaier unsigned char fast; /* bus master timing (Sigma-22 and -800) */ 295184654Smlaier} cx_board_opt_t; 296184654Smlaier 297184654Smlaier#define NCHIP 4 /* the number of controllers per board */ 298184654Smlaier#define NCHAN 16 /* the number of channels on the board */ 29932097Sjkh 300184654Smlaiertypedef struct { 301184654Smlaier unsigned char tbuffer [2] [DMABUFSZ]; 302184654Smlaier unsigned char rbuffer [2] [DMABUFSZ]; 30332097Sjkh} cx_buf_t; 30478158Sroam 305184733Smlaiertypedef struct _cx_chan_t { 306184733Smlaier struct _cx_board_t *board; /* board pointer */ 307184733Smlaier unsigned char type; /* channel type */ 308184733Smlaier unsigned char num; /* channel number, 0..15 */ 309227335Sed port_t port; /* base port address */ 310184654Smlaier unsigned long oscfreq; /* oscillator frequency in Hz */ 311184733Smlaier unsigned long rxbaud; /* receiver speed */ 312184654Smlaier unsigned long txbaud; /* transmitter speed */ 313184654Smlaier unsigned char mode; /* channel mode */ 314184654Smlaier cx_chan_opt_t opt; /* common channel options */ 315184742Smlaier cx_opt_async_t aopt; /* async mode options */ 316184742Smlaier cx_opt_hdlc_t hopt; /* hdlc mode options */ 317184742Smlaier unsigned char *arbuf; /* receiver A dma buffer */ 31858601Scharnier unsigned char *brbuf; /* receiver B dma buffer */ 319184654Smlaier unsigned char *atbuf; /* transmitter A dma buffer */ 32032097Sjkh unsigned char *btbuf; /* transmitter B dma buffer */ 321184733Smlaier unsigned long arphys; /* receiver A phys address */ 3221590Srgrimes unsigned long brphys; /* receiver B phys address */ 323139813Spjd unsigned long atphys; /* transmitter A phys address */ 32432097Sjkh unsigned long btphys; /* transmitter B phys address */ 32532097Sjkh unsigned char dtr; /* DTR signal value */ 3261590Srgrimes unsigned char rts; /* RTS signal value */ 3271590Srgrimes 32832097Sjkh unsigned long rintr; /* receive interrupts */ 32958601Scharnier unsigned long tintr; /* transmit interrupts */ 33056597Smharo unsigned long mintr; /* modem interrupts */ 331184733Smlaier unsigned long ibytes; /* input bytes */ 332184654Smlaier unsigned long ipkts; /* input packets */ 33356597Smharo unsigned long ierrs; /* input errors */ 334184654Smlaier unsigned long obytes; /* output bytes */ 335184733Smlaier unsigned long opkts; /* output packets */ 33656597Smharo unsigned long oerrs; /* output errors */ 33758601Scharnier 33832097Sjkh void *sys; 33978158Sroam int debug; 34028891Swosch int debug_shadow; 3411590Srgrimes void *attach [2]; 3421590Srgrimes char *received_data; 343128772Skientzle int received_len; 344128772Skientzle int overflow; 345128772Skientzle 346128772Skientzle void (*call_on_rx) (struct _cx_chan_t*, char*, int); 347128806Skientzle void (*call_on_tx) (struct _cx_chan_t*, void*, int); 348128806Skientzle void (*call_on_msig) (struct _cx_chan_t*); 349128806Skientzle void (*call_on_err) (struct _cx_chan_t*, int); 350128806Skientzle 351128806Skientzle} cx_chan_t; 352128772Skientzle 353128806Skientzletypedef struct _cx_board_t { 354128806Skientzle unsigned char type; /* board type */ 355128806Skientzle unsigned char num; /* board number, 0..2 */ 356128806Skientzle port_t port; /* base board port, 0..3f0 */ 357128806Skientzle unsigned char irq; /* irq {3 5 7 10 11 12 15} */ 358128806Skientzle unsigned char dma; /* DMA request {5 6 7} */ 359128806Skientzle char name[16]; /* board version name */ 360128806Skientzle unsigned char nuniv; /* number of universal channels */ 361128806Skientzle unsigned char nsync; /* number of sync. channels */ 362144840Sstefanf unsigned char nasync; /* number of async. channels */ 36332097Sjkh unsigned char if0type; /* chan0 interface RS-232/RS-449/V.35 */ 364128772Skientzle unsigned char if8type; /* chan8 interface RS-232/RS-449/V.35 */ 36532097Sjkh unsigned short bcr0; /* BCR0 image */ 366128772Skientzle unsigned short bcr0b; /* BCR0b image */ 367128772Skientzle unsigned short bcr1; /* BCR1 image */ 368128772Skientzle unsigned short bcr1b; /* BCR1b image */ 369128772Skientzle cx_board_opt_t opt; /* board options */ 370128772Skientzle cx_chan_t chan[NCHAN]; /* channel structures */ 371128834Skientzle void *sys; 372128772Skientzle} cx_board_t; 373128772Skientzle 374128772Skientzleextern long cx_rxbaud, cx_txbaud; 3751590Srgrimesextern int cx_univ_mode, cx_sync_mode, cx_iftype; 376128772Skientzle 377128772Skientzleextern cx_chan_opt_t chan_opt_dflt; /* default mode-independent options */ 378128772Skientzleextern cx_opt_async_t opt_async_dflt; /* default async options */ 379128772Skientzleextern cx_opt_hdlc_t opt_hdlc_dflt; /* default hdlc options */ 380128772Skientzleextern cx_board_opt_t board_opt_dflt; /* default board options */ 381128772Skientzle 382128772Skientzlestruct _cr_dat_tst; 383128772Skientzleint cx_probe_board (port_t port, int irq, int dma); 384128772Skientzlevoid cx_init (cx_board_t *b, int num, port_t port, int irq, int dma); 385128772Skientzlevoid cx_init_board (cx_board_t *b, int num, port_t port, int irq, int dma, 386128772Skientzle int chain, int rev, int osc, int mod, int rev2, int osc2, int mod2); 387128772Skientzlevoid cx_init_2x (cx_board_t *b, int num, port_t port, int irq, int dma, 388184654Smlaier int rev, int osc); 389184654Smlaiervoid cx_init_800 (cx_board_t *b, int num, port_t port, int irq, int dma, 390128772Skientzle int chain); 391128772Skientzleint cx_download (port_t port, const unsigned char *firmware, long bits, 392128772Skientzle const struct _cr_dat_tst *tst); 393128772Skientzleint cx_setup_board (cx_board_t *b, const unsigned char *firmware, 394128834Skientzle long bits, const struct _cr_dat_tst *tst); 395128772Skientzlevoid cx_setup_chan (cx_chan_t *c); 396128772Skientzlevoid cx_update_chan (cx_chan_t *c); 397128772Skientzlevoid cx_set_dtr (cx_chan_t *c, int on); 398128772Skientzlevoid cx_set_rts (cx_chan_t *c, int on); 399128772Skientzlevoid cx_led (cx_board_t *b, int on); 400128772Skientzlevoid cx_cmd (port_t base, int cmd); 401128772Skientzlevoid cx_disable_dma (cx_board_t *b); 402128772Skientzlevoid cx_reinit_board (cx_board_t *b); 403128772Skientzleint cx_get_dsr (cx_chan_t *c); 404128772Skientzleint cx_get_cts (cx_chan_t *c); 405128772Skientzleint cx_get_cd (cx_chan_t *c); 406128772Skientzlevoid cx_clock (long hz, long ba, int *clk, int *div); 407128772Skientzle 408128772Skientzle/* DDK errors */ 409128772Skientzle#define CX_FRAME 1 410128772Skientzle#define CX_CRC 2 411128772Skientzle#define CX_OVERRUN 3 412128772Skientzle#define CX_OVERFLOW 4 413128772Skientzle#define CX_UNDERRUN 5 414128772Skientzle#define CX_BREAK 6 415128772Skientzle 416128772Skientzle/* clock sources */ 417128772Skientzle#define CX_CLK_INT 0 418128772Skientzle#define CX_CLK_EXT 6 419128772Skientzle#define CX_CLK_RCV 7 420128772Skientzle#define CX_CLK_DPLL 8 421128772Skientzle#define CX_CLK_DPLL_EXT 14 422128772Skientzle 423128772Skientzle/* functions dealing with interrupt vector in DOS */ 424128772Skientzle#if defined (MSDOS) || defined (__MSDOS__) 425128772Skientzleint ddk_int_alloc (int irq, void (*func)(), void *arg); 426128772Skientzleint ddk_int_restore (int irq); 427128772Skientzle#endif 428128772Skientzle 429128772Skientzleint cx_probe_irq (cx_board_t *b, int irq); 430128772Skientzlevoid cx_int_handler (cx_board_t *b); 431128772Skientzle 432128772Skientzleint cx_find (port_t *board_ports); 433128772Skientzleint cx_open_board (cx_board_t *b, int num, port_t port, int irq, int dma); 434128772Skientzlevoid cx_close_board (cx_board_t *b); 435128772Skientzle 436128772Skientzlevoid cx_start_chan (cx_chan_t *c, cx_buf_t *cb, unsigned long phys); 437128772Skientzle 438128772Skientzle/* 439128772Skientzle Set port type for old models of Sigma 440128772Skientzle */ 441128772Skientzlevoid cx_set_port (cx_chan_t *c, int iftype); 442128772Skientzle 443128772Skientzle/* 444128772Skientzle Get port type for old models of Sigma 445128772Skientzle -1 Fixed port type or auto detect 446128772Skientzle 0 RS232 447128772Skientzle 1 V35 448128772Skientzle 2 RS449 449128772Skientzle */ 450128772Skientzleint cx_get_port (cx_chan_t *c); 451128772Skientzle 452128772Skientzlevoid cx_enable_receive (cx_chan_t *c, int on); 453128772Skientzlevoid cx_enable_transmit (cx_chan_t *c, int on); 454128772Skientzleint cx_receive_enabled (cx_chan_t *c); 455128772Skientzleint cx_transmit_enabled (cx_chan_t *c); 456128772Skientzle 457128772Skientzlevoid cx_set_baud (cx_chan_t *, unsigned long baud); 458128772Skientzleint cx_set_mode (cx_chan_t *c, int mode); 459128772Skientzlevoid cx_set_loop (cx_chan_t *c, int on); 460128772Skientzlevoid cx_set_nrzi (cx_chan_t *c, int nrzi); 461128772Skientzlevoid cx_set_dpll (cx_chan_t *c, int on); 462128834Skientzle 463128772Skientzleunsigned long cx_get_baud (cx_chan_t *c); 464128772Skientzleint cx_get_loop (cx_chan_t *c); 465128772Skientzleint cx_get_nrzi (cx_chan_t *c); 466128772Skientzleint cx_get_dpll (cx_chan_t *c); 467128772Skientzle 468128772Skientzleint cx_send_packet (cx_chan_t *c, char *data, int len, void *attachment); 469128772Skientzleint cx_buf_free (cx_chan_t *c); 470128772Skientzle 471128772Skientzlevoid cx_register_transmit (cx_chan_t *c, 472128772Skientzle void (*func) (cx_chan_t *c, void *attachment, int len)); 473128772Skientzlevoid cx_register_receive (cx_chan_t *c, 4741590Srgrimes void (*func) (cx_chan_t *c, char *data, int len)); 4751590Srgrimesvoid cx_register_modem (cx_chan_t *c, void (*func) (cx_chan_t *c)); 4761590Srgrimesvoid cx_register_error (cx_chan_t *c, void (*func) (cx_chan_t *c, int data)); 477184656Smlaiervoid cx_intr_off (cx_board_t *b); 478129678Spjdvoid cx_intr_on (cx_board_t *b); 47956597Smharoint cx_checkintr (cx_board_t *b); 480129678Spjd 48156597Smharo/* Async functions */ 482184733Smlaiervoid cx_transmitter_ctl (cx_chan_t *c, int start); 483184733Smlaiervoid cx_flush_transmit (cx_chan_t *c); 484184733Smlaiervoid cx_xflow_ctl (cx_chan_t *c, int on); 48556597Smharovoid cx_send_break (cx_chan_t *c, int msec); 486129678Spjdvoid cx_set_async_param (cx_chan_t *c, int baud, int bits, int parity, 487129678Spjd int stop2, int ignpar, int rtscts, 48856597Smharo int ixon, int ixany, int symstart, int symstop); 489129678Spjd