1/*- 2 * Defines for Cronyx-Tau adapter, based on Hitachi HD64570 controller. 3 * 4 * Copyright (C) 1996 Cronyx Engineering. 5 * Author: Serge Vakulenko, <vak@cronyx.ru> 6 * 7 * This software is distributed with NO WARRANTIES, not even the implied 8 * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 9 * 10 * Authors grant any other persons or organisations permission to use 11 * or modify this software as long as this message is kept with the software, 12 * all derivative works or modified versions. 13 * 14 * Cronyx Id: ctaureg.h,v 1.1.2.1 2003/11/12 17:16:10 rik Exp $ 15 * $FreeBSD: releng/10.3/sys/dev/ctau/ctaureg.h 139749 2005-01-06 01:43:34Z imp $ 16 */ 17 18/* 19 * Chip register address, B is chip base port, R is chip register number. 20 */ 21#define R(b,r) ((b) | 0x8000 | (((r)<<6 & 0x3c00) | ((r) & 0xf))) 22 23/* 24 * Interface board registers, R is register number 0..7. 25 */ 26#define GR(p,r) ((p) | 0x0010 | (r)<<1) 27 28/*------------------------------------------------------------ 29 * Basic Tau model. 30 */ 31#define BSR0(p) (p) /* board status register 0, read only */ 32#define BSR1(p) ((p) | 0x2000) /* board status register 1, read only */ 33#define BSR2(p) ((p) | 0x4010) /* board status register 2, read only */ 34#define BSR3(p) ((p) | 0x4000) /* board status register 3, read only */ 35#define BCR0(p) (p) /* board command register 0, write only */ 36#define BCR1(p) ((p) | 0x2000) /* board command register 1, write only */ 37#define BCR2(p) ((p) | 0x4010) /* board command register 2, write only */ 38#define BCR3(p) ((p) | 0x4000) /* board command register 3, write only */ 39#define IACK(p) ((p) | 0x6000) /* interrupt acknowledge register, ro */ 40 41/* 42 * Board status register 0 bits. 43 */ 44#define BSR0_INTR 0x01 /* interrupt pending flag */ 45#define BSR0_HDINT 0x02 /* HD64570 interrupt pending */ 46#define BSR0_GINT 0x04 /* interface board interrupt pending */ 47#define BSR0_RDYERR 0x10 /* HD64570 reg.i/o error - not ready */ 48 49#define BSR0_TE1 0x02 /* 0 - E1 daughter board installed */ 50#define BSR0_T703 0x04 /* 0 - G.703 daughter board installed */ 51 52/* 53 * Board status register 1 bits. 54 */ 55#define BSR1_DSR0 0x01 /* DSR from channel 0 */ 56#define BSR1_DSR1 0x02 /* DSR from channel 1 */ 57 58#define BSR1_CH0_CABLE 0x0c /* channel 0 cable type mask */ 59#define BSR1_CH0_V35 0x0c /* channel 0 is V.35 */ 60#define BSR1_CH0_RS232 0x08 /* channel 0 is RS-232 or not connected */ 61#define BSR1_CH0_X21 0x04 /* channel 0 is X.21 */ 62#define BSR1_CH0_RS530 0x00 /* channel 0 is RS-530 */ 63 64#define BSR1_CH1_CABLE 0x30 /* channel 1 cable type mask */ 65#define BSR1_CH1_SHIFT 2 66#define BSR1_CH1_V35 0x0c /* channel 1 is V.35 */ 67#define BSR1_CH1_RS232 0x08 /* channel 1 is RS-232 or not connected */ 68#define BSR1_CH1_X21 0x04 /* channel 1 is X.21 */ 69#define BSR1_CH1_RS530 0x00 /* channel 1 is RS-530 */ 70 71/* 72 * Board status register 2 bits. 73 */ 74#define BSR2_GINT0 0x08 /* interface board chan0 interrupt pending */ 75#define BSR2_GINT1 0x40 /* interface board chan1 interrupt pending */ 76#define BSR2_LERR 0x80 /* firmware download error signal */ 77 78/* 79 * Board status register 3 bits. 80 */ 81#define BSR3_IB 0x08 /* identification bit */ 82#define BSR3_NSTATUS 0x10 /* firmware download status */ 83#define BSR3_CONF_DN 0x20 /* firmware download done */ 84#define BSR3_IB_NEG 0x40 /* negated identification bit */ 85#define BSR3_ZERO 0x80 /* always zero */ 86 87/* 88 * Board control register 0 bits. 89 */ 90#define BCR0_IRQ_DIS 0x00 /* no interrupt generated */ 91#define BCR0_IRQ_3 0x01 /* select IRQ number 3 */ 92#define BCR0_IRQ_5 0x02 /* select IRQ number 5 */ 93#define BCR0_IRQ_7 0x03 /* select IRQ number 7 */ 94#define BCR0_IRQ_10 0x04 /* select IRQ number 10 */ 95#define BCR0_IRQ_11 0x05 /* select IRQ number 11 */ 96#define BCR0_IRQ_12 0x06 /* select IRQ number 12 */ 97#define BCR0_IRQ_15 0x07 /* select IRQ number 15 */ 98#define BCR0_IRQ_MASK 0x07 /* IRQ mask */ 99 100#define BCR0_HDRUN 0x08 /* inverted board reset flag */ 101 102#define BCR0_DMA_DIS 0x00 /* no interrupt generated */ 103#define BCR0_DMA_5 0x10 /* select DMA channel 5 */ 104#define BCR0_DMA_6 0x20 /* select DMA channel 6 */ 105#define BCR0_DMA_7 0x30 /* select DMA channel 7 */ 106 107#define BCR0_TCK 0x80 /* firmware download TCK signal */ 108 109/* 110 * Board control register 1 bits. 111 */ 112#define BCR1_DTR0 0x01 /* channel 0 DTR enable */ 113#define BCR1_DTR1 0x02 /* channel 1 DTR enable */ 114 115#define BCR1_TXCOUT0 0x10 /* channel 0 TXCOUT enable */ 116#define BCR1_TXCOUT1 0x20 /* channel 1 TXCOUT enable */ 117 118#define BCR1_TMS 0x08 /* firmware download TMS signal */ 119#define BCR1_TDI 0x80 /* firmware download TDI signal */ 120 121#define BCR1_NCONFIGI 0x08 /* firmware download start */ 122#define BCR1_DCLK 0x40 /* firmware download clock */ 123#define BCR1_1KDAT 0x80 /* firmware download data */ 124 125/* 126 * Board control register 2 bits -- see ctau.h. 127 */ 128 129#define IMVR(b) R(b,HD_IMVR) /* interrupt modified vector reg. */ 130#define ITCR(b) R(b,HD_ITCR) /* interrupt control register */ 131#define ISR0(b) R(b,HD_ISR0) /* interrupt status register 0, ro */ 132#define ISR1(b) R(b,HD_ISR1) /* interrupt status register 1, ro */ 133#define ISR2(b) R(b,HD_ISR2) /* interrupt status register 2, ro */ 134#define IER0(b) R(b,HD_IER0) /* interrupt enable register 0 */ 135#define IER1(b) R(b,HD_IER1) /* interrupt enable register 1 */ 136#define IER2(b) R(b,HD_IER2) /* interrupt enable register 2 */ 137#define PCR(b) R(b,HD_PCR) /* DMA priority control register */ 138#define DMER(b) R(b,HD_DMER) /* DMA master enable register */ 139#define WCRL(b) R(b,HD_WCRL) /* wait control register L */ 140#define WCRM(b) R(b,HD_WCRM) /* wait control register M */ 141#define WCRH(b) R(b,HD_WCRH) /* wait control register H */ 142 143/*------------------------------------------------------------ 144 * Tau/E1 model. 145 */ 146#define E1CFG(p) GR(p,0) /* control register 0, write only */ 147#define E1SR(p) GR(p,0) /* status register, read only */ 148#define E1CS2(p) GR(p,1) /* chip select 2/IACK, read/write */ 149#define E1SYN(p) GR(p,3) /* sync mode enable, write only */ 150#define E1CS0(p) GR(p,4) /* chip select 0, write only */ 151#define E1CS1(p) GR(p,5) /* chip select 1, write only */ 152#define E1DAT(p) GR(p,7) /* selected chip read/write */ 153 154/* 155 * Tau/E1 CS2/IACK register bits. 156 */ 157#define E1CS2_IACK 0x08 /* serial controller interrupt acknowledge */ 158#define E1CS2_SCC 0x04 /* serial controller select */ 159#define E1CS2_AB 0x02 /* serial controller A/B signal */ 160#define E1CS2_DC 0x01 /* serial controller D/C signal */ 161 162/* 163 * Tau/E1 control register bits. 164 */ 165#define E1CFG_II 0x00 /* configuration II */ 166#define E1CFG_K 0x01 /* configuration K */ 167#define E1CFG_HI 0x02 /* configuration HI */ 168#define E1CFG_D 0x03 /* configuration D */ 169 170#define E1CFG_CLK0_INT 0x00 /* channel E0 transmit clock - internal */ 171#define E1CFG_CLK0_RCV 0x04 /* channel E0 transmit clock - RCLK0 */ 172#define E1CFG_CLK0_RCLK1 0x08 /* channel E0 transmit clock - RCLK1 */ 173 174#define E1CFG_CLK1_INT 0x00 /* channel E1 transmit clock - internal */ 175#define E1CFG_CLK1_RCLK0 0x10 /* channel E1 transmit clock - RCLK0 */ 176#define E1CFG_CLK1_RCV 0x20 /* channel E1 transmit clock - RCLK1 */ 177 178#define E1CFG_LED 0x40 /* LED control */ 179#define E1CFG_GRUN 0x80 /* global run flag */ 180 181/* 182 * Tau/E1 sync control register bits. 183 */ 184#define E1SYN_ENS0 0x01 /* enable channel 0 sync mode */ 185#define E1SYN_ENS1 0x02 /* enable channel 1 sync mode */ 186 187/* 188 * Tau/E1 status register bits. 189 */ 190#define E1SR_E0_IRQ0 0x01 /* E0 controller interrupt 0 */ 191#define E1SR_E0_IRQ1 0x02 /* E0 controller interrupt 1 */ 192#define E1SR_E1_IRQ0 0x04 /* E1 controller interrupt 0 */ 193#define E1SR_E1_IRQ1 0x08 /* E1 controller interrupt 1 */ 194#define E1SR_SCC_IRQ 0x10 /* serial controller interrupt */ 195#define E1SR_TP0 0x20 /* channel 0 is twisted pair */ 196#define E1SR_TP1 0x40 /* channel 1 is twisted pair */ 197#define E1SR_REV 0x80 /* Tau/E1 revision */ 198 199/* 200 * Tau/E1 serial memory register bits. 201 */ 202 203/*------------------------------------------------------------ 204 * Tau/G.703 model. 205 */ 206#define GLCR0(p) GR(p,3) /* line control register 0, write only */ 207#define GMD0(p) GR(p,4) /* mode register 0, write only */ 208#define GMD1(p) GR(p,5) /* mode register 1, write only */ 209#define GMD2(p) GR(p,6) /* mode register 2, write only */ 210#define GLCR1(p) GR(p,7) /* line control register 1, write only */ 211#define GERR(p) GR(p,0) /* error register, read/write */ 212#define GLQ(p) GR(p,1) /* line quality register, read only */ 213#define GLDR(p) GR(p,2) /* loop detect request, read only */ 214 215/* 216 * Tau/G.703 mode register 0/1 bits. 217 */ 218#define GMD_2048 0x00 /* 2048 kbit/sec */ 219#define GMD_1024 0x02 /* 1024 kbit/sec */ 220#define GMD_512 0x03 /* 512 kbit/sec */ 221#define GMD_256 0x04 /* 256 kbit/sec */ 222#define GMD_128 0x05 /* 128 kbit/sec */ 223#define GMD_64 0x06 /* 64 kbit/sec */ 224 225#define GMD_RSYNC 0x08 /* receive synchronization */ 226#define GMD_PCE_PCM2 0x10 /* precoder enable, mode PCM2 */ 227#define GMD_PCE_PCM2D 0x20 /* precoder enable, mode PCM2D */ 228 229#define GMD0_SDI 0x40 /* serial data input */ 230#define GMD0_SCLK 0x80 /* serial data clock */ 231 232#define GMD1_NCS0 0x40 /* chip select 0 inverted */ 233#define GMD1_NCS1 0x80 /* chip select 1 inverted */ 234 235/* 236 * Tau/G.703 mode register 2 bits. 237 */ 238#define GMD2_SERIAL 0x01 /* channel 1 serial interface V.35/RS-232/etc */ 239#define GMD2_LED 0x02 /* LED control */ 240#define GMD2_RAW0 0x04 /* channel 0 raw mode (byte-sync) */ 241#define GMD2_RAW1 0x08 /* channel 1 raw mode (byte-sync) */ 242 243/* 244 * Tau/G.703 interrupt status register bits. 245 */ 246#define GERR_BPV0 0x01 /* channel 0 bipolar violation */ 247#define GERR_ERR0 0x02 /* channel 0 test error */ 248#define GERR_BPV1 0x04 /* channel 1 bipolar violation */ 249#define GERR_ERR1 0x08 /* channel 1 test error */ 250 251/* 252 * Tau/G.703 line quality register bits. 253 */ 254#define GLQ_MASK 0x03 /* channel 0 mask */ 255#define GLQ_SHIFT 2 /* channel 1 shift */ 256 257#define GLQ_DB0 0x00 /* channel 0 level 0.0 dB */ 258#define GLQ_DB95 0x01 /* channel 0 level -9.5 dB */ 259#define GLQ_DB195 0x02 /* channel 0 level -19.5 dB */ 260#define GLQ_DB285 0x03 /* channel 0 level -28.5 dB */ 261 262/* 263 * Tau/G.703 serial data output register bits. 264 */ 265#define GLDR_C0 0x01 /* chip 0 serial data output */ 266#define GLDR_LREQ0 0x02 /* channel 0 remote loop request */ 267#define GLDR_C1 0x04 /* chip 1 serial data output */ 268#define GLDR_LREQ1 0x08 /* channel 1 remote loop request */ 269 270/* 271 * Tau/G.703 line control register 0/1 bits. 272 */ 273#define GLCR_RENABLE 0x00 /* normal mode, auto remote loop enabled */ 274#define GLCR_RDISABLE 0x01 /* normal mode, auto remote loop disabled */ 275#define GLCR_RREFUSE 0x02 /* send the remote loop request sequence */ 276#define GLCR_RREQUEST 0x03 /* send the remote loop refuse sequence */ 277