if_casvar.h revision 194904
1193323Sed/*- 2193323Sed * Copyright (C) 2001 Eduardo Horvath. 3193323Sed * Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org> 4193323Sed * All rights reserved. 5193323Sed * 6193323Sed * Redistribution and use in source and binary forms, with or without 7193323Sed * modification, are permitted provided that the following conditions 8193323Sed * are met: 9193323Sed * 1. Redistributions of source code must retain the above copyright 10193323Sed * notice, this list of conditions and the following disclaimer. 11193323Sed * 2. Redistributions in binary form must reproduce the above copyright 12193323Sed * notice, this list of conditions and the following disclaimer in the 13193323Sed * documentation and/or other materials provided with the distribution. 14193323Sed * 15193323Sed * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 16193323Sed * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17193323Sed * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18193323Sed * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 19193323Sed * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20193323Sed * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21193323Sed * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22193323Sed * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23193323Sed * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24193323Sed * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25193323Sed * SUCH DAMAGE. 26193323Sed * 27193323Sed * from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp 28193323Sed * from: FreeBSD: if_gemvar.h 177560 2008-03-24 17:23:53Z marius 29193323Sed * 30193323Sed * $FreeBSD: head/sys/dev/cas/if_casvar.h 194904 2009-06-24 20:56:06Z marius $ 31193323Sed */ 32193323Sed 33193323Sed#ifndef _IF_CASVAR_H 34193323Sed#define _IF_CASVAR_H 35193323Sed 36193323Sed/* 37193323Sed * The page size is configurable, but needs to be at least 8k (the 38193323Sed * default) in order to also support jumbo buffers. 39193323Sed */ 40193323Sed#define CAS_PAGE_SIZE 8192 41193323Sed 42193323Sed/* 43193323Sed * Transmit descriptor ring size - this is arbitrary, but allocate 44193323Sed * enough descriptors for 64 pending transmissions and 16 segments 45193323Sed * per packet. This limit is not actually enforced (packets with 46193323Sed * more segments can be sent, depending on the busdma backend); it 47193323Sed * is however used as an estimate for the TX window size. 48193323Sed */ 49193323Sed#define CAS_NTXSEGS 16 50212904Sdim 51218893Sdim#define CAS_TXQUEUELEN 64 52193323Sed#define CAS_NTXDESC (CAS_TXQUEUELEN * CAS_NTXSEGS) 53193323Sed#define CAS_MAXTXFREE (CAS_NTXDESC - 1) 54193323Sed#define CAS_NTXDESC_MASK (CAS_NTXDESC - 1) 55193323Sed#define CAS_NEXTTX(x) ((x + 1) & CAS_NTXDESC_MASK) 56193323Sed 57193323Sed/* 58193323Sed * Receive completion ring size - we have one completion per 59193323Sed * incoming packet (though the opposite isn't necesarrily true), 60193323Sed * so this logic is a little simpler. 61193323Sed */ 62193323Sed#define CAS_NRXCOMP 4096 63193323Sed#define CAS_NRXCOMP_MASK (CAS_NRXCOMP - 1) 64193323Sed#define CAS_NEXTRXCOMP(x) ((x + 1) & CAS_NRXCOMP_MASK) 65193323Sed 66193323Sed/* 67193323Sed * Receive descriptor ring sizes - for Cassini+ and Saturn both 68193323Sed * rings must be at least initialized. 69193323Sed */ 70193323Sed#define CAS_NRXDESC 1024 71193323Sed#define CAS_NRXDESC_MASK (CAS_NRXDESC - 1) 72193323Sed#define CAS_NEXTRXDESC(x) ((x + 1) & CAS_NRXDESC_MASK) 73193323Sed#define CAS_NRXDESC2 32 74193323Sed#define CAS_NRXDESC2_MASK (CAS_NRXDESC2 - 1) 75193323Sed#define CAS_NEXTRXDESC2(x) ((x + 1) & CAS_NRXDESC2_MASK) 76193323Sed 77193323Sed/* 78193323Sed * How many ticks to wait until to retry on a RX descriptor that is 79193323Sed * still owned by the hardware. 80193323Sed */ 81193323Sed#define CAS_RXOWN_TICKS (hz / 50) 82193323Sed 83193323Sed/* 84193323Sed * Control structures are DMA'd to the chip. We allocate them 85193323Sed * in a single clump that maps to a single DMA segment to make 86193323Sed * several things easier. 87193323Sed */ 88193323Sedstruct cas_control_data { 89193323Sed struct cas_desc ccd_txdescs[CAS_NTXDESC]; /* TX descriptors */ 90193323Sed struct cas_rx_comp ccd_rxcomps[CAS_NRXCOMP]; /* RX completions */ 91193323Sed struct cas_desc ccd_rxdescs[CAS_NRXDESC]; /* RX descriptors */ 92193323Sed struct cas_desc ccd_rxdescs2[CAS_NRXDESC2]; /* RX descriptors 2 */ 93193323Sed}; 94193323Sed 95193323Sed#define CAS_CDOFF(x) offsetof(struct cas_control_data, x) 96193323Sed#define CAS_CDTXDOFF(x) CAS_CDOFF(ccd_txdescs[(x)]) 97193323Sed#define CAS_CDRXCOFF(x) CAS_CDOFF(ccd_rxcomps[(x)]) 98193323Sed#define CAS_CDRXDOFF(x) CAS_CDOFF(ccd_rxdescs[(x)]) 99193323Sed#define CAS_CDRXD2OFF(x) CAS_CDOFF(ccd_rxdescs2[(x)]) 100193323Sed 101193323Sed/* 102193323Sed * software state for transmit job mbufs (may be elements of mbuf chains) 103193323Sed */ 104193323Sedstruct cas_txsoft { 105193323Sed struct mbuf *txs_mbuf; /* head of our mbuf chain */ 106193323Sed bus_dmamap_t txs_dmamap; /* our DMA map */ 107193323Sed u_int txs_firstdesc; /* first descriptor in packet */ 108193323Sed u_int txs_lastdesc; /* last descriptor in packet */ 109193323Sed u_int txs_ndescs; /* number of descriptors */ 110193323Sed STAILQ_ENTRY(cas_txsoft) txs_q; 111193323Sed}; 112193323Sed 113193323SedSTAILQ_HEAD(cas_txsq, cas_txsoft); 114193323Sed 115193323Sed/* 116193323Sed * software state for receive descriptors 117193323Sed */ 118193323Sedstruct cas_rxdsoft { 119193323Sed void *rxds_buf; /* receive buffer */ 120193323Sed bus_dmamap_t rxds_dmamap; /* our DMA map */ 121193323Sed bus_addr_t rxds_paddr; /* physical address of the segment */ 122193323Sed#if __FreeBSD_version < 800016 123193323Sed struct cas_softc *rxds_sc; /* softc pointer */ 124193323Sed u_int rxds_idx; /* our index */ 125193323Sed#endif 126193323Sed u_int rxds_refcount; /* hardware + mbuf references */ 127193323Sed}; 128193323Sed 129193323Sed/* 130193323Sed * software state per device 131193323Sed */ 132193323Sedstruct cas_softc { 133193323Sed struct ifnet *sc_ifp; 134193323Sed struct mtx sc_mtx; 135193323Sed device_t sc_miibus; 136193323Sed struct mii_data *sc_mii; /* MII media control */ 137193323Sed device_t sc_dev; /* generic device information */ 138193323Sed u_char sc_enaddr[ETHER_ADDR_LEN]; 139193323Sed struct callout sc_tick_ch; /* tick callout */ 140193323Sed struct callout sc_rx_ch; /* delayed RX callout */ 141193323Sed struct task sc_intr_task; 142193323Sed struct task sc_tx_task; 143193323Sed struct taskqueue *sc_tq; 144193323Sed u_int sc_wdog_timer; /* watchdog timer */ 145193323Sed 146212904Sdim void *sc_ih; 147193323Sed struct resource *sc_res[2]; 148193323Sed#define CAS_RES_INTR 0 149193323Sed#define CAS_RES_MEM 1 150193323Sed 151193323Sed bus_dma_tag_t sc_pdmatag; /* parent bus DMA tag */ 152193323Sed bus_dma_tag_t sc_rdmatag; /* RX bus DMA tag */ 153193323Sed bus_dma_tag_t sc_tdmatag; /* TX bus DMA tag */ 154193323Sed bus_dma_tag_t sc_cdmatag; /* control data bus DMA tag */ 155193323Sed bus_dmamap_t sc_dmamap; /* bus DMA handle */ 156193323Sed 157193323Sed u_int sc_phyad; /* PHY to use or -1 for any */ 158193323Sed 159193323Sed u_int sc_variant; 160193323Sed#define CAS_UNKNOWN 0 /* don't know */ 161193323Sed#define CAS_CAS 1 /* Sun Cassini */ 162193323Sed#define CAS_CASPLUS 2 /* Sun Cassini+ */ 163193323Sed#define CAS_SATURN 3 /* National Semiconductor Saturn */ 164193323Sed 165193323Sed u_int sc_flags; 166193323Sed#define CAS_INITED (1 << 0) /* reset persistent regs init'ed */ 167193323Sed#define CAS_NO_CSUM (1 << 1) /* don't use hardware checksumming */ 168#define CAS_LINK (1 << 2) /* link is up */ 169#define CAS_REG_PLUS (1 << 3) /* has Cassini+ registers */ 170#define CAS_SERDES (1 << 4) /* use the SERDES */ 171#define CAS_TABORT (1 << 5) /* has target abort issues */ 172 173 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 174 bus_addr_t sc_cddma; 175 176 /* 177 * software state for transmit and receive descriptors 178 */ 179 struct cas_txsoft sc_txsoft[CAS_TXQUEUELEN]; 180 struct cas_rxdsoft sc_rxdsoft[CAS_NRXDESC]; 181 182 /* 183 * control data structures 184 */ 185 struct cas_control_data *sc_control_data; 186#define sc_txdescs sc_control_data->ccd_txdescs 187#define sc_rxcomps sc_control_data->ccd_rxcomps 188#define sc_rxdescs sc_control_data->ccd_rxdescs 189#define sc_rxdescs2 sc_control_data->ccd_rxdescs2 190 191 u_int sc_txfree; /* number of free TX descriptors */ 192 u_int sc_txnext; /* next ready TX descriptor */ 193 u_int sc_txwin; /* TX desc. since last TX intr. */ 194 195 struct cas_txsq sc_txfreeq; /* free software TX descriptors */ 196 struct cas_txsq sc_txdirtyq; /* dirty software TX descriptors */ 197 198 u_int sc_rxcptr; /* next ready RX completion */ 199 u_int sc_rxdptr; /* next ready RX descriptor */ 200 201 int sc_ifflags; 202}; 203 204#define CAS_BARRIER(sc, offs, len, flags) \ 205 bus_barrier((sc)->sc_res[CAS_RES_MEM], (offs), (len), (flags)) 206 207#define CAS_READ_N(n, sc, offs) \ 208 bus_read_ ## n((sc)->sc_res[CAS_RES_MEM], (offs)) 209#define CAS_READ_1(sc, offs) CAS_READ_N(1, (sc), (offs)) 210#define CAS_READ_2(sc, offs) CAS_READ_N(2, (sc), (offs)) 211#define CAS_READ_4(sc, offs) CAS_READ_N(4, (sc), (offs)) 212 213#define CAS_WRITE_N(n, sc, offs, v) \ 214 bus_write_ ## n((sc)->sc_res[CAS_RES_MEM], (offs), (v)) 215#define CAS_WRITE_1(sc, offs, v) CAS_WRITE_N(1, (sc), (offs), (v)) 216#define CAS_WRITE_2(sc, offs, v) CAS_WRITE_N(2, (sc), (offs), (v)) 217#define CAS_WRITE_4(sc, offs, v) CAS_WRITE_N(4, (sc), (offs), (v)) 218 219#define CAS_CDTXDADDR(sc, x) ((sc)->sc_cddma + CAS_CDTXDOFF((x))) 220#define CAS_CDRXCADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXCOFF((x))) 221#define CAS_CDRXDADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXDOFF((x))) 222#define CAS_CDRXD2ADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXD2OFF((x))) 223 224#define CAS_CDSYNC(sc, ops) \ 225 bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops)); 226 227#define __CAS_UPDATE_RXDESC(rxd, rxds, s) \ 228do { \ 229 \ 230 refcount_init(&(rxds)->rxds_refcount, 1); \ 231 (rxd)->cd_buf_ptr = htole64((rxds)->rxds_paddr); \ 232 KASSERT((s) < CAS_RD_BUF_INDEX_MASK >> CAS_RD_BUF_INDEX_SHFT, \ 233 ("%s: RX buffer index too large!", __func__)); \ 234 (rxd)->cd_flags = \ 235 htole64((uint64_t)((s) << CAS_RD_BUF_INDEX_SHFT)); \ 236} while (0) 237 238#define CAS_UPDATE_RXDESC(sc, d, s) \ 239 __CAS_UPDATE_RXDESC(&(sc)->sc_rxdescs[(d)], \ 240 &(sc)->sc_rxdsoft[(s)], (s)) 241 242#if __FreeBSD_version < 800016 243#define CAS_INIT_RXDESC(sc, d, s) \ 244do { \ 245 struct cas_rxdsoft *__rxds = &(sc)->sc_rxdsoft[(s)]; \ 246 \ 247 __rxds->rxds_sc = (sc); \ 248 __rxds->rxds_idx = (s); \ 249 __CAS_UPDATE_RXDESC(&(sc)->sc_rxdescs[(d)], __rxds, (s)); \ 250} while (0) 251#else 252#define CAS_INIT_RXDESC(sc, d, s) CAS_UPDATE_RXDESC(sc, d, s) 253#endif 254 255#define CAS_LOCK_INIT(_sc, _name) \ 256 mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 257#define CAS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 258#define CAS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 259#define CAS_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what)) 260#define CAS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 261#define CAS_LOCK_OWNED(_sc) mtx_owned(&(_sc)->sc_mtx) 262 263#endif 264