ecore_reg.h revision 296373
1/*- 2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: releng/10.3/sys/dev/bxe/ecore_reg.h 284962 2015-06-30 17:44:44Z davidcs $"); 29 30#ifndef ECORE_REG_H 31#define ECORE_REG_H 32 33 34#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR \ 35 (0x1<<0) 36#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS \ 37 (0x1<<2) 38#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU \ 39 (0x1<<5) 40#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT \ 41 (0x1<<3) 42#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR \ 43 (0x1<<4) 44#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND \ 45 (0x1<<1) 46#define ATC_REG_ATC_INIT_DONE \ 47 0x1100bcUL 48#define ATC_REG_ATC_INT_STS_CLR \ 49 0x1101c0UL 50#define ATC_REG_ATC_PRTY_MASK \ 51 0x1101d8UL 52#define ATC_REG_ATC_PRTY_STS_CLR \ 53 0x1101d0UL 54#define BRB1_REG_BRB1_INT_MASK \ 55 0x60128UL 56#define BRB1_REG_BRB1_PRTY_MASK \ 57 0x60138UL 58#define BRB1_REG_BRB1_PRTY_STS_CLR \ 59 0x60130UL 60#define BRB1_REG_MAC_GUARANTIED_0 \ 61 0x601e8UL 62#define BRB1_REG_MAC_GUARANTIED_1 \ 63 0x60240UL 64#define BRB1_REG_NUM_OF_FULL_BLOCKS \ 65 0x60090UL 66#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 \ 67 0x60078UL 68#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 \ 69 0x60068UL 70#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 \ 71 0x60094UL 72#define CCM_REG_CCM_INT_MASK \ 73 0xd01e4UL 74#define CCM_REG_CCM_PRTY_MASK \ 75 0xd01f4UL 76#define CCM_REG_CCM_PRTY_STS_CLR \ 77 0xd01ecUL 78#define CDU_REG_CDU_GLOBAL_PARAMS \ 79 0x101020UL 80#define CDU_REG_CDU_INT_MASK \ 81 0x10103cUL 82#define CDU_REG_CDU_PRTY_MASK \ 83 0x10104cUL 84#define CDU_REG_CDU_PRTY_STS_CLR \ 85 0x101044UL 86#define CFC_REG_AC_INIT_DONE \ 87 0x104078UL 88#define CFC_REG_CAM_INIT_DONE \ 89 0x10407cUL 90#define CFC_REG_CFC_INT_MASK \ 91 0x104108UL 92#define CFC_REG_CFC_INT_STS_CLR \ 93 0x104100UL 94#define CFC_REG_CFC_PRTY_MASK \ 95 0x104118UL 96#define CFC_REG_CFC_PRTY_STS_CLR \ 97 0x104110UL 98#define CFC_REG_DEBUG0 \ 99 0x104050UL 100#define CFC_REG_INIT_REG \ 101 0x10404cUL 102#define CFC_REG_LL_INIT_DONE \ 103 0x104074UL 104#define CFC_REG_NUM_LCIDS_INSIDE_PF \ 105 0x104120UL 106#define CFC_REG_STRONG_ENABLE_PF \ 107 0x104128UL 108#define CFC_REG_WEAK_ENABLE_PF \ 109 0x104124UL 110#define CSDM_REG_CSDM_INT_MASK_0 \ 111 0xc229cUL 112#define CSDM_REG_CSDM_INT_MASK_1 \ 113 0xc22acUL 114#define CSDM_REG_CSDM_PRTY_MASK \ 115 0xc22bcUL 116#define CSDM_REG_CSDM_PRTY_STS_CLR \ 117 0xc22b4UL 118#define CSEM_REG_CSEM_INT_MASK_0 \ 119 0x200110UL 120#define CSEM_REG_CSEM_INT_MASK_1 \ 121 0x200120UL 122#define CSEM_REG_CSEM_PRTY_MASK_0 \ 123 0x200130UL 124#define CSEM_REG_CSEM_PRTY_MASK_1 \ 125 0x200140UL 126#define CSEM_REG_CSEM_PRTY_STS_CLR_0 \ 127 0x200128UL 128#define CSEM_REG_CSEM_PRTY_STS_CLR_1 \ 129 0x200138UL 130#define CSEM_REG_FAST_MEMORY \ 131 0x220000UL 132#define CSEM_REG_INT_TABLE \ 133 0x200400UL 134#define CSEM_REG_PASSIVE_BUFFER \ 135 0x202000UL 136#define CSEM_REG_PRAM \ 137 0x240000UL 138#define CSEM_REG_VFPF_ERR_NUM \ 139 0x200380UL 140#define DBG_REG_DBG_PRTY_MASK \ 141 0xc0a8UL 142#define DBG_REG_DBG_PRTY_STS_CLR \ 143 0xc0a0UL 144#define DMAE_REG_BACKWARD_COMP_EN \ 145 0x10207cUL 146#define DMAE_REG_CMD_MEM \ 147 0x102400UL 148#define DMAE_REG_DMAE_INT_MASK \ 149 0x102054UL 150#define DMAE_REG_DMAE_PRTY_MASK \ 151 0x102064UL 152#define DMAE_REG_DMAE_PRTY_STS_CLR \ 153 0x10205cUL 154#define DMAE_REG_GO_C0 \ 155 0x102080UL 156#define DMAE_REG_GO_C1 \ 157 0x102084UL 158#define DMAE_REG_GO_C10 \ 159 0x102088UL 160#define DMAE_REG_GO_C11 \ 161 0x10208cUL 162#define DMAE_REG_GO_C12 \ 163 0x102090UL 164#define DMAE_REG_GO_C13 \ 165 0x102094UL 166#define DMAE_REG_GO_C14 \ 167 0x102098UL 168#define DMAE_REG_GO_C15 \ 169 0x10209cUL 170#define DMAE_REG_GO_C2 \ 171 0x1020a0UL 172#define DMAE_REG_GO_C3 \ 173 0x1020a4UL 174#define DMAE_REG_GO_C4 \ 175 0x1020a8UL 176#define DMAE_REG_GO_C5 \ 177 0x1020acUL 178#define DMAE_REG_GO_C6 \ 179 0x1020b0UL 180#define DMAE_REG_GO_C7 \ 181 0x1020b4UL 182#define DMAE_REG_GO_C8 \ 183 0x1020b8UL 184#define DMAE_REG_GO_C9 \ 185 0x1020bcUL 186#define DORQ_REG_DORQ_INT_MASK \ 187 0x170180UL 188#define DORQ_REG_DORQ_INT_STS_CLR \ 189 0x170178UL 190#define DORQ_REG_DORQ_PRTY_MASK \ 191 0x170190UL 192#define DORQ_REG_DORQ_PRTY_STS_CLR \ 193 0x170188UL 194#define DORQ_REG_DPM_CID_OFST \ 195 0x170030UL 196#define DORQ_REG_MAX_RVFID_SIZE \ 197 0x1701ecUL 198#define DORQ_REG_NORM_CID_OFST \ 199 0x17002cUL 200#define DORQ_REG_PF_USAGE_CNT \ 201 0x1701d0UL 202#define DORQ_REG_VF_NORM_CID_BASE \ 203 0x1701a0UL 204#define DORQ_REG_VF_NORM_CID_OFST \ 205 0x1701f4UL 206#define DORQ_REG_VF_NORM_CID_WND_SIZE \ 207 0x1701a4UL 208#define DORQ_REG_VF_NORM_MAX_CID_COUNT \ 209 0x1701e4UL 210#define DORQ_REG_VF_NORM_VF_BASE \ 211 0x1701a8UL 212#define DORQ_REG_VF_TYPE_MASK_0 \ 213 0x170218UL 214#define DORQ_REG_VF_TYPE_MAX_MCID_0 \ 215 0x1702d8UL 216#define DORQ_REG_VF_TYPE_MIN_MCID_0 \ 217 0x170298UL 218#define DORQ_REG_VF_TYPE_VALUE_0 \ 219 0x170258UL 220#define DORQ_REG_VF_USAGE_CT_LIMIT \ 221 0x170340UL 222#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 \ 223 (0x1<<4) 224#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 \ 225 (0x1<<0) 226#define HC_CONFIG_0_REG_INT_LINE_EN_0 \ 227 (0x1<<3) 228#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 \ 229 (0x1<<7) 230#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 \ 231 (0x1<<2) 232#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 \ 233 (0x1<<1) 234#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 \ 235 (0x1<<0) 236#define HC_REG_ATTN_MSG0_ADDR_L \ 237 0x108018UL 238#define HC_REG_ATTN_MSG1_ADDR_L \ 239 0x108020UL 240#define HC_REG_COMMAND_REG \ 241 0x108180UL 242#define HC_REG_CONFIG_0 \ 243 0x108000UL 244#define HC_REG_CONFIG_1 \ 245 0x108004UL 246#define HC_REG_HC_PRTY_MASK \ 247 0x1080a0UL 248#define HC_REG_HC_PRTY_STS_CLR \ 249 0x108098UL 250#define HC_REG_INT_MASK \ 251 0x108108UL 252#define HC_REG_LEADING_EDGE_0 \ 253 0x108040UL 254#define HC_REG_MAIN_MEMORY \ 255 0x108800UL 256#define HC_REG_MAIN_MEMORY_SIZE \ 257 152 258#define HC_REG_TRAILING_EDGE_0 \ 259 0x108044UL 260#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN \ 261 (0x1<<1) 262#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE \ 263 (0x1<<0) 264#define IGU_REG_ATTENTION_ACK_BITS \ 265 0x130108UL 266#define IGU_REG_ATTN_MSG_ADDR_H \ 267 0x13011cUL 268#define IGU_REG_ATTN_MSG_ADDR_L \ 269 0x130120UL 270#define IGU_REG_BLOCK_CONFIGURATION \ 271 0x130000UL 272#define IGU_REG_COMMAND_REG_32LSB_DATA \ 273 0x130124UL 274#define IGU_REG_COMMAND_REG_CTRL \ 275 0x13012cUL 276#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP \ 277 0x130200UL 278#define IGU_REG_IGU_PRTY_MASK \ 279 0x1300a8UL 280#define IGU_REG_IGU_PRTY_STS_CLR \ 281 0x1300a0UL 282#define IGU_REG_LEADING_EDGE_LATCH \ 283 0x130134UL 284#define IGU_REG_MAPPING_MEMORY \ 285 0x131000UL 286#define IGU_REG_MAPPING_MEMORY_SIZE \ 287 136 288#define IGU_REG_PBA_STATUS_LSB \ 289 0x130138UL 290#define IGU_REG_PBA_STATUS_MSB \ 291 0x13013cUL 292#define IGU_REG_PCI_PF_MSIX_EN \ 293 0x130144UL 294#define IGU_REG_PCI_PF_MSIX_FUNC_MASK \ 295 0x130148UL 296#define IGU_REG_PCI_PF_MSI_EN \ 297 0x130140UL 298#define IGU_REG_PENDING_BITS_STATUS \ 299 0x130300UL 300#define IGU_REG_PF_CONFIGURATION \ 301 0x130154UL 302#define IGU_REG_PROD_CONS_MEMORY \ 303 0x132000UL 304#define IGU_REG_RESET_MEMORIES \ 305 0x130158UL 306#define IGU_REG_SB_INT_BEFORE_MASK_LSB \ 307 0x13015cUL 308#define IGU_REG_SB_INT_BEFORE_MASK_MSB \ 309 0x130160UL 310#define IGU_REG_SB_MASK_LSB \ 311 0x130164UL 312#define IGU_REG_SB_MASK_MSB \ 313 0x130168UL 314#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT \ 315 0x130800UL 316#define IGU_REG_TRAILING_EDGE_LATCH \ 317 0x130104UL 318#define MCP_REG_MCPR_ACCESS_LOCK \ 319 0x8009c 320#define MCP_REG_MCPR_GP_INPUTS \ 321 0x800c0 322#define MCP_REG_MCPR_GP_OENABLE \ 323 0x800c8 324#define MCP_REG_MCPR_GP_OUTPUTS \ 325 0x800c4 326#define MCP_REG_MCPR_IMC_COMMAND \ 327 0x85900 328#define MCP_REG_MCPR_IMC_DATAREG0 \ 329 0x85920 330#define MCP_REG_MCPR_IMC_SLAVE_CONTROL \ 331 0x85904 332#define MCP_REG_MCPR_NVM_ACCESS_ENABLE \ 333 0x86424 334#define MCP_REG_MCPR_NVM_ADDR \ 335 0x8640c 336#define MCP_REG_MCPR_NVM_CFG4 \ 337 0x8642c 338#define MCP_REG_MCPR_NVM_COMMAND \ 339 0x86400 340#define MCP_REG_MCPR_NVM_READ \ 341 0x86410 342#define MCP_REG_MCPR_NVM_SW_ARB \ 343 0x86420 344#define MCP_REG_MCPR_NVM_WRITE \ 345 0x86408 346#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK \ 347 (0x1<<1) 348#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK \ 349 (0x1<<0) 350#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 \ 351 0xa42cUL 352#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 \ 353 0xa438UL 354#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 \ 355 0xa444UL 356#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 \ 357 0xa450UL 358#define MISC_REG_AEU_AFTER_INVERT_4_MCP \ 359 0xa458UL 360#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 \ 361 0xa700UL 362#define MISC_REG_AEU_CLR_LATCH_SIGNAL \ 363 0xa45cUL 364#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 \ 365 0xa06cUL 366#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 \ 367 0xa07cUL 368#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 \ 369 0xa08cUL 370#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 \ 371 0xa10cUL 372#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 \ 373 0xa11cUL 374#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 \ 375 0xa12cUL 376#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 \ 377 0xa078UL 378#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 \ 379 0xa118UL 380#define MISC_REG_AEU_ENABLE4_NIG_0 \ 381 0xa0f8UL 382#define MISC_REG_AEU_ENABLE4_NIG_1 \ 383 0xa198UL 384#define MISC_REG_AEU_ENABLE4_PXP_0 \ 385 0xa108UL 386#define MISC_REG_AEU_ENABLE4_PXP_1 \ 387 0xa1a8UL 388#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 \ 389 0xa688UL 390#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 \ 391 0xa6b0UL 392#define MISC_REG_AEU_GENERAL_ATTN_1 \ 393 0xa004UL 394#define MISC_REG_AEU_GENERAL_ATTN_10 \ 395 0xa028UL 396#define MISC_REG_AEU_GENERAL_ATTN_11 \ 397 0xa02cUL 398#define MISC_REG_AEU_GENERAL_ATTN_12 \ 399 0xa030UL 400#define MISC_REG_AEU_GENERAL_ATTN_2 \ 401 0xa008UL 402#define MISC_REG_AEU_GENERAL_ATTN_3 \ 403 0xa00cUL 404#define MISC_REG_AEU_GENERAL_ATTN_4 \ 405 0xa010UL 406#define MISC_REG_AEU_GENERAL_ATTN_5 \ 407 0xa014UL 408#define MISC_REG_AEU_GENERAL_ATTN_6 \ 409 0xa018UL 410#define MISC_REG_AEU_GENERAL_ATTN_7 \ 411 0xa01cUL 412#define MISC_REG_AEU_GENERAL_ATTN_8 \ 413 0xa020UL 414#define MISC_REG_AEU_GENERAL_ATTN_9 \ 415 0xa024UL 416#define MISC_REG_AEU_GENERAL_MASK \ 417 0xa61cUL 418#define MISC_REG_AEU_MASK_ATTN_FUNC_0 \ 419 0xa060UL 420#define MISC_REG_AEU_MASK_ATTN_FUNC_1 \ 421 0xa064UL 422#define MISC_REG_BOND_ID \ 423 0xa400UL 424#define MISC_REG_CHIP_NUM \ 425 0xa408UL 426#define MISC_REG_CHIP_REV \ 427 0xa40cUL 428#define MISC_REG_CHIP_TYPE \ 429 0xac60UL 430#define MISC_REG_CHIP_TYPE_57811_MASK \ 431 (1<<1) 432#define MISC_REG_CPMU_LP_DR_ENABLE \ 433 0xa858UL 434#define MISC_REG_CPMU_LP_FW_ENABLE_P0 \ 435 0xa84cUL 436#define MISC_REG_CPMU_LP_IDLE_THR_P0 \ 437 0xa8a0UL 438#define MISC_REG_CPMU_LP_MASK_ENT_P0 \ 439 0xa880UL 440#define MISC_REG_CPMU_LP_MASK_EXT_P0 \ 441 0xa888UL 442#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 \ 443 0xa8b8UL 444#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 \ 445 0xa8bcUL 446#define MISC_REG_DRIVER_CONTROL_1 \ 447 0xa510UL 448#define MISC_REG_DRIVER_CONTROL_7 \ 449 0xa3c8UL 450#define MISC_REG_FOUR_PORT_PATH_SWAP \ 451 0xa75cUL 452#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR \ 453 0xa738UL 454#define MISC_REG_FOUR_PORT_PORT_SWAP \ 455 0xa754UL 456#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR \ 457 0xa734UL 458#define MISC_REG_GENERIC_CR_0 \ 459 0xa460UL 460#define MISC_REG_GENERIC_CR_1 \ 461 0xa464UL 462#define MISC_REG_GENERIC_POR_1 \ 463 0xa474UL 464#define MISC_REG_GEN_PURP_HWG \ 465 0xa9a0UL 466#define MISC_REG_GPIO \ 467 0xa490UL 468#define MISC_REG_GPIO_EVENT_EN \ 469 0xa2bcUL 470#define MISC_REG_GPIO_INT \ 471 0xa494UL 472#define MISC_REG_GRC_RSV_ATTN \ 473 0xa3c0UL 474#define MISC_REG_GRC_TIMEOUT_ATTN \ 475 0xa3c4UL 476#define MISC_REG_LCPLL_E40_PWRDWN \ 477 0xaa74UL 478#define MISC_REG_LCPLL_E40_RESETB_ANA \ 479 0xaa78UL 480#define MISC_REG_LCPLL_E40_RESETB_DIG \ 481 0xaa7cUL 482#define MISC_REG_MISC_INT_MASK \ 483 0xa388UL 484#define MISC_REG_MISC_PRTY_MASK \ 485 0xa398UL 486#define MISC_REG_MISC_PRTY_STS_CLR \ 487 0xa390UL 488#define MISC_REG_PORT4MODE_EN \ 489 0xa750UL 490#define MISC_REG_PORT4MODE_EN_OVWR \ 491 0xa720UL 492#define MISC_REG_RESET_REG_1 \ 493 0xa580UL 494#define MISC_REG_RESET_REG_2 \ 495 0xa590UL 496#define MISC_REG_SHARED_MEM_ADDR \ 497 0xa2b4UL 498#define MISC_REG_SPIO \ 499 0xa4fcUL 500#define MISC_REG_SPIO_EVENT_EN \ 501 0xa2b8UL 502#define MISC_REG_SPIO_INT \ 503 0xa500UL 504#define MISC_REG_TWO_PORT_PATH_SWAP \ 505 0xa758UL 506#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR \ 507 0xa72cUL 508#define MISC_REG_UNPREPARED \ 509 0xa424UL 510#define MISC_REG_WC0_CTRL_PHY_ADDR \ 511 0xa9ccUL 512#define MISC_REG_WC0_RESET \ 513 0xac30UL 514#define MISC_REG_XMAC_CORE_PORT_MODE \ 515 0xa964UL 516#define MISC_REG_XMAC_PHY_PORT_MODE \ 517 0xa960UL 518#define MSTAT_REG_RX_STAT_GR64_LO \ 519 0x200UL 520#define MSTAT_REG_TX_STAT_GTXPOK_LO \ 521 0UL 522#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN \ 523 (0x1<<0) 524#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN \ 525 (0x1<<0) 526#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT \ 527 (0x1<<0) 528#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS \ 529 (0x1<<9) 530#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G \ 531 (0x1<<15) 532#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS \ 533 (0xf<<18) 534#define NIG_REG_BMAC0_IN_EN \ 535 0x100acUL 536#define NIG_REG_BMAC0_OUT_EN \ 537 0x100e0UL 538#define NIG_REG_BMAC0_PAUSE_OUT_EN \ 539 0x10110UL 540#define NIG_REG_BMAC0_REGS_OUT_EN \ 541 0x100e8UL 542#define NIG_REG_BRB0_PAUSE_IN_EN \ 543 0x100c4UL 544#define NIG_REG_BRB1_PAUSE_IN_EN \ 545 0x100c8UL 546#define NIG_REG_DEBUG_PACKET_LB \ 547 0x10800UL 548#define NIG_REG_EGRESS_DRAIN0_MODE \ 549 0x10060UL 550#define NIG_REG_EGRESS_EMAC0_OUT_EN \ 551 0x10120UL 552#define NIG_REG_EGRESS_EMAC0_PORT \ 553 0x10058UL 554#define NIG_REG_EMAC0_IN_EN \ 555 0x100a4UL 556#define NIG_REG_EMAC0_PAUSE_OUT_EN \ 557 0x10118UL 558#define NIG_REG_EMAC0_STATUS_MISC_MI_INT \ 559 0x10494UL 560#define NIG_REG_INGRESS_BMAC0_MEM \ 561 0x10c00UL 562#define NIG_REG_INGRESS_BMAC1_MEM \ 563 0x11000UL 564#define NIG_REG_INGRESS_EOP_LB_EMPTY \ 565 0x104e0UL 566#define NIG_REG_INGRESS_EOP_LB_FIFO \ 567 0x104e4UL 568#define NIG_REG_LATCH_BC_0 \ 569 0x16210UL 570#define NIG_REG_LATCH_STATUS_0 \ 571 0x18000UL 572#define NIG_REG_LED_10G_P0 \ 573 0x10320UL 574#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 \ 575 0x10318UL 576#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 \ 577 0x10310UL 578#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 \ 579 0x10308UL 580#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 \ 581 0x102f8UL 582#define NIG_REG_LED_CONTROL_TRAFFIC_P0 \ 583 0x10300UL 584#define NIG_REG_LED_MODE_P0 \ 585 0x102f0UL 586#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 \ 587 0x16070UL 588#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 \ 589 0x16074UL 590#define NIG_REG_LLFC_ENABLE_0 \ 591 0x16208UL 592#define NIG_REG_LLFC_ENABLE_1 \ 593 0x1620cUL 594#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 \ 595 0x16058UL 596#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 \ 597 0x1605cUL 598#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 \ 599 0x16060UL 600#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 \ 601 0x16064UL 602#define NIG_REG_LLFC_OUT_EN_0 \ 603 0x160c8UL 604#define NIG_REG_LLFC_OUT_EN_1 \ 605 0x160ccUL 606#define NIG_REG_LLH0_BRB1_DRV_MASK \ 607 0x10244UL 608#define NIG_REG_LLH0_BRB1_DRV_MASK_MF \ 609 0x16048UL 610#define NIG_REG_LLH0_BRB1_NOT_MCP \ 611 0x1025cUL 612#define NIG_REG_LLH0_CLS_TYPE \ 613 0x16080UL 614#define NIG_REG_LLH0_FUNC_EN \ 615 0x160fcUL 616#define NIG_REG_LLH0_FUNC_MEM \ 617 0x16180UL 618#define NIG_REG_LLH0_FUNC_MEM_ENABLE \ 619 0x16140UL 620#define NIG_REG_LLH0_FUNC_VLAN_ID \ 621 0x16100UL 622#define NIG_REG_LLH0_XCM_MASK \ 623 0x10130UL 624#define NIG_REG_LLH1_BRB1_NOT_MCP \ 625 0x102dcUL 626#define NIG_REG_LLH1_CLS_TYPE \ 627 0x16084UL 628#define NIG_REG_LLH1_FUNC_MEM \ 629 0x161c0UL 630#define NIG_REG_LLH1_FUNC_MEM_ENABLE \ 631 0x16160UL 632#define NIG_REG_LLH1_FUNC_MEM_SIZE \ 633 16 634#define NIG_REG_LLH1_MF_MODE \ 635 0x18614UL 636#define NIG_REG_LLH1_XCM_MASK \ 637 0x10134UL 638#define NIG_REG_LLH_E1HOV_MODE \ 639 0x160d8UL 640#define NIG_REG_LLH_MF_MODE \ 641 0x16024UL 642#define NIG_REG_MASK_INTERRUPT_PORT0 \ 643 0x10330UL 644#define NIG_REG_MASK_INTERRUPT_PORT1 \ 645 0x10334UL 646#define NIG_REG_NIG_EMAC0_EN \ 647 0x1003cUL 648#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC \ 649 0x10044UL 650#define NIG_REG_NIG_INT_STS_CLR_0 \ 651 0x103b4UL 652#define NIG_REG_NIG_PRTY_MASK \ 653 0x103dcUL 654#define NIG_REG_NIG_PRTY_MASK_0 \ 655 0x183c8UL 656#define NIG_REG_NIG_PRTY_MASK_1 \ 657 0x183d8UL 658#define NIG_REG_NIG_PRTY_STS_CLR \ 659 0x103d4UL 660#define NIG_REG_NIG_PRTY_STS_CLR_0 \ 661 0x183c0UL 662#define NIG_REG_NIG_PRTY_STS_CLR_1 \ 663 0x183d0UL 664#define NIG_REG_P0_HDRS_AFTER_BASIC \ 665 0x18038UL 666#define NIG_REG_P0_HWPFC_ENABLE \ 667 0x18078UL 668#define NIG_REG_P0_LLH_FUNC_MEM2 \ 669 0x18480UL 670#define NIG_REG_P0_MAC_IN_EN \ 671 0x185acUL 672#define NIG_REG_P0_MAC_OUT_EN \ 673 0x185b0UL 674#define NIG_REG_P0_MAC_PAUSE_OUT_EN \ 675 0x185b4UL 676#define NIG_REG_P0_PKT_PRIORITY_TO_COS \ 677 0x18054UL 678#define NIG_REG_P0_RX_COS0_PRIORITY_MASK \ 679 0x18058UL 680#define NIG_REG_P0_RX_COS1_PRIORITY_MASK \ 681 0x1805cUL 682#define NIG_REG_P0_RX_COS2_PRIORITY_MASK \ 683 0x186b0UL 684#define NIG_REG_P0_RX_COS3_PRIORITY_MASK \ 685 0x186b4UL 686#define NIG_REG_P0_RX_COS4_PRIORITY_MASK \ 687 0x186b8UL 688#define NIG_REG_P0_RX_COS5_PRIORITY_MASK \ 689 0x186bcUL 690#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP \ 691 0x180f0UL 692#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB \ 693 0x18688UL 694#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB \ 695 0x1868cUL 696#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT \ 697 0x180e8UL 698#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ \ 699 0x180ecUL 700#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 \ 701 0x1810cUL 702#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 \ 703 0x18110UL 704#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 \ 705 0x18114UL 706#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 \ 707 0x18118UL 708#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 \ 709 0x1811cUL 710#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 \ 711 0x186a0UL 712#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 \ 713 0x186a4UL 714#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 \ 715 0x186a8UL 716#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 \ 717 0x186acUL 718#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 \ 719 0x180f8UL 720#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 \ 721 0x180fcUL 722#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 \ 723 0x18100UL 724#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 \ 725 0x18104UL 726#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 \ 727 0x18108UL 728#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 \ 729 0x18690UL 730#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 \ 731 0x18694UL 732#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 \ 733 0x18698UL 734#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 \ 735 0x1869cUL 736#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS \ 737 0x180f4UL 738#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT \ 739 0x180e4UL 740#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB \ 741 0x18680UL 742#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB \ 743 0x18684UL 744#define NIG_REG_P1_HDRS_AFTER_BASIC \ 745 0x1818cUL 746#define NIG_REG_P1_HWPFC_ENABLE \ 747 0x181d0UL 748#define NIG_REG_P1_LLH_FUNC_MEM2 \ 749 0x184c0UL 750#define NIG_REG_P1_MAC_IN_EN \ 751 0x185c0UL 752#define NIG_REG_P1_MAC_OUT_EN \ 753 0x185c4UL 754#define NIG_REG_P1_MAC_PAUSE_OUT_EN \ 755 0x185c8UL 756#define NIG_REG_P1_PKT_PRIORITY_TO_COS \ 757 0x181a8UL 758#define NIG_REG_P1_RX_COS0_PRIORITY_MASK \ 759 0x181acUL 760#define NIG_REG_P1_RX_COS1_PRIORITY_MASK \ 761 0x181b0UL 762#define NIG_REG_P1_RX_COS2_PRIORITY_MASK \ 763 0x186f8UL 764#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB \ 765 0x186e8UL 766#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB \ 767 0x186ecUL 768#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT \ 769 0x18234UL 770#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ \ 771 0x18238UL 772#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 \ 773 0x18258UL 774#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 \ 775 0x1825cUL 776#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 \ 777 0x18260UL 778#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 \ 779 0x18264UL 780#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 \ 781 0x18268UL 782#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 \ 783 0x186f4UL 784#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 \ 785 0x18244UL 786#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 \ 787 0x18248UL 788#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 \ 789 0x1824cUL 790#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 \ 791 0x18250UL 792#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 \ 793 0x18254UL 794#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 \ 795 0x186f0UL 796#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS \ 797 0x18240UL 798#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB \ 799 0x186e0UL 800#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB \ 801 0x186e4UL 802#define NIG_REG_PAUSE_ENABLE_0 \ 803 0x160c0UL 804#define NIG_REG_PAUSE_ENABLE_1 \ 805 0x160c4UL 806#define NIG_REG_PORT_SWAP \ 807 0x10394UL 808#define NIG_REG_PPP_ENABLE_0 \ 809 0x160b0UL 810#define NIG_REG_PPP_ENABLE_1 \ 811 0x160b4UL 812#define NIG_REG_PRS_REQ_IN_EN \ 813 0x100b8UL 814#define NIG_REG_SERDES0_CTRL_MD_DEVAD \ 815 0x10370UL 816#define NIG_REG_SERDES0_CTRL_MD_ST \ 817 0x1036cUL 818#define NIG_REG_SERDES0_CTRL_PHY_ADDR \ 819 0x10374UL 820#define NIG_REG_SERDES0_STATUS_LINK_STATUS \ 821 0x10578UL 822#define NIG_REG_STAT0_BRB_DISCARD \ 823 0x105f0UL 824#define NIG_REG_STAT0_BRB_TRUNCATE \ 825 0x105f8UL 826#define NIG_REG_STAT0_EGRESS_MAC_PKT0 \ 827 0x10750UL 828#define NIG_REG_STAT0_EGRESS_MAC_PKT1 \ 829 0x10760UL 830#define NIG_REG_STAT1_BRB_DISCARD \ 831 0x10628UL 832#define NIG_REG_STAT1_EGRESS_MAC_PKT0 \ 833 0x107a0UL 834#define NIG_REG_STAT1_EGRESS_MAC_PKT1 \ 835 0x107b0UL 836#define NIG_REG_STAT2_BRB_OCTET \ 837 0x107e0UL 838#define NIG_REG_STATUS_INTERRUPT_PORT0 \ 839 0x10328UL 840#define NIG_REG_STRAP_OVERRIDE \ 841 0x10398UL 842#define NIG_REG_XCM0_OUT_EN \ 843 0x100f0UL 844#define NIG_REG_XCM1_OUT_EN \ 845 0x100f4UL 846#define NIG_REG_XGXS0_CTRL_MD_DEVAD \ 847 0x1033cUL 848#define NIG_REG_XGXS0_CTRL_MD_ST \ 849 0x10338UL 850#define NIG_REG_XGXS0_CTRL_PHY_ADDR \ 851 0x10340UL 852#define NIG_REG_XGXS0_STATUS_LINK10G \ 853 0x10680UL 854#define NIG_REG_XGXS0_STATUS_LINK_STATUS \ 855 0x10684UL 856#define NIG_REG_XGXS_LANE_SEL_P0 \ 857 0x102e8UL 858#define NIG_REG_XGXS_SERDES0_MODE_SEL \ 859 0x102e0UL 860#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT \ 861 (0x1<<0) 862#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS \ 863 (0x1<<9) 864#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G \ 865 (0x1<<15) 866#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS \ 867 (0xf<<18) 868#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE \ 869 18 870#define PBF_REG_COS0_UPPER_BOUND \ 871 0x15c05cUL 872#define PBF_REG_COS0_UPPER_BOUND_P0 \ 873 0x15c2ccUL 874#define PBF_REG_COS0_UPPER_BOUND_P1 \ 875 0x15c2e4UL 876#define PBF_REG_COS0_WEIGHT \ 877 0x15c054UL 878#define PBF_REG_COS0_WEIGHT_P0 \ 879 0x15c2a8UL 880#define PBF_REG_COS0_WEIGHT_P1 \ 881 0x15c2c0UL 882#define PBF_REG_COS1_UPPER_BOUND \ 883 0x15c060UL 884#define PBF_REG_COS1_WEIGHT \ 885 0x15c058UL 886#define PBF_REG_COS1_WEIGHT_P0 \ 887 0x15c2acUL 888#define PBF_REG_COS1_WEIGHT_P1 \ 889 0x15c2c4UL 890#define PBF_REG_COS2_WEIGHT_P0 \ 891 0x15c2b0UL 892#define PBF_REG_COS2_WEIGHT_P1 \ 893 0x15c2c8UL 894#define PBF_REG_COS3_WEIGHT_P0 \ 895 0x15c2b4UL 896#define PBF_REG_COS4_WEIGHT_P0 \ 897 0x15c2b8UL 898#define PBF_REG_COS5_WEIGHT_P0 \ 899 0x15c2bcUL 900#define PBF_REG_CREDIT_LB_Q \ 901 0x140338UL 902#define PBF_REG_CREDIT_Q0 \ 903 0x14033cUL 904#define PBF_REG_CREDIT_Q1 \ 905 0x140340UL 906#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 \ 907 0x14005cUL 908#define PBF_REG_DISABLE_PF \ 909 0x1402e8UL 910#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 \ 911 0x15c288UL 912#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 \ 913 0x15c28cUL 914#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 \ 915 0x15c278UL 916#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 \ 917 0x15c27cUL 918#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 \ 919 0x15c280UL 920#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 \ 921 0x15c284UL 922#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 \ 923 0x15c2a0UL 924#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 \ 925 0x15c2a4UL 926#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 \ 927 0x15c270UL 928#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 \ 929 0x15c274UL 930#define PBF_REG_ETS_ENABLED \ 931 0x15c050UL 932#define PBF_REG_HDRS_AFTER_BASIC \ 933 0x15c0a8UL 934#define PBF_REG_HDRS_AFTER_TAG_0 \ 935 0x15c0b8UL 936#define PBF_REG_HIGH_PRIORITY_COS_NUM \ 937 0x15c04cUL 938#define PBF_REG_INIT_CRD_LB_Q \ 939 0x15c248UL 940#define PBF_REG_INIT_CRD_Q0 \ 941 0x15c230UL 942#define PBF_REG_INIT_CRD_Q1 \ 943 0x15c234UL 944#define PBF_REG_INIT_P0 \ 945 0x140004UL 946#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q \ 947 0x140354UL 948#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 \ 949 0x140358UL 950#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 \ 951 0x14035cUL 952#define PBF_REG_MUST_HAVE_HDRS \ 953 0x15c0c4UL 954#define PBF_REG_NUM_STRICT_ARB_SLOTS \ 955 0x15c064UL 956#define PBF_REG_P0_ARB_THRSH \ 957 0x1400e4UL 958#define PBF_REG_P0_CREDIT \ 959 0x140200UL 960#define PBF_REG_P0_INIT_CRD \ 961 0x1400d0UL 962#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT \ 963 0x140308UL 964#define PBF_REG_P0_PAUSE_ENABLE \ 965 0x140014UL 966#define PBF_REG_P0_TQ_LINES_FREED_CNT \ 967 0x1402f0UL 968#define PBF_REG_P0_TQ_OCCUPANCY \ 969 0x1402fcUL 970#define PBF_REG_P1_CREDIT \ 971 0x140208UL 972#define PBF_REG_P1_INIT_CRD \ 973 0x1400d4UL 974#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT \ 975 0x14030cUL 976#define PBF_REG_P1_TQ_LINES_FREED_CNT \ 977 0x1402f4UL 978#define PBF_REG_P1_TQ_OCCUPANCY \ 979 0x140300UL 980#define PBF_REG_P4_CREDIT \ 981 0x140210UL 982#define PBF_REG_P4_INIT_CRD \ 983 0x1400e0UL 984#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT \ 985 0x140310UL 986#define PBF_REG_P4_TQ_LINES_FREED_CNT \ 987 0x1402f8UL 988#define PBF_REG_P4_TQ_OCCUPANCY \ 989 0x140304UL 990#define PBF_REG_PBF_INT_MASK \ 991 0x1401d4UL 992#define PBF_REG_PBF_PRTY_MASK \ 993 0x1401e4UL 994#define PBF_REG_PBF_PRTY_STS_CLR \ 995 0x1401dcUL 996#define PBF_REG_TAG_ETHERTYPE_0 \ 997 0x15c090UL 998#define PBF_REG_TAG_LEN_0 \ 999 0x15c09cUL 1000#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q \ 1001 0x14038cUL 1002#define PBF_REG_TQ_LINES_FREED_CNT_Q0 \ 1003 0x140390UL 1004#define PBF_REG_TQ_LINES_FREED_CNT_Q1 \ 1005 0x140394UL 1006#define PBF_REG_TQ_OCCUPANCY_LB_Q \ 1007 0x1403a8UL 1008#define PBF_REG_TQ_OCCUPANCY_Q0 \ 1009 0x1403acUL 1010#define PBF_REG_TQ_OCCUPANCY_Q1 \ 1011 0x1403b0UL 1012#define PB_REG_PB_INT_MASK \ 1013 0x28UL 1014#define PB_REG_PB_PRTY_MASK \ 1015 0x38UL 1016#define PB_REG_PB_PRTY_STS_CLR \ 1017 0x30UL 1018#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR \ 1019 (0x1<<0) 1020#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW \ 1021 (0x1<<8) 1022#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR \ 1023 (0x1<<1) 1024#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN \ 1025 (0x1<<6) 1026#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN \ 1027 (0x1<<7) 1028#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN \ 1029 (0x1<<4) 1030#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN \ 1031 (0x1<<3) 1032#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN \ 1033 (0x1<<5) 1034#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN \ 1035 (0x1<<2) 1036#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR \ 1037 0x9418UL 1038#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ 1039 0x942cUL 1040#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ 1041 0x9430UL 1042#define PGLUE_B_REG_LATCHED_ERRORS_CLR \ 1043 0x943CUL 1044#define PGLUE_B_REG_PGLUE_B_INT_STS \ 1045 0x9298UL 1046#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR \ 1047 0x929cUL 1048#define PGLUE_B_REG_PGLUE_B_PRTY_MASK \ 1049 0x92b4UL 1050#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR \ 1051 0x92acUL 1052#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR \ 1053 0x9458UL 1054#define PGLUE_B_REG_TAGS_63_32 \ 1055 0x9244UL 1056#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR \ 1057 0x9470UL 1058#define PRS_REG_A_PRSU_20 \ 1059 0x40134UL 1060#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT \ 1061 0x4011cUL 1062#define PRS_REG_E1HOV_MODE \ 1063 0x401c8UL 1064#define PRS_REG_HDRS_AFTER_BASIC \ 1065 0x40238UL 1066#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 \ 1067 0x40270UL 1068#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 \ 1069 0x40290UL 1070#define PRS_REG_HDRS_AFTER_TAG_0 \ 1071 0x40248UL 1072#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 \ 1073 0x40280UL 1074#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 \ 1075 0x402a0UL 1076#define PRS_REG_MUST_HAVE_HDRS \ 1077 0x40254UL 1078#define PRS_REG_MUST_HAVE_HDRS_PORT_0 \ 1079 0x4028cUL 1080#define PRS_REG_MUST_HAVE_HDRS_PORT_1 \ 1081 0x402acUL 1082#define PRS_REG_NIC_MODE \ 1083 0x40138UL 1084#define PRS_REG_NUM_OF_PACKETS \ 1085 0x40124UL 1086#define PRS_REG_PRS_PRTY_MASK \ 1087 0x401a4UL 1088#define PRS_REG_PRS_PRTY_STS_CLR \ 1089 0x4019cUL 1090#define PRS_REG_TAG_ETHERTYPE_0 \ 1091 0x401d4UL 1092#define PRS_REG_TAG_LEN_0 \ 1093 0x4022cUL 1094#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT \ 1095 (0x1<<19) 1096#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF \ 1097 (0x1<<20) 1098#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN \ 1099 (0x1<<22) 1100#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED \ 1101 (0x1<<23) 1102#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED \ 1103 (0x1<<24) 1104#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR \ 1105 (0x1<<7) 1106#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR \ 1107 (0x1<<7) 1108#define PXP2_REG_PGL_ADDR_88_F0 \ 1109 0x120534UL 1110#define PXP2_REG_PGL_ADDR_88_F1 \ 1111 0x120544UL 1112#define PXP2_REG_PGL_ADDR_8C_F0 \ 1113 0x120538UL 1114#define PXP2_REG_PGL_ADDR_8C_F1 \ 1115 0x120548UL 1116#define PXP2_REG_PGL_ADDR_90_F0 \ 1117 0x12053cUL 1118#define PXP2_REG_PGL_ADDR_90_F1 \ 1119 0x12054cUL 1120#define PXP2_REG_PGL_ADDR_94_F0 \ 1121 0x120540UL 1122#define PXP2_REG_PGL_ADDR_94_F1 \ 1123 0x120550UL 1124#define PXP2_REG_PGL_EXP_ROM2 \ 1125 0x120808UL 1126#define PXP2_REG_PGL_PRETEND_FUNC_F0 \ 1127 0x120674UL 1128#define PXP2_REG_PGL_PRETEND_FUNC_F1 \ 1129 0x120678UL 1130#define PXP2_REG_PGL_TAGS_LIMIT \ 1131 0x1205a8UL 1132#define PXP2_REG_PSWRQ_BW_ADD1 \ 1133 0x1201c0UL 1134#define PXP2_REG_PSWRQ_BW_ADD10 \ 1135 0x1201e4UL 1136#define PXP2_REG_PSWRQ_BW_ADD11 \ 1137 0x1201e8UL 1138#define PXP2_REG_PSWRQ_BW_ADD2 \ 1139 0x1201c4UL 1140#define PXP2_REG_PSWRQ_BW_ADD28 \ 1141 0x120228UL 1142#define PXP2_REG_PSWRQ_BW_ADD3 \ 1143 0x1201c8UL 1144#define PXP2_REG_PSWRQ_BW_ADD6 \ 1145 0x1201d4UL 1146#define PXP2_REG_PSWRQ_BW_ADD7 \ 1147 0x1201d8UL 1148#define PXP2_REG_PSWRQ_BW_ADD8 \ 1149 0x1201dcUL 1150#define PXP2_REG_PSWRQ_BW_ADD9 \ 1151 0x1201e0UL 1152#define PXP2_REG_PSWRQ_BW_L1 \ 1153 0x1202b0UL 1154#define PXP2_REG_PSWRQ_BW_L10 \ 1155 0x1202d4UL 1156#define PXP2_REG_PSWRQ_BW_L11 \ 1157 0x1202d8UL 1158#define PXP2_REG_PSWRQ_BW_L2 \ 1159 0x1202b4UL 1160#define PXP2_REG_PSWRQ_BW_L28 \ 1161 0x120318UL 1162#define PXP2_REG_PSWRQ_BW_L3 \ 1163 0x1202b8UL 1164#define PXP2_REG_PSWRQ_BW_L6 \ 1165 0x1202c4UL 1166#define PXP2_REG_PSWRQ_BW_L7 \ 1167 0x1202c8UL 1168#define PXP2_REG_PSWRQ_BW_L8 \ 1169 0x1202ccUL 1170#define PXP2_REG_PSWRQ_BW_L9 \ 1171 0x1202d0UL 1172#define PXP2_REG_PSWRQ_BW_RD \ 1173 0x120324UL 1174#define PXP2_REG_PSWRQ_BW_UB1 \ 1175 0x120238UL 1176#define PXP2_REG_PSWRQ_BW_UB10 \ 1177 0x12025cUL 1178#define PXP2_REG_PSWRQ_BW_UB11 \ 1179 0x120260UL 1180#define PXP2_REG_PSWRQ_BW_UB2 \ 1181 0x12023cUL 1182#define PXP2_REG_PSWRQ_BW_UB28 \ 1183 0x1202a0UL 1184#define PXP2_REG_PSWRQ_BW_UB3 \ 1185 0x120240UL 1186#define PXP2_REG_PSWRQ_BW_UB6 \ 1187 0x12024cUL 1188#define PXP2_REG_PSWRQ_BW_UB7 \ 1189 0x120250UL 1190#define PXP2_REG_PSWRQ_BW_UB8 \ 1191 0x120254UL 1192#define PXP2_REG_PSWRQ_BW_UB9 \ 1193 0x120258UL 1194#define PXP2_REG_PSWRQ_BW_WR \ 1195 0x120328UL 1196#define PXP2_REG_PSWRQ_CDU0_L2P \ 1197 0x120000UL 1198#define PXP2_REG_PSWRQ_QM0_L2P \ 1199 0x120038UL 1200#define PXP2_REG_PSWRQ_SRC0_L2P \ 1201 0x120054UL 1202#define PXP2_REG_PSWRQ_TM0_L2P \ 1203 0x12001cUL 1204#define PXP2_REG_PXP2_INT_MASK_0 \ 1205 0x120578UL 1206#define PXP2_REG_PXP2_INT_MASK_1 \ 1207 0x120614UL 1208#define PXP2_REG_PXP2_INT_STS_0 \ 1209 0x12056cUL 1210#define PXP2_REG_PXP2_INT_STS_1 \ 1211 0x120608UL 1212#define PXP2_REG_PXP2_INT_STS_CLR_0 \ 1213 0x120570UL 1214#define PXP2_REG_PXP2_PRTY_MASK_0 \ 1215 0x120588UL 1216#define PXP2_REG_PXP2_PRTY_MASK_1 \ 1217 0x120598UL 1218#define PXP2_REG_PXP2_PRTY_STS_CLR_0 \ 1219 0x120580UL 1220#define PXP2_REG_PXP2_PRTY_STS_CLR_1 \ 1221 0x120590UL 1222#define PXP2_REG_RD_BLK_CNT \ 1223 0x120418UL 1224#define PXP2_REG_RD_CDURD_SWAP_MODE \ 1225 0x120404UL 1226#define PXP2_REG_RD_DISABLE_INPUTS \ 1227 0x120374UL 1228#define PXP2_REG_RD_INIT_DONE \ 1229 0x120370UL 1230#define PXP2_REG_RD_PBF_SWAP_MODE \ 1231 0x1203f4UL 1232#define PXP2_REG_RD_PORT_IS_IDLE_0 \ 1233 0x12041cUL 1234#define PXP2_REG_RD_PORT_IS_IDLE_1 \ 1235 0x120420UL 1236#define PXP2_REG_RD_QM_SWAP_MODE \ 1237 0x1203f8UL 1238#define PXP2_REG_RD_SRC_SWAP_MODE \ 1239 0x120400UL 1240#define PXP2_REG_RD_SR_CNT \ 1241 0x120414UL 1242#define PXP2_REG_RD_START_INIT \ 1243 0x12036cUL 1244#define PXP2_REG_RD_TM_SWAP_MODE \ 1245 0x1203fcUL 1246#define PXP2_REG_RQ_BW_RD_ADD0 \ 1247 0x1201bcUL 1248#define PXP2_REG_RQ_BW_RD_ADD12 \ 1249 0x1201ecUL 1250#define PXP2_REG_RQ_BW_RD_ADD13 \ 1251 0x1201f0UL 1252#define PXP2_REG_RQ_BW_RD_ADD14 \ 1253 0x1201f4UL 1254#define PXP2_REG_RQ_BW_RD_ADD15 \ 1255 0x1201f8UL 1256#define PXP2_REG_RQ_BW_RD_ADD16 \ 1257 0x1201fcUL 1258#define PXP2_REG_RQ_BW_RD_ADD17 \ 1259 0x120200UL 1260#define PXP2_REG_RQ_BW_RD_ADD18 \ 1261 0x120204UL 1262#define PXP2_REG_RQ_BW_RD_ADD19 \ 1263 0x120208UL 1264#define PXP2_REG_RQ_BW_RD_ADD20 \ 1265 0x12020cUL 1266#define PXP2_REG_RQ_BW_RD_ADD22 \ 1267 0x120210UL 1268#define PXP2_REG_RQ_BW_RD_ADD23 \ 1269 0x120214UL 1270#define PXP2_REG_RQ_BW_RD_ADD24 \ 1271 0x120218UL 1272#define PXP2_REG_RQ_BW_RD_ADD25 \ 1273 0x12021cUL 1274#define PXP2_REG_RQ_BW_RD_ADD26 \ 1275 0x120220UL 1276#define PXP2_REG_RQ_BW_RD_ADD27 \ 1277 0x120224UL 1278#define PXP2_REG_RQ_BW_RD_ADD4 \ 1279 0x1201ccUL 1280#define PXP2_REG_RQ_BW_RD_ADD5 \ 1281 0x1201d0UL 1282#define PXP2_REG_RQ_BW_RD_L0 \ 1283 0x1202acUL 1284#define PXP2_REG_RQ_BW_RD_L12 \ 1285 0x1202dcUL 1286#define PXP2_REG_RQ_BW_RD_L13 \ 1287 0x1202e0UL 1288#define PXP2_REG_RQ_BW_RD_L14 \ 1289 0x1202e4UL 1290#define PXP2_REG_RQ_BW_RD_L15 \ 1291 0x1202e8UL 1292#define PXP2_REG_RQ_BW_RD_L16 \ 1293 0x1202ecUL 1294#define PXP2_REG_RQ_BW_RD_L17 \ 1295 0x1202f0UL 1296#define PXP2_REG_RQ_BW_RD_L18 \ 1297 0x1202f4UL 1298#define PXP2_REG_RQ_BW_RD_L19 \ 1299 0x1202f8UL 1300#define PXP2_REG_RQ_BW_RD_L20 \ 1301 0x1202fcUL 1302#define PXP2_REG_RQ_BW_RD_L22 \ 1303 0x120300UL 1304#define PXP2_REG_RQ_BW_RD_L23 \ 1305 0x120304UL 1306#define PXP2_REG_RQ_BW_RD_L24 \ 1307 0x120308UL 1308#define PXP2_REG_RQ_BW_RD_L25 \ 1309 0x12030cUL 1310#define PXP2_REG_RQ_BW_RD_L26 \ 1311 0x120310UL 1312#define PXP2_REG_RQ_BW_RD_L27 \ 1313 0x120314UL 1314#define PXP2_REG_RQ_BW_RD_L4 \ 1315 0x1202bcUL 1316#define PXP2_REG_RQ_BW_RD_L5 \ 1317 0x1202c0UL 1318#define PXP2_REG_RQ_BW_RD_UBOUND0 \ 1319 0x120234UL 1320#define PXP2_REG_RQ_BW_RD_UBOUND12 \ 1321 0x120264UL 1322#define PXP2_REG_RQ_BW_RD_UBOUND13 \ 1323 0x120268UL 1324#define PXP2_REG_RQ_BW_RD_UBOUND14 \ 1325 0x12026cUL 1326#define PXP2_REG_RQ_BW_RD_UBOUND15 \ 1327 0x120270UL 1328#define PXP2_REG_RQ_BW_RD_UBOUND16 \ 1329 0x120274UL 1330#define PXP2_REG_RQ_BW_RD_UBOUND17 \ 1331 0x120278UL 1332#define PXP2_REG_RQ_BW_RD_UBOUND18 \ 1333 0x12027cUL 1334#define PXP2_REG_RQ_BW_RD_UBOUND19 \ 1335 0x120280UL 1336#define PXP2_REG_RQ_BW_RD_UBOUND20 \ 1337 0x120284UL 1338#define PXP2_REG_RQ_BW_RD_UBOUND22 \ 1339 0x120288UL 1340#define PXP2_REG_RQ_BW_RD_UBOUND23 \ 1341 0x12028cUL 1342#define PXP2_REG_RQ_BW_RD_UBOUND24 \ 1343 0x120290UL 1344#define PXP2_REG_RQ_BW_RD_UBOUND25 \ 1345 0x120294UL 1346#define PXP2_REG_RQ_BW_RD_UBOUND26 \ 1347 0x120298UL 1348#define PXP2_REG_RQ_BW_RD_UBOUND27 \ 1349 0x12029cUL 1350#define PXP2_REG_RQ_BW_RD_UBOUND4 \ 1351 0x120244UL 1352#define PXP2_REG_RQ_BW_RD_UBOUND5 \ 1353 0x120248UL 1354#define PXP2_REG_RQ_BW_WR_ADD29 \ 1355 0x12022cUL 1356#define PXP2_REG_RQ_BW_WR_ADD30 \ 1357 0x120230UL 1358#define PXP2_REG_RQ_BW_WR_L29 \ 1359 0x12031cUL 1360#define PXP2_REG_RQ_BW_WR_L30 \ 1361 0x120320UL 1362#define PXP2_REG_RQ_BW_WR_UBOUND29 \ 1363 0x1202a4UL 1364#define PXP2_REG_RQ_BW_WR_UBOUND30 \ 1365 0x1202a8UL 1366#define PXP2_REG_RQ_CDU_ENDIAN_M \ 1367 0x1201a0UL 1368#define PXP2_REG_RQ_CDU_FIRST_ILT \ 1369 0x12061cUL 1370#define PXP2_REG_RQ_CDU_LAST_ILT \ 1371 0x120620UL 1372#define PXP2_REG_RQ_CDU_P_SIZE \ 1373 0x120018UL 1374#define PXP2_REG_RQ_CFG_DONE \ 1375 0x1201b4UL 1376#define PXP2_REG_RQ_DBG_ENDIAN_M \ 1377 0x1201a4UL 1378#define PXP2_REG_RQ_DISABLE_INPUTS \ 1379 0x120330UL 1380#define PXP2_REG_RQ_DRAM_ALIGN \ 1381 0x1205b0UL 1382#define PXP2_REG_RQ_DRAM_ALIGN_RD \ 1383 0x12092cUL 1384#define PXP2_REG_RQ_DRAM_ALIGN_SEL \ 1385 0x120930UL 1386#define PXP2_REG_RQ_HC_ENDIAN_M \ 1387 0x1201a8UL 1388#define PXP2_REG_RQ_ONCHIP_AT \ 1389 0x122000UL 1390#define PXP2_REG_RQ_ONCHIP_AT_B0 \ 1391 0x128000UL 1392#define PXP2_REG_RQ_PDR_LIMIT \ 1393 0x12033cUL 1394#define PXP2_REG_RQ_QM_ENDIAN_M \ 1395 0x120194UL 1396#define PXP2_REG_RQ_QM_FIRST_ILT \ 1397 0x120634UL 1398#define PXP2_REG_RQ_QM_LAST_ILT \ 1399 0x120638UL 1400#define PXP2_REG_RQ_QM_P_SIZE \ 1401 0x120050UL 1402#define PXP2_REG_RQ_RBC_DONE \ 1403 0x1201b0UL 1404#define PXP2_REG_RQ_RD_MBS0 \ 1405 0x120160UL 1406#define PXP2_REG_RQ_RD_MBS1 \ 1407 0x120168UL 1408#define PXP2_REG_RQ_SRC_ENDIAN_M \ 1409 0x12019cUL 1410#define PXP2_REG_RQ_SRC_FIRST_ILT \ 1411 0x12063cUL 1412#define PXP2_REG_RQ_SRC_LAST_ILT \ 1413 0x120640UL 1414#define PXP2_REG_RQ_SRC_P_SIZE \ 1415 0x12006cUL 1416#define PXP2_REG_RQ_TM_ENDIAN_M \ 1417 0x120198UL 1418#define PXP2_REG_RQ_TM_FIRST_ILT \ 1419 0x120644UL 1420#define PXP2_REG_RQ_TM_LAST_ILT \ 1421 0x120648UL 1422#define PXP2_REG_RQ_TM_P_SIZE \ 1423 0x120034UL 1424#define PXP2_REG_RQ_WR_MBS0 \ 1425 0x12015cUL 1426#define PXP2_REG_RQ_WR_MBS1 \ 1427 0x120164UL 1428#define PXP2_REG_WR_CDU_MPS \ 1429 0x1205f0UL 1430#define PXP2_REG_WR_CSDM_MPS \ 1431 0x1205d0UL 1432#define PXP2_REG_WR_DBG_MPS \ 1433 0x1205e8UL 1434#define PXP2_REG_WR_DMAE_MPS \ 1435 0x1205ecUL 1436#define PXP2_REG_WR_HC_MPS \ 1437 0x1205c8UL 1438#define PXP2_REG_WR_QM_MPS \ 1439 0x1205dcUL 1440#define PXP2_REG_WR_SRC_MPS \ 1441 0x1205e4UL 1442#define PXP2_REG_WR_TM_MPS \ 1443 0x1205e0UL 1444#define PXP2_REG_WR_TSDM_MPS \ 1445 0x1205d4UL 1446#define PXP2_REG_WR_USDMDP_TH \ 1447 0x120348UL 1448#define PXP2_REG_WR_USDM_MPS \ 1449 0x1205ccUL 1450#define PXP2_REG_WR_XSDM_MPS \ 1451 0x1205d8UL 1452#define PXP_REG_HST_DISCARD_DOORBELLS \ 1453 0x1030a4UL 1454#define PXP_REG_HST_DISCARD_INTERNAL_WRITES \ 1455 0x1030a8UL 1456#define PXP_REG_PXP_INT_MASK_0 \ 1457 0x103074UL 1458#define PXP_REG_PXP_INT_MASK_1 \ 1459 0x103084UL 1460#define PXP_REG_PXP_INT_STS_CLR_0 \ 1461 0x10306cUL 1462#define PXP_REG_PXP_INT_STS_CLR_1 \ 1463 0x10307cUL 1464#define PXP_REG_PXP_PRTY_MASK \ 1465 0x103094UL 1466#define PXP_REG_PXP_PRTY_STS_CLR \ 1467 0x10308cUL 1468#define QM_REG_BASEADDR \ 1469 0x168900UL 1470#define QM_REG_BASEADDR_EXT_A \ 1471 0x16e100UL 1472#define QM_REG_BYTECRDCMDQ_0 \ 1473 0x16e6e8UL 1474#define QM_REG_CONNNUM_0 \ 1475 0x168020UL 1476#define QM_REG_PF_EN \ 1477 0x16e70cUL 1478#define QM_REG_PF_USG_CNT_0 \ 1479 0x16e040UL 1480#define QM_REG_PTRTBL \ 1481 0x168a00UL 1482#define QM_REG_PTRTBL_EXT_A \ 1483 0x16e200UL 1484#define QM_REG_QM_INT_MASK \ 1485 0x168444UL 1486#define QM_REG_QM_PRTY_MASK \ 1487 0x168454UL 1488#define QM_REG_QM_PRTY_STS_CLR \ 1489 0x16844cUL 1490#define QM_REG_QVOQIDX_0 \ 1491 0x1680f4UL 1492#define QM_REG_SOFT_RESET \ 1493 0x168428UL 1494#define QM_REG_VOQQMASK_0_LSB \ 1495 0x168240UL 1496#define SEM_FAST_REG_PARITY_RST \ 1497 0x18840UL 1498#define SRC_REG_COUNTFREE0 \ 1499 0x40500UL 1500#define SRC_REG_FIRSTFREE0 \ 1501 0x40510UL 1502#define SRC_REG_KEYSEARCH_0 \ 1503 0x40458UL 1504#define SRC_REG_KEYSEARCH_1 \ 1505 0x4045cUL 1506#define SRC_REG_KEYSEARCH_2 \ 1507 0x40460UL 1508#define SRC_REG_KEYSEARCH_3 \ 1509 0x40464UL 1510#define SRC_REG_KEYSEARCH_4 \ 1511 0x40468UL 1512#define SRC_REG_KEYSEARCH_5 \ 1513 0x4046cUL 1514#define SRC_REG_KEYSEARCH_6 \ 1515 0x40470UL 1516#define SRC_REG_KEYSEARCH_7 \ 1517 0x40474UL 1518#define SRC_REG_KEYSEARCH_8 \ 1519 0x40478UL 1520#define SRC_REG_KEYSEARCH_9 \ 1521 0x4047cUL 1522#define SRC_REG_LASTFREE0 \ 1523 0x40530UL 1524#define SRC_REG_NUMBER_HASH_BITS0 \ 1525 0x40400UL 1526#define SRC_REG_SOFT_RST \ 1527 0x4049cUL 1528#define SRC_REG_SRC_PRTY_MASK \ 1529 0x404c8UL 1530#define SRC_REG_SRC_PRTY_STS_CLR \ 1531 0x404c0UL 1532#define TCM_REG_PRS_IFEN \ 1533 0x50020UL 1534#define TCM_REG_TCM_INT_MASK \ 1535 0x501dcUL 1536#define TCM_REG_TCM_PRTY_MASK \ 1537 0x501ecUL 1538#define TCM_REG_TCM_PRTY_STS_CLR \ 1539 0x501e4UL 1540#define TM_REG_EN_LINEAR0_TIMER \ 1541 0x164014UL 1542#define TM_REG_LIN0_MAX_ACTIVE_CID \ 1543 0x164048UL 1544#define TM_REG_LIN0_NUM_SCANS \ 1545 0x1640a0UL 1546#define TM_REG_LIN0_SCAN_ON \ 1547 0x1640d0UL 1548#define TM_REG_LIN0_SCAN_TIME \ 1549 0x16403cUL 1550#define TM_REG_LIN0_VNIC_UC \ 1551 0x164128UL 1552#define TM_REG_TM_INT_MASK \ 1553 0x1640fcUL 1554#define TM_REG_TM_PRTY_MASK \ 1555 0x16410cUL 1556#define TM_REG_TM_PRTY_STS_CLR \ 1557 0x164104UL 1558#define TSDM_REG_ENABLE_IN1 \ 1559 0x42238UL 1560#define TSDM_REG_TSDM_INT_MASK_0 \ 1561 0x4229cUL 1562#define TSDM_REG_TSDM_INT_MASK_1 \ 1563 0x422acUL 1564#define TSDM_REG_TSDM_PRTY_MASK \ 1565 0x422bcUL 1566#define TSDM_REG_TSDM_PRTY_STS_CLR \ 1567 0x422b4UL 1568#define TSEM_REG_FAST_MEMORY \ 1569 0x1a0000UL 1570#define TSEM_REG_INT_TABLE \ 1571 0x180400UL 1572#define TSEM_REG_PASSIVE_BUFFER \ 1573 0x181000UL 1574#define TSEM_REG_PRAM \ 1575 0x1c0000UL 1576#define TSEM_REG_TSEM_INT_MASK_0 \ 1577 0x180100UL 1578#define TSEM_REG_TSEM_INT_MASK_1 \ 1579 0x180110UL 1580#define TSEM_REG_TSEM_PRTY_MASK_0 \ 1581 0x180120UL 1582#define TSEM_REG_TSEM_PRTY_MASK_1 \ 1583 0x180130UL 1584#define TSEM_REG_TSEM_PRTY_STS_CLR_0 \ 1585 0x180118UL 1586#define TSEM_REG_TSEM_PRTY_STS_CLR_1 \ 1587 0x180128UL 1588#define TSEM_REG_VFPF_ERR_NUM \ 1589 0x180380UL 1590#define UCM_REG_UCM_INT_MASK \ 1591 0xe01d4UL 1592#define UCM_REG_UCM_PRTY_MASK \ 1593 0xe01e4UL 1594#define UCM_REG_UCM_PRTY_STS_CLR \ 1595 0xe01dcUL 1596#define UMAC_COMMAND_CONFIG_REG_HD_ENA \ 1597 (0x1<<10) 1598#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE \ 1599 (0x1<<28) 1600#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA \ 1601 (0x1<<15) 1602#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK \ 1603 (0x1<<24) 1604#define UMAC_COMMAND_CONFIG_REG_PAD_EN \ 1605 (0x1<<5) 1606#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE \ 1607 (0x1<<8) 1608#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN \ 1609 (0x1<<4) 1610#define UMAC_COMMAND_CONFIG_REG_RX_ENA \ 1611 (0x1<<1) 1612#define UMAC_COMMAND_CONFIG_REG_SW_RESET \ 1613 (0x1<<13) 1614#define UMAC_COMMAND_CONFIG_REG_TX_ENA \ 1615 (0x1<<0) 1616#define UMAC_REG_COMMAND_CONFIG \ 1617 0x8UL 1618#define UMAC_REG_EEE_WAKE_TIMER \ 1619 0x6cUL 1620#define UMAC_REG_MAC_ADDR0 \ 1621 0xcUL 1622#define UMAC_REG_MAC_ADDR1 \ 1623 0x10UL 1624#define UMAC_REG_MAXFR \ 1625 0x14UL 1626#define UMAC_REG_UMAC_EEE_CTRL \ 1627 0x64UL 1628#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN \ 1629 (0x1<<3) 1630#define USDM_REG_USDM_INT_MASK_0 \ 1631 0xc42a0UL 1632#define USDM_REG_USDM_INT_MASK_1 \ 1633 0xc42b0UL 1634#define USDM_REG_USDM_PRTY_MASK \ 1635 0xc42c0UL 1636#define USDM_REG_USDM_PRTY_STS_CLR \ 1637 0xc42b8UL 1638#define USEM_REG_FAST_MEMORY \ 1639 0x320000UL 1640#define USEM_REG_INT_TABLE \ 1641 0x300400UL 1642#define USEM_REG_PASSIVE_BUFFER \ 1643 0x302000UL 1644#define USEM_REG_PRAM \ 1645 0x340000UL 1646#define USEM_REG_USEM_INT_MASK_0 \ 1647 0x300110UL 1648#define USEM_REG_USEM_INT_MASK_1 \ 1649 0x300120UL 1650#define USEM_REG_USEM_PRTY_MASK_0 \ 1651 0x300130UL 1652#define USEM_REG_USEM_PRTY_MASK_1 \ 1653 0x300140UL 1654#define USEM_REG_USEM_PRTY_STS_CLR_0 \ 1655 0x300128UL 1656#define USEM_REG_USEM_PRTY_STS_CLR_1 \ 1657 0x300138UL 1658#define USEM_REG_VFPF_ERR_NUM \ 1659 0x300380UL 1660#define VFC_MEMORIES_RST_REG_CAM_RST \ 1661 (0x1<<0) 1662#define VFC_MEMORIES_RST_REG_RAM_RST \ 1663 (0x1<<1) 1664#define VFC_REG_MEMORIES_RST \ 1665 0x1943cUL 1666#define XCM_REG_XCM_INT_MASK \ 1667 0x202b4UL 1668#define XCM_REG_XCM_PRTY_MASK \ 1669 0x202c4UL 1670#define XCM_REG_XCM_PRTY_STS_CLR \ 1671 0x202bcUL 1672#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS \ 1673 (0x1<<0) 1674#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS \ 1675 (0x1<<1) 1676#define XMAC_CTRL_REG_LINE_LOCAL_LPBK \ 1677 (0x1<<2) 1678#define XMAC_CTRL_REG_RX_EN \ 1679 (0x1<<1) 1680#define XMAC_CTRL_REG_SOFT_RESET \ 1681 (0x1<<6) 1682#define XMAC_CTRL_REG_TX_EN \ 1683 (0x1<<0) 1684#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB \ 1685 (0x1<<7) 1686#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN \ 1687 (0x1<<18) 1688#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN \ 1689 (0x1<<17) 1690#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON \ 1691 (0x1<<1) 1692#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN \ 1693 (0x1<<0) 1694#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN \ 1695 (0x1<<3) 1696#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN \ 1697 (0x1<<4) 1698#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN \ 1699 (0x1<<5) 1700#define XMAC_REG_CLEAR_RX_LSS_STATUS \ 1701 0x60UL 1702#define XMAC_REG_CTRL \ 1703 0UL 1704#define XMAC_REG_CTRL_SA_HI \ 1705 0x2cUL 1706#define XMAC_REG_CTRL_SA_LO \ 1707 0x28UL 1708#define XMAC_REG_EEE_CTRL \ 1709 0xd8UL 1710#define XMAC_REG_EEE_TIMERS_HI \ 1711 0xe4UL 1712#define XMAC_REG_PAUSE_CTRL \ 1713 0x68UL 1714#define XMAC_REG_PFC_CTRL \ 1715 0x70UL 1716#define XMAC_REG_PFC_CTRL_HI \ 1717 0x74UL 1718#define XMAC_REG_RX_LSS_CTRL \ 1719 0x50UL 1720#define XMAC_REG_RX_LSS_STATUS \ 1721 0x58UL 1722#define XMAC_REG_RX_MAX_SIZE \ 1723 0x40UL 1724#define XMAC_REG_TX_CTRL \ 1725 0x20UL 1726#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE \ 1727 (0x1<<0) 1728#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE \ 1729 (0x1<<1) 1730#define XSDM_REG_OPERATION_GEN \ 1731 0x1664c4UL 1732#define XSDM_REG_XSDM_INT_MASK_0 \ 1733 0x16629cUL 1734#define XSDM_REG_XSDM_INT_MASK_1 \ 1735 0x1662acUL 1736#define XSDM_REG_XSDM_PRTY_MASK \ 1737 0x1662bcUL 1738#define XSDM_REG_XSDM_PRTY_STS_CLR \ 1739 0x1662b4UL 1740#define XSEM_REG_FAST_MEMORY \ 1741 0x2a0000UL 1742#define XSEM_REG_INT_TABLE \ 1743 0x280400UL 1744#define XSEM_REG_PASSIVE_BUFFER \ 1745 0x282000UL 1746#define XSEM_REG_PRAM \ 1747 0x2c0000UL 1748#define XSEM_REG_VFPF_ERR_NUM \ 1749 0x280380UL 1750#define XSEM_REG_XSEM_INT_MASK_0 \ 1751 0x280110UL 1752#define XSEM_REG_XSEM_INT_MASK_1 \ 1753 0x280120UL 1754#define XSEM_REG_XSEM_PRTY_MASK_0 \ 1755 0x280130UL 1756#define XSEM_REG_XSEM_PRTY_MASK_1 \ 1757 0x280140UL 1758#define XSEM_REG_XSEM_PRTY_STS_CLR_0 \ 1759 0x280128UL 1760#define XSEM_REG_XSEM_PRTY_STS_CLR_1 \ 1761 0x280138UL 1762#define MCPR_ACCESS_LOCK_LOCK (1L<<31) 1763#define MCPR_IMC_COMMAND_ENABLE (1L<<31) 1764#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16 1765#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28 1766#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8 1767#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0) 1768#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 1769#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 1770#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0) 1771#define MCPR_NVM_COMMAND_DOIT (1L<<4) 1772#define MCPR_NVM_COMMAND_DONE (1L<<3) 1773#define MCPR_NVM_COMMAND_FIRST (1L<<7) 1774#define MCPR_NVM_COMMAND_LAST (1L<<8) 1775#define MCPR_NVM_COMMAND_WR (1L<<5) 1776#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9) 1777#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 1778#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 1779 1780 1781#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3) 1782#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 1783#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3) 1784#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3) 1785#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3) 1786#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3) 1787#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3) 1788#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3) 1789#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3) 1790#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3) 1791#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3) 1792#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3) 1793#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) 1794#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) 1795#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) 1796#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3) 1797#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 1798#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3) 1799#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3) 1800#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3) 1801#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3) 1802#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3) 1803#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3) 1804#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3) 1805#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3) 1806#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3) 1807#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3) 1808#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3) 1809#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3) 1810#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3) 1811#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3) 1812 1813 1814#define EMAC_LED_1000MB_OVERRIDE (1L<<1) 1815#define EMAC_LED_100MB_OVERRIDE (1L<<2) 1816#define EMAC_LED_10MB_OVERRIDE (1L<<3) 1817#define EMAC_LED_OVERRIDE (1L<<0) 1818#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) 1819#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26) 1820#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) 1821#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26) 1822#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) 1823#define EMAC_MDIO_COMM_DATA (0xffffL<<0) 1824#define EMAC_MDIO_COMM_START_BUSY (1L<<29) 1825#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 1826#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) 1827#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16) 1828#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 1829#define EMAC_MDIO_STATUS_10MB (1L<<1) 1830#define EMAC_MODE_25G_MODE (1L<<5) 1831#define EMAC_MODE_HALF_DUPLEX (1L<<1) 1832#define EMAC_MODE_PORT_GMII (2L<<2) 1833#define EMAC_MODE_PORT_MII (1L<<2) 1834#define EMAC_MODE_PORT_MII_10M (3L<<2) 1835#define EMAC_MODE_RESET (1L<<0) 1836#define EMAC_REG_EMAC_LED 0xc 1837#define EMAC_REG_EMAC_MAC_MATCH 0x10 1838#define EMAC_REG_EMAC_MDIO_COMM 0xac 1839#define EMAC_REG_EMAC_MDIO_MODE 0xb4 1840#define EMAC_REG_EMAC_MDIO_STATUS 0xb0 1841#define EMAC_REG_EMAC_MODE 0x0 1842#define EMAC_REG_EMAC_RX_MODE 0xc8 1843#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c 1844#define EMAC_REG_EMAC_RX_STAT_AC 0x180 1845#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4 1846#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23 1847#define EMAC_REG_EMAC_TX_MODE 0xbc 1848#define EMAC_REG_EMAC_TX_STAT_AC 0x280 1849#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22 1850#define EMAC_REG_RX_PFC_MODE 0x320 1851#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2) 1852#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1) 1853#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0) 1854#define EMAC_REG_RX_PFC_PARAM 0x324 1855#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0 1856#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16 1857#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328 1858#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0) 1859#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330 1860#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0) 1861#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c 1862#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0) 1863#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334 1864#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0) 1865#define EMAC_RX_MODE_FLOW_EN (1L<<2) 1866#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 1867#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 1868#define EMAC_RX_MODE_PROMISCUOUS (1L<<8) 1869#define EMAC_RX_MODE_RESET (1L<<0) 1870#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 1871#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 1872#define EMAC_TX_MODE_FLOW_EN (1L<<4) 1873#define EMAC_TX_MODE_RESET (1L<<0) 1874 1875 1876#define MISC_REGISTERS_GPIO_0 0 1877#define MISC_REGISTERS_GPIO_1 1 1878#define MISC_REGISTERS_GPIO_2 2 1879#define MISC_REGISTERS_GPIO_3 3 1880#define MISC_REGISTERS_GPIO_CLR_POS 16 1881#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) 1882#define MISC_REGISTERS_GPIO_FLOAT_POS 24 1883#define MISC_REGISTERS_GPIO_HIGH 1 1884#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 1885#define MISC_REGISTERS_GPIO_INT_CLR_POS 24 1886#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0 1887#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1 1888#define MISC_REGISTERS_GPIO_INT_SET_POS 16 1889#define MISC_REGISTERS_GPIO_LOW 0 1890#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 1891#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 1892#define MISC_REGISTERS_GPIO_PORT_SHIFT 4 1893#define MISC_REGISTERS_GPIO_SET_POS 8 1894#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 1895#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0) 1896#define MISC_REGISTERS_RESET_REG_1_RST_DORQ \ 1897 (0x1<<19) 1898#define MISC_REGISTERS_RESET_REG_1_RST_HC \ 1899 (0x1<<29) 1900#define MISC_REGISTERS_RESET_REG_1_RST_PXP \ 1901 (0x1<<26) 1902#define MISC_REGISTERS_RESET_REG_1_RST_PXPV \ 1903 (0x1<<27) 1904#define MISC_REGISTERS_RESET_REG_1_RST_QM \ 1905 (0x1<<17) 1906#define MISC_REGISTERS_RESET_REG_1_SET 0x584 1907#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 1908#define MISC_REGISTERS_RESET_REG_2_MSTAT0 \ 1909 (0x1<<24) 1910#define MISC_REGISTERS_RESET_REG_2_MSTAT1 \ 1911 (0x1<<25) 1912#define MISC_REGISTERS_RESET_REG_2_PGLC \ 1913 (0x1<<19) 1914#define MISC_REGISTERS_RESET_REG_2_RST_ATC \ 1915 (0x1<<17) 1916#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) 1917#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1) 1918#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2) 1919#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE \ 1920 (0x1<<14) 1921#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3) 1922#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE \ 1923 (0x1<<15) 1924#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4) 1925#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6) 1926#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8) 1927#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7) 1928#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5) 1929#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE \ 1930 (0x1<<11) 1931#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO \ 1932 (0x1<<13) 1933#define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR \ 1934 (0x1<<16) 1935#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9) 1936#define MISC_REGISTERS_RESET_REG_2_SET 0x594 1937#define MISC_REGISTERS_RESET_REG_2_UMAC0 \ 1938 (0x1<<20) 1939#define MISC_REGISTERS_RESET_REG_2_UMAC1 \ 1940 (0x1<<21) 1941#define MISC_REGISTERS_RESET_REG_2_XMAC \ 1942 (0x1<<22) 1943#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT \ 1944 (0x1<<23) 1945#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 1946#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) 1947#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) 1948#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3) 1949#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0) 1950#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5) 1951#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6) 1952#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7) 1953#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) 1954#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) 1955#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 1956#define MISC_SPIO_CLR_POS 16 1957#define MISC_SPIO_FLOAT (0xffL<<24) 1958#define MISC_SPIO_FLOAT_POS 24 1959#define MISC_SPIO_INPUT_HI_Z 2 1960#define MISC_SPIO_INT_OLD_SET_POS 16 1961#define MISC_SPIO_OUTPUT_HIGH 1 1962#define MISC_SPIO_OUTPUT_LOW 0 1963#define MISC_SPIO_SET_POS 8 1964#define MISC_SPIO_SPIO4 0x10 1965#define MISC_SPIO_SPIO5 0x20 1966#define HW_LOCK_MAX_RESOURCE_VALUE 31 1967#define HW_LOCK_RESOURCE_DRV_FLAGS 10 1968#define HW_LOCK_RESOURCE_MDIO 0 1969#define HW_LOCK_RESOURCE_GPIO 1 1970#define HW_LOCK_RESOURCE_NVRAM 12 1971#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 1972#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8 1973#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9 1974#define HW_LOCK_RESOURCE_RECOVERY_REG 11 1975#define HW_LOCK_RESOURCE_RESET 5 1976#define HW_LOCK_RESOURCE_SPIO 2 1977 1978 1979#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4) 1980#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) 1981#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19) 1982#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18) 1983#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31) 1984#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30) 1985#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9) 1986#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8) 1987#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7) 1988#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6) 1989#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29) 1990#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28) 1991#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1) 1992#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0) 1993#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18) 1994#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11) 1995#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10) 1996#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13) 1997#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12) 1998#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2) 1999#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12) 2000#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28) 2001#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1UL<<31) 2002#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29) 2003#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30) 2004#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15) 2005#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14) 2006#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14) 2007#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20) 2008#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1UL<<31) 2009#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30) 2010#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0) 2011#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2) 2012#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3) 2013#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5) 2014#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4) 2015#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3) 2016#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2) 2017#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3) 2018#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2) 2019#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22) 2020#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15) 2021#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27) 2022#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26) 2023#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5) 2024#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4) 2025#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25) 2026#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24) 2027#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29) 2028#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28) 2029#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23) 2030#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22) 2031#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27) 2032#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26) 2033#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21) 2034#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20) 2035#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25) 2036#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24) 2037#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16) 2038#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9) 2039#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8) 2040#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7) 2041#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6) 2042#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11) 2043#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10) 2044#define HW_PRTY_ASSERT_SET_0 \ 2045(AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR |\ 2046 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR |\ 2047 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR |\ 2048 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2049 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2050 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2051 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2052#define HW_PRTY_ASSERT_SET_1 \ 2053(AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2054 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR |\ 2055 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2056 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR |\ 2057 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2058 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR |\ 2059 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2060 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2061 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2062 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR |\ 2063 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR |\ 2064 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2065 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR |\ 2066 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR |\ 2067 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2068 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2069#define HW_PRTY_ASSERT_SET_2 \ 2070(AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR |\ 2071 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR |\ 2072 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2073 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR |\ 2074 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR |\ 2075 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2076 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR |\ 2077 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2078#define HW_PRTY_ASSERT_SET_3 \ 2079(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2080 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2081 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2082 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2083#define HW_PRTY_ASSERT_SET_4 \ 2084(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |\ 2085 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2086#define HW_INTERRUT_ASSERT_SET_0 \ 2087(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT |\ 2088 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT |\ 2089 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT |\ 2090 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT |\ 2091 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2092#define HW_INTERRUT_ASSERT_SET_1 \ 2093(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT |\ 2094 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT |\ 2095 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT |\ 2096 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT |\ 2097 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT |\ 2098 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT |\ 2099 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT |\ 2100 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT |\ 2101 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT |\ 2102 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT |\ 2103 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2104#define HW_INTERRUT_ASSERT_SET_2 \ 2105(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT |\ 2106 AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT |\ 2107 AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT |\ 2108 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT |\ 2109 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT |\ 2110 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2111 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2112 2113 2114#define RESERVED_GENERAL_ATTENTION_BIT_0 0 2115 2116#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0 2117#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 2118 2119#define RESERVED_GENERAL_ATTENTION_BIT_6 6 2120#define RESERVED_GENERAL_ATTENTION_BIT_7 7 2121#define RESERVED_GENERAL_ATTENTION_BIT_8 8 2122#define RESERVED_GENERAL_ATTENTION_BIT_9 9 2123#define RESERVED_GENERAL_ATTENTION_BIT_10 10 2124#define RESERVED_GENERAL_ATTENTION_BIT_11 11 2125#define RESERVED_GENERAL_ATTENTION_BIT_12 12 2126#define RESERVED_GENERAL_ATTENTION_BIT_13 13 2127#define RESERVED_GENERAL_ATTENTION_BIT_14 14 2128#define RESERVED_GENERAL_ATTENTION_BIT_15 15 2129#define RESERVED_GENERAL_ATTENTION_BIT_16 16 2130#define RESERVED_GENERAL_ATTENTION_BIT_17 17 2131#define RESERVED_GENERAL_ATTENTION_BIT_18 18 2132#define RESERVED_GENERAL_ATTENTION_BIT_19 19 2133#define RESERVED_GENERAL_ATTENTION_BIT_20 20 2134#define RESERVED_GENERAL_ATTENTION_BIT_21 21 2135 2136/* storm asserts attention bits */ 2137#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7 2138#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8 2139#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9 2140#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10 2141 2142/* mcp error attention bit */ 2143#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11 2144 2145/*E1H NIG status sync attention mapped to group 4-7*/ 2146#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12 2147#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13 2148#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14 2149#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15 2150#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16 2151#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17 2152#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18 2153#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19 2154 2155 /* Used For Error Recovery: changing this will require more \ 2156 changes in code that assume 2157 * error recovery uses general attn bit20 ! */ 2158#define ERROR_RECOVERY_ATTENTION_BIT \ 2159 RESERVED_GENERAL_ATTENTION_BIT_20 2160#define RESERVED_ATTENTION_BIT \ 2161 RESERVED_GENERAL_ATTENTION_BIT_21 2162 2163#define LATCHED_ATTN_RBCR 23 2164#define LATCHED_ATTN_RBCT 24 2165#define LATCHED_ATTN_RBCN 25 2166#define LATCHED_ATTN_RBCU 26 2167#define LATCHED_ATTN_RBCP 27 2168#define LATCHED_ATTN_TIMEOUT_GRC 28 2169#define LATCHED_ATTN_RSVD_GRC 29 2170#define LATCHED_ATTN_ROM_PARITY_MCP 30 2171#define LATCHED_ATTN_UM_RX_PARITY_MCP 31 2172#define LATCHED_ATTN_UM_TX_PARITY_MCP 32 2173#define LATCHED_ATTN_SCPAD_PARITY_MCP 33 2174 2175#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32) 2176#define GENERAL_ATTEN_OFFSET(atten_name) (1UL << ((94 + atten_name) % 32)) 2177 2178 2179/* 2180 * This file defines GRC base address for every block. 2181 * This file is included by chipsim, asm microcode and cpp microcode. 2182 * These values are used in Design.xml on regBase attribute 2183 * Use the base with the generated offsets of specific registers. 2184 */ 2185 2186#define GRCBASE_PXPCS 0x000000 2187#define GRCBASE_PCICONFIG 0x002000 2188#define GRCBASE_PCIREG 0x002400 2189#define GRCBASE_EMAC0 0x008000 2190#define GRCBASE_EMAC1 0x008400 2191#define GRCBASE_DBU 0x008800 2192#define GRCBASE_PGLUE_B 0x009000 2193#define GRCBASE_MISC 0x00A000 2194#define GRCBASE_DBG 0x00C000 2195#define GRCBASE_NIG 0x010000 2196#define GRCBASE_XCM 0x020000 2197#define GRCBASE_PRS 0x040000 2198#define GRCBASE_SRCH 0x040400 2199#define GRCBASE_TSDM 0x042000 2200#define GRCBASE_TCM 0x050000 2201#define GRCBASE_BRB1 0x060000 2202#define GRCBASE_MCP 0x080000 2203#define GRCBASE_UPB 0x0C1000 2204#define GRCBASE_CSDM 0x0C2000 2205#define GRCBASE_USDM 0x0C4000 2206#define GRCBASE_CCM 0x0D0000 2207#define GRCBASE_UCM 0x0E0000 2208#define GRCBASE_CDU 0x101000 2209#define GRCBASE_DMAE 0x102000 2210#define GRCBASE_PXP 0x103000 2211#define GRCBASE_CFC 0x104000 2212#define GRCBASE_HC 0x108000 2213#define GRCBASE_ATC 0x110000 2214#define GRCBASE_PXP2 0x120000 2215#define GRCBASE_IGU 0x130000 2216#define GRCBASE_PBF 0x140000 2217#define GRCBASE_UMAC0 0x160000 2218#define GRCBASE_UMAC1 0x160400 2219#define GRCBASE_XPB 0x161000 2220#define GRCBASE_MSTAT0 0x162000 2221#define GRCBASE_MSTAT1 0x162800 2222#define GRCBASE_XMAC0 0x163000 2223#define GRCBASE_XMAC1 0x163800 2224#define GRCBASE_TIMERS 0x164000 2225#define GRCBASE_XSDM 0x166000 2226#define GRCBASE_QM 0x168000 2227#define GRCBASE_QM_4PORT 0x168000 2228#define GRCBASE_DQ 0x170000 2229#define GRCBASE_TSEM 0x180000 2230#define GRCBASE_CSEM 0x200000 2231#define GRCBASE_XSEM 0x280000 2232#define GRCBASE_XSEM_4PORT 0x280000 2233#define GRCBASE_USEM 0x300000 2234#define GRCBASE_MCP_A 0x380000 2235#define GRCBASE_MISC_AEU GRCBASE_MISC 2236#define GRCBASE_Tstorm GRCBASE_TSEM 2237#define GRCBASE_Cstorm GRCBASE_CSEM 2238#define GRCBASE_Xstorm GRCBASE_XSEM 2239#define GRCBASE_Ustorm GRCBASE_USEM 2240 2241 2242/* offset of configuration space in the pci core register */ 2243#define PCICFG_OFFSET 0x2000 2244#define PCICFG_VENDOR_ID_OFFSET 0x00 2245#define PCICFG_DEVICE_ID_OFFSET 0x02 2246#define PCICFG_COMMAND_OFFSET 0x04 2247#define PCICFG_COMMAND_IO_SPACE (1<<0) 2248#define PCICFG_COMMAND_MEM_SPACE (1<<1) 2249#define PCICFG_COMMAND_BUS_MASTER (1<<2) 2250#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 2251#define PCICFG_COMMAND_MWI_CYCLES (1<<4) 2252#define PCICFG_COMMAND_VGA_SNOOP (1<<5) 2253#define PCICFG_COMMAND_PERR_ENA (1<<6) 2254#define PCICFG_COMMAND_STEPPING (1<<7) 2255#define PCICFG_COMMAND_SERR_ENA (1<<8) 2256#define PCICFG_COMMAND_FAST_B2B (1<<9) 2257#define PCICFG_COMMAND_INT_DISABLE (1<<10) 2258#define PCICFG_COMMAND_RESERVED (0x1f<<11) 2259#define PCICFG_STATUS_OFFSET 0x06 2260#define PCICFG_REVISION_ID_OFFSET 0x08 2261#define PCICFG_REVESION_ID_MASK 0xff 2262#define PCICFG_REVESION_ID_ERROR_VAL 0xff 2263#define PCICFG_CACHE_LINE_SIZE 0x0c 2264#define PCICFG_LATENCY_TIMER 0x0d 2265#define PCICFG_HEADER_TYPE 0x0e 2266#define PCICFG_HEADER_TYPE_NORMAL 0 2267#define PCICFG_HEADER_TYPE_BRIDGE 1 2268#define PCICFG_HEADER_TYPE_CARDBUS 2 2269#define PCICFG_BAR_1_LOW 0x10 2270#define PCICFG_BAR_1_HIGH 0x14 2271#define PCICFG_BAR_2_LOW 0x18 2272#define PCICFG_BAR_2_HIGH 0x1c 2273#define PCICFG_BAR_3_LOW 0x20 2274#define PCICFG_BAR_3_HIGH 0x24 2275#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 2276#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 2277#define PCICFG_INT_LINE 0x3c 2278#define PCICFG_INT_PIN 0x3d 2279#define PCICFG_PM_CAPABILITY 0x48 2280#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 2281#define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 2282#define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 2283#define PCICFG_PM_CAPABILITY_DSI (1<<21) 2284#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 2285#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 2286#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 2287#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 2288#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 2289#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 2290#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 2291#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 2292#define PCICFG_PM_CSR_OFFSET 0x4c 2293#define PCICFG_PM_CSR_STATE (0x3<<0) 2294#define PCICFG_PM_CSR_PME_ENABLE (1<<8) 2295#define PCICFG_PM_CSR_PME_STATUS (1<<15) 2296#define PCICFG_VPD_FLAG_ADDR_OFFSET 0x50 2297#define PCICFG_VPD_DATA_OFFSET 0x54 2298#define PCICFG_MSI_CAP_ID_OFFSET 0x58 2299#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) 2300#define PCICFG_MSI_CONTROL_MCAP (0x7<<17) 2301#define PCICFG_MSI_CONTROL_MENA (0x7<<20) 2302#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) 2303#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) 2304#define PCICFG_MSI_ADDR_LOW_OFFSET 0x5c 2305#define PCICFG_MSI_ADDR_HIGH_OFFSET 0x60 2306#define PCICFG_MSI_DATA_OFFSET 0x64 2307#define PCICFG_GRC_ADDRESS 0x78 2308#define PCICFG_GRC_DATA 0x80 2309#define PCICFG_ME_REGISTER 0x98 2310#define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 2311#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) 2312#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) 2313#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) 2314#define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) 2315 2316#define PCICFG_DEVICE_CONTROL 0xb4 2317#define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND (1<<21) 2318#define PCICFG_DEVICE_STATUS 0xb6 2319#define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 2320#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 2321#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 2322#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 2323#define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 2324#define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 2325#define PCICFG_LINK_CONTROL 0xbc 2326 2327 2328/* config_2 offset */ 2329#define GRC_CONFIG_2_SIZE_REG 0x408 2330#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 2331#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 2332#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 2333#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 2334#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 2335#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 2336#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 2337#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 2338#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 2339#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 2340#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 2341#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 2342#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 2343#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 2344#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 2345#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 2346#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 2347#define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 2348#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 2349#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 2350#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 2351#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 2352#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 2353#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 2354#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 2355#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 2356#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 2357#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 2358#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 2359#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 2360#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 2361#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 2362#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 2363#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 2364#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 2365#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 2366#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 2367#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 2368#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 2369#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 2370 2371/* config_3 offset */ 2372#define GRC_CONFIG_3_SIZE_REG 0x40c 2373#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 2374#define PCI_CONFIG_3_FORCE_PME (1L<<24) 2375#define PCI_CONFIG_3_PME_STATUS (1L<<25) 2376#define PCI_CONFIG_3_PME_ENABLE (1L<<26) 2377#define PCI_CONFIG_3_PM_STATE (0x3L<<27) 2378#define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 2379#define PCI_CONFIG_3_PCI_POWER (1L<<31) 2380 2381#define GRC_REG_DEVICE_CONTROL 0x4d8 2382#define PCIE_SRIOV_DISABLE_IN_PROGRESS \ 2383 (1 << 29) /*When VF Enable is cleared(after it was previously set), 2384 this register will read a value of 1, indicating that all the 2385 VFs that belong to this PF should be flushed. 2386 Software should clear this bit within 1 second of VF Enable 2387 being set by writing a 1 to it, so that VFs are visible to the system again. 2388 WC */ 2389#define PCIE_FLR_IN_PROGRESS \ 2390 (1 << 27) /*When FLR is initiated, this register will read a \ 2391 value of 1 indicating that the 2392 Function is in FLR state. Func can be brought out of FLR state either by 2393 writing 1 to this register (at least 50 ms after FLR was initiated), 2394 or it can also be cleared automatically after 55 ms if auto_clear bit 2395 in private reg space is set. This bit also exists in VF register space 2396 WC */ 2397 2398#define GRC_BAR2_CONFIG 0x4e0 2399#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 2400#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 2401#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 2402#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 2403#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 2404#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 2405#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 2406#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 2407#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 2408#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 2409#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 2410#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 2411#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 2412#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 2413#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 2414#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 2415#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 2416#define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 2417 2418#define GRC_BAR3_CONFIG 0x4f4 2419#define PCI_CONFIG_2_BAR3_SIZE (0xfL<<0) 2420#define PCI_CONFIG_2_BAR3_SIZE_DISABLED (0L<<0) 2421#define PCI_CONFIG_2_BAR3_SIZE_64K (1L<<0) 2422#define PCI_CONFIG_2_BAR3_SIZE_128K (2L<<0) 2423#define PCI_CONFIG_2_BAR3_SIZE_256K (3L<<0) 2424#define PCI_CONFIG_2_BAR3_SIZE_512K (4L<<0) 2425#define PCI_CONFIG_2_BAR3_SIZE_1M (5L<<0) 2426#define PCI_CONFIG_2_BAR3_SIZE_2M (6L<<0) 2427#define PCI_CONFIG_2_BAR3_SIZE_4M (7L<<0) 2428#define PCI_CONFIG_2_BAR3_SIZE_8M (8L<<0) 2429#define PCI_CONFIG_2_BAR3_SIZE_16M (9L<<0) 2430#define PCI_CONFIG_2_BAR3_SIZE_32M (10L<<0) 2431#define PCI_CONFIG_2_BAR3_SIZE_64M (11L<<0) 2432#define PCI_CONFIG_2_BAR3_SIZE_128M (12L<<0) 2433#define PCI_CONFIG_2_BAR3_SIZE_256M (13L<<0) 2434#define PCI_CONFIG_2_BAR3_SIZE_512M (14L<<0) 2435#define PCI_CONFIG_2_BAR3_SIZE_1G (15L<<0) 2436#define PCI_CONFIG_2_BAR3_64ENA (1L<<4) 2437 2438#define PCI_PM_DATA_A 0x410 2439#define PCI_PM_DATA_B 0x414 2440#define PCI_ID_VAL1 0x434 2441#define PCI_ID_VAL2 0x438 2442#define PCI_ID_VAL3 0x43c 2443#define PCI_ID_VAL3_REVISION_ID_ERROR (0xffL<<24) 2444 2445 2446#define GRC_CONFIG_REG_VF_BAR_REG_1 0x608 2447#define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE 0xf 2448 2449#define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C 2450#define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK \ 2451 0x3F /*This field resides in VF only and does not exist in PF. 2452 This register controls the read value of the MSIX_CONTROL[10:0] register 2453 in the VF configuration space. A value of "00000000011" indicates 2454 a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ 2455 define in version.v */ 2456 2457#define GRC_CONFIG_REG_PF_INIT_VF 0x624 2458#define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK \ 2459 0xf /*First VF_NUM for PF is encoded in this register. 2460 The number of VFs assigned to a PF is assumed to be a multiple of 8. 2461 Software should program these bits based on Total Number of VFs \ 2462 programmed for each PF. 2463 Since registers from 0x000-0x7ff are spilt across functions, each PF will have 2464 the same location for the same 4 bits*/ 2465 2466#define PXPCS_TL_CONTROL_5 0x814 2467#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ 2468#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ 2469#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ 2470#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ 2471#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ 2472#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ 2473#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ 2474#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ 2475#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ 2476#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ 2477#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ 2478#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ 2479#define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ 2480#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ 2481#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ 2482#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ 2483#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ 2484#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ 2485#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ 2486#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ 2487#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ 2488#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ 2489#define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ 2490#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ 2491#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ 2492#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ 2493#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ 2494#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ 2495#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ 2496#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ 2497 2498 2499#define PXPCS_TL_FUNC345_STAT 0x854 2500#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ 2501#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 \ 2502 (1 << 28) /* Unsupported Request Error Status in function4, if \ 2503 set, generate pcie_err_attn output when this error is seen. WC */ 2504#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 \ 2505 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \ 2506 generate pcie_err_attn output when this error is seen.. WC */ 2507#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 \ 2508 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \ 2509 generate pcie_err_attn output when this error is seen.. WC */ 2510#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 \ 2511 (1 << 25) /* Receiver Overflow Status Status in function 4, if \ 2512 set, generate pcie_err_attn output when this error is seen.. WC \ 2513 */ 2514#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 \ 2515 (1 << 24) /* Unexpected Completion Status Status in function 4, \ 2516 if set, generate pcie_err_attn output when this error is seen. WC \ 2517 */ 2518#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 \ 2519 (1 << 23) /* Receive UR Statusin function 4. If set, generate \ 2520 pcie_err_attn output when this error is seen. WC */ 2521#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 \ 2522 (1 << 22) /* Completer Timeout Status Status in function 4, if \ 2523 set, generate pcie_err_attn output when this error is seen. WC */ 2524#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 \ 2525 (1 << 21) /* Flow Control Protocol Error Status Status in \ 2526 function 4, if set, generate pcie_err_attn output when this error \ 2527 is seen. WC */ 2528#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 \ 2529 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \ 2530 generate pcie_err_attn output when this error is seen.. WC */ 2531#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ 2532#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 \ 2533 (1 << 18) /* Unsupported Request Error Status in function3, if \ 2534 set, generate pcie_err_attn output when this error is seen. WC */ 2535#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 \ 2536 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \ 2537 generate pcie_err_attn output when this error is seen.. WC */ 2538#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 \ 2539 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \ 2540 generate pcie_err_attn output when this error is seen.. WC */ 2541#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 \ 2542 (1 << 15) /* Receiver Overflow Status Status in function 3, if \ 2543 set, generate pcie_err_attn output when this error is seen.. WC \ 2544 */ 2545#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 \ 2546 (1 << 14) /* Unexpected Completion Status Status in function 3, \ 2547 if set, generate pcie_err_attn output when this error is seen. WC \ 2548 */ 2549#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 \ 2550 (1 << 13) /* Receive UR Statusin function 3. If set, generate \ 2551 pcie_err_attn output when this error is seen. WC */ 2552#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 \ 2553 (1 << 12) /* Completer Timeout Status Status in function 3, if \ 2554 set, generate pcie_err_attn output when this error is seen. WC */ 2555#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 \ 2556 (1 << 11) /* Flow Control Protocol Error Status Status in \ 2557 function 3, if set, generate pcie_err_attn output when this error \ 2558 is seen. WC */ 2559#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 \ 2560 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \ 2561 generate pcie_err_attn output when this error is seen.. WC */ 2562#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ 2563#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 \ 2564 (1 << 8) /* Unsupported Request Error Status for Function 2, if \ 2565 set, generate pcie_err_attn output when this error is seen. WC */ 2566#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 \ 2567 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \ 2568 generate pcie_err_attn output when this error is seen.. WC */ 2569#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 \ 2570 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \ 2571 generate pcie_err_attn output when this error is seen.. WC */ 2572#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 \ 2573 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \ 2574 set, generate pcie_err_attn output when this error is seen.. WC \ 2575 */ 2576#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 \ 2577 (1 << 4) /* Unexpected Completion Status Status for Function 2, \ 2578 if set, generate pcie_err_attn output when this error is seen. WC \ 2579 */ 2580#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 \ 2581 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \ 2582 pcie_err_attn output when this error is seen. WC */ 2583#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 \ 2584 (1 << 2) /* Completer Timeout Status Status for Function 2, if \ 2585 set, generate pcie_err_attn output when this error is seen. WC */ 2586#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 \ 2587 (1 << 1) /* Flow Control Protocol Error Status Status for \ 2588 Function 2, if set, generate pcie_err_attn output when this error \ 2589 is seen. WC */ 2590#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 \ 2591 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \ 2592 generate pcie_err_attn output when this error is seen.. WC */ 2593 2594 2595#define PXPCS_TL_FUNC678_STAT 0x85C 2596#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ 2597#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 \ 2598 (1 << 28) /* Unsupported Request Error Status in function7, if \ 2599 set, generate pcie_err_attn output when this error is seen. WC */ 2600#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 \ 2601 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \ 2602 generate pcie_err_attn output when this error is seen.. WC */ 2603#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 \ 2604 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \ 2605 generate pcie_err_attn output when this error is seen.. WC */ 2606#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 \ 2607 (1 << 25) /* Receiver Overflow Status Status in function 7, if \ 2608 set, generate pcie_err_attn output when this error is seen.. WC \ 2609 */ 2610#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 \ 2611 (1 << 24) /* Unexpected Completion Status Status in function 7, \ 2612 if set, generate pcie_err_attn output when this error is seen. WC \ 2613 */ 2614#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 \ 2615 (1 << 23) /* Receive UR Statusin function 7. If set, generate \ 2616 pcie_err_attn output when this error is seen. WC */ 2617#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 \ 2618 (1 << 22) /* Completer Timeout Status Status in function 7, if \ 2619 set, generate pcie_err_attn output when this error is seen. WC */ 2620#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 \ 2621 (1 << 21) /* Flow Control Protocol Error Status Status in \ 2622 function 7, if set, generate pcie_err_attn output when this error \ 2623 is seen. WC */ 2624#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 \ 2625 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \ 2626 generate pcie_err_attn output when this error is seen.. WC */ 2627#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ 2628#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 \ 2629 (1 << 18) /* Unsupported Request Error Status in function6, if \ 2630 set, generate pcie_err_attn output when this error is seen. WC */ 2631#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 \ 2632 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \ 2633 generate pcie_err_attn output when this error is seen.. WC */ 2634#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 \ 2635 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \ 2636 generate pcie_err_attn output when this error is seen.. WC */ 2637#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 \ 2638 (1 << 15) /* Receiver Overflow Status Status in function 6, if \ 2639 set, generate pcie_err_attn output when this error is seen.. WC \ 2640 */ 2641#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 \ 2642 (1 << 14) /* Unexpected Completion Status Status in function 6, \ 2643 if set, generate pcie_err_attn output when this error is seen. WC \ 2644 */ 2645#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 \ 2646 (1 << 13) /* Receive UR Statusin function 6. If set, generate \ 2647 pcie_err_attn output when this error is seen. WC */ 2648#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 \ 2649 (1 << 12) /* Completer Timeout Status Status in function 6, if \ 2650 set, generate pcie_err_attn output when this error is seen. WC */ 2651#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 \ 2652 (1 << 11) /* Flow Control Protocol Error Status Status in \ 2653 function 6, if set, generate pcie_err_attn output when this error \ 2654 is seen. WC */ 2655#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 \ 2656 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \ 2657 generate pcie_err_attn output when this error is seen.. WC */ 2658#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ 2659#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 \ 2660 (1 << 8) /* Unsupported Request Error Status for Function 5, if \ 2661 set, generate pcie_err_attn output when this error is seen. WC */ 2662#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 \ 2663 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \ 2664 generate pcie_err_attn output when this error is seen.. WC */ 2665#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 \ 2666 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \ 2667 generate pcie_err_attn output when this error is seen.. WC */ 2668#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 \ 2669 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \ 2670 set, generate pcie_err_attn output when this error is seen.. WC \ 2671 */ 2672#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 \ 2673 (1 << 4) /* Unexpected Completion Status Status for Function 5, \ 2674 if set, generate pcie_err_attn output when this error is seen. WC \ 2675 */ 2676#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 \ 2677 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \ 2678 pcie_err_attn output when this error is seen. WC */ 2679#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 \ 2680 (1 << 2) /* Completer Timeout Status Status for Function 5, if \ 2681 set, generate pcie_err_attn output when this error is seen. WC */ 2682#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 \ 2683 (1 << 1) /* Flow Control Protocol Error Status Status for \ 2684 Function 5, if set, generate pcie_err_attn output when this error \ 2685 is seen. WC */ 2686#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 \ 2687 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \ 2688 generate pcie_err_attn output when this error is seen.. WC */ 2689 2690 2691#define BAR_USTRORM_INTMEM 0x400000 2692#define BAR_CSTRORM_INTMEM 0x410000 2693#define BAR_XSTRORM_INTMEM 0x420000 2694#define BAR_TSTRORM_INTMEM 0x430000 2695 2696/* for accessing the IGU in case of status block ACK */ 2697#define BAR_IGU_INTMEM 0x440000 2698 2699#define BAR_DOORBELL_OFFSET 0x800000 2700 2701#define BAR_ME_REGISTER 0x450000 2702#define ME_REG_PF_NUM_SHIFT 0 2703#define ME_REG_PF_NUM \ 2704 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */ 2705#define ME_REG_VF_VALID (1<<8) 2706#define ME_REG_VF_NUM_SHIFT 9 2707#define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT) 2708#define ME_REG_VF_ERR (0x1<<3) 2709#define ME_REG_ABS_PF_NUM_SHIFT 16 2710#define ME_REG_ABS_PF_NUM \ 2711 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */ 2712 2713 2714#define PXP_VF_ADRR_NUM_QUEUES 136 2715#define PXP_ADDR_QUEUE_SIZE 32 2716#define PXP_ADDR_REG_SIZE 512 2717 2718 2719#define PXP_VF_ADDR_IGU_START 0 2720#define PXP_VF_ADDR_IGU_SIZE (0x3000) 2721#define PXP_VF_ADDR_IGU_END \ 2722 ((PXP_VF_ADDR_IGU_START) + (PXP_VF_ADDR_IGU_SIZE) - 1) 2723 2724#define PXP_VF_ADDR_USDM_QUEUES_START 0x3000 2725#define PXP_VF_ADDR_USDM_QUEUES_SIZE \ 2726 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE) 2727#define PXP_VF_ADDR_USDM_QUEUES_END \ 2728 ((PXP_VF_ADDR_USDM_QUEUES_START) + (PXP_VF_ADDR_USDM_QUEUES_SIZE) - 1) 2729 2730#define PXP_VF_ADDR_CSDM_QUEUES_START 0x4100 2731#define PXP_VF_ADDR_CSDM_QUEUES_SIZE \ 2732 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE) 2733#define PXP_VF_ADDR_CSDM_QUEUES_END \ 2734 ((PXP_VF_ADDR_CSDM_QUEUES_START) + (PXP_VF_ADDR_CSDM_QUEUES_SIZE) - 1) 2735 2736#define PXP_VF_ADDR_XSDM_QUEUES_START 0x5200 2737#define PXP_VF_ADDR_XSDM_QUEUES_SIZE \ 2738 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE) 2739#define PXP_VF_ADDR_XSDM_QUEUES_END \ 2740 ((PXP_VF_ADDR_XSDM_QUEUES_START) + (PXP_VF_ADDR_XSDM_QUEUES_SIZE) - 1) 2741 2742#define PXP_VF_ADDR_TSDM_QUEUES_START 0x6300 2743#define PXP_VF_ADDR_TSDM_QUEUES_SIZE \ 2744 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE) 2745#define PXP_VF_ADDR_TSDM_QUEUES_END \ 2746 ((PXP_VF_ADDR_TSDM_QUEUES_START) + (PXP_VF_ADDR_TSDM_QUEUES_SIZE) - 1) 2747 2748#define PXP_VF_ADDR_USDM_GLOBAL_START 0x7400 2749#define PXP_VF_ADDR_USDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE) 2750#define PXP_VF_ADDR_USDM_GLOBAL_END \ 2751 ((PXP_VF_ADDR_USDM_GLOBAL_START) + (PXP_VF_ADDR_USDM_GLOBAL_SIZE) - 1) 2752 2753#define PXP_VF_ADDR_CSDM_GLOBAL_START 0x7600 2754#define PXP_VF_ADDR_CSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE) 2755#define PXP_VF_ADDR_CSDM_GLOBAL_END \ 2756 ((PXP_VF_ADDR_CSDM_GLOBAL_START) + (PXP_VF_ADDR_CSDM_GLOBAL_SIZE) - 1) 2757 2758#define PXP_VF_ADDR_XSDM_GLOBAL_START 0x7800 2759#define PXP_VF_ADDR_XSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE) 2760#define PXP_VF_ADDR_XSDM_GLOBAL_END \ 2761 ((PXP_VF_ADDR_XSDM_GLOBAL_START) + (PXP_VF_ADDR_XSDM_GLOBAL_SIZE) - 1) 2762 2763#define PXP_VF_ADDR_TSDM_GLOBAL_START 0x7a00 2764#define PXP_VF_ADDR_TSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE) 2765#define PXP_VF_ADDR_TSDM_GLOBAL_END \ 2766 ((PXP_VF_ADDR_TSDM_GLOBAL_START) + (PXP_VF_ADDR_TSDM_GLOBAL_SIZE) - 1) 2767 2768#define PXP_VF_ADDR_DB_START 0x7c00 2769#define PXP_VF_ADDR_DB_SIZE (0x200) 2770#define PXP_VF_ADDR_DB_END \ 2771 ((PXP_VF_ADDR_DB_START) + (PXP_VF_ADDR_DB_SIZE) - 1) 2772 2773#define PXP_VF_ADDR_GRC_START 0x7e00 2774#define PXP_VF_ADDR_GRC_SIZE (0x200) 2775#define PXP_VF_ADDR_GRC_END \ 2776 ((PXP_VF_ADDR_GRC_START) + (PXP_VF_ADDR_GRC_SIZE) - 1) 2777 2778#define PXP_VF_ADDR_DORQ_START (0x0) 2779#define PXP_VF_ADDR_DORQ_SIZE (0xffffffff) 2780#define PXP_VF_ADDR_DORQ_END (0xffffffff) 2781 2782#define PXP_BAR_GRC 0 2783#define PXP_BAR_TSDM 0 2784#define PXP_BAR_USDM 0 2785#define PXP_BAR_XSDM 0 2786#define PXP_BAR_CSDM 0 2787#define PXP_BAR_IGU 0 2788#define PXP_BAR_DQ 1 2789 2790#define PXP_VF_BAR_IGU 0 2791#define PXP_VF_BAR_USDM_QUEUES 0 2792#define PXP_VF_BAR_TSDM_QUEUES 0 2793#define PXP_VF_BAR_XSDM_QUEUES 0 2794#define PXP_VF_BAR_CSDM_QUEUES 0 2795#define PXP_VF_BAR_USDM_GLOBAL 0 2796#define PXP_VF_BAR_TSDM_GLOBAL 0 2797#define PXP_VF_BAR_XSDM_GLOBAL 0 2798#define PXP_VF_BAR_CSDM_GLOBAL 0 2799#define PXP_VF_BAR_DB 0 2800#define PXP_VF_BAR_GRC 0 2801#define PXP_VF_BAR_DORQ 1 2802 2803/* PCI CAPABILITIES*/ 2804 2805#define PCI_CAP_PCIE 0x10 /*PCIe capability ID*/ 2806 2807#define PCIE_DEV_CAPS 0x04 2808 2809#define PCIE_DEV_CTRL 0x08 2810#define PCIE_DEV_CTRL_FLR 0x8000; 2811 2812#define PCIE_DEV_STATUS 0x0A 2813 2814#define PCI_CAP_MSIX 0x11 /*MSI-X capability ID*/ 2815#define PCI_MSIX_CONTROL_SHIFT 16 2816#define PCI_MSIX_TABLE_SIZE_MASK 0x07FF 2817#define PCI_MSIX_TABLE_ENABLE_MASK 0x8000 2818 2819 2820#define MDIO_REG_BANK_CL73_IEEEB0 0x0 2821#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 2822#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 2823#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 2824#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 2825 2826#define MDIO_REG_BANK_CL73_IEEEB1 0x10 2827#define MDIO_CL73_IEEEB1_AN_ADV1 0x00 2828#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400 2829#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800 2830#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00 2831#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00 2832#define MDIO_CL73_IEEEB1_AN_ADV2 0x01 2833#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 2834#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 2835#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 2836#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 2837#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03 2838#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400 2839#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800 2840#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00 2841#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00 2842#define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04 2843 2844#define MDIO_REG_BANK_RX0 0x80b0 2845#define MDIO_RX0_RX_STATUS 0x10 2846#define MDIO_RX0_RX_STATUS_SIGDET 0x8000 2847#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 2848#define MDIO_RX0_RX_EQ_BOOST 0x1c 2849#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 2850#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 2851 2852#define MDIO_REG_BANK_RX1 0x80c0 2853#define MDIO_RX1_RX_EQ_BOOST 0x1c 2854#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 2855#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 2856 2857#define MDIO_REG_BANK_RX2 0x80d0 2858#define MDIO_RX2_RX_EQ_BOOST 0x1c 2859#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 2860#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 2861 2862#define MDIO_REG_BANK_RX3 0x80e0 2863#define MDIO_RX3_RX_EQ_BOOST 0x1c 2864#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 2865#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 2866 2867#define MDIO_REG_BANK_RX_ALL 0x80f0 2868#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c 2869#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 2870#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 2871 2872#define MDIO_REG_BANK_TX0 0x8060 2873#define MDIO_TX0_TX_DRIVER 0x17 2874#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 2875#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 2876#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 2877#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 2878#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 2879#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 2880#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 2881#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 2882#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 2883 2884#define MDIO_REG_BANK_TX1 0x8070 2885#define MDIO_TX1_TX_DRIVER 0x17 2886#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 2887#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 2888#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 2889#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 2890#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 2891#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 2892#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 2893#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 2894#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 2895 2896#define MDIO_REG_BANK_TX2 0x8080 2897#define MDIO_TX2_TX_DRIVER 0x17 2898#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 2899#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 2900#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 2901#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 2902#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 2903#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 2904#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 2905#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 2906#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 2907 2908#define MDIO_REG_BANK_TX3 0x8090 2909#define MDIO_TX3_TX_DRIVER 0x17 2910#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 2911#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 2912#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 2913#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 2914#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 2915#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 2916#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 2917#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 2918#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 2919 2920#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 2921#define MDIO_BLOCK0_XGXS_CONTROL 0x10 2922 2923#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 2924#define MDIO_BLOCK1_LANE_CTRL0 0x15 2925#define MDIO_BLOCK1_LANE_CTRL1 0x16 2926#define MDIO_BLOCK1_LANE_CTRL2 0x17 2927#define MDIO_BLOCK1_LANE_PRBS 0x19 2928 2929#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 2930#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 2931#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 2932#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 2933#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 2934#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 2935#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 2936#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 2937#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 2938#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 2939 2940#define MDIO_REG_BANK_GP_STATUS 0x8120 2941#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B 2942#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 2943#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 2944#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 2945#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 2946#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 2947#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 2948#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 2949#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 2950#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 2951#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 2952#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 2953#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 2954#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 2955#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 2956#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 2957#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 2958#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 2959#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 2960#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 2961#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 2962#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 2963#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 2964#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 2965#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 2966#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00 2967#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00 2968#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00 2969#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00 2970#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900 2971 2972 2973#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 2974#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 2975#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000 2976#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 2977#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 2978#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 2979#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) 2980 2981#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 2982#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 2983#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 2984#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 2985#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 2986#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 2987#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 2988#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 2989#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 2990#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 2991#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 2992#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 2993#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001 2994#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002 2995#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 2996#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 2997#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 2998#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 2999#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 3000#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 3001#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 3002#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15 3003#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002 3004#define MDIO_SERDES_DIGITAL_MISC1 0x18 3005#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 3006#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 3007#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 3008#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 3009#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 3010#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 3011#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 3012#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 3013#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 3014#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 3015#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 3016#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 3017#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 3018#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 3019#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 3020#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 3021#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 3022#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 3023 3024#define MDIO_REG_BANK_OVER_1G 0x8320 3025#define MDIO_OVER_1G_DIGCTL_3_4 0x14 3026#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 3027#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 3028#define MDIO_OVER_1G_UP1 0x19 3029#define MDIO_OVER_1G_UP1_2_5G 0x0001 3030#define MDIO_OVER_1G_UP1_5G 0x0002 3031#define MDIO_OVER_1G_UP1_6G 0x0004 3032#define MDIO_OVER_1G_UP1_10G 0x0010 3033#define MDIO_OVER_1G_UP1_10GH 0x0008 3034#define MDIO_OVER_1G_UP1_12G 0x0020 3035#define MDIO_OVER_1G_UP1_12_5G 0x0040 3036#define MDIO_OVER_1G_UP1_13G 0x0080 3037#define MDIO_OVER_1G_UP1_15G 0x0100 3038#define MDIO_OVER_1G_UP1_16G 0x0200 3039#define MDIO_OVER_1G_UP2 0x1A 3040#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 3041#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 3042#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 3043#define MDIO_OVER_1G_UP3 0x1B 3044#define MDIO_OVER_1G_UP3_HIGIG2 0x0001 3045#define MDIO_OVER_1G_LP_UP1 0x1C 3046#define MDIO_OVER_1G_LP_UP2 0x1D 3047#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff 3048#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 3049#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 3050#define MDIO_OVER_1G_LP_UP3 0x1E 3051 3052#define MDIO_REG_BANK_REMOTE_PHY 0x8330 3053#define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10 3054#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010 3055#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600 3056 3057#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 3058#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 3059#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 3060#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 3061 3062#define MDIO_REG_BANK_CL73_USERB0 0x8370 3063#define MDIO_CL73_USERB0_CL73_UCTRL 0x10 3064#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002 3065#define MDIO_CL73_USERB0_CL73_USTAT1 0x11 3066#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100 3067#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400 3068#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 3069#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 3070#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 3071#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 3072#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14 3073#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001 3074 3075#define MDIO_REG_BANK_AER_BLOCK 0xFFD0 3076#define MDIO_AER_BLOCK_AER_REG 0x1E 3077 3078#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0 3079#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10 3080#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 3081#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000 3082#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000 3083#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040 3084#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 3085#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200 3086#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000 3087#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000 3088#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000 3089#define MDIO_COMBO_IEEE0_MII_STATUS 0x11 3090#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 3091#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020 3092#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14 3093#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020 3094#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040 3095#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180 3096#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000 3097#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080 3098#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100 3099#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180 3100#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 3101#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15 3102#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 3103#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 3104#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180 3105#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000 3106#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180 3107#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040 3108#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020 3109/*WhenthelinkpartnerisinSGMIImode(bit0=1), then 3110bit15=link, bit12=duplex, bits11:10=speed, bit14=acknowledge. 3111Theotherbitsarereservedandshouldbezero*/ 3112#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 3113 3114 3115#define MDIO_PMA_DEVAD 0x1 3116/*ieee*/ 3117#define MDIO_PMA_REG_CTRL 0x0 3118#define MDIO_PMA_REG_STATUS 0x1 3119#define MDIO_PMA_REG_10G_CTRL2 0x7 3120#define MDIO_PMA_REG_TX_DISABLE 0x0009 3121#define MDIO_PMA_REG_RX_SD 0xa 3122/*bcm*/ 3123#define MDIO_PMA_REG_BCM_CTRL 0x0096 3124#define MDIO_PMA_REG_FEC_CTRL 0x00ab 3125#define MDIO_PMA_LASI_RXCTRL 0x9000 3126#define MDIO_PMA_LASI_TXCTRL 0x9001 3127#define MDIO_PMA_LASI_CTRL 0x9002 3128#define MDIO_PMA_LASI_RXSTAT 0x9003 3129#define MDIO_PMA_LASI_TXSTAT 0x9004 3130#define MDIO_PMA_LASI_STAT 0x9005 3131#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 3132#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 3133#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 3134#define MDIO_PMA_REG_TX_POWER_DOWN 0xca02 3135#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 3136#define MDIO_PMA_REG_MISC_CTRL 0xca0a 3137#define MDIO_PMA_REG_GEN_CTRL 0xca10 3138#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 3139#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a 3140#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 3141#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 3142#define MDIO_PMA_REG_ROM_VER1 0xca19 3143#define MDIO_PMA_REG_ROM_VER2 0xca1a 3144#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b 3145#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d 3146#define MDIO_PMA_REG_PLL_CTRL 0xca1e 3147#define MDIO_PMA_REG_MISC_CTRL0 0xca23 3148#define MDIO_PMA_REG_LRM_MODE 0xca3f 3149#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 3150#define MDIO_PMA_REG_MISC_CTRL1 0xca85 3151 3152#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000 3153#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c 3154#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 3155#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 3156#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 3157#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c 3158#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002 3159#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003 3160#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 3161#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff 3162#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 3163#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 3164 3165#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005 3166#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007 3167#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff 3168#define MDIO_PMA_REG_8727_MISC_CTRL 0x8309 3169#define MDIO_PMA_REG_8727_TX_CTRL1 0xca02 3170#define MDIO_PMA_REG_8727_TX_CTRL2 0xca05 3171#define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808 3172#define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e 3173#define MDIO_PMA_REG_8727_PCS_GP 0xc842 3174#define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4 3175 3176#define MDIO_AN_REG_8727_MISC_CTRL 0x8309 3177#define MDIO_PMA_REG_8073_CHIP_REV 0xc801 3178#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 3179#define MDIO_PMA_REG_8073_XAUI_WA 0xc841 3180#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08 3181 3182#define MDIO_PMA_REG_7101_RESET 0xc000 3183#define MDIO_PMA_REG_7107_LED_CNTL 0xc007 3184#define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009 3185#define MDIO_PMA_REG_7101_VER1 0xc026 3186#define MDIO_PMA_REG_7101_VER2 0xc027 3187 3188#define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811 3189#define MDIO_PMA_REG_8481_LED1_MASK 0xa82c 3190#define MDIO_PMA_REG_8481_LED2_MASK 0xa82f 3191#define MDIO_PMA_REG_8481_LED3_MASK 0xa832 3192#define MDIO_PMA_REG_8481_LED3_BLINK 0xa834 3193#define MDIO_PMA_REG_8481_LED5_MASK 0xa838 3194#define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835 3195#define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b 3196#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800 3197#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11 3198 3199 3200#define MDIO_WIS_DEVAD 0x2 3201/*bcm*/ 3202#define MDIO_WIS_REG_LASI_CNTL 0x9002 3203#define MDIO_WIS_REG_LASI_STATUS 0x9005 3204 3205#define MDIO_PCS_DEVAD 0x3 3206#define MDIO_PCS_REG_STATUS 0x0020 3207#define MDIO_PCS_REG_LASI_STATUS 0x9005 3208#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 3209#define MDIO_PCS_REG_7101_SPI_MUX 0xD008 3210#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A 3211#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) 3212#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A 3213#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) 3214#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) 3215#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) 3216#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 3217 3218 3219#define MDIO_XS_DEVAD 0x4 3220#define MDIO_XS_REG_STATUS 0x0001 3221#define MDIO_XS_PLL_SEQUENCER 0x8000 3222#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a 3223 3224#define MDIO_XS_8706_REG_BANK_RX0 0x80bc 3225#define MDIO_XS_8706_REG_BANK_RX1 0x80cc 3226#define MDIO_XS_8706_REG_BANK_RX2 0x80dc 3227#define MDIO_XS_8706_REG_BANK_RX3 0x80ec 3228#define MDIO_XS_8706_REG_BANK_RXA 0x80fc 3229 3230#define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA 3231 3232#define MDIO_AN_DEVAD 0x7 3233/*ieee*/ 3234#define MDIO_AN_REG_CTRL 0x0000 3235#define MDIO_AN_REG_STATUS 0x0001 3236#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 3237#define MDIO_AN_REG_ADV_PAUSE 0x0010 3238#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 3239#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 3240#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 3241#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 3242#define MDIO_AN_REG_ADV 0x0011 3243#define MDIO_AN_REG_ADV2 0x0012 3244#define MDIO_AN_REG_LP_AUTO_NEG 0x0013 3245#define MDIO_AN_REG_LP_AUTO_NEG2 0x0014 3246#define MDIO_AN_REG_MASTER_STATUS 0x0021 3247#define MDIO_AN_REG_EEE_ADV 0x003c 3248#define MDIO_AN_REG_LP_EEE_ADV 0x003d 3249/*bcm*/ 3250#define MDIO_AN_REG_LINK_STATUS 0x8304 3251#define MDIO_AN_REG_CL37_CL73 0x8370 3252#define MDIO_AN_REG_CL37_AN 0xffe0 3253#define MDIO_AN_REG_CL37_FC_LD 0xffe4 3254#define MDIO_AN_REG_CL37_FC_LP 0xffe5 3255#define MDIO_AN_REG_1000T_STATUS 0xffea 3256 3257#define MDIO_AN_REG_8073_2_5G 0x8329 3258#define MDIO_AN_REG_8073_BAM 0x8350 3259 3260#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020 3261#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 3262#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40 3263#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1 3264#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 3265#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6 3266#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 3267#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0 3268#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008 3269#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 3270#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 3271#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 3272#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc 3273 3274/* BCM84823 only */ 3275#define MDIO_CTL_DEVAD 0x1e 3276#define MDIO_CTL_REG_84823_MEDIA 0x401a 3277#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018 3278 /* These pins configure the BCM84823 interface to MAC after reset. */ 3279#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008 3280#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010 3281 /* These pins configure the BCM84823 interface to Line after reset. */ 3282#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060 3283#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020 3284#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040 3285 /* When this pin is active high during reset, 10GBASE-T core is power 3286 * down, When it is active low the 10GBASE-T is power up 3287 */ 3288#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080 3289#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100 3290#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000 3291#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100 3292#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000 3293#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005 3294#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080 3295#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b 3296#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f 3297#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 3298#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec 3299#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 3300 3301/* BCM84833 only */ 3302#define MDIO_84833_TOP_CFG_FW_REV 0x400f 3303#define MDIO_84833_TOP_CFG_FW_EEE 0x10b1 3304#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81 3305#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a 3306#define MDIO_84833_SUPER_ISOLATE 0x8000 3307/* These are mailbox register set used by 84833. */ 3308#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005 3309#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006 3310#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007 3311#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008 3312#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009 3313#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037 3314#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038 3315#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039 3316#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a 3317#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b 3318#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c 3319#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0 3320#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26 3321#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27 3322#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28 3323#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29 3324#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30 3325#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31 3326 3327/* Mailbox command set used by 84833. */ 3328#define PHY84833_CMD_SET_PAIR_SWAP 0x8001 3329#define PHY84833_CMD_GET_EEE_MODE 0x8008 3330#define PHY84833_CMD_SET_EEE_MODE 0x8009 3331#define PHY84833_CMD_GET_CURRENT_TEMP 0x8031 3332/* Mailbox status set used by 84833. */ 3333#define PHY84833_STATUS_CMD_RECEIVED 0x0001 3334#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002 3335#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004 3336#define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008 3337#define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010 3338#define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020 3339#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040 3340#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080 3341#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5 3342 3343 3344/* Warpcore clause 45 addressing */ 3345#define MDIO_WC_DEVAD 0x3 3346#define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0 3347#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7 3348#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 3349#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 3350#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12 3351#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000 3352#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000 3353#define MDIO_WC_REG_PCS_STATUS2 0x0021 3354#define MDIO_WC_REG_PMD_KR_CONTROL 0x0096 3355#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 3356#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e 3357#define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010 3358#define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015 3359#define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016 3360#define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017 3361#define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018 3362#define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a 3363#define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061 3364#define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071 3365#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081 3366#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091 3367#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067 3368#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04 3369#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0 3370#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08 3371#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 3372#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c 3373#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000 3374#define MDIO_WC_REG_TX1_TX_DRIVER 0x8077 3375#define MDIO_WC_REG_TX2_TX_DRIVER 0x8087 3376#define MDIO_WC_REG_TX3_TX_DRIVER 0x8097 3377#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9 3378#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9 3379#define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba 3380#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca 3381#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da 3382#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea 3383#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa 3384#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104 3385#define MDIO_WC_REG_XGXS_STATUS3 0x8129 3386#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130 3387#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131 3388#define MDIO_WC_REG_XGXS_STATUS4 0x813c 3389#define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141 3390#define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142 3391#define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B 3392#define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169 3393#define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0 3394#define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1 3395#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2 3396#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3 3397#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4 3398#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000 3399#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100 3400#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010 3401#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1 3402#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE 3403#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0 3404#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2 3405#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0 3406#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0 3407#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1 3408#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2 3409#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3 3410#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4 3411#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4 3412#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8 3413#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc 3414#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE 3415#define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e 3416#define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7) 3417#define MDIO_WC_REG_DSC_SMC 0x8213 3418#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e 3419#define MDIO_WC_REG_TX_FIR_TAP 0x82e2 3420#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00 3421#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f 3422#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04 3423#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0 3424#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a 3425#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00 3426#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000 3427#define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2 3428#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 3429#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6 3430#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7 3431#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8 3432#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec 3433#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300 3434#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301 3435#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302 3436#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304 3437#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308 3438#define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309 3439#define MDIO_WC_REG_DIGITAL3_UP1 0x8329 3440#define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c 3441#define MDIO_WC_REG_DIGITAL4_MISC3 0x833c 3442#define MDIO_WC_REG_DIGITAL4_MISC5 0x833e 3443#define MDIO_WC_REG_DIGITAL5_MISC6 0x8345 3444#define MDIO_WC_REG_DIGITAL5_MISC7 0x8349 3445#define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d 3446#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e 3447#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350 3448#define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368 3449#define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370 3450#define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371 3451#define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372 3452#define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373 3453#define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374 3454#define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b 3455#define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390 3456#define MDIO_WC_REG_TX66_CONTROL 0x83b0 3457#define MDIO_WC_REG_RX66_CONTROL 0x83c0 3458#define MDIO_WC_REG_RX66_SCW0 0x83c2 3459#define MDIO_WC_REG_RX66_SCW1 0x83c3 3460#define MDIO_WC_REG_RX66_SCW2 0x83c4 3461#define MDIO_WC_REG_RX66_SCW3 0x83c5 3462#define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6 3463#define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7 3464#define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8 3465#define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9 3466#define MDIO_WC_REG_FX100_CTRL1 0x8400 3467#define MDIO_WC_REG_FX100_CTRL3 0x8402 3468#define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436 3469#define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437 3470#define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438 3471#define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439 3472#define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a 3473#define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b 3474#define MDIO_WC_REG_ETA_CL73_OUI1 0x8453 3475#define MDIO_WC_REG_ETA_CL73_OUI2 0x8454 3476#define MDIO_WC_REG_ETA_CL73_OUI3 0x8455 3477#define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456 3478#define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457 3479#define MDIO_WC_REG_MICROBLK_CMD 0xffc2 3480#define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5 3481#define MDIO_WC_REG_MICROBLK_CMD3 0xffcc 3482 3483#define MDIO_WC_REG_AERBLK_AER 0xffde 3484#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0 3485#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1 3486 3487#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A 3488#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0 3489#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4 3490 3491#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141 3492 3493#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f 3494 3495/* 54618se */ 3496#define MDIO_REG_GPHY_MII_STATUS 0x1 3497#define MDIO_REG_GPHY_PHYID_LSB 0x3 3498#define MDIO_REG_GPHY_CL45_ADDR_REG 0xd 3499#define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000 3500#define MDIO_REG_GPHY_CL45_REG_READ 0xc000 3501#define MDIO_REG_GPHY_CL45_DATA_REG 0xe 3502#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e 3503#define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15 3504#define MDIO_REG_GPHY_EXP_ACCESS 0x17 3505#define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00 3506#define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40 3507#define MDIO_REG_GPHY_AUX_STATUS 0x19 3508#define MDIO_REG_INTR_STATUS 0x1a 3509#define MDIO_REG_INTR_MASK 0x1b 3510#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1) 3511#define MDIO_REG_GPHY_SHADOW 0x1c 3512#define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10) 3513#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10) 3514#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15) 3515#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10) 3516#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8) 3517 3518 3519#define IGU_FUNC_BASE 0x0400 3520 3521#define IGU_ADDR_MSIX 0x0000 3522#define IGU_ADDR_INT_ACK 0x0200 3523#define IGU_ADDR_PROD_UPD 0x0201 3524#define IGU_ADDR_ATTN_BITS_UPD 0x0202 3525#define IGU_ADDR_ATTN_BITS_SET 0x0203 3526#define IGU_ADDR_ATTN_BITS_CLR 0x0204 3527#define IGU_ADDR_COALESCE_NOW 0x0205 3528#define IGU_ADDR_SIMD_MASK 0x0206 3529#define IGU_ADDR_SIMD_NOMASK 0x0207 3530#define IGU_ADDR_MSI_CTL 0x0210 3531#define IGU_ADDR_MSI_ADDR_LO 0x0211 3532#define IGU_ADDR_MSI_ADDR_HI 0x0212 3533#define IGU_ADDR_MSI_DATA 0x0213 3534 3535 3536#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0 3537#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1 3538#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2 3539#define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3 3540 3541#define COMMAND_REG_INT_ACK 0x0 3542#define COMMAND_REG_PROD_UPD 0x4 3543#define COMMAND_REG_ATTN_BITS_UPD 0x8 3544#define COMMAND_REG_ATTN_BITS_SET 0xc 3545#define COMMAND_REG_ATTN_BITS_CLR 0x10 3546#define COMMAND_REG_COALESCE_NOW 0x14 3547#define COMMAND_REG_SIMD_MASK 0x18 3548#define COMMAND_REG_SIMD_NOMASK 0x1c 3549 3550 3551#define IGU_MEM_BASE 0x0000 3552 3553#define IGU_MEM_MSIX_BASE 0x0000 3554#define IGU_MEM_MSIX_UPPER 0x007f 3555#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 3556 3557#define IGU_MEM_PBA_MSIX_BASE 0x0200 3558#define IGU_MEM_PBA_MSIX_UPPER 0x0200 3559 3560#define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201 3561#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 3562 3563#define IGU_CMD_INT_ACK_BASE 0x0400 3564#define IGU_CMD_INT_ACK_UPPER \ 3565 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PATH - 1) 3566#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff 3567 3568#define IGU_CMD_E2_PROD_UPD_BASE 0x0500 3569#define IGU_CMD_E2_PROD_UPD_UPPER \ 3570 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PATH - 1) 3571#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f 3572 3573#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0 3574#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1 3575#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2 3576 3577#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3 3578#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4 3579#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5 3580#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6 3581 3582 3583#define IGU_REG_RESERVED_UPPER 0x05ff 3584 3585#define IGU_SEG_IDX_ATTN 2 3586#define IGU_SEG_IDX_DEFAULT 1 3587/* Fields of IGU PF CONFIGRATION REGISTER */ 3588#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */ 3589#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 3590#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */ 3591#define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */ 3592#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 3593#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */ 3594 3595/* Fields of IGU VF CONFIGRATION REGISTER */ 3596#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */ 3597#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 3598#define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */ 3599#define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */ 3600#define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 3601 3602 3603#define IGU_BC_DSB_NUM_SEGS 5 3604#define IGU_BC_NDSB_NUM_SEGS 2 3605#define IGU_NORM_DSB_NUM_SEGS 2 3606#define IGU_NORM_NDSB_NUM_SEGS 1 3607#define IGU_BC_BASE_DSB_PROD 128 3608#define IGU_NORM_BASE_DSB_PROD 136 3609 3610 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \ 3611 [5:2] = 0; [1:0] = PF number) */ 3612#define IGU_FID_ENCODE_IS_PF (0x1<<6) 3613#define IGU_FID_ENCODE_IS_PF_SHIFT 6 3614#define IGU_FID_VF_NUM_MASK (0x3f) 3615#define IGU_FID_PF_NUM_MASK (0x7) 3616 3617#define IGU_REG_MAPPING_MEMORY_VALID (1<<0) 3618#define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1) 3619#define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1 3620#define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7) 3621#define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7 3622 3623 3624#define CDU_REGION_NUMBER_XCM_AG 2 3625#define CDU_REGION_NUMBER_UCM_AG 4 3626 3627 3628/* String-to-compress [31:8] = CID (all 24 bits) 3629 * String-to-compress [7:4] = Region 3630 * String-to-compress [3:0] = Type 3631 */ 3632#define CDU_VALID_DATA(_cid, _region, _type) \ 3633 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf))) 3634#define CDU_CRC8(_cid, _region, _type) \ 3635 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)) 3636#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \ 3637 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f)) 3638#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \ 3639 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7)) 3640#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) 3641 3642/****************************************************************************** 3643 * Description: 3644 * Calculates crc 8 on a word value: polynomial 0-1-2-8 3645 * Code was translated from Verilog. 3646 * Return: 3647 *****************************************************************************/ 3648static inline uint8_t calc_crc8(uint32_t data, uint8_t crc) 3649{ 3650 uint8_t D[32]; 3651 uint8_t NewCRC[8]; 3652 uint8_t C[8]; 3653 uint8_t crc_res; 3654 uint8_t i; 3655 3656 /* split the data into 31 bits */ 3657 for (i = 0; i < 32; i++) { 3658 D[i] = (uint8_t)(data & 1); 3659 data = data >> 1; 3660 } 3661 3662 /* split the crc into 8 bits */ 3663 for (i = 0; i < 8; i++) { 3664 C[i] = crc & 1; 3665 crc = crc >> 1; 3666 } 3667 3668 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ 3669 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ 3670 C[6] ^ C[7]; 3671 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^ 3672 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ 3673 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6]; 3674 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^ 3675 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ 3676 C[0] ^ C[1] ^ C[4] ^ C[5]; 3677 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ 3678 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ 3679 C[1] ^ C[2] ^ C[5] ^ C[6]; 3680 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^ 3681 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ 3682 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; 3683 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^ 3684 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ 3685 C[3] ^ C[4] ^ C[7]; 3686 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^ 3687 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ C[5]; 3688 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^ 3689 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ C[6]; 3690 3691 crc_res = 0; 3692 for (i = 0; i < 8; i++) { 3693 crc_res |= (NewCRC[i] << i); 3694 } 3695 3696 return crc_res; 3697} 3698 3699 3700#endif /* ECORE_REG_H */ 3701 3702