if_ath_rx.c revision 238316
1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath_rx.c 238316 2012-07-10 00:02:19Z adrian $"); 32 33/* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40#include "opt_inet.h" 41#include "opt_ath.h" 42/* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49#include "opt_ah.h" 50#include "opt_wlan.h" 51 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/sysctl.h> 55#include <sys/mbuf.h> 56#include <sys/malloc.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/kernel.h> 60#include <sys/socket.h> 61#include <sys/sockio.h> 62#include <sys/errno.h> 63#include <sys/callout.h> 64#include <sys/bus.h> 65#include <sys/endian.h> 66#include <sys/kthread.h> 67#include <sys/taskqueue.h> 68#include <sys/priv.h> 69#include <sys/module.h> 70#include <sys/ktr.h> 71#include <sys/smp.h> /* for mp_ncpus */ 72 73#include <machine/bus.h> 74 75#include <net/if.h> 76#include <net/if_dl.h> 77#include <net/if_media.h> 78#include <net/if_types.h> 79#include <net/if_arp.h> 80#include <net/ethernet.h> 81#include <net/if_llc.h> 82 83#include <net80211/ieee80211_var.h> 84#include <net80211/ieee80211_regdomain.h> 85#ifdef IEEE80211_SUPPORT_SUPERG 86#include <net80211/ieee80211_superg.h> 87#endif 88#ifdef IEEE80211_SUPPORT_TDMA 89#include <net80211/ieee80211_tdma.h> 90#endif 91 92#include <net/bpf.h> 93 94#ifdef INET 95#include <netinet/in.h> 96#include <netinet/if_ether.h> 97#endif 98 99#include <dev/ath/if_athvar.h> 100#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101#include <dev/ath/ath_hal/ah_diagcodes.h> 102 103#include <dev/ath/if_ath_debug.h> 104#include <dev/ath/if_ath_misc.h> 105#include <dev/ath/if_ath_tsf.h> 106#include <dev/ath/if_ath_tx.h> 107#include <dev/ath/if_ath_sysctl.h> 108#include <dev/ath/if_ath_led.h> 109#include <dev/ath/if_ath_keycache.h> 110#include <dev/ath/if_ath_rx.h> 111#include <dev/ath/if_ath_beacon.h> 112#include <dev/ath/if_athdfs.h> 113 114#ifdef ATH_TX99_DIAG 115#include <dev/ath/ath_tx99/ath_tx99.h> 116#endif 117 118#define ATH_KTR_INTR KTR_SPARE4 119#define ATH_KTR_ERR KTR_SPARE3 120 121/* 122 * Calculate the receive filter according to the 123 * operating mode and state: 124 * 125 * o always accept unicast, broadcast, and multicast traffic 126 * o accept PHY error frames when hardware doesn't have MIB support 127 * to count and we need them for ANI (sta mode only until recently) 128 * and we are not scanning (ANI is disabled) 129 * NB: older hal's add rx filter bits out of sight and we need to 130 * blindly preserve them 131 * o probe request frames are accepted only when operating in 132 * hostap, adhoc, mesh, or monitor modes 133 * o enable promiscuous mode 134 * - when in monitor mode 135 * - if interface marked PROMISC (assumes bridge setting is filtered) 136 * o accept beacons: 137 * - when operating in station mode for collecting rssi data when 138 * the station is otherwise quiet, or 139 * - when operating in adhoc mode so the 802.11 layer creates 140 * node table entries for peers, 141 * - when scanning 142 * - when doing s/w beacon miss (e.g. for ap+sta) 143 * - when operating in ap mode in 11g to detect overlapping bss that 144 * require protection 145 * - when operating in mesh mode to detect neighbors 146 * o accept control frames: 147 * - when in monitor mode 148 * XXX HT protection for 11n 149 */ 150u_int32_t 151ath_calcrxfilter(struct ath_softc *sc) 152{ 153 struct ifnet *ifp = sc->sc_ifp; 154 struct ieee80211com *ic = ifp->if_l2com; 155 u_int32_t rfilt; 156 157 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 158 if (!sc->sc_needmib && !sc->sc_scanning) 159 rfilt |= HAL_RX_FILTER_PHYERR; 160 if (ic->ic_opmode != IEEE80211_M_STA) 161 rfilt |= HAL_RX_FILTER_PROBEREQ; 162 /* XXX ic->ic_monvaps != 0? */ 163 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 164 rfilt |= HAL_RX_FILTER_PROM; 165 if (ic->ic_opmode == IEEE80211_M_STA || 166 ic->ic_opmode == IEEE80211_M_IBSS || 167 sc->sc_swbmiss || sc->sc_scanning) 168 rfilt |= HAL_RX_FILTER_BEACON; 169 /* 170 * NB: We don't recalculate the rx filter when 171 * ic_protmode changes; otherwise we could do 172 * this only when ic_protmode != NONE. 173 */ 174 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 175 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 176 rfilt |= HAL_RX_FILTER_BEACON; 177 178 /* 179 * Enable hardware PS-POLL RX only for hostap mode; 180 * STA mode sends PS-POLL frames but never 181 * receives them. 182 */ 183 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 184 0, NULL) == HAL_OK && 185 ic->ic_opmode == IEEE80211_M_HOSTAP) 186 rfilt |= HAL_RX_FILTER_PSPOLL; 187 188 if (sc->sc_nmeshvaps) { 189 rfilt |= HAL_RX_FILTER_BEACON; 190 if (sc->sc_hasbmatch) 191 rfilt |= HAL_RX_FILTER_BSSID; 192 else 193 rfilt |= HAL_RX_FILTER_PROM; 194 } 195 if (ic->ic_opmode == IEEE80211_M_MONITOR) 196 rfilt |= HAL_RX_FILTER_CONTROL; 197 198 /* 199 * Enable RX of compressed BAR frames only when doing 200 * 802.11n. Required for A-MPDU. 201 */ 202 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 203 rfilt |= HAL_RX_FILTER_COMPBAR; 204 205 /* 206 * Enable radar PHY errors if requested by the 207 * DFS module. 208 */ 209 if (sc->sc_dodfs) 210 rfilt |= HAL_RX_FILTER_PHYRADAR; 211 212 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 213 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 214 return rfilt; 215} 216 217static int 218ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 219{ 220 struct ath_hal *ah = sc->sc_ah; 221 int error; 222 struct mbuf *m; 223 struct ath_desc *ds; 224 225 m = bf->bf_m; 226 if (m == NULL) { 227 /* 228 * NB: by assigning a page to the rx dma buffer we 229 * implicitly satisfy the Atheros requirement that 230 * this buffer be cache-line-aligned and sized to be 231 * multiple of the cache line size. Not doing this 232 * causes weird stuff to happen (for the 5210 at least). 233 */ 234 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 235 if (m == NULL) { 236 DPRINTF(sc, ATH_DEBUG_ANY, 237 "%s: no mbuf/cluster\n", __func__); 238 sc->sc_stats.ast_rx_nombuf++; 239 return ENOMEM; 240 } 241 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 242 243 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 244 bf->bf_dmamap, m, 245 bf->bf_segs, &bf->bf_nseg, 246 BUS_DMA_NOWAIT); 247 if (error != 0) { 248 DPRINTF(sc, ATH_DEBUG_ANY, 249 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 250 __func__, error); 251 sc->sc_stats.ast_rx_busdma++; 252 m_freem(m); 253 return error; 254 } 255 KASSERT(bf->bf_nseg == 1, 256 ("multi-segment packet; nseg %u", bf->bf_nseg)); 257 bf->bf_m = m; 258 } 259 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 260 261 /* 262 * Setup descriptors. For receive we always terminate 263 * the descriptor list with a self-linked entry so we'll 264 * not get overrun under high load (as can happen with a 265 * 5212 when ANI processing enables PHY error frames). 266 * 267 * To insure the last descriptor is self-linked we create 268 * each descriptor as self-linked and add it to the end. As 269 * each additional descriptor is added the previous self-linked 270 * entry is ``fixed'' naturally. This should be safe even 271 * if DMA is happening. When processing RX interrupts we 272 * never remove/process the last, self-linked, entry on the 273 * descriptor list. This insures the hardware always has 274 * someplace to write a new frame. 275 */ 276 /* 277 * 11N: we can no longer afford to self link the last descriptor. 278 * MAC acknowledges BA status as long as it copies frames to host 279 * buffer (or rx fifo). This can incorrectly acknowledge packets 280 * to a sender if last desc is self-linked. 281 */ 282 ds = bf->bf_desc; 283 if (sc->sc_rxslink) 284 ds->ds_link = bf->bf_daddr; /* link to self */ 285 else 286 ds->ds_link = 0; /* terminate the list */ 287 ds->ds_data = bf->bf_segs[0].ds_addr; 288 ath_hal_setuprxdesc(ah, ds 289 , m->m_len /* buffer size */ 290 , 0 291 ); 292 293 if (sc->sc_rxlink != NULL) 294 *sc->sc_rxlink = bf->bf_daddr; 295 sc->sc_rxlink = &ds->ds_link; 296 return 0; 297} 298 299/* 300 * Intercept management frames to collect beacon rssi data 301 * and to do ibss merges. 302 */ 303void 304ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 305 int subtype, int rssi, int nf) 306{ 307 struct ieee80211vap *vap = ni->ni_vap; 308 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 309 310 /* 311 * Call up first so subsequent work can use information 312 * potentially stored in the node (e.g. for ibss merge). 313 */ 314 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 315 switch (subtype) { 316 case IEEE80211_FC0_SUBTYPE_BEACON: 317 /* update rssi statistics for use by the hal */ 318 /* XXX unlocked check against vap->iv_bss? */ 319 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 320 if (sc->sc_syncbeacon && 321 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 322 /* 323 * Resync beacon timers using the tsf of the beacon 324 * frame we just received. 325 */ 326 ath_beacon_config(sc, vap); 327 } 328 /* fall thru... */ 329 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 330 if (vap->iv_opmode == IEEE80211_M_IBSS && 331 vap->iv_state == IEEE80211_S_RUN) { 332 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 333 uint64_t tsf = ath_extend_tsf(sc, rstamp, 334 ath_hal_gettsf64(sc->sc_ah)); 335 /* 336 * Handle ibss merge as needed; check the tsf on the 337 * frame before attempting the merge. The 802.11 spec 338 * says the station should change it's bssid to match 339 * the oldest station with the same ssid, where oldest 340 * is determined by the tsf. Note that hardware 341 * reconfiguration happens through callback to 342 * ath_newstate as the state machine will go from 343 * RUN -> RUN when this happens. 344 */ 345 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 346 DPRINTF(sc, ATH_DEBUG_STATE, 347 "ibss merge, rstamp %u tsf %ju " 348 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 349 (uintmax_t)ni->ni_tstamp.tsf); 350 (void) ieee80211_ibss_merge(ni); 351 } 352 } 353 break; 354 } 355} 356 357#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 358static void 359ath_rx_tap_vendor(struct ifnet *ifp, struct mbuf *m, 360 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 361{ 362 struct ath_softc *sc = ifp->if_softc; 363 364 /* Fill in the extension bitmap */ 365 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 366 367 /* Fill in the vendor header */ 368 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 369 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 370 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 371 372 /* XXX what should this be? */ 373 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 374 sc->sc_rx_th.wr_vh.vh_skip_len = 375 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 376 377 /* General version info */ 378 sc->sc_rx_th.wr_v.vh_version = 1; 379 380 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 381 382 /* rssi */ 383 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 384 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 385 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 386 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 387 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 388 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 389 390 /* evm */ 391 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 392 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 393 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 394 /* XXX TODO: extend this to include 3-stream EVM */ 395 396 /* phyerr info */ 397 if (rs->rs_status & HAL_RXERR_PHY) 398 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 399 else 400 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 401 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 402 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 403} 404#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 405 406static void 407ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 408 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 409{ 410#define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 411#define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 412#define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 413#define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 414 struct ath_softc *sc = ifp->if_softc; 415 const HAL_RATE_TABLE *rt; 416 uint8_t rix; 417 418 rt = sc->sc_currates; 419 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 420 rix = rt->rateCodeToIndex[rs->rs_rate]; 421 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 422 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 423#ifdef AH_SUPPORT_AR5416 424 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 425 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 426 struct ieee80211com *ic = ifp->if_l2com; 427 428 if ((rs->rs_flags & HAL_RX_2040) == 0) 429 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 430 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 431 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 432 else 433 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 434 if ((rs->rs_flags & HAL_RX_GI) == 0) 435 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 436 } 437#endif 438 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 439 if (rs->rs_status & HAL_RXERR_CRC) 440 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 441 /* XXX propagate other error flags from descriptor */ 442 sc->sc_rx_th.wr_antnoise = nf; 443 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 444 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 445#undef CHAN_HT 446#undef CHAN_HT20 447#undef CHAN_HT40U 448#undef CHAN_HT40D 449} 450 451static void 452ath_handle_micerror(struct ieee80211com *ic, 453 struct ieee80211_frame *wh, int keyix) 454{ 455 struct ieee80211_node *ni; 456 457 /* XXX recheck MIC to deal w/ chips that lie */ 458 /* XXX discard MIC errors on !data frames */ 459 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 460 if (ni != NULL) { 461 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 462 ieee80211_free_node(ni); 463 } 464} 465 466int 467ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 468 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf) 469{ 470 struct ath_hal *ah = sc->sc_ah; 471 struct mbuf *m = bf->bf_m; 472 uint64_t rstamp; 473 int len, type; 474 struct ifnet *ifp = sc->sc_ifp; 475 struct ieee80211com *ic = ifp->if_l2com; 476 struct ieee80211_node *ni; 477 int is_good = 0; 478 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 479 480 /* 481 * Calculate the correct 64 bit TSF given 482 * the TSF64 register value and rs_tstamp. 483 */ 484 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 485 486 /* These aren't specifically errors */ 487#ifdef AH_SUPPORT_AR5416 488 if (rs->rs_flags & HAL_RX_GI) 489 sc->sc_stats.ast_rx_halfgi++; 490 if (rs->rs_flags & HAL_RX_2040) 491 sc->sc_stats.ast_rx_2040++; 492 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 493 sc->sc_stats.ast_rx_pre_crc_err++; 494 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 495 sc->sc_stats.ast_rx_post_crc_err++; 496 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 497 sc->sc_stats.ast_rx_decrypt_busy_err++; 498 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 499 sc->sc_stats.ast_rx_hi_rx_chain++; 500#endif /* AH_SUPPORT_AR5416 */ 501 502 if (rs->rs_status != 0) { 503 if (rs->rs_status & HAL_RXERR_CRC) 504 sc->sc_stats.ast_rx_crcerr++; 505 if (rs->rs_status & HAL_RXERR_FIFO) 506 sc->sc_stats.ast_rx_fifoerr++; 507 if (rs->rs_status & HAL_RXERR_PHY) { 508 sc->sc_stats.ast_rx_phyerr++; 509 /* Process DFS radar events */ 510 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 511 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 512 /* Since we're touching the frame data, sync it */ 513 bus_dmamap_sync(sc->sc_dmat, 514 bf->bf_dmamap, 515 BUS_DMASYNC_POSTREAD); 516 /* Now pass it to the radar processing code */ 517 ath_dfs_process_phy_err(sc, m, rstamp, rs); 518 } 519 520 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 521 if (rs->rs_phyerr < 64) 522 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 523 goto rx_error; /* NB: don't count in ierrors */ 524 } 525 if (rs->rs_status & HAL_RXERR_DECRYPT) { 526 /* 527 * Decrypt error. If the error occurred 528 * because there was no hardware key, then 529 * let the frame through so the upper layers 530 * can process it. This is necessary for 5210 531 * parts which have no way to setup a ``clear'' 532 * key cache entry. 533 * 534 * XXX do key cache faulting 535 */ 536 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 537 goto rx_accept; 538 sc->sc_stats.ast_rx_badcrypt++; 539 } 540 if (rs->rs_status & HAL_RXERR_MIC) { 541 sc->sc_stats.ast_rx_badmic++; 542 /* 543 * Do minimal work required to hand off 544 * the 802.11 header for notification. 545 */ 546 /* XXX frag's and qos frames */ 547 len = rs->rs_datalen; 548 if (len >= sizeof (struct ieee80211_frame)) { 549 bus_dmamap_sync(sc->sc_dmat, 550 bf->bf_dmamap, 551 BUS_DMASYNC_POSTREAD); 552 ath_handle_micerror(ic, 553 mtod(m, struct ieee80211_frame *), 554 sc->sc_splitmic ? 555 rs->rs_keyix-32 : rs->rs_keyix); 556 } 557 } 558 ifp->if_ierrors++; 559rx_error: 560 /* 561 * Cleanup any pending partial frame. 562 */ 563 if (re->m_rxpending != NULL) { 564 m_freem(re->m_rxpending); 565 re->m_rxpending = NULL; 566 } 567 /* 568 * When a tap is present pass error frames 569 * that have been requested. By default we 570 * pass decrypt+mic errors but others may be 571 * interesting (e.g. crc). 572 */ 573 if (ieee80211_radiotap_active(ic) && 574 (rs->rs_status & sc->sc_monpass)) { 575 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 576 BUS_DMASYNC_POSTREAD); 577 /* NB: bpf needs the mbuf length setup */ 578 len = rs->rs_datalen; 579 m->m_pkthdr.len = m->m_len = len; 580 bf->bf_m = NULL; 581 ath_rx_tap(ifp, m, rs, rstamp, nf); 582#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 583 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 584#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 585 ieee80211_radiotap_rx_all(ic, m); 586 m_freem(m); 587 } 588 /* XXX pass MIC errors up for s/w reclaculation */ 589 goto rx_next; 590 } 591rx_accept: 592 /* 593 * Sync and unmap the frame. At this point we're 594 * committed to passing the mbuf somewhere so clear 595 * bf_m; this means a new mbuf must be allocated 596 * when the rx descriptor is setup again to receive 597 * another frame. 598 */ 599 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 600 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 601 bf->bf_m = NULL; 602 603 len = rs->rs_datalen; 604 m->m_len = len; 605 606 if (rs->rs_more) { 607 /* 608 * Frame spans multiple descriptors; save 609 * it for the next completed descriptor, it 610 * will be used to construct a jumbogram. 611 */ 612 if (re->m_rxpending != NULL) { 613 /* NB: max frame size is currently 2 clusters */ 614 sc->sc_stats.ast_rx_toobig++; 615 m_freem(re->m_rxpending); 616 } 617 m->m_pkthdr.rcvif = ifp; 618 m->m_pkthdr.len = len; 619 re->m_rxpending = m; 620 goto rx_next; 621 } else if (re->m_rxpending != NULL) { 622 /* 623 * This is the second part of a jumbogram, 624 * chain it to the first mbuf, adjust the 625 * frame length, and clear the rxpending state. 626 */ 627 re->m_rxpending->m_next = m; 628 re->m_rxpending->m_pkthdr.len += len; 629 m = re->m_rxpending; 630 re->m_rxpending = NULL; 631 } else { 632 /* 633 * Normal single-descriptor receive; setup 634 * the rcvif and packet length. 635 */ 636 m->m_pkthdr.rcvif = ifp; 637 m->m_pkthdr.len = len; 638 } 639 640 /* 641 * Validate rs->rs_antenna. 642 * 643 * Some users w/ AR9285 NICs have reported crashes 644 * here because rs_antenna field is bogusly large. 645 * Let's enforce the maximum antenna limit of 8 646 * (and it shouldn't be hard coded, but that's a 647 * separate problem) and if there's an issue, print 648 * out an error and adjust rs_antenna to something 649 * sensible. 650 * 651 * This code should be removed once the actual 652 * root cause of the issue has been identified. 653 * For example, it may be that the rs_antenna 654 * field is only valid for the lsat frame of 655 * an aggregate and it just happens that it is 656 * "mostly" right. (This is a general statement - 657 * the majority of the statistics are only valid 658 * for the last frame in an aggregate. 659 */ 660 if (rs->rs_antenna > 7) { 661 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 662 __func__, rs->rs_antenna); 663#ifdef ATH_DEBUG 664 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 665#endif /* ATH_DEBUG */ 666 rs->rs_antenna = 0; /* XXX better than nothing */ 667 } 668 669 ifp->if_ipackets++; 670 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 671 672 /* 673 * Populate the rx status block. When there are bpf 674 * listeners we do the additional work to provide 675 * complete status. Otherwise we fill in only the 676 * material required by ieee80211_input. Note that 677 * noise setting is filled in above. 678 */ 679 if (ieee80211_radiotap_active(ic)) { 680 ath_rx_tap(ifp, m, rs, rstamp, nf); 681#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 682 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 683#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 684 } 685 686 /* 687 * From this point on we assume the frame is at least 688 * as large as ieee80211_frame_min; verify that. 689 */ 690 if (len < IEEE80211_MIN_LEN) { 691 if (!ieee80211_radiotap_active(ic)) { 692 DPRINTF(sc, ATH_DEBUG_RECV, 693 "%s: short packet %d\n", __func__, len); 694 sc->sc_stats.ast_rx_tooshort++; 695 } else { 696 /* NB: in particular this captures ack's */ 697 ieee80211_radiotap_rx_all(ic, m); 698 } 699 m_freem(m); 700 goto rx_next; 701 } 702 703 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 704 const HAL_RATE_TABLE *rt = sc->sc_currates; 705 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 706 707 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 708 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 709 } 710 711 m_adj(m, -IEEE80211_CRC_LEN); 712 713 /* 714 * Locate the node for sender, track state, and then 715 * pass the (referenced) node up to the 802.11 layer 716 * for its use. 717 */ 718 ni = ieee80211_find_rxnode_withkey(ic, 719 mtod(m, const struct ieee80211_frame_min *), 720 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 721 IEEE80211_KEYIX_NONE : rs->rs_keyix); 722 sc->sc_lastrs = rs; 723 724#ifdef AH_SUPPORT_AR5416 725 if (rs->rs_isaggr) 726 sc->sc_stats.ast_rx_agg++; 727#endif /* AH_SUPPORT_AR5416 */ 728 729 if (ni != NULL) { 730 /* 731 * Only punt packets for ampdu reorder processing for 732 * 11n nodes; net80211 enforces that M_AMPDU is only 733 * set for 11n nodes. 734 */ 735 if (ni->ni_flags & IEEE80211_NODE_HT) 736 m->m_flags |= M_AMPDU; 737 738 /* 739 * Sending station is known, dispatch directly. 740 */ 741 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 742 ieee80211_free_node(ni); 743 /* 744 * Arrange to update the last rx timestamp only for 745 * frames from our ap when operating in station mode. 746 * This assumes the rx key is always setup when 747 * associated. 748 */ 749 if (ic->ic_opmode == IEEE80211_M_STA && 750 rs->rs_keyix != HAL_RXKEYIX_INVALID) 751 is_good = 1; 752 } else { 753 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 754 } 755 /* 756 * Track rx rssi and do any rx antenna management. 757 */ 758 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 759 if (sc->sc_diversity) { 760 /* 761 * When using fast diversity, change the default rx 762 * antenna if diversity chooses the other antenna 3 763 * times in a row. 764 */ 765 if (sc->sc_defant != rs->rs_antenna) { 766 if (++sc->sc_rxotherant >= 3) 767 ath_setdefantenna(sc, rs->rs_antenna); 768 } else 769 sc->sc_rxotherant = 0; 770 } 771 772 /* Newer school diversity - kite specific for now */ 773 /* XXX perhaps migrate the normal diversity code to this? */ 774 if ((ah)->ah_rxAntCombDiversity) 775 (*(ah)->ah_rxAntCombDiversity)(ah, rs, ticks, hz); 776 777 if (sc->sc_softled) { 778 /* 779 * Blink for any data frame. Otherwise do a 780 * heartbeat-style blink when idle. The latter 781 * is mainly for station mode where we depend on 782 * periodic beacon frames to trigger the poll event. 783 */ 784 if (type == IEEE80211_FC0_TYPE_DATA) { 785 const HAL_RATE_TABLE *rt = sc->sc_currates; 786 ath_led_event(sc, 787 rt->rateCodeToIndex[rs->rs_rate]); 788 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 789 ath_led_event(sc, 0); 790 } 791rx_next: 792 return (is_good); 793} 794 795static void 796ath_rx_proc(struct ath_softc *sc, int resched) 797{ 798#define PA2DESC(_sc, _pa) \ 799 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 800 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 801 struct ath_buf *bf; 802 struct ifnet *ifp = sc->sc_ifp; 803 struct ath_hal *ah = sc->sc_ah; 804#ifdef IEEE80211_SUPPORT_SUPERG 805 struct ieee80211com *ic = ifp->if_l2com; 806#endif 807 struct ath_desc *ds; 808 struct ath_rx_status *rs; 809 struct mbuf *m; 810 int ngood; 811 HAL_STATUS status; 812 int16_t nf; 813 u_int64_t tsf; 814 int npkts = 0; 815 816 /* XXX we must not hold the ATH_LOCK here */ 817 ATH_UNLOCK_ASSERT(sc); 818 ATH_PCU_UNLOCK_ASSERT(sc); 819 820 ATH_PCU_LOCK(sc); 821 sc->sc_rxproc_cnt++; 822 ATH_PCU_UNLOCK(sc); 823 824 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 825 ngood = 0; 826 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 827 sc->sc_stats.ast_rx_noise = nf; 828 tsf = ath_hal_gettsf64(ah); 829 do { 830 bf = TAILQ_FIRST(&sc->sc_rxbuf); 831 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 832 if_printf(ifp, "%s: no buffer!\n", __func__); 833 break; 834 } else if (bf == NULL) { 835 /* 836 * End of List: 837 * this can happen for non-self-linked RX chains 838 */ 839 sc->sc_stats.ast_rx_hitqueueend++; 840 break; 841 } 842 m = bf->bf_m; 843 if (m == NULL) { /* NB: shouldn't happen */ 844 /* 845 * If mbuf allocation failed previously there 846 * will be no mbuf; try again to re-populate it. 847 */ 848 /* XXX make debug msg */ 849 if_printf(ifp, "%s: no mbuf!\n", __func__); 850 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 851 goto rx_proc_next; 852 } 853 ds = bf->bf_desc; 854 if (ds->ds_link == bf->bf_daddr) { 855 /* NB: never process the self-linked entry at the end */ 856 sc->sc_stats.ast_rx_hitqueueend++; 857 break; 858 } 859 /* XXX sync descriptor memory */ 860 /* 861 * Must provide the virtual address of the current 862 * descriptor, the physical address, and the virtual 863 * address of the next descriptor in the h/w chain. 864 * This allows the HAL to look ahead to see if the 865 * hardware is done with a descriptor by checking the 866 * done bit in the following descriptor and the address 867 * of the current descriptor the DMA engine is working 868 * on. All this is necessary because of our use of 869 * a self-linked list to avoid rx overruns. 870 */ 871 rs = &bf->bf_status.ds_rxstat; 872 status = ath_hal_rxprocdesc(ah, ds, 873 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 874#ifdef ATH_DEBUG 875 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 876 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 877#endif 878 if (status == HAL_EINPROGRESS) 879 break; 880 881 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 882 npkts++; 883 884 /* 885 * Process a single frame. 886 */ 887 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf)) 888 ngood++; 889rx_proc_next: 890 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 891 } while (ath_rxbuf_init(sc, bf) == 0); 892 893 /* rx signal state monitoring */ 894 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 895 if (ngood) 896 sc->sc_lastrx = tsf; 897 898 CTR2(ATH_KTR_INTR, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 899 /* Queue DFS tasklet if needed */ 900 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 901 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 902 903 /* 904 * Now that all the RX frames were handled that 905 * need to be handled, kick the PCU if there's 906 * been an RXEOL condition. 907 */ 908 ATH_PCU_LOCK(sc); 909 if (resched && sc->sc_kickpcu) { 910 CTR0(ATH_KTR_ERR, "ath_rx_proc: kickpcu"); 911 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 912 __func__, npkts); 913 914 /* XXX rxslink? */ 915 /* 916 * XXX can we hold the PCU lock here? 917 * Are there any net80211 buffer calls involved? 918 */ 919 bf = TAILQ_FIRST(&sc->sc_rxbuf); 920 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 921 ath_hal_rxena(ah); /* enable recv descriptors */ 922 ath_mode_init(sc); /* set filters, etc. */ 923 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 924 925 ath_hal_intrset(ah, sc->sc_imask); 926 sc->sc_kickpcu = 0; 927 } 928 ATH_PCU_UNLOCK(sc); 929 930 /* XXX check this inside of IF_LOCK? */ 931 if (resched && (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 932#ifdef IEEE80211_SUPPORT_SUPERG 933 ieee80211_ff_age_all(ic, 100); 934#endif 935 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 936 ath_tx_kick(sc); 937 } 938#undef PA2DESC 939 940 ATH_PCU_LOCK(sc); 941 sc->sc_rxproc_cnt--; 942 ATH_PCU_UNLOCK(sc); 943} 944 945/* 946 * Only run the RX proc if it's not already running. 947 * Since this may get run as part of the reset/flush path, 948 * the task can't clash with an existing, running tasklet. 949 */ 950static void 951ath_legacy_rx_tasklet(void *arg, int npending) 952{ 953 struct ath_softc *sc = arg; 954 955 CTR1(ATH_KTR_INTR, "ath_rx_proc: pending=%d", npending); 956 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 957 ATH_PCU_LOCK(sc); 958 if (sc->sc_inreset_cnt > 0) { 959 device_printf(sc->sc_dev, 960 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 961 ATH_PCU_UNLOCK(sc); 962 return; 963 } 964 ATH_PCU_UNLOCK(sc); 965 966 ath_rx_proc(sc, 1); 967} 968 969static void 970ath_legacy_flushrecv(struct ath_softc *sc) 971{ 972 973 ath_rx_proc(sc, 0); 974} 975 976/* 977 * Disable the receive h/w in preparation for a reset. 978 */ 979static void 980ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 981{ 982#define PA2DESC(_sc, _pa) \ 983 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 984 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 985 struct ath_hal *ah = sc->sc_ah; 986 987 ath_hal_stoppcurecv(ah); /* disable PCU */ 988 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 989 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 990 /* 991 * TODO: see if this particular DELAY() is required; it may be 992 * masking some missing FIFO flush or DMA sync. 993 */ 994#if 0 995 if (dodelay) 996#endif 997 DELAY(3000); /* 3ms is long enough for 1 frame */ 998#ifdef ATH_DEBUG 999 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1000 struct ath_buf *bf; 1001 u_int ix; 1002 1003 device_printf(sc->sc_dev, 1004 "%s: rx queue %p, link %p\n", 1005 __func__, 1006 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1007 sc->sc_rxlink); 1008 ix = 0; 1009 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1010 struct ath_desc *ds = bf->bf_desc; 1011 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1012 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1013 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1014 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1015 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1016 ix++; 1017 } 1018 } 1019#endif 1020 /* 1021 * Free both high/low RX pending, just in case. 1022 */ 1023 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1024 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1025 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1026 } 1027 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1028 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1029 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1030 } 1031 sc->sc_rxlink = NULL; /* just in case */ 1032#undef PA2DESC 1033} 1034 1035/* 1036 * Enable the receive h/w following a reset. 1037 */ 1038static int 1039ath_legacy_startrecv(struct ath_softc *sc) 1040{ 1041 struct ath_hal *ah = sc->sc_ah; 1042 struct ath_buf *bf; 1043 1044 sc->sc_rxlink = NULL; 1045 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1046 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1047 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1048 int error = ath_rxbuf_init(sc, bf); 1049 if (error != 0) { 1050 DPRINTF(sc, ATH_DEBUG_RECV, 1051 "%s: ath_rxbuf_init failed %d\n", 1052 __func__, error); 1053 return error; 1054 } 1055 } 1056 1057 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1058 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1059 ath_hal_rxena(ah); /* enable recv descriptors */ 1060 ath_mode_init(sc); /* set filters, etc. */ 1061 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1062 return 0; 1063} 1064 1065static int 1066ath_legacy_dma_rxsetup(struct ath_softc *sc) 1067{ 1068 int error; 1069 1070 device_printf(sc->sc_dev, "%s: called\n", __func__); 1071 1072 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1073 "rx", ath_rxbuf, 1); 1074 if (error != 0) 1075 return (error); 1076 1077 return (0); 1078} 1079 1080static int 1081ath_legacy_dma_rxteardown(struct ath_softc *sc) 1082{ 1083 1084 device_printf(sc->sc_dev, "%s: called\n", __func__); 1085 1086 if (sc->sc_rxdma.dd_desc_len != 0) 1087 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1088 return (0); 1089} 1090 1091void 1092ath_recv_setup_legacy(struct ath_softc *sc) 1093{ 1094 1095 device_printf(sc->sc_dev, "DMA setup: legacy\n"); 1096 1097 sc->sc_rx.recv_start = ath_legacy_startrecv; 1098 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1099 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1100 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1101 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1102 1103 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1104 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1105} 1106