ar2133.c revision 219605
1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar2133.c 219605 2011-03-13 13:00:45Z adrian $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23
24#include "ah_eeprom_v14.h"
25
26#include "ar5416/ar5416.h"
27#include "ar5416/ar5416reg.h"
28#include "ar5416/ar5416phy.h"
29
30#define N(a)    (sizeof(a)/sizeof(a[0]))
31
32struct ar2133State {
33	RF_HAL_FUNCS	base;		/* public state, must be first */
34	uint16_t	pcdacTable[1];
35
36	uint32_t	*Bank0Data;
37	uint32_t	*Bank1Data;
38	uint32_t	*Bank2Data;
39	uint32_t	*Bank3Data;
40	uint32_t	*Bank6Data;
41	uint32_t	*Bank7Data;
42
43	/* NB: Bank*Data storage follows */
44};
45#define	AR2133(ah)	((struct ar2133State *) AH5212(ah)->ah_rfHal)
46
47#define	ar5416ModifyRfBuffer	ar5212ModifyRfBuffer	/*XXX*/
48
49void	ar5416ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
50	    uint32_t numBits, uint32_t firstBit, uint32_t column);
51
52static void
53ar2133WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
54	int writes)
55{
56	(void) ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_bb_rfgain,
57		freqIndex, writes);
58}
59
60/*
61 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
62 * rf_pwd_icsyndiv.
63 *
64 * Theoretical Rules:
65 *   if 2 GHz band
66 *      if forceBiasAuto
67 *         if synth_freq < 2412
68 *            bias = 0
69 *         else if 2412 <= synth_freq <= 2422
70 *            bias = 1
71 *         else // synth_freq > 2422
72 *            bias = 2
73 *      else if forceBias > 0
74 *         bias = forceBias & 7
75 *      else
76 *         no change, use value from ini file
77 *   else
78 *      no change, invalid band
79 *
80 *  1st Mod:
81 *    2422 also uses value of 2
82 *    <approved>
83 *
84 *  2nd Mod:
85 *    Less than 2412 uses value of 0, 2412 and above uses value of 2
86 */
87static void
88ar2133ForceBias(struct ath_hal *ah, uint16_t synth_freq)
89{
90        uint32_t tmp_reg;
91        int reg_writes = 0;
92        uint32_t new_bias = 0;
93	struct ar2133State *priv = AR2133(ah);
94
95	/* XXX this is a bit of a silly check for 2.4ghz channels -adrian */
96        if (synth_freq >= 3000)
97                return;
98
99        if (synth_freq < 2412)
100                new_bias = 0;
101        else if (synth_freq < 2422)
102                new_bias = 1;
103        else
104                new_bias = 2;
105
106        /* pre-reverse this field */
107        tmp_reg = ath_hal_reverseBits(new_bias, 3);
108
109        HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Force rf_pwd_icsyndiv to %1d on %4d\n",
110                  __func__, new_bias, synth_freq);
111
112        /* swizzle rf_pwd_icsyndiv */
113        ar5416ModifyRfBuffer(priv->Bank6Data, tmp_reg, 3, 181, 3);
114
115        /* write Bank 6 with new params */
116        ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank6, priv->Bank6Data, reg_writes);
117}
118
119/*
120 * Take the MHz channel value and set the Channel value
121 *
122 * ASSUMES: Writes enabled to analog bus
123 */
124static HAL_BOOL
125ar2133SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
126{
127	uint32_t channelSel  = 0;
128	uint32_t bModeSynth  = 0;
129	uint32_t aModeRefSel = 0;
130	uint32_t reg32       = 0;
131	uint16_t freq;
132	CHAN_CENTERS centers;
133
134	OS_MARK(ah, AH_MARK_SETCHANNEL, chan->ic_freq);
135
136	ar5416GetChannelCenters(ah, chan, &centers);
137	freq = centers.synth_center;
138
139	if (freq < 4800) {
140		uint32_t txctl;
141
142		if (((freq - 2192) % 5) == 0) {
143			channelSel = ((freq - 672) * 2 - 3040)/10;
144			bModeSynth = 0;
145		} else if (((freq - 2224) % 5) == 0) {
146			channelSel = ((freq - 704) * 2 - 3040) / 10;
147			bModeSynth = 1;
148		} else {
149			HALDEBUG(ah, HAL_DEBUG_ANY,
150			    "%s: invalid channel %u MHz\n", __func__, freq);
151			return AH_FALSE;
152		}
153
154		channelSel = (channelSel << 2) & 0xff;
155		channelSel = ath_hal_reverseBits(channelSel, 8);
156
157		txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
158		if (freq == 2484) {
159			/* Enable channel spreading for channel 14 */
160			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
161				txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
162		} else {
163			OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
164 			txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
165		}
166	} else if ((freq % 20) == 0 && freq >= 5120) {
167		channelSel = ath_hal_reverseBits(((freq - 4800) / 20 << 2), 8);
168		if (AR_SREV_SOWL_10_OR_LATER(ah))
169			aModeRefSel = ath_hal_reverseBits(3, 2);
170		else
171			aModeRefSel = ath_hal_reverseBits(1, 2);
172	} else if ((freq % 10) == 0) {
173		channelSel = ath_hal_reverseBits(((freq - 4800) / 10 << 1), 8);
174		if (AR_SREV_SOWL_10_OR_LATER(ah))
175			aModeRefSel = ath_hal_reverseBits(2, 2);
176		else
177			aModeRefSel = ath_hal_reverseBits(1, 2);
178	} else if ((freq % 5) == 0) {
179		channelSel = ath_hal_reverseBits((freq - 4800) / 5, 8);
180		aModeRefSel = ath_hal_reverseBits(1, 2);
181	} else {
182		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
183		    __func__, freq);
184		return AH_FALSE;
185	}
186
187	/* Workaround for hw bug - AR5416 specific */
188	if (AR_SREV_OWL(ah))
189		ar2133ForceBias(ah, freq);
190
191	reg32 = (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
192		(1 << 5) | 0x1;
193
194	OS_REG_WRITE(ah, AR_PHY(0x37), reg32);
195
196	AH_PRIVATE(ah)->ah_curchan = chan;
197	return AH_TRUE;
198
199}
200
201/*
202 * Return a reference to the requested RF Bank.
203 */
204static uint32_t *
205ar2133GetRfBank(struct ath_hal *ah, int bank)
206{
207	struct ar2133State *priv = AR2133(ah);
208
209	HALASSERT(priv != AH_NULL);
210	switch (bank) {
211	case 1: return priv->Bank1Data;
212	case 2: return priv->Bank2Data;
213	case 3: return priv->Bank3Data;
214	case 6: return priv->Bank6Data;
215	case 7: return priv->Bank7Data;
216	}
217	HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
218	    __func__, bank);
219	return AH_NULL;
220}
221
222/*
223 * Reads EEPROM header info from device structure and programs
224 * all rf registers
225 *
226 * REQUIRES: Access to the analog rf device
227 */
228static HAL_BOOL
229ar2133SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
230                uint16_t modesIndex, uint16_t *rfXpdGain)
231{
232	struct ar2133State *priv = AR2133(ah);
233	int writes;
234
235	HALASSERT(priv);
236
237	/* Setup Bank 0 Write */
238	ath_hal_ini_bank_setup(priv->Bank0Data, &AH5416(ah)->ah_ini_bank0, 1);
239
240	/* Setup Bank 1 Write */
241	ath_hal_ini_bank_setup(priv->Bank1Data, &AH5416(ah)->ah_ini_bank1, 1);
242
243	/* Setup Bank 2 Write */
244	ath_hal_ini_bank_setup(priv->Bank2Data, &AH5416(ah)->ah_ini_bank2, 1);
245
246	/* Setup Bank 3 Write */
247	ath_hal_ini_bank_setup(priv->Bank3Data, &AH5416(ah)->ah_ini_bank3, modesIndex);
248
249	/* Setup Bank 6 Write */
250	ath_hal_ini_bank_setup(priv->Bank6Data, &AH5416(ah)->ah_ini_bank6, modesIndex);
251
252	/* Only the 5 or 2 GHz OB/DB need to be set for a mode */
253	if (IEEE80211_IS_CHAN_2GHZ(chan)) {
254		ar5416ModifyRfBuffer(priv->Bank6Data,
255		    ath_hal_eepromGet(ah, AR_EEP_OB_2, AH_NULL), 3, 197, 0);
256		ar5416ModifyRfBuffer(priv->Bank6Data,
257		    ath_hal_eepromGet(ah, AR_EEP_DB_2, AH_NULL), 3, 194, 0);
258	} else {
259		ar5416ModifyRfBuffer(priv->Bank6Data,
260		    ath_hal_eepromGet(ah, AR_EEP_OB_5, AH_NULL), 3, 203, 0);
261		ar5416ModifyRfBuffer(priv->Bank6Data,
262		    ath_hal_eepromGet(ah, AR_EEP_DB_5, AH_NULL), 3, 200, 0);
263	}
264	/* Setup Bank 7 Setup */
265	ath_hal_ini_bank_setup(priv->Bank7Data, &AH5416(ah)->ah_ini_bank7, 1);
266
267	/* Write Analog registers */
268	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank0,
269	    priv->Bank0Data, 0);
270	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank1,
271	    priv->Bank1Data, writes);
272	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank2,
273	    priv->Bank2Data, writes);
274	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank3,
275	    priv->Bank3Data, writes);
276	writes = ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank6,
277	    priv->Bank6Data, writes);
278	(void) ath_hal_ini_bank_write(ah, &AH5416(ah)->ah_ini_bank7,
279	    priv->Bank7Data, writes);
280
281	return AH_TRUE;
282#undef  RF_BANK_SETUP
283}
284
285/*
286 * Read the transmit power levels from the structures taken from EEPROM
287 * Interpolate read transmit power values for this channel
288 * Organize the transmit power values into a table for writing into the hardware
289 */
290
291static HAL_BOOL
292ar2133SetPowerTable(struct ath_hal *ah, int16_t *pPowerMin, int16_t *pPowerMax,
293	const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
294{
295	return AH_TRUE;
296}
297
298#if 0
299static int16_t
300ar2133GetMinPower(struct ath_hal *ah, EXPN_DATA_PER_CHANNEL_5112 *data)
301{
302    int i, minIndex;
303    int16_t minGain,minPwr,minPcdac,retVal;
304
305    /* Assume NUM_POINTS_XPD0 > 0 */
306    minGain = data->pDataPerXPD[0].xpd_gain;
307    for (minIndex=0,i=1; i<NUM_XPD_PER_CHANNEL; i++) {
308        if (data->pDataPerXPD[i].xpd_gain < minGain) {
309            minIndex = i;
310            minGain = data->pDataPerXPD[i].xpd_gain;
311        }
312    }
313    minPwr = data->pDataPerXPD[minIndex].pwr_t4[0];
314    minPcdac = data->pDataPerXPD[minIndex].pcdac[0];
315    for (i=1; i<NUM_POINTS_XPD0; i++) {
316        if (data->pDataPerXPD[minIndex].pwr_t4[i] < minPwr) {
317            minPwr = data->pDataPerXPD[minIndex].pwr_t4[i];
318            minPcdac = data->pDataPerXPD[minIndex].pcdac[i];
319        }
320    }
321    retVal = minPwr - (minPcdac*2);
322    return(retVal);
323}
324#endif
325
326static HAL_BOOL
327ar2133GetChannelMaxMinPower(struct ath_hal *ah,
328	const struct ieee80211_channel *chan,
329	int16_t *maxPow, int16_t *minPow)
330{
331#if 0
332    struct ath_hal_5212 *ahp = AH5212(ah);
333    int numChannels=0,i,last;
334    int totalD, totalF,totalMin;
335    EXPN_DATA_PER_CHANNEL_5112 *data=AH_NULL;
336    EEPROM_POWER_EXPN_5112 *powerArray=AH_NULL;
337
338    *maxPow = 0;
339    if (IS_CHAN_A(chan)) {
340        powerArray = ahp->ah_modePowerArray5112;
341        data = powerArray[headerInfo11A].pDataPerChannel;
342        numChannels = powerArray[headerInfo11A].numChannels;
343    } else if (IS_CHAN_G(chan) || IS_CHAN_108G(chan)) {
344        /* XXX - is this correct? Should we also use the same power for turbo G? */
345        powerArray = ahp->ah_modePowerArray5112;
346        data = powerArray[headerInfo11G].pDataPerChannel;
347        numChannels = powerArray[headerInfo11G].numChannels;
348    } else if (IS_CHAN_B(chan)) {
349        powerArray = ahp->ah_modePowerArray5112;
350        data = powerArray[headerInfo11B].pDataPerChannel;
351        numChannels = powerArray[headerInfo11B].numChannels;
352    } else {
353        return (AH_TRUE);
354    }
355    /* Make sure the channel is in the range of the TP values
356     *  (freq piers)
357     */
358    if ((numChannels < 1) ||
359        (chan->channel < data[0].channelValue) ||
360        (chan->channel > data[numChannels-1].channelValue))
361        return(AH_FALSE);
362
363    /* Linearly interpolate the power value now */
364    for (last=0,i=0;
365         (i<numChannels) && (chan->channel > data[i].channelValue);
366         last=i++);
367    totalD = data[i].channelValue - data[last].channelValue;
368    if (totalD > 0) {
369        totalF = data[i].maxPower_t4 - data[last].maxPower_t4;
370        *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) + data[last].maxPower_t4*totalD)/totalD);
371
372        totalMin = ar2133GetMinPower(ah,&data[i]) - ar2133GetMinPower(ah, &data[last]);
373        *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) + ar2133GetMinPower(ah, &data[last])*totalD)/totalD);
374        return (AH_TRUE);
375    } else {
376        if (chan->channel == data[i].channelValue) {
377            *maxPow = data[i].maxPower_t4;
378            *minPow = ar2133GetMinPower(ah, &data[i]);
379            return(AH_TRUE);
380        } else
381            return(AH_FALSE);
382    }
383#else
384    *maxPow = *minPow = 0;
385	return AH_FALSE;
386#endif
387}
388
389/*
390 * The ordering of nfarray is thus:
391 *
392 * nfarray[0]:	Chain 0 ctl
393 * nfarray[1]:	Chain 1 ctl
394 * nfarray[2]:	Chain 2 ctl
395 * nfarray[3]:	Chain 0 ext
396 * nfarray[4]:	Chain 1 ext
397 * nfarray[5]:	Chain 2 ext
398 */
399static void
400ar2133GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[])
401{
402	struct ath_hal_5416 *ahp = AH5416(ah);
403	int16_t nf;
404
405	/*
406	 * Blank nf array - some chips may only
407	 * have one or two RX chainmasks enabled.
408	 */
409	nfarray[0] = nfarray[1] = nfarray[2] = 0;
410	nfarray[3] = nfarray[4] = nfarray[5] = 0;
411
412	switch (ahp->ah_rx_chainmask) {
413        case 0x7:
414		nf = MS(OS_REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
415		if (nf & 0x100)
416			nf = 0 - ((nf ^ 0x1ff) + 1);
417		HALDEBUG(ah, HAL_DEBUG_NFCAL,
418		    "NF calibrated [ctl] [chain 2] is %d\n", nf);
419		nfarray[2] = nf;
420
421		nf = MS(OS_REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
422		if (nf & 0x100)
423			nf = 0 - ((nf ^ 0x1ff) + 1);
424		HALDEBUG(ah, HAL_DEBUG_NFCAL,
425		    "NF calibrated [ext] [chain 2] is %d\n", nf);
426		nfarray[5] = nf;
427		/* fall thru... */
428        case 0x3:
429        case 0x5:
430		nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
431		if (nf & 0x100)
432			nf = 0 - ((nf ^ 0x1ff) + 1);
433		HALDEBUG(ah, HAL_DEBUG_NFCAL,
434		    "NF calibrated [ctl] [chain 1] is %d\n", nf);
435		nfarray[1] = nf;
436
437
438		nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
439		if (nf & 0x100)
440			nf = 0 - ((nf ^ 0x1ff) + 1);
441		HALDEBUG(ah, HAL_DEBUG_NFCAL,
442		    "NF calibrated [ext] [chain 1] is %d\n", nf);
443		nfarray[4] = nf;
444		/* fall thru... */
445        case 0x1:
446		nf = MS(OS_REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
447		if (nf & 0x100)
448			nf = 0 - ((nf ^ 0x1ff) + 1);
449		HALDEBUG(ah, HAL_DEBUG_NFCAL,
450		    "NF calibrated [ctl] [chain 0] is %d\n", nf);
451		nfarray[0] = nf;
452
453		nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
454		if (nf & 0x100)
455			nf = 0 - ((nf ^ 0x1ff) + 1);
456		HALDEBUG(ah, HAL_DEBUG_NFCAL,
457		    "NF calibrated [ext] [chain 0] is %d\n", nf);
458		nfarray[3] = nf;
459
460		break;
461	}
462}
463
464/*
465 * Adjust NF based on statistical values for 5GHz frequencies.
466 * Stubbed:Not used by Fowl
467 */
468static int16_t
469ar2133GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
470{
471	return 0;
472}
473
474/*
475 * Free memory for analog bank scratch buffers
476 */
477static void
478ar2133RfDetach(struct ath_hal *ah)
479{
480	struct ath_hal_5212 *ahp = AH5212(ah);
481
482	HALASSERT(ahp->ah_rfHal != AH_NULL);
483	ath_hal_free(ahp->ah_rfHal);
484	ahp->ah_rfHal = AH_NULL;
485}
486
487/*
488 * Allocate memory for analog bank scratch buffers
489 * Scratch Buffer will be reinitialized every reset so no need to zero now
490 */
491HAL_BOOL
492ar2133RfAttach(struct ath_hal *ah, HAL_STATUS *status)
493{
494	struct ath_hal_5212 *ahp = AH5212(ah);
495	struct ar2133State *priv;
496	uint32_t *bankData;
497
498	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: attach AR2133 radio\n", __func__);
499
500	HALASSERT(ahp->ah_rfHal == AH_NULL);
501	priv = ath_hal_malloc(sizeof(struct ar2133State)
502	    + AH5416(ah)->ah_ini_bank0.rows * sizeof(uint32_t)
503	    + AH5416(ah)->ah_ini_bank1.rows * sizeof(uint32_t)
504	    + AH5416(ah)->ah_ini_bank2.rows * sizeof(uint32_t)
505	    + AH5416(ah)->ah_ini_bank3.rows * sizeof(uint32_t)
506	    + AH5416(ah)->ah_ini_bank6.rows * sizeof(uint32_t)
507	    + AH5416(ah)->ah_ini_bank7.rows * sizeof(uint32_t)
508	);
509	if (priv == AH_NULL) {
510		HALDEBUG(ah, HAL_DEBUG_ANY,
511		    "%s: cannot allocate private state\n", __func__);
512		*status = HAL_ENOMEM;		/* XXX */
513		return AH_FALSE;
514	}
515	priv->base.rfDetach		= ar2133RfDetach;
516	priv->base.writeRegs		= ar2133WriteRegs;
517	priv->base.getRfBank		= ar2133GetRfBank;
518	priv->base.setChannel		= ar2133SetChannel;
519	priv->base.setRfRegs		= ar2133SetRfRegs;
520	priv->base.setPowerTable	= ar2133SetPowerTable;
521	priv->base.getChannelMaxMinPower = ar2133GetChannelMaxMinPower;
522	priv->base.getNfAdjust		= ar2133GetNfAdjust;
523
524	bankData = (uint32_t *) &priv[1];
525	priv->Bank0Data = bankData, bankData += AH5416(ah)->ah_ini_bank0.rows;
526	priv->Bank1Data = bankData, bankData += AH5416(ah)->ah_ini_bank1.rows;
527	priv->Bank2Data = bankData, bankData += AH5416(ah)->ah_ini_bank2.rows;
528	priv->Bank3Data = bankData, bankData += AH5416(ah)->ah_ini_bank3.rows;
529	priv->Bank6Data = bankData, bankData += AH5416(ah)->ah_ini_bank6.rows;
530	priv->Bank7Data = bankData, bankData += AH5416(ah)->ah_ini_bank7.rows;
531
532	ahp->ah_pcdacTable = priv->pcdacTable;
533	ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
534	ahp->ah_rfHal = &priv->base;
535	/*
536	 * Set noise floor adjust method; we arrange a
537	 * direct call instead of thunking.
538	 */
539	AH_PRIVATE(ah)->ah_getNfAdjust = priv->base.getNfAdjust;
540	AH_PRIVATE(ah)->ah_getNoiseFloor = ar2133GetNoiseFloor;
541
542	return AH_TRUE;
543}
544