ar5212_reset.c revision 188011
1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187611Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c 188011 2009-02-02 16:55:57Z sam $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25185377Ssam#include "ar5212/ar5212.h" 26185377Ssam#include "ar5212/ar5212reg.h" 27185377Ssam#include "ar5212/ar5212phy.h" 28185377Ssam 29185377Ssam#include "ah_eeprom_v3.h" 30185377Ssam 31185377Ssam/* Additional Time delay to wait after activiting the Base band */ 32185377Ssam#define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 33185377Ssam#define PLL_SETTLE_DELAY 300 /* 300 usec */ 34185377Ssam 35185377Ssamstatic HAL_BOOL ar5212SetResetReg(struct ath_hal *, uint32_t resetMask); 36185377Ssam/* NB: public for 5312 use */ 37187831SsamHAL_BOOL ar5212IsSpurChannel(struct ath_hal *, 38187831Ssam const struct ieee80211_channel *); 39187831SsamHAL_BOOL ar5212ChannelChange(struct ath_hal *, 40187831Ssam const struct ieee80211_channel *); 41187831Ssamint16_t ar5212GetNf(struct ath_hal *, struct ieee80211_channel *); 42187831SsamHAL_BOOL ar5212SetBoardValues(struct ath_hal *, 43187831Ssam const struct ieee80211_channel *); 44187831Ssamvoid ar5212SetDeltaSlope(struct ath_hal *, 45187831Ssam const struct ieee80211_channel *); 46185377SsamHAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah, 47187831Ssam const struct ieee80211_channel *chan, uint16_t *rfXpdGain); 48185377Ssamstatic HAL_BOOL ar5212SetRateTable(struct ath_hal *, 49187831Ssam const struct ieee80211_channel *, int16_t tpcScaleReduction, 50187831Ssam int16_t powerLimit, 51185380Ssam HAL_BOOL commit, int16_t *minPower, int16_t *maxPower); 52185377Ssamstatic void ar5212CorrectGainDelta(struct ath_hal *, int twiceOfdmCckDelta); 53187831Ssamstatic void ar5212GetTargetPowers(struct ath_hal *, 54187831Ssam const struct ieee80211_channel *, 55185380Ssam const TRGT_POWER_INFO *pPowerInfo, uint16_t numChannels, 56185380Ssam TRGT_POWER_INFO *pNewPower); 57185377Ssamstatic uint16_t ar5212GetMaxEdgePower(uint16_t channel, 58185380Ssam const RD_EDGES_POWER *pRdEdgesPower); 59187831Ssamvoid ar5212SetRateDurationTable(struct ath_hal *, 60187831Ssam const struct ieee80211_channel *); 61187831Ssamvoid ar5212SetIFSTiming(struct ath_hal *, 62187831Ssam const struct ieee80211_channel *); 63185377Ssam 64185377Ssam/* NB: public for RF backend use */ 65185380Ssamvoid ar5212GetLowerUpperValues(uint16_t value, 66185380Ssam uint16_t *pList, uint16_t listSize, 67185380Ssam uint16_t *pLowerValue, uint16_t *pUpperValue); 68185380Ssamvoid ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, 69185380Ssam uint32_t numBits, uint32_t firstBit, uint32_t column); 70185377Ssam 71185377Ssamstatic int 72185377Ssamwrite_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia, 73185377Ssam HAL_BOOL bChannelChange, int writes) 74185377Ssam{ 75185377Ssam#define IS_NO_RESET_TIMER_ADDR(x) \ 76185377Ssam ( (((x) >= AR_BEACON) && ((x) <= AR_CFP_DUR)) || \ 77185377Ssam (((x) >= AR_SLEEP1) && ((x) <= AR_SLEEP3))) 78185377Ssam#define V(r, c) (ia)->data[((r)*(ia)->cols) + (c)] 79185377Ssam int r; 80185377Ssam 81185377Ssam /* Write Common Array Parameters */ 82185377Ssam for (r = 0; r < ia->rows; r++) { 83185377Ssam uint32_t reg = V(r, 0); 84185377Ssam /* XXX timer/beacon setup registers? */ 85185377Ssam /* On channel change, don't reset the PCU registers */ 86185377Ssam if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) { 87185377Ssam OS_REG_WRITE(ah, reg, V(r, 1)); 88185377Ssam DMA_YIELD(writes); 89185377Ssam } 90185377Ssam } 91185377Ssam return writes; 92185377Ssam#undef IS_NO_RESET_TIMER_ADDR 93185377Ssam#undef V 94185377Ssam} 95185377Ssam 96185377Ssam#define IS_DISABLE_FAST_ADC_CHAN(x) (((x) == 2462) || ((x) == 2467)) 97185377Ssam 98185377Ssam/* 99185377Ssam * Places the device in and out of reset and then places sane 100185377Ssam * values in the registers based on EEPROM config, initialization 101185377Ssam * vectors (as determined by the mode), and station configuration 102185377Ssam * 103185377Ssam * bChannelChange is used to preserve DMA/PCU registers across 104185377Ssam * a HW Reset during channel change. 105185377Ssam */ 106185377SsamHAL_BOOL 107185377Ssamar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 108187831Ssam struct ieee80211_channel *chan, 109187831Ssam HAL_BOOL bChannelChange, HAL_STATUS *status) 110185377Ssam{ 111185377Ssam#define N(a) (sizeof (a) / sizeof (a[0])) 112185377Ssam#define FAIL(_code) do { ecode = _code; goto bad; } while (0) 113185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 114185377Ssam HAL_CHANNEL_INTERNAL *ichan = AH_NULL; 115185377Ssam const HAL_EEPROM *ee; 116185377Ssam uint32_t softLedCfg, softLedState; 117185377Ssam uint32_t saveFrameSeqCount, saveDefAntenna, saveLedState; 118185377Ssam uint32_t macStaId1, synthDelay, txFrm2TxDStart; 119185377Ssam uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 120185377Ssam int16_t cckOfdmPwrDelta = 0; 121185377Ssam u_int modesIndex, freqIndex; 122185377Ssam HAL_STATUS ecode; 123185377Ssam int i, regWrites; 124185377Ssam uint32_t testReg, powerVal; 125185377Ssam int8_t twiceAntennaGain, twiceAntennaReduction; 126185377Ssam uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow; 127185377Ssam HAL_BOOL isBmode = AH_FALSE; 128185377Ssam 129185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 130185377Ssam ee = AH_PRIVATE(ah)->ah_eeprom; 131185377Ssam 132185377Ssam OS_MARK(ah, AH_MARK_RESET, bChannelChange); 133185377Ssam 134185377Ssam /* Bring out of sleep mode */ 135185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 136185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n", 137185377Ssam __func__); 138185377Ssam FAIL(HAL_EIO); 139185377Ssam } 140185377Ssam 141185377Ssam /* 142185377Ssam * Map public channel to private. 143185377Ssam */ 144185377Ssam ichan = ath_hal_checkchannel(ah, chan); 145187831Ssam if (ichan == AH_NULL) 146185377Ssam FAIL(HAL_EINVAL); 147185377Ssam switch (opmode) { 148185377Ssam case HAL_M_STA: 149185377Ssam case HAL_M_IBSS: 150185377Ssam case HAL_M_HOSTAP: 151185377Ssam case HAL_M_MONITOR: 152185377Ssam break; 153185377Ssam default: 154185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", 155185377Ssam __func__, opmode); 156185377Ssam FAIL(HAL_EINVAL); 157185377Ssam break; 158185377Ssam } 159185377Ssam HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER3); 160185377Ssam 161185377Ssam SAVE_CCK(ah, chan, isBmode); 162185377Ssam 163185377Ssam /* Preserve certain DMA hardware registers on a channel change */ 164185377Ssam if (bChannelChange) { 165185377Ssam /* 166185377Ssam * On Venice, the TSF is almost preserved across a reset; 167185377Ssam * it requires doubling writes to the RESET_TSF 168185377Ssam * bit in the AR_BEACON register; it also has the quirk 169185377Ssam * of the TSF going back in time on the station (station 170185377Ssam * latches onto the last beacon's tsf during a reset 50% 171185377Ssam * of the times); the latter is not a problem for adhoc 172185377Ssam * stations since as long as the TSF is behind, it will 173185377Ssam * get resynchronized on receiving the next beacon; the 174185377Ssam * TSF going backwards in time could be a problem for the 175185377Ssam * sleep operation (supported on infrastructure stations 176185377Ssam * only) - the best and most general fix for this situation 177185377Ssam * is to resynchronize the various sleep/beacon timers on 178185377Ssam * the receipt of the next beacon i.e. when the TSF itself 179185377Ssam * gets resynchronized to the AP's TSF - power save is 180185377Ssam * needed to be temporarily disabled until that time 181185377Ssam * 182185377Ssam * Need to save the sequence number to restore it after 183185377Ssam * the reset! 184185377Ssam */ 185185377Ssam saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM); 186185377Ssam } else 187185377Ssam saveFrameSeqCount = 0; /* NB: silence compiler */ 188185377Ssam#if 0 189185377Ssam /* 190185377Ssam * XXX disable for now; this appears to sometimes cause OFDM 191185377Ssam * XXX timing error floods when ani is enabled and bg scanning 192185377Ssam * XXX kicks in 193185377Ssam */ 194185377Ssam /* If the channel change is across the same mode - perform a fast channel change */ 195185377Ssam if (IS_2413(ah) || IS_5413(ah)) { 196185377Ssam /* 197185377Ssam * Fast channel change can only be used when: 198185377Ssam * -channel change requested - so it's not the initial reset. 199185377Ssam * -it's not a change to the current channel - 200185377Ssam * often called when switching modes on a channel 201185377Ssam * -the modes of the previous and requested channel are the 202185377Ssam * same 203185377Ssam * XXX opmode shouldn't change either? 204185377Ssam */ 205185377Ssam if (bChannelChange && 206185377Ssam (AH_PRIVATE(ah)->ah_curchan != AH_NULL) && 207187831Ssam (chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) && 208187831Ssam ((chan->ic_flags & IEEE80211_CHAN_ALLTURBO) == 209187831Ssam (AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) { 210185377Ssam if (ar5212ChannelChange(ah, chan)) { 211185377Ssam /* If ChannelChange completed - skip the rest of reset */ 212185377Ssam /* XXX ani? */ 213187831Ssam goto done; 214185377Ssam } 215185377Ssam } 216185377Ssam } 217185377Ssam#endif 218185377Ssam /* 219185377Ssam * Preserve the antenna on a channel change 220185377Ssam */ 221185377Ssam saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); 222185377Ssam if (saveDefAntenna == 0) /* XXX magic constants */ 223185377Ssam saveDefAntenna = 1; 224185377Ssam 225185377Ssam /* Save hardware flag before chip reset clears the register */ 226185377Ssam macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 227185377Ssam (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT); 228185377Ssam 229185377Ssam /* Save led state from pci config register */ 230185377Ssam saveLedState = OS_REG_READ(ah, AR_PCICFG) & 231185377Ssam (AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK | 232185377Ssam AR_PCICFG_LEDSLOW); 233185377Ssam softLedCfg = OS_REG_READ(ah, AR_GPIOCR); 234185377Ssam softLedState = OS_REG_READ(ah, AR_GPIODO); 235185377Ssam 236185377Ssam ar5212RestoreClock(ah, opmode); /* move to refclk operation */ 237185377Ssam 238185377Ssam /* 239185377Ssam * Adjust gain parameters before reset if 240185377Ssam * there's an outstanding gain updated. 241185377Ssam */ 242185377Ssam (void) ar5212GetRfgain(ah); 243185377Ssam 244185377Ssam if (!ar5212ChipReset(ah, chan)) { 245185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 246185377Ssam FAIL(HAL_EIO); 247185377Ssam } 248185377Ssam 249185377Ssam /* Setup the indices for the next set of register array writes */ 250187831Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 251187831Ssam freqIndex = 2; 252187831Ssam if (IEEE80211_IS_CHAN_108G(chan)) 253187831Ssam modesIndex = 5; 254187831Ssam else if (IEEE80211_IS_CHAN_G(chan)) 255187831Ssam modesIndex = 4; 256187831Ssam else if (IEEE80211_IS_CHAN_B(chan)) 257187831Ssam modesIndex = 3; 258187831Ssam else { 259187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 260187831Ssam "%s: invalid channel %u/0x%x\n", 261187831Ssam __func__, chan->ic_freq, chan->ic_flags); 262187831Ssam FAIL(HAL_EINVAL); 263187831Ssam } 264187831Ssam } else { 265185377Ssam freqIndex = 1; 266187831Ssam if (IEEE80211_IS_CHAN_TURBO(chan)) 267187831Ssam modesIndex = 2; 268187831Ssam else if (IEEE80211_IS_CHAN_A(chan)) 269187831Ssam modesIndex = 1; 270187831Ssam else { 271187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 272187831Ssam "%s: invalid channel %u/0x%x\n", 273187831Ssam __func__, chan->ic_freq, chan->ic_flags); 274187831Ssam FAIL(HAL_EINVAL); 275187831Ssam } 276185377Ssam } 277185377Ssam 278185377Ssam OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 279185377Ssam 280185377Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 281185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 282185377Ssam 283185377Ssam regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0); 284185377Ssam regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange, 285185377Ssam regWrites); 286185377Ssam ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 287185377Ssam 288185377Ssam OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 289185377Ssam 290187831Ssam if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan)) { 291185377Ssam ar5212SetIFSTiming(ah, chan); 292185377Ssam if (IS_5413(ah)) { 293185377Ssam /* 294185377Ssam * Force window_length for 1/2 and 1/4 rate channels, 295185377Ssam * the ini file sets this to zero otherwise. 296185377Ssam */ 297185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 298185377Ssam AR_PHY_FRAME_CTL_WINLEN, 3); 299185377Ssam } 300185377Ssam } 301185377Ssam 302185377Ssam /* Overwrite INI values for revised chipsets */ 303185377Ssam if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) { 304185377Ssam /* ADC_CTL */ 305185377Ssam OS_REG_WRITE(ah, AR_PHY_ADC_CTL, 306185377Ssam SM(2, AR_PHY_ADC_CTL_OFF_INBUFGAIN) | 307185377Ssam SM(2, AR_PHY_ADC_CTL_ON_INBUFGAIN) | 308185377Ssam AR_PHY_ADC_CTL_OFF_PWDDAC | 309185377Ssam AR_PHY_ADC_CTL_OFF_PWDADC); 310185377Ssam 311185377Ssam /* TX_PWR_ADJ */ 312187831Ssam if (ichan->channel == 2484) { 313185377Ssam cckOfdmPwrDelta = SCALE_OC_DELTA( 314185377Ssam ee->ee_cckOfdmPwrDelta - 315185377Ssam ee->ee_scaledCh14FilterCckDelta); 316185377Ssam } else { 317185377Ssam cckOfdmPwrDelta = SCALE_OC_DELTA( 318185377Ssam ee->ee_cckOfdmPwrDelta); 319185377Ssam } 320185377Ssam 321187831Ssam if (IEEE80211_IS_CHAN_G(chan)) { 322185377Ssam OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 323185377Ssam SM((ee->ee_cckOfdmPwrDelta*-1), 324185377Ssam AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) | 325185377Ssam SM((cckOfdmPwrDelta*-1), 326185377Ssam AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX)); 327185377Ssam } else { 328185377Ssam OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0); 329185377Ssam } 330185377Ssam 331185377Ssam /* Add barker RSSI thresh enable as disabled */ 332185377Ssam OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK, 333185377Ssam AR_PHY_DAG_CTRLCCK_EN_RSSI_THR); 334185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK, 335185377Ssam AR_PHY_DAG_CTRLCCK_RSSI_THR, 2); 336185377Ssam 337185377Ssam /* Set the mute mask to the correct default */ 338185377Ssam OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); 339185377Ssam } 340185377Ssam 341185377Ssam if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) { 342185377Ssam /* Clear reg to alllow RX_CLEAR line debug */ 343185377Ssam OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); 344185377Ssam } 345185377Ssam if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) { 346185377Ssam#ifdef notyet 347185377Ssam /* Enable burst prefetch for the data queues */ 348185377Ssam OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... ); 349185377Ssam /* Enable double-buffering */ 350185377Ssam OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS); 351185377Ssam#endif 352185377Ssam } 353185377Ssam 354185377Ssam /* Set ADC/DAC select values */ 355185377Ssam OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); 356185377Ssam 357185377Ssam if (IS_5413(ah) || IS_2417(ah)) { 358187831Ssam uint32_t newReg = 1; 359187831Ssam if (IS_DISABLE_FAST_ADC_CHAN(ichan->channel)) 360185377Ssam newReg = 0; 361185377Ssam /* As it's a clock changing register, only write when the value needs to be changed */ 362185377Ssam if (OS_REG_READ(ah, AR_PHY_FAST_ADC) != newReg) 363185377Ssam OS_REG_WRITE(ah, AR_PHY_FAST_ADC, newReg); 364185377Ssam } 365185377Ssam 366185377Ssam /* Setup the transmit power values. */ 367187831Ssam if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) { 368185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 369185377Ssam "%s: error init'ing transmit power\n", __func__); 370185377Ssam FAIL(HAL_EIO); 371185377Ssam } 372185377Ssam 373185377Ssam /* Write the analog registers */ 374187831Ssam if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) { 375185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n", 376185377Ssam __func__); 377185377Ssam FAIL(HAL_EIO); 378185377Ssam } 379185377Ssam 380185377Ssam /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 381187831Ssam if (IEEE80211_IS_CHAN_OFDM(chan)) { 382187831Ssam if (IS_5413(ah) || 383187831Ssam AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3) 384187831Ssam ar5212SetSpurMitigation(ah, chan); 385185377Ssam ar5212SetDeltaSlope(ah, chan); 386185377Ssam } 387185377Ssam 388185377Ssam /* Setup board specific options for EEPROM version 3 */ 389187831Ssam if (!ar5212SetBoardValues(ah, chan)) { 390185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 391185377Ssam "%s: error setting board options\n", __func__); 392185377Ssam FAIL(HAL_EIO); 393185377Ssam } 394185377Ssam 395185377Ssam /* Restore certain DMA hardware registers on a channel change */ 396185377Ssam if (bChannelChange) 397185377Ssam OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount); 398185377Ssam 399185377Ssam OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 400185377Ssam 401185377Ssam OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 402185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) 403185377Ssam | macStaId1 404185377Ssam | AR_STA_ID1_RTS_USE_DEF 405185377Ssam | ahp->ah_staId1Defaults 406185377Ssam ); 407185377Ssam ar5212SetOperatingMode(ah, opmode); 408185377Ssam 409185377Ssam /* Set Venice BSSID mask according to current state */ 410185377Ssam OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); 411185377Ssam OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); 412185377Ssam 413185377Ssam /* Restore previous led state */ 414185377Ssam OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState); 415185377Ssam 416185377Ssam /* Restore soft Led state to GPIO */ 417185377Ssam OS_REG_WRITE(ah, AR_GPIOCR, softLedCfg); 418185377Ssam OS_REG_WRITE(ah, AR_GPIODO, softLedState); 419185377Ssam 420185377Ssam /* Restore previous antenna */ 421185377Ssam OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 422185377Ssam 423185377Ssam /* then our BSSID */ 424185377Ssam OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 425185377Ssam OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); 426185377Ssam 427185377Ssam /* Restore bmiss rssi & count thresholds */ 428185377Ssam OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 429185377Ssam 430185377Ssam OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ 431185377Ssam 432187831Ssam if (!ar5212SetChannel(ah, chan)) 433185377Ssam FAIL(HAL_EIO); 434185377Ssam 435185377Ssam OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 436185377Ssam 437185377Ssam ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); 438185377Ssam 439185377Ssam ar5212SetRateDurationTable(ah, chan); 440185377Ssam 441185377Ssam /* Set Tx frame start to tx data start delay */ 442185380Ssam if (IS_RAD5112_ANY(ah) && 443187831Ssam (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))) { 444185377Ssam txFrm2TxDStart = 445187831Ssam IEEE80211_IS_CHAN_HALF(chan) ? 446185377Ssam TX_FRAME_D_START_HALF_RATE: 447185377Ssam TX_FRAME_D_START_QUARTER_RATE; 448185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL, 449185377Ssam AR_PHY_TX_FRAME_TO_TX_DATA_START, txFrm2TxDStart); 450185377Ssam } 451185377Ssam 452185377Ssam /* 453185377Ssam * Setup fast diversity. 454185377Ssam * Fast diversity can be enabled or disabled via regadd.txt. 455185377Ssam * Default is enabled. 456185377Ssam * For reference, 457185377Ssam * Disable: reg val 458185377Ssam * 0x00009860 0x00009d18 (if 11a / 11g, else no change) 459185377Ssam * 0x00009970 0x192bb514 460185377Ssam * 0x0000a208 0xd03e4648 461185377Ssam * 462185377Ssam * Enable: 0x00009860 0x00009d10 (if 11a / 11g, else no change) 463185377Ssam * 0x00009970 0x192fb514 464185377Ssam * 0x0000a208 0xd03e6788 465185377Ssam */ 466185377Ssam 467185377Ssam /* XXX Setup pre PHY ENABLE EAR additions */ 468185377Ssam /* 469185377Ssam * Wait for the frequency synth to settle (synth goes on 470185377Ssam * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 471185377Ssam * Value is in 100ns increments. 472185377Ssam */ 473185377Ssam synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 474187831Ssam if (IEEE80211_IS_CHAN_B(chan)) { 475185377Ssam synthDelay = (4 * synthDelay) / 22; 476185377Ssam } else { 477185377Ssam synthDelay /= 10; 478185377Ssam } 479185377Ssam 480185377Ssam /* Activate the PHY (includes baseband activate and synthesizer on) */ 481185377Ssam OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 482185377Ssam 483185377Ssam /* 484185377Ssam * There is an issue if the AP starts the calibration before 485185377Ssam * the base band timeout completes. This could result in the 486185377Ssam * rx_clear false triggering. As a workaround we add delay an 487185377Ssam * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 488185377Ssam * does not happen. 489185377Ssam */ 490187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) { 491185377Ssam OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY); 492187831Ssam } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 493185377Ssam OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY); 494185377Ssam } else { 495185377Ssam OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 496185377Ssam } 497185377Ssam 498185377Ssam /* 499185377Ssam * The udelay method is not reliable with notebooks. 500185377Ssam * Need to check to see if the baseband is ready 501185377Ssam */ 502185377Ssam testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL); 503185377Ssam /* Selects the Tx hold */ 504185377Ssam OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD); 505185377Ssam i = 0; 506185377Ssam while ((i++ < 20) && 507185377Ssam (OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */ OS_DELAY(200); 508185377Ssam OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg); 509185377Ssam 510185377Ssam /* Calibrate the AGC and start a NF calculation */ 511185377Ssam OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, 512185377Ssam OS_REG_READ(ah, AR_PHY_AGC_CONTROL) 513185377Ssam | AR_PHY_AGC_CONTROL_CAL 514185377Ssam | AR_PHY_AGC_CONTROL_NF); 515185377Ssam 516187831Ssam if (!IEEE80211_IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) { 517185377Ssam /* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */ 518185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 519185377Ssam AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 520185377Ssam INIT_IQCAL_LOG_COUNT_MAX); 521185377Ssam OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 522185377Ssam AR_PHY_TIMING_CTRL4_DO_IQCAL); 523185377Ssam ahp->ah_bIQCalibration = IQ_CAL_RUNNING; 524185377Ssam } else 525185377Ssam ahp->ah_bIQCalibration = IQ_CAL_INACTIVE; 526185377Ssam 527185377Ssam /* Setup compression registers */ 528185377Ssam ar5212SetCompRegs(ah); 529185377Ssam 530185377Ssam /* Set 1:1 QCU to DCU mapping for all queues */ 531185377Ssam for (i = 0; i < AR_NUM_DCU; i++) 532185377Ssam OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 533185377Ssam 534185377Ssam ahp->ah_intrTxqs = 0; 535185377Ssam for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) 536185377Ssam ar5212ResetTxQueue(ah, i); 537185377Ssam 538185377Ssam /* 539185377Ssam * Setup interrupt handling. Note that ar5212ResetTxQueue 540185377Ssam * manipulates the secondary IMR's as queues are enabled 541185377Ssam * and disabled. This is done with RMW ops to insure the 542185377Ssam * settings we make here are preserved. 543185377Ssam */ 544185377Ssam ahp->ah_maskReg = AR_IMR_TXOK | AR_IMR_TXERR | AR_IMR_TXURN 545185377Ssam | AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXORN 546185377Ssam | AR_IMR_HIUERR 547185377Ssam ; 548185377Ssam if (opmode == HAL_M_HOSTAP) 549185377Ssam ahp->ah_maskReg |= AR_IMR_MIB; 550185377Ssam OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 551185377Ssam /* Enable bus errors that are OR'd to set the HIUERR bit */ 552185377Ssam OS_REG_WRITE(ah, AR_IMR_S2, 553185377Ssam OS_REG_READ(ah, AR_IMR_S2) 554185377Ssam | AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR); 555185377Ssam 556185377Ssam if (AH_PRIVATE(ah)->ah_rfkillEnabled) 557185377Ssam ar5212EnableRfKill(ah); 558185377Ssam 559185377Ssam if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { 560185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 561185377Ssam "%s: offset calibration failed to complete in 1ms;" 562185377Ssam " noisy environment?\n", __func__); 563185377Ssam } 564185377Ssam 565185377Ssam /* 566185377Ssam * Set clocks back to 32kHz if they had been using refClk, then 567185377Ssam * use an external 32kHz crystal when sleeping, if one exists. 568185377Ssam */ 569185377Ssam ar5212SetupClock(ah, opmode); 570185377Ssam 571185377Ssam /* 572185377Ssam * Writing to AR_BEACON will start timers. Hence it should 573185377Ssam * be the last register to be written. Do not reset tsf, do 574185377Ssam * not enable beacons at this point, but preserve other values 575185377Ssam * like beaconInterval. 576185377Ssam */ 577185377Ssam OS_REG_WRITE(ah, AR_BEACON, 578185377Ssam (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF))); 579185377Ssam 580185377Ssam /* XXX Setup post reset EAR additions */ 581185377Ssam 582185377Ssam /* QoS support */ 583185377Ssam if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE || 584185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 585185377Ssam AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) { 586185377Ssam OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ 587185377Ssam OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ 588185377Ssam } 589185377Ssam 590185377Ssam /* Turn on NOACK Support for QoS packets */ 591185377Ssam OS_REG_WRITE(ah, AR_NOACK, 592185377Ssam SM(2, AR_NOACK_2BIT_VALUE) | 593185377Ssam SM(5, AR_NOACK_BIT_OFFSET) | 594185377Ssam SM(0, AR_NOACK_BYTE_OFFSET)); 595185377Ssam 596185377Ssam /* Get Antenna Gain reduction */ 597187831Ssam if (IEEE80211_IS_CHAN_5GHZ(chan)) { 598185377Ssam ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain); 599185377Ssam } else { 600185377Ssam ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain); 601185377Ssam } 602185377Ssam twiceAntennaReduction = 603185377Ssam ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 604185377Ssam 605185377Ssam /* TPC for self-generated frames */ 606185377Ssam 607185377Ssam ackTpcPow = MS(ahp->ah_macTPC, AR_TPC_ACK); 608187831Ssam if ((ackTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 609187831Ssam ackTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 610185377Ssam 611187831Ssam if (ackTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 612187831Ssam ackTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 613185377Ssam + ahp->ah_txPowerIndexOffset; 614185377Ssam 615185377Ssam ctsTpcPow = MS(ahp->ah_macTPC, AR_TPC_CTS); 616187831Ssam if ((ctsTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 617187831Ssam ctsTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 618185377Ssam 619187831Ssam if (ctsTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 620187831Ssam ctsTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 621185377Ssam + ahp->ah_txPowerIndexOffset; 622185377Ssam 623185377Ssam chirpTpcPow = MS(ahp->ah_macTPC, AR_TPC_CHIRP); 624187831Ssam if ((chirpTpcPow-ahp->ah_txPowerIndexOffset) > chan->ic_maxpower) 625187831Ssam chirpTpcPow = chan->ic_maxpower+ahp->ah_txPowerIndexOffset; 626185377Ssam 627187831Ssam if (chirpTpcPow > (2*chan->ic_maxregpower - twiceAntennaReduction)) 628187831Ssam chirpTpcPow = (2*chan->ic_maxregpower - twiceAntennaReduction) 629185377Ssam + ahp->ah_txPowerIndexOffset; 630185377Ssam 631185377Ssam if (ackTpcPow > 63) 632185377Ssam ackTpcPow = 63; 633185377Ssam if (ctsTpcPow > 63) 634185377Ssam ctsTpcPow = 63; 635185377Ssam if (chirpTpcPow > 63) 636185377Ssam chirpTpcPow = 63; 637185377Ssam 638185377Ssam powerVal = SM(ackTpcPow, AR_TPC_ACK) | 639185377Ssam SM(ctsTpcPow, AR_TPC_CTS) | 640185377Ssam SM(chirpTpcPow, AR_TPC_CHIRP); 641185377Ssam 642185377Ssam OS_REG_WRITE(ah, AR_TPC, powerVal); 643185377Ssam 644185377Ssam /* Restore user-specified settings */ 645185377Ssam if (ahp->ah_miscMode != 0) 646185377Ssam OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 647185377Ssam if (ahp->ah_sifstime != (u_int) -1) 648185377Ssam ar5212SetSifsTime(ah, ahp->ah_sifstime); 649185377Ssam if (ahp->ah_slottime != (u_int) -1) 650185377Ssam ar5212SetSlotTime(ah, ahp->ah_slottime); 651185377Ssam if (ahp->ah_acktimeout != (u_int) -1) 652185377Ssam ar5212SetAckTimeout(ah, ahp->ah_acktimeout); 653185377Ssam if (ahp->ah_ctstimeout != (u_int) -1) 654185377Ssam ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); 655185377Ssam if (AH_PRIVATE(ah)->ah_diagreg != 0) 656185377Ssam OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 657185377Ssam 658185377Ssam AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 659187831Ssam#if 0 660187831Ssamdone: 661187831Ssam#endif 662187831Ssam if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan)) 663187831Ssam chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 664185377Ssam 665185377Ssam HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 666185377Ssam 667185377Ssam RESTORE_CCK(ah, chan, isBmode); 668185377Ssam 669185377Ssam OS_MARK(ah, AH_MARK_RESET_DONE, 0); 670185377Ssam 671185377Ssam return AH_TRUE; 672185377Ssambad: 673185377Ssam RESTORE_CCK(ah, chan, isBmode); 674185377Ssam 675185377Ssam OS_MARK(ah, AH_MARK_RESET_DONE, ecode); 676187611Ssam if (status != AH_NULL) 677185377Ssam *status = ecode; 678185377Ssam return AH_FALSE; 679185377Ssam#undef FAIL 680185377Ssam#undef N 681185377Ssam} 682185377Ssam 683185377Ssam/* 684185377Ssam * Call the rf backend to change the channel. 685185377Ssam */ 686185377SsamHAL_BOOL 687187831Ssamar5212SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 688185377Ssam{ 689185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 690185377Ssam 691185377Ssam /* Change the synth */ 692185377Ssam if (!ahp->ah_rfHal->setChannel(ah, chan)) 693185377Ssam return AH_FALSE; 694185377Ssam return AH_TRUE; 695185377Ssam} 696185377Ssam 697185377Ssam/* 698185377Ssam * This channel change evaluates whether the selected hardware can 699185377Ssam * perform a synthesizer-only channel change (no reset). If the 700185377Ssam * TX is not stopped, or the RFBus cannot be granted in the given 701185377Ssam * time, the function returns false as a reset is necessary 702185377Ssam */ 703185377SsamHAL_BOOL 704187831Ssamar5212ChannelChange(struct ath_hal *ah, const struct ieee80211_channel *chan) 705185377Ssam{ 706185377Ssam uint32_t ulCount; 707185377Ssam uint32_t data, synthDelay, qnum; 708185377Ssam uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 709185377Ssam HAL_BOOL txStopped = AH_TRUE; 710185377Ssam HAL_CHANNEL_INTERNAL *ichan; 711185377Ssam 712185377Ssam /* 713185377Ssam * Map public channel to private. 714185377Ssam */ 715185377Ssam ichan = ath_hal_checkchannel(ah, chan); 716185377Ssam 717185377Ssam /* TX must be stopped or RF Bus grant will not work */ 718185377Ssam for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) { 719185377Ssam if (ar5212NumTxPending(ah, qnum)) { 720185377Ssam txStopped = AH_FALSE; 721185377Ssam break; 722185377Ssam } 723185377Ssam } 724185377Ssam if (!txStopped) 725185377Ssam return AH_FALSE; 726185377Ssam 727185377Ssam /* Kill last Baseband Rx Frame */ 728185377Ssam OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); /* Request analog bus grant */ 729185377Ssam for (ulCount = 0; ulCount < 100; ulCount++) { 730185377Ssam if (OS_REG_READ(ah, AR_PHY_RFBUS_GNT)) 731185377Ssam break; 732185377Ssam OS_DELAY(5); 733185377Ssam } 734185377Ssam if (ulCount >= 100) 735185377Ssam return AH_FALSE; 736185377Ssam 737185377Ssam /* Change the synth */ 738187831Ssam if (!ar5212SetChannel(ah, chan)) 739185377Ssam return AH_FALSE; 740185377Ssam 741185377Ssam /* 742185377Ssam * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). 743185377Ssam * Read the phy active delay register. Value is in 100ns increments. 744185377Ssam */ 745185377Ssam data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 746187831Ssam if (IEEE80211_IS_CHAN_B(chan)) { 747185377Ssam synthDelay = (4 * data) / 22; 748185377Ssam } else { 749185377Ssam synthDelay = data / 10; 750185377Ssam } 751185377Ssam OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 752185377Ssam 753185377Ssam /* Setup the transmit power values. */ 754187831Ssam if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) { 755185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 756185377Ssam "%s: error init'ing transmit power\n", __func__); 757185377Ssam return AH_FALSE; 758185377Ssam } 759185377Ssam 760185377Ssam /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 761187831Ssam if (IEEE80211_IS_CHAN_OFDM(chan)) { 762187831Ssam if (IS_5413(ah) || 763187831Ssam AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3) 764187831Ssam ar5212SetSpurMitigation(ah, chan); 765185377Ssam ar5212SetDeltaSlope(ah, chan); 766185377Ssam } 767185377Ssam 768185377Ssam /* Release the RFBus Grant */ 769185377Ssam OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 770185377Ssam 771185377Ssam /* Start Noise Floor Cal */ 772185377Ssam OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 773185377Ssam return AH_TRUE; 774185377Ssam} 775185377Ssam 776185377Ssamvoid 777185377Ssamar5212SetOperatingMode(struct ath_hal *ah, int opmode) 778185377Ssam{ 779185377Ssam uint32_t val; 780185377Ssam 781185377Ssam val = OS_REG_READ(ah, AR_STA_ID1); 782185377Ssam val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 783185377Ssam switch (opmode) { 784185377Ssam case HAL_M_HOSTAP: 785185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 786185377Ssam | AR_STA_ID1_KSRCH_MODE); 787185377Ssam OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 788185377Ssam break; 789185377Ssam case HAL_M_IBSS: 790185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 791185377Ssam | AR_STA_ID1_KSRCH_MODE); 792185377Ssam OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 793185377Ssam break; 794185377Ssam case HAL_M_STA: 795185377Ssam case HAL_M_MONITOR: 796185377Ssam OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 797185377Ssam break; 798185377Ssam } 799185377Ssam} 800185377Ssam 801185377Ssam/* 802185377Ssam * Places the PHY and Radio chips into reset. A full reset 803185377Ssam * must be called to leave this state. The PCI/MAC/PCU are 804185377Ssam * not placed into reset as we must receive interrupt to 805185377Ssam * re-enable the hardware. 806185377Ssam */ 807185377SsamHAL_BOOL 808185377Ssamar5212PhyDisable(struct ath_hal *ah) 809185377Ssam{ 810185377Ssam return ar5212SetResetReg(ah, AR_RC_BB); 811185377Ssam} 812185377Ssam 813185377Ssam/* 814185377Ssam * Places all of hardware into reset 815185377Ssam */ 816185377SsamHAL_BOOL 817185377Ssamar5212Disable(struct ath_hal *ah) 818185377Ssam{ 819185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 820185377Ssam return AH_FALSE; 821185377Ssam /* 822185377Ssam * Reset the HW - PCI must be reset after the rest of the 823185377Ssam * device has been reset. 824185377Ssam */ 825185377Ssam return ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI); 826185377Ssam} 827185377Ssam 828185377Ssam/* 829185377Ssam * Places the hardware into reset and then pulls it out of reset 830185377Ssam * 831185377Ssam * TODO: Only write the PLL if we're changing to or from CCK mode 832185377Ssam * 833185377Ssam * WARNING: The order of the PLL and mode registers must be correct. 834185377Ssam */ 835185377SsamHAL_BOOL 836187831Ssamar5212ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan) 837185377Ssam{ 838185377Ssam 839187831Ssam OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); 840185377Ssam 841185377Ssam /* 842185377Ssam * Reset the HW - PCI must be reset after the rest of the 843185377Ssam * device has been reset 844185377Ssam */ 845185377Ssam if (!ar5212SetResetReg(ah, AR_RC_MAC | AR_RC_BB | AR_RC_PCI)) 846185377Ssam return AH_FALSE; 847185377Ssam 848185377Ssam /* Bring out of sleep mode (AGAIN) */ 849185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 850185377Ssam return AH_FALSE; 851185377Ssam 852185377Ssam /* Clear warm reset register */ 853185377Ssam if (!ar5212SetResetReg(ah, 0)) 854185377Ssam return AH_FALSE; 855185377Ssam 856185377Ssam /* 857185377Ssam * Perform warm reset before the mode/PLL/turbo registers 858185377Ssam * are changed in order to deactivate the radio. Mode changes 859185377Ssam * with an active radio can result in corrupted shifts to the 860185377Ssam * radio device. 861185377Ssam */ 862185377Ssam 863185377Ssam /* 864185377Ssam * Set CCK and Turbo modes correctly. 865185377Ssam */ 866185377Ssam if (chan != AH_NULL) { /* NB: can be null during attach */ 867185377Ssam uint32_t rfMode, phyPLL = 0, curPhyPLL, turbo; 868185377Ssam 869185380Ssam if (IS_5413(ah)) { /* NB: =>'s 5424 also */ 870185377Ssam rfMode = AR_PHY_MODE_AR5112; 871187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) 872185377Ssam rfMode |= AR_PHY_MODE_HALF; 873187831Ssam else if (IEEE80211_IS_CHAN_QUARTER(chan)) 874185377Ssam rfMode |= AR_PHY_MODE_QUARTER; 875185377Ssam 876187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) 877185377Ssam phyPLL = AR_PHY_PLL_CTL_44_5112; 878185377Ssam else 879185377Ssam phyPLL = AR_PHY_PLL_CTL_40_5413; 880185380Ssam } else if (IS_RAD5111(ah)) { 881185380Ssam rfMode = AR_PHY_MODE_AR5111; 882187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) 883185380Ssam phyPLL = AR_PHY_PLL_CTL_44; 884185380Ssam else 885185380Ssam phyPLL = AR_PHY_PLL_CTL_40; 886187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) 887185380Ssam phyPLL = AR_PHY_PLL_CTL_HALF; 888187831Ssam else if (IEEE80211_IS_CHAN_QUARTER(chan)) 889185380Ssam phyPLL = AR_PHY_PLL_CTL_QUARTER; 890185380Ssam } else { /* 5112, 2413, 2316, 2317 */ 891185377Ssam rfMode = AR_PHY_MODE_AR5112; 892187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) 893185377Ssam phyPLL = AR_PHY_PLL_CTL_44_5112; 894185380Ssam else 895185380Ssam phyPLL = AR_PHY_PLL_CTL_40_5112; 896187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) 897185380Ssam phyPLL |= AR_PHY_PLL_CTL_HALF; 898187831Ssam else if (IEEE80211_IS_CHAN_QUARTER(chan)) 899185380Ssam phyPLL |= AR_PHY_PLL_CTL_QUARTER; 900185377Ssam } 901187831Ssam if (IEEE80211_IS_CHAN_G(chan)) 902185377Ssam rfMode |= AR_PHY_MODE_DYNAMIC; 903187831Ssam else if (IEEE80211_IS_CHAN_OFDM(chan)) 904185377Ssam rfMode |= AR_PHY_MODE_OFDM; 905185377Ssam else 906185377Ssam rfMode |= AR_PHY_MODE_CCK; 907187831Ssam if (IEEE80211_IS_CHAN_5GHZ(chan)) 908185377Ssam rfMode |= AR_PHY_MODE_RF5GHZ; 909185377Ssam else 910185377Ssam rfMode |= AR_PHY_MODE_RF2GHZ; 911187831Ssam turbo = IEEE80211_IS_CHAN_TURBO(chan) ? 912185377Ssam (AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT) : 0; 913185377Ssam curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL); 914185377Ssam /* 915185377Ssam * PLL, Mode, and Turbo values must be written in the correct 916185377Ssam * order to ensure: 917185377Ssam * - The PLL cannot be set to 44 unless the CCK or DYNAMIC 918185377Ssam * mode bit is set 919185377Ssam * - Turbo cannot be set at the same time as CCK or DYNAMIC 920185377Ssam */ 921187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) { 922185377Ssam OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); 923185377Ssam OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 924185377Ssam if (curPhyPLL != phyPLL) { 925185377Ssam OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); 926185377Ssam /* Wait for the PLL to settle */ 927185377Ssam OS_DELAY(PLL_SETTLE_DELAY); 928185377Ssam } 929185377Ssam } else { 930185377Ssam if (curPhyPLL != phyPLL) { 931185377Ssam OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); 932185377Ssam /* Wait for the PLL to settle */ 933185377Ssam OS_DELAY(PLL_SETTLE_DELAY); 934185377Ssam } 935185377Ssam OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); 936185377Ssam OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 937185377Ssam } 938185377Ssam } 939185377Ssam return AH_TRUE; 940185377Ssam} 941185377Ssam 942185377Ssam/* 943185377Ssam * Recalibrate the lower PHY chips to account for temperature/environment 944185377Ssam * changes. 945185377Ssam */ 946185377SsamHAL_BOOL 947187831Ssamar5212PerCalibrationN(struct ath_hal *ah, 948187831Ssam struct ieee80211_channel *chan, 949187831Ssam u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone) 950185377Ssam{ 951185377Ssam#define IQ_CAL_TRIES 10 952185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 953185377Ssam HAL_CHANNEL_INTERNAL *ichan; 954185377Ssam int32_t qCoff, qCoffDenom; 955185377Ssam int32_t iqCorrMeas, iCoff, iCoffDenom; 956185377Ssam uint32_t powerMeasQ, powerMeasI; 957188011Ssam HAL_BOOL isBmode = AH_FALSE; 958185377Ssam 959187831Ssam OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq); 960185380Ssam *isCalDone = AH_FALSE; 961185377Ssam ichan = ath_hal_checkchannel(ah, chan); 962185377Ssam if (ichan == AH_NULL) { 963185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 964185377Ssam "%s: invalid channel %u/0x%x; no mapping\n", 965187831Ssam __func__, chan->ic_freq, chan->ic_flags); 966185377Ssam return AH_FALSE; 967185377Ssam } 968185377Ssam SAVE_CCK(ah, chan, isBmode); 969185377Ssam 970185380Ssam if (ahp->ah_bIQCalibration == IQ_CAL_DONE || 971185380Ssam ahp->ah_bIQCalibration == IQ_CAL_INACTIVE) 972185380Ssam *isCalDone = AH_TRUE; 973185377Ssam 974185377Ssam /* IQ calibration in progress. Check to see if it has finished. */ 975185377Ssam if (ahp->ah_bIQCalibration == IQ_CAL_RUNNING && 976185377Ssam !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) { 977185377Ssam int i; 978185377Ssam 979185377Ssam /* IQ Calibration has finished. */ 980185377Ssam ahp->ah_bIQCalibration = IQ_CAL_INACTIVE; 981185380Ssam *isCalDone = AH_TRUE; 982185377Ssam 983185377Ssam /* workaround for misgated IQ Cal results */ 984185377Ssam i = 0; 985185377Ssam do { 986185377Ssam /* Read calibration results. */ 987185377Ssam powerMeasI = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_I); 988185377Ssam powerMeasQ = OS_REG_READ(ah, AR_PHY_IQCAL_RES_PWR_MEAS_Q); 989185377Ssam iqCorrMeas = OS_REG_READ(ah, AR_PHY_IQCAL_RES_IQ_CORR_MEAS); 990185377Ssam if (powerMeasI && powerMeasQ) 991185377Ssam break; 992185377Ssam /* Do we really need this??? */ 993185377Ssam OS_REG_WRITE (ah, AR_PHY_TIMING_CTRL4, 994185377Ssam OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) | 995185377Ssam AR_PHY_TIMING_CTRL4_DO_IQCAL); 996185377Ssam } while (++i < IQ_CAL_TRIES); 997185377Ssam 998185377Ssam /* 999185377Ssam * Prescale these values to remove 64-bit operation 1000185377Ssam * requirement at the loss of a little precision. 1001185377Ssam */ 1002185377Ssam iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 1003185377Ssam qCoffDenom = powerMeasQ / 128; 1004185377Ssam 1005185377Ssam /* Protect against divide-by-0 and loss of sign bits. */ 1006185377Ssam if (iCoffDenom != 0 && qCoffDenom >= 2) { 1007185377Ssam iCoff = (int8_t)(-iqCorrMeas) / iCoffDenom; 1008185377Ssam /* IQCORR_Q_I_COFF is a signed 6 bit number */ 1009185377Ssam if (iCoff < -32) { 1010185377Ssam iCoff = -32; 1011185377Ssam } else if (iCoff > 31) { 1012185377Ssam iCoff = 31; 1013185377Ssam } 1014185377Ssam 1015185377Ssam /* IQCORR_Q_Q_COFF is a signed 5 bit number */ 1016185377Ssam qCoff = (powerMeasI / qCoffDenom) - 128; 1017185377Ssam if (qCoff < -16) { 1018185377Ssam qCoff = -16; 1019185377Ssam } else if (qCoff > 15) { 1020185377Ssam qCoff = 15; 1021185377Ssam } 1022185377Ssam 1023185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 1024185377Ssam "****************** MISGATED IQ CAL! *******************\n"); 1025185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 1026185377Ssam "time = %d, i = %d, \n", OS_GETUPTIME(ah), i); 1027185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 1028185377Ssam "powerMeasI = 0x%08x\n", powerMeasI); 1029185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 1030185377Ssam "powerMeasQ = 0x%08x\n", powerMeasQ); 1031185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 1032185377Ssam "iqCorrMeas = 0x%08x\n", iqCorrMeas); 1033185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 1034185377Ssam "iCoff = %d\n", iCoff); 1035185377Ssam HALDEBUG(ah, HAL_DEBUG_PERCAL, 1036185377Ssam "qCoff = %d\n", qCoff); 1037185377Ssam 1038185377Ssam /* Write values and enable correction */ 1039185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1040185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff); 1041185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1042185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff); 1043185377Ssam OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1044185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 1045185377Ssam 1046185377Ssam ahp->ah_bIQCalibration = IQ_CAL_DONE; 1047187831Ssam ichan->privFlags |= CHANNEL_IQVALID; 1048185377Ssam ichan->iCoff = iCoff; 1049185377Ssam ichan->qCoff = qCoff; 1050185377Ssam } 1051187831Ssam } else if (!IEEE80211_IS_CHAN_B(chan) && ahp->ah_bIQCalibration == IQ_CAL_DONE && 1052187831Ssam (ichan->privFlags & CHANNEL_IQVALID) == 0) { 1053185377Ssam /* 1054185377Ssam * Start IQ calibration if configured channel has changed. 1055185377Ssam * Use a magic number of 15 based on default value. 1056185377Ssam */ 1057185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1058185377Ssam AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, 1059185377Ssam INIT_IQCAL_LOG_COUNT_MAX); 1060185377Ssam OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1061185377Ssam AR_PHY_TIMING_CTRL4_DO_IQCAL); 1062185377Ssam ahp->ah_bIQCalibration = IQ_CAL_RUNNING; 1063185377Ssam } 1064185377Ssam /* XXX EAR */ 1065185377Ssam 1066185380Ssam if (longCal) { 1067185380Ssam /* Check noise floor results */ 1068187831Ssam ar5212GetNf(ah, chan); 1069187831Ssam if (!IEEE80211_IS_CHAN_CWINT(chan)) { 1070185380Ssam /* Perform cal for 5Ghz channels and any OFDM on 5112 */ 1071187831Ssam if (IEEE80211_IS_CHAN_5GHZ(chan) || 1072187831Ssam (IS_RAD5112(ah) && IEEE80211_IS_CHAN_OFDM(chan))) 1073185380Ssam ar5212RequestRfgain(ah); 1074185380Ssam } 1075185377Ssam } 1076185377Ssam RESTORE_CCK(ah, chan, isBmode); 1077185377Ssam 1078185377Ssam return AH_TRUE; 1079185377Ssam#undef IQ_CAL_TRIES 1080185377Ssam} 1081185377Ssam 1082185380SsamHAL_BOOL 1083187831Ssamar5212PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan, 1084187831Ssam HAL_BOOL *isIQdone) 1085185380Ssam{ 1086185380Ssam return ar5212PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone); 1087185380Ssam} 1088185380Ssam 1089185380SsamHAL_BOOL 1090187831Ssamar5212ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan) 1091185380Ssam{ 1092185380Ssam /* XXX */ 1093185380Ssam return AH_TRUE; 1094185380Ssam} 1095185380Ssam 1096185377Ssam/* 1097185377Ssam * Write the given reset bit mask into the reset register 1098185377Ssam */ 1099185377Ssamstatic HAL_BOOL 1100185377Ssamar5212SetResetReg(struct ath_hal *ah, uint32_t resetMask) 1101185377Ssam{ 1102185377Ssam uint32_t mask = resetMask ? resetMask : ~0; 1103185377Ssam HAL_BOOL rt; 1104185377Ssam 1105185377Ssam /* XXX ar5212MacStop & co. */ 1106185377Ssam 1107185377Ssam if (IS_PCIE(ah)) { 1108185377Ssam resetMask &= ~AR_RC_PCI; 1109185377Ssam } 1110185377Ssam 1111185377Ssam (void) OS_REG_READ(ah, AR_RXDP);/* flush any pending MMR writes */ 1112185377Ssam OS_REG_WRITE(ah, AR_RC, resetMask); 1113185377Ssam OS_DELAY(15); /* need to wait at least 128 clocks 1114185377Ssam when reseting PCI before read */ 1115185377Ssam mask &= (AR_RC_MAC | AR_RC_BB); 1116185377Ssam resetMask &= (AR_RC_MAC | AR_RC_BB); 1117185377Ssam rt = ath_hal_wait(ah, AR_RC, mask, resetMask); 1118185377Ssam if ((resetMask & AR_RC_MAC) == 0) { 1119185377Ssam if (isBigEndian()) { 1120185377Ssam /* 1121185377Ssam * Set CFG, little-endian for register 1122185377Ssam * and descriptor accesses. 1123185377Ssam */ 1124185377Ssam mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG; 1125185377Ssam#ifndef AH_NEED_DESC_SWAP 1126185377Ssam mask |= AR_CFG_SWTD; 1127185377Ssam#endif 1128185377Ssam OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); 1129185377Ssam } else 1130185377Ssam OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); 1131185377Ssam if (ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 1132185377Ssam (void) OS_REG_READ(ah, AR_ISR_RAC); 1133185377Ssam } 1134185380Ssam 1135185380Ssam /* track PHY power state so we don't try to r/w BB registers */ 1136185380Ssam AH5212(ah)->ah_phyPowerOn = ((resetMask & AR_RC_BB) == 0); 1137185377Ssam return rt; 1138185377Ssam} 1139185377Ssam 1140185377Ssamint16_t 1141185377Ssamar5212GetNoiseFloor(struct ath_hal *ah) 1142185377Ssam{ 1143185377Ssam int16_t nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 1144185377Ssam if (nf & 0x100) 1145185377Ssam nf = 0 - ((nf ^ 0x1ff) + 1); 1146185377Ssam return nf; 1147185377Ssam} 1148185377Ssam 1149185377Ssamstatic HAL_BOOL 1150187831SsamgetNoiseFloorThresh(struct ath_hal *ah, const struct ieee80211_channel *chan, 1151185377Ssam int16_t *nft) 1152185377Ssam{ 1153185377Ssam const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1154185377Ssam 1155185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 1156185377Ssam 1157187831Ssam switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 1158187831Ssam case IEEE80211_CHAN_A: 1159185377Ssam *nft = ee->ee_noiseFloorThresh[headerInfo11A]; 1160185377Ssam break; 1161187831Ssam case IEEE80211_CHAN_B: 1162185377Ssam *nft = ee->ee_noiseFloorThresh[headerInfo11B]; 1163185377Ssam break; 1164187831Ssam case IEEE80211_CHAN_G: 1165187831Ssam case IEEE80211_CHAN_PUREG: /* NB: really 108G */ 1166185377Ssam *nft = ee->ee_noiseFloorThresh[headerInfo11G]; 1167185377Ssam break; 1168185377Ssam default: 1169187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 1170187831Ssam "%s: invalid channel flags %u/0x%x\n", 1171187831Ssam __func__, chan->ic_freq, chan->ic_flags); 1172185377Ssam return AH_FALSE; 1173185377Ssam } 1174185377Ssam return AH_TRUE; 1175185377Ssam} 1176185377Ssam 1177185377Ssam/* 1178185377Ssam * Setup the noise floor cal history buffer. 1179185377Ssam */ 1180185377Ssamvoid 1181185377Ssamar5212InitNfCalHistBuffer(struct ath_hal *ah) 1182185377Ssam{ 1183185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 1184185377Ssam int i; 1185185377Ssam 1186185377Ssam ahp->ah_nfCalHist.first_run = 1; 1187185377Ssam ahp->ah_nfCalHist.currIndex = 0; 1188185377Ssam ahp->ah_nfCalHist.privNF = AR5212_CCA_MAX_GOOD_VALUE; 1189185377Ssam ahp->ah_nfCalHist.invalidNFcount = AR512_NF_CAL_HIST_MAX; 1190185377Ssam for (i = 0; i < AR512_NF_CAL_HIST_MAX; i ++) 1191185377Ssam ahp->ah_nfCalHist.nfCalBuffer[i] = AR5212_CCA_MAX_GOOD_VALUE; 1192185377Ssam} 1193185377Ssam 1194185377Ssam/* 1195185377Ssam * Add a noise floor value to the ring buffer. 1196185377Ssam */ 1197185377Ssamstatic __inline void 1198185377SsamupdateNFHistBuff(struct ar5212NfCalHist *h, int16_t nf) 1199185377Ssam{ 1200185377Ssam h->nfCalBuffer[h->currIndex] = nf; 1201185377Ssam if (++h->currIndex >= AR512_NF_CAL_HIST_MAX) 1202185377Ssam h->currIndex = 0; 1203185377Ssam} 1204185377Ssam 1205185377Ssam/* 1206185377Ssam * Return the median noise floor value in the ring buffer. 1207185377Ssam */ 1208185377Ssamint16_t 1209185377Ssamar5212GetNfHistMid(const int16_t calData[AR512_NF_CAL_HIST_MAX]) 1210185377Ssam{ 1211185377Ssam int16_t sort[AR512_NF_CAL_HIST_MAX]; 1212185377Ssam int i, j; 1213185377Ssam 1214185377Ssam OS_MEMCPY(sort, calData, AR512_NF_CAL_HIST_MAX*sizeof(int16_t)); 1215185377Ssam for (i = 0; i < AR512_NF_CAL_HIST_MAX-1; i ++) { 1216185377Ssam for (j = 1; j < AR512_NF_CAL_HIST_MAX-i; j ++) { 1217185377Ssam if (sort[j] > sort[j-1]) { 1218185377Ssam int16_t nf = sort[j]; 1219185377Ssam sort[j] = sort[j-1]; 1220185377Ssam sort[j-1] = nf; 1221185377Ssam } 1222185377Ssam } 1223185377Ssam } 1224185377Ssam return sort[(AR512_NF_CAL_HIST_MAX-1)>>1]; 1225185377Ssam} 1226185377Ssam 1227185377Ssam/* 1228185377Ssam * Read the NF and check it against the noise floor threshhold 1229185377Ssam */ 1230185377Ssamint16_t 1231187831Ssamar5212GetNf(struct ath_hal *ah, struct ieee80211_channel *chan) 1232185377Ssam{ 1233185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 1234185377Ssam struct ar5212NfCalHist *h = &ahp->ah_nfCalHist; 1235187831Ssam HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 1236185377Ssam int16_t nf, nfThresh; 1237185377Ssam int32_t val; 1238185377Ssam 1239185377Ssam if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 1240185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 1241185377Ssam "%s: NF did not complete in calibration window\n", __func__); 1242187831Ssam ichan->rawNoiseFloor = h->privNF; /* most recent value */ 1243187831Ssam return ichan->rawNoiseFloor; 1244185377Ssam } 1245185377Ssam 1246185377Ssam /* 1247185377Ssam * Finished NF cal, check against threshold. 1248185377Ssam */ 1249185377Ssam nf = ar5212GetNoiseFloor(ah); 1250185377Ssam if (getNoiseFloorThresh(ah, chan, &nfThresh)) { 1251185377Ssam if (nf > nfThresh) { 1252185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 1253185377Ssam "%s: noise floor failed detected; detected %u, " 1254185377Ssam "threshold %u\n", __func__, nf, nfThresh); 1255185377Ssam /* 1256185377Ssam * NB: Don't discriminate 2.4 vs 5Ghz, if this 1257185377Ssam * happens it indicates a problem regardless 1258185377Ssam * of the band. 1259185377Ssam */ 1260187831Ssam chan->ic_state |= IEEE80211_CHANSTATE_CWINT; 1261185377Ssam nf = 0; 1262185377Ssam } 1263185377Ssam } else 1264185377Ssam nf = 0; 1265185377Ssam 1266185377Ssam /* 1267185377Ssam * Pass through histogram and write median value as 1268185377Ssam * calculated from the accrued window. We require a 1269185377Ssam * full window of in-range values to be seen before we 1270185377Ssam * start using the history. 1271185377Ssam */ 1272185377Ssam updateNFHistBuff(h, nf); 1273185377Ssam if (h->first_run) { 1274185377Ssam if (nf < AR5212_CCA_MIN_BAD_VALUE || 1275185377Ssam nf > AR5212_CCA_MAX_HIGH_VALUE) { 1276185377Ssam nf = AR5212_CCA_MAX_GOOD_VALUE; 1277185377Ssam h->invalidNFcount = AR512_NF_CAL_HIST_MAX; 1278185377Ssam } else if (--(h->invalidNFcount) == 0) { 1279185377Ssam h->first_run = 0; 1280185377Ssam h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer); 1281185377Ssam } else { 1282185377Ssam nf = AR5212_CCA_MAX_GOOD_VALUE; 1283185377Ssam } 1284185377Ssam } else { 1285185377Ssam h->privNF = nf = ar5212GetNfHistMid(h->nfCalBuffer); 1286185377Ssam } 1287185377Ssam 1288185377Ssam val = OS_REG_READ(ah, AR_PHY(25)); 1289185377Ssam val &= 0xFFFFFE00; 1290185377Ssam val |= (((uint32_t)nf << 1) & 0x1FF); 1291185377Ssam OS_REG_WRITE(ah, AR_PHY(25), val); 1292185377Ssam OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 1293185377Ssam OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 1294185377Ssam OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 1295185377Ssam 1296185377Ssam if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF, 0)) { 1297185377Ssam#ifdef AH_DEBUG 1298185377Ssam ath_hal_printf(ah, "%s: AGC not ready AGC_CONTROL 0x%x\n", 1299185377Ssam __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL)); 1300185377Ssam#endif 1301185377Ssam } 1302185377Ssam 1303185377Ssam /* 1304185377Ssam * Now load a high maxCCAPower value again so that we're 1305185377Ssam * not capped by the median we just loaded 1306185377Ssam */ 1307185377Ssam val &= 0xFFFFFE00; 1308185377Ssam val |= (((uint32_t)(-50) << 1) & 0x1FF); 1309185377Ssam OS_REG_WRITE(ah, AR_PHY(25), val); 1310185377Ssam OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); 1311185377Ssam OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); 1312185377Ssam OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); 1313185377Ssam 1314187831Ssam return (ichan->rawNoiseFloor = nf); 1315185377Ssam} 1316185377Ssam 1317185377Ssam/* 1318185377Ssam * Set up compression configuration registers 1319185377Ssam */ 1320185377Ssamvoid 1321185377Ssamar5212SetCompRegs(struct ath_hal *ah) 1322185377Ssam{ 1323185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 1324185377Ssam int i; 1325185377Ssam 1326185377Ssam /* Check if h/w supports compression */ 1327185377Ssam if (!AH_PRIVATE(ah)->ah_caps.halCompressSupport) 1328185377Ssam return; 1329185377Ssam 1330185377Ssam OS_REG_WRITE(ah, AR_DCCFG, 1); 1331185377Ssam 1332185377Ssam OS_REG_WRITE(ah, AR_CCFG, 1333185377Ssam (AR_COMPRESSION_WINDOW_SIZE >> 8) & AR_CCFG_WIN_M); 1334185377Ssam 1335185377Ssam OS_REG_WRITE(ah, AR_CCFG, 1336185377Ssam OS_REG_READ(ah, AR_CCFG) | AR_CCFG_MIB_INT_EN); 1337185377Ssam OS_REG_WRITE(ah, AR_CCUCFG, 1338185377Ssam AR_CCUCFG_RESET_VAL | AR_CCUCFG_CATCHUP_EN); 1339185377Ssam 1340185377Ssam OS_REG_WRITE(ah, AR_CPCOVF, 0); 1341185377Ssam 1342185377Ssam /* reset decompression mask */ 1343185377Ssam for (i = 0; i < HAL_DECOMP_MASK_SIZE; i++) { 1344185377Ssam OS_REG_WRITE(ah, AR_DCM_A, i); 1345185377Ssam OS_REG_WRITE(ah, AR_DCM_D, ahp->ah_decompMask[i]); 1346185377Ssam } 1347185377Ssam} 1348185377Ssam 1349185377SsamHAL_BOOL 1350185377Ssamar5212SetAntennaSwitchInternal(struct ath_hal *ah, HAL_ANT_SETTING settings, 1351187831Ssam const struct ieee80211_channel *chan) 1352185377Ssam{ 1353185377Ssam#define ANT_SWITCH_TABLE1 AR_PHY(88) 1354185377Ssam#define ANT_SWITCH_TABLE2 AR_PHY(89) 1355185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 1356185377Ssam const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1357185377Ssam uint32_t antSwitchA, antSwitchB; 1358185377Ssam int ix; 1359185377Ssam 1360185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 1361185380Ssam HALASSERT(ahp->ah_phyPowerOn); 1362185377Ssam 1363187831Ssam switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) { 1364187831Ssam case IEEE80211_CHAN_A: 1365187831Ssam ix = 0; 1366187831Ssam break; 1367187831Ssam case IEEE80211_CHAN_G: 1368187831Ssam case IEEE80211_CHAN_PUREG: /* NB: 108G */ 1369187831Ssam ix = 2; 1370187831Ssam break; 1371187831Ssam case IEEE80211_CHAN_B: 1372187831Ssam if (IS_2425(ah) || IS_2417(ah)) { 1373187831Ssam /* NB: Nala/Swan: 11b is handled using 11g */ 1374187831Ssam ix = 2; 1375187831Ssam } else 1376187831Ssam ix = 1; 1377187831Ssam break; 1378185377Ssam default: 1379185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1380187831Ssam __func__, chan->ic_flags); 1381185377Ssam return AH_FALSE; 1382185377Ssam } 1383185377Ssam 1384185377Ssam antSwitchA = ee->ee_antennaControl[1][ix] 1385185377Ssam | (ee->ee_antennaControl[2][ix] << 6) 1386185377Ssam | (ee->ee_antennaControl[3][ix] << 12) 1387185377Ssam | (ee->ee_antennaControl[4][ix] << 18) 1388185377Ssam | (ee->ee_antennaControl[5][ix] << 24) 1389185377Ssam ; 1390185377Ssam antSwitchB = ee->ee_antennaControl[6][ix] 1391185377Ssam | (ee->ee_antennaControl[7][ix] << 6) 1392185377Ssam | (ee->ee_antennaControl[8][ix] << 12) 1393185377Ssam | (ee->ee_antennaControl[9][ix] << 18) 1394185377Ssam | (ee->ee_antennaControl[10][ix] << 24) 1395185377Ssam ; 1396185377Ssam /* 1397185377Ssam * For fixed antenna, give the same setting for both switch banks 1398185377Ssam */ 1399185377Ssam switch (settings) { 1400185377Ssam case HAL_ANT_FIXED_A: 1401185377Ssam antSwitchB = antSwitchA; 1402185377Ssam break; 1403185377Ssam case HAL_ANT_FIXED_B: 1404185377Ssam antSwitchA = antSwitchB; 1405185377Ssam break; 1406185377Ssam case HAL_ANT_VARIABLE: 1407185377Ssam break; 1408185377Ssam default: 1409185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad antenna setting %u\n", 1410185377Ssam __func__, settings); 1411185377Ssam return AH_FALSE; 1412185377Ssam } 1413185377Ssam if (antSwitchB == antSwitchA) { 1414185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 1415185377Ssam "%s: Setting fast diversity off.\n", __func__); 1416185377Ssam OS_REG_CLR_BIT(ah,AR_PHY_CCK_DETECT, 1417185377Ssam AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1418185380Ssam ahp->ah_diversity = AH_FALSE; 1419185377Ssam } else { 1420185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 1421185377Ssam "%s: Setting fast diversity on.\n", __func__); 1422185377Ssam OS_REG_SET_BIT(ah,AR_PHY_CCK_DETECT, 1423185377Ssam AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); 1424185380Ssam ahp->ah_diversity = AH_TRUE; 1425185377Ssam } 1426185380Ssam ahp->ah_antControl = settings; 1427185377Ssam 1428185377Ssam OS_REG_WRITE(ah, ANT_SWITCH_TABLE1, antSwitchA); 1429185377Ssam OS_REG_WRITE(ah, ANT_SWITCH_TABLE2, antSwitchB); 1430185377Ssam 1431185377Ssam return AH_TRUE; 1432185377Ssam#undef ANT_SWITCH_TABLE2 1433185377Ssam#undef ANT_SWITCH_TABLE1 1434185377Ssam} 1435185377Ssam 1436185377SsamHAL_BOOL 1437187831Ssamar5212IsSpurChannel(struct ath_hal *ah, const struct ieee80211_channel *chan) 1438185377Ssam{ 1439187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 1440187831Ssam uint32_t clockFreq = 1441187831Ssam ((IS_5413(ah) || IS_RAD5112_ANY(ah) || IS_2417(ah)) ? 40 : 32); 1442187831Ssam return ( ((freq % clockFreq) != 0) 1443187831Ssam && (((freq % clockFreq) < 10) 1444187831Ssam || (((freq) % clockFreq) > 22)) ); 1445185377Ssam} 1446185377Ssam 1447185377Ssam/* 1448185377Ssam * Read EEPROM header info and program the device for correct operation 1449185377Ssam * given the channel value. 1450185377Ssam */ 1451185377SsamHAL_BOOL 1452187831Ssamar5212SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 1453185377Ssam{ 1454185377Ssam#define NO_FALSE_DETECT_BACKOFF 2 1455185377Ssam#define CB22_FALSE_DETECT_BACKOFF 6 1456185377Ssam#define AR_PHY_BIS(_ah, _reg, _mask, _val) \ 1457185377Ssam OS_REG_WRITE(_ah, AR_PHY(_reg), \ 1458185377Ssam (OS_REG_READ(_ah, AR_PHY(_reg)) & _mask) | (_val)); 1459185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 1460185377Ssam const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1461185377Ssam int arrayMode, falseDectectBackoff; 1462187831Ssam int is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 1463187831Ssam HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 1464185377Ssam int8_t adcDesiredSize, pgaDesiredSize; 1465185377Ssam uint16_t switchSettling, txrxAtten, rxtxMargin; 1466185377Ssam int iCoff, qCoff; 1467185377Ssam 1468185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 1469185377Ssam 1470187831Ssam switch (chan->ic_flags & IEEE80211_CHAN_ALLTURBOFULL) { 1471187831Ssam case IEEE80211_CHAN_A: 1472187831Ssam case IEEE80211_CHAN_ST: 1473185377Ssam arrayMode = headerInfo11A; 1474185380Ssam if (!IS_RAD5112_ANY(ah) && !IS_2413(ah) && !IS_5413(ah)) 1475185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, 1476185377Ssam AR_PHY_FRAME_CTL_TX_CLIP, 1477185377Ssam ahp->ah_gainValues.currStep->paramVal[GP_TXCLIP]); 1478185377Ssam break; 1479187831Ssam case IEEE80211_CHAN_B: 1480185377Ssam arrayMode = headerInfo11B; 1481185377Ssam break; 1482187831Ssam case IEEE80211_CHAN_G: 1483187831Ssam case IEEE80211_CHAN_108G: 1484185377Ssam arrayMode = headerInfo11G; 1485185377Ssam break; 1486185377Ssam default: 1487185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n", 1488187831Ssam __func__, chan->ic_flags); 1489185377Ssam return AH_FALSE; 1490185377Ssam } 1491185377Ssam 1492185377Ssam /* Set the antenna register(s) correctly for the chip revision */ 1493185377Ssam AR_PHY_BIS(ah, 68, 0xFFFFFC06, 1494185377Ssam (ee->ee_antennaControl[0][arrayMode] << 4) | 0x1); 1495185377Ssam 1496185380Ssam ar5212SetAntennaSwitchInternal(ah, ahp->ah_antControl, chan); 1497185377Ssam 1498185377Ssam /* Set the Noise Floor Thresh on ar5211 devices */ 1499185377Ssam OS_REG_WRITE(ah, AR_PHY(90), 1500185377Ssam (ee->ee_noiseFloorThresh[arrayMode] & 0x1FF) 1501185377Ssam | (1 << 9)); 1502185377Ssam 1503187831Ssam if (ee->ee_version >= AR_EEPROM_VER5_0 && IEEE80211_IS_CHAN_TURBO(chan)) { 1504185377Ssam switchSettling = ee->ee_switchSettlingTurbo[is2GHz]; 1505185377Ssam adcDesiredSize = ee->ee_adcDesiredSizeTurbo[is2GHz]; 1506185377Ssam pgaDesiredSize = ee->ee_pgaDesiredSizeTurbo[is2GHz]; 1507185377Ssam txrxAtten = ee->ee_txrxAttenTurbo[is2GHz]; 1508185377Ssam rxtxMargin = ee->ee_rxtxMarginTurbo[is2GHz]; 1509185377Ssam } else { 1510185377Ssam switchSettling = ee->ee_switchSettling[arrayMode]; 1511185377Ssam adcDesiredSize = ee->ee_adcDesiredSize[arrayMode]; 1512185377Ssam pgaDesiredSize = ee->ee_pgaDesiredSize[is2GHz]; 1513185377Ssam txrxAtten = ee->ee_txrxAtten[is2GHz]; 1514185377Ssam rxtxMargin = ee->ee_rxtxMargin[is2GHz]; 1515185377Ssam } 1516185377Ssam 1517185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, 1518185377Ssam AR_PHY_SETTLING_SWITCH, switchSettling); 1519185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 1520185377Ssam AR_PHY_DESIRED_SZ_ADC, adcDesiredSize); 1521185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 1522185377Ssam AR_PHY_DESIRED_SZ_PGA, pgaDesiredSize); 1523185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, 1524185377Ssam AR_PHY_RXGAIN_TXRX_ATTEN, txrxAtten); 1525185377Ssam OS_REG_WRITE(ah, AR_PHY(13), 1526185377Ssam (ee->ee_txEndToXPAOff[arrayMode] << 24) 1527185377Ssam | (ee->ee_txEndToXPAOff[arrayMode] << 16) 1528185377Ssam | (ee->ee_txFrameToXPAOn[arrayMode] << 8) 1529185377Ssam | ee->ee_txFrameToXPAOn[arrayMode]); 1530185377Ssam AR_PHY_BIS(ah, 10, 0xFFFF00FF, 1531185377Ssam ee->ee_txEndToXLNAOn[arrayMode] << 8); 1532185377Ssam AR_PHY_BIS(ah, 25, 0xFFF80FFF, 1533185377Ssam (ee->ee_thresh62[arrayMode] << 12) & 0x7F000); 1534185377Ssam 1535185377Ssam /* 1536185377Ssam * False detect backoff - suspected 32 MHz spur causes false 1537185377Ssam * detects in OFDM, causing Tx Hangs. Decrease weak signal 1538185377Ssam * sensitivity for this card. 1539185377Ssam */ 1540185377Ssam falseDectectBackoff = NO_FALSE_DETECT_BACKOFF; 1541185377Ssam if (ee->ee_version < AR_EEPROM_VER3_3) { 1542185377Ssam /* XXX magic number */ 1543185377Ssam if (AH_PRIVATE(ah)->ah_subvendorid == 0x1022 && 1544187831Ssam IEEE80211_IS_CHAN_OFDM(chan)) 1545185377Ssam falseDectectBackoff += CB22_FALSE_DETECT_BACKOFF; 1546185377Ssam } else { 1547187831Ssam if (ar5212IsSpurChannel(ah, chan)) 1548185377Ssam falseDectectBackoff += ee->ee_falseDetectBackoff[arrayMode]; 1549185377Ssam } 1550185377Ssam AR_PHY_BIS(ah, 73, 0xFFFFFF01, (falseDectectBackoff << 1) & 0xFE); 1551185377Ssam 1552187831Ssam if (ichan->privFlags & CHANNEL_IQVALID) { 1553187831Ssam iCoff = ichan->iCoff; 1554187831Ssam qCoff = ichan->qCoff; 1555185377Ssam } else { 1556185377Ssam iCoff = ee->ee_iqCalI[is2GHz]; 1557185377Ssam qCoff = ee->ee_iqCalQ[is2GHz]; 1558185377Ssam } 1559185377Ssam 1560185377Ssam /* write previous IQ results */ 1561185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1562185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, iCoff); 1563185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, 1564185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, qCoff); 1565185377Ssam OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, 1566185377Ssam AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); 1567185377Ssam 1568185377Ssam if (ee->ee_version >= AR_EEPROM_VER4_1) { 1569187831Ssam if (!IEEE80211_IS_CHAN_108G(chan) || ee->ee_version >= AR_EEPROM_VER5_0) 1570185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, 1571185377Ssam AR_PHY_GAIN_2GHZ_RXTX_MARGIN, rxtxMargin); 1572185377Ssam } 1573185377Ssam if (ee->ee_version >= AR_EEPROM_VER5_1) { 1574185377Ssam /* for now always disabled */ 1575185377Ssam OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_ENABLE, 0); 1576185377Ssam } 1577185377Ssam 1578185377Ssam return AH_TRUE; 1579185377Ssam#undef AR_PHY_BIS 1580185377Ssam#undef NO_FALSE_DETECT_BACKOFF 1581185377Ssam#undef CB22_FALSE_DETECT_BACKOFF 1582185377Ssam} 1583185377Ssam 1584185377Ssam/* 1585185377Ssam * Apply Spur Immunity to Boards that require it. 1586185377Ssam * Applies only to OFDM RX operation. 1587185377Ssam */ 1588185377Ssam 1589185377Ssamvoid 1590187831Ssamar5212SetSpurMitigation(struct ath_hal *ah, 1591187831Ssam const struct ieee80211_channel *chan) 1592185377Ssam{ 1593185377Ssam uint32_t pilotMask[2] = {0, 0}, binMagMask[4] = {0, 0, 0 , 0}; 1594185377Ssam uint16_t i, finalSpur, curChanAsSpur, binWidth = 0, spurDetectWidth, spurChan; 1595185377Ssam int32_t spurDeltaPhase = 0, spurFreqSd = 0, spurOffset, binOffsetNumT16, curBinOffset; 1596185377Ssam int16_t numBinOffsets; 1597185377Ssam static const uint16_t magMapFor4[4] = {1, 2, 2, 1}; 1598185377Ssam static const uint16_t magMapFor3[3] = {1, 2, 1}; 1599185377Ssam const uint16_t *pMagMap; 1600187831Ssam HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 1601187831Ssam HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 1602185377Ssam uint32_t val; 1603185377Ssam 1604185377Ssam#define CHAN_TO_SPUR(_f, _freq) ( ((_freq) - ((_f) ? 2300 : 4900)) * 10 ) 1605185377Ssam if (IS_2417(ah)) { 1606185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: no spur mitigation\n", 1607185377Ssam __func__); 1608185377Ssam return; 1609185377Ssam } 1610185377Ssam 1611185377Ssam curChanAsSpur = CHAN_TO_SPUR(is2GHz, ichan->channel); 1612185377Ssam 1613185377Ssam if (ichan->mainSpur) { 1614185377Ssam /* Pull out the saved spur value */ 1615185377Ssam finalSpur = ichan->mainSpur; 1616185377Ssam } else { 1617185377Ssam /* 1618185377Ssam * Check if spur immunity should be performed for this channel 1619185377Ssam * Should only be performed once per channel and then saved 1620185377Ssam */ 1621185377Ssam finalSpur = AR_NO_SPUR; 1622185377Ssam spurDetectWidth = HAL_SPUR_CHAN_WIDTH; 1623187831Ssam if (IEEE80211_IS_CHAN_TURBO(chan)) 1624185377Ssam spurDetectWidth *= 2; 1625185377Ssam 1626185377Ssam /* Decide if any spur affects the current channel */ 1627185377Ssam for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 1628185377Ssam spurChan = ath_hal_getSpurChan(ah, i, is2GHz); 1629185377Ssam if (spurChan == AR_NO_SPUR) { 1630185377Ssam break; 1631185377Ssam } 1632185377Ssam if ((curChanAsSpur - spurDetectWidth <= (spurChan & HAL_SPUR_VAL_MASK)) && 1633185377Ssam (curChanAsSpur + spurDetectWidth >= (spurChan & HAL_SPUR_VAL_MASK))) { 1634185377Ssam finalSpur = spurChan & HAL_SPUR_VAL_MASK; 1635185377Ssam break; 1636185377Ssam } 1637185377Ssam } 1638185377Ssam /* Save detected spur (or no spur) for this channel */ 1639185377Ssam ichan->mainSpur = finalSpur; 1640185377Ssam } 1641185377Ssam 1642185377Ssam /* Write spur immunity data */ 1643185377Ssam if (finalSpur == AR_NO_SPUR) { 1644185377Ssam /* Disable Spur Immunity Regs if they appear set */ 1645185377Ssam if (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER) { 1646185377Ssam /* Clear Spur Delta Phase, Spur Freq, and enable bits */ 1647185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0); 1648185377Ssam val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4); 1649185377Ssam val &= ~(AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 1650185377Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 1651185377Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 1652185377Ssam OS_REG_WRITE(ah, AR_PHY_MASK_CTL, val); 1653185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, 0); 1654185377Ssam 1655185377Ssam /* Clear pilot masks */ 1656185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING7, 0); 1657185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, 0); 1658185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING9, 0); 1659185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, 0); 1660185377Ssam 1661185377Ssam /* Clear magnitude masks */ 1662185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, 0); 1663185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, 0); 1664185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, 0); 1665185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, 0); 1666185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, 0); 1667185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, 0); 1668185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, 0); 1669185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, 0); 1670185377Ssam } 1671185377Ssam } else { 1672185377Ssam spurOffset = finalSpur - curChanAsSpur; 1673185377Ssam /* 1674185377Ssam * Spur calculations: 1675185377Ssam * spurDeltaPhase is (spurOffsetIn100KHz / chipFrequencyIn100KHz) << 21 1676185377Ssam * spurFreqSd is (spurOffsetIn100KHz / sampleFrequencyIn100KHz) << 11 1677185377Ssam */ 1678187831Ssam if (IEEE80211_IS_CHAN_TURBO(chan)) { 1679187831Ssam /* Chip Frequency & sampleFrequency are 80 MHz */ 1680187831Ssam spurDeltaPhase = (spurOffset << 16) / 25; 1681185377Ssam spurFreqSd = spurDeltaPhase >> 10; 1682187831Ssam binWidth = HAL_BIN_WIDTH_TURBO_100HZ; 1683187831Ssam } else if (IEEE80211_IS_CHAN_G(chan)) { 1684187831Ssam /* Chip Frequency is 44MHz, sampleFrequency is 40 MHz */ 1685185377Ssam spurFreqSd = (spurOffset << 8) / 55; 1686185377Ssam spurDeltaPhase = (spurOffset << 17) / 25; 1687185377Ssam binWidth = HAL_BIN_WIDTH_BASE_100HZ; 1688187831Ssam } else { 1689187831Ssam HALASSERT(!IEEE80211_IS_CHAN_B(chan)); 1690187831Ssam /* Chip Frequency & sampleFrequency are 40 MHz */ 1691187831Ssam spurDeltaPhase = (spurOffset << 17) / 25; 1692185377Ssam spurFreqSd = spurDeltaPhase >> 10; 1693187831Ssam binWidth = HAL_BIN_WIDTH_BASE_100HZ; 1694185377Ssam } 1695185377Ssam 1696185377Ssam /* Compute Pilot Mask */ 1697185377Ssam binOffsetNumT16 = ((spurOffset * 1000) << 4) / binWidth; 1698185377Ssam /* The spur is on a bin if it's remainder at times 16 is 0 */ 1699185377Ssam if (binOffsetNumT16 & 0xF) { 1700185377Ssam numBinOffsets = 4; 1701185377Ssam pMagMap = magMapFor4; 1702185377Ssam } else { 1703185377Ssam numBinOffsets = 3; 1704185377Ssam pMagMap = magMapFor3; 1705185377Ssam } 1706185377Ssam for (i = 0; i < numBinOffsets; i++) { 1707185377Ssam if ((binOffsetNumT16 >> 4) > HAL_MAX_BINS_ALLOWED) { 1708185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 1709185377Ssam "Too man bins in spur mitigation\n"); 1710185377Ssam return; 1711185377Ssam } 1712185377Ssam 1713185377Ssam /* Get Pilot Mask values */ 1714185377Ssam curBinOffset = (binOffsetNumT16 >> 4) + i + 25; 1715185377Ssam if ((curBinOffset >= 0) && (curBinOffset <= 32)) { 1716185377Ssam if (curBinOffset <= 25) 1717185377Ssam pilotMask[0] |= 1 << curBinOffset; 1718185377Ssam else if (curBinOffset >= 27) 1719185377Ssam pilotMask[0] |= 1 << (curBinOffset - 1); 1720185377Ssam } else if ((curBinOffset >= 33) && (curBinOffset <= 52)) 1721185377Ssam pilotMask[1] |= 1 << (curBinOffset - 33); 1722185377Ssam 1723185377Ssam /* Get viterbi values */ 1724185377Ssam if ((curBinOffset >= -1) && (curBinOffset <= 14)) 1725185377Ssam binMagMask[0] |= pMagMap[i] << (curBinOffset + 1) * 2; 1726185377Ssam else if ((curBinOffset >= 15) && (curBinOffset <= 30)) 1727185377Ssam binMagMask[1] |= pMagMap[i] << (curBinOffset - 15) * 2; 1728185377Ssam else if ((curBinOffset >= 31) && (curBinOffset <= 46)) 1729185377Ssam binMagMask[2] |= pMagMap[i] << (curBinOffset -31) * 2; 1730185377Ssam else if((curBinOffset >= 47) && (curBinOffset <= 53)) 1731185377Ssam binMagMask[3] |= pMagMap[i] << (curBinOffset -47) * 2; 1732185377Ssam } 1733185377Ssam 1734185377Ssam /* Write Spur Delta Phase, Spur Freq, and enable bits */ 1735185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_RATE, 0xFF); 1736185377Ssam val = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4); 1737185377Ssam val |= (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 1738185377Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 1739185377Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 1740185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, val); 1741185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_USE_SPUR_IN_AGC | 1742185377Ssam SM(spurFreqSd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 1743185377Ssam SM(spurDeltaPhase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 1744185377Ssam 1745185377Ssam /* Write pilot masks */ 1746185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING7, pilotMask[0]); 1747185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING8, AR_PHY_TIMING8_PILOT_MASK_2, pilotMask[1]); 1748185377Ssam OS_REG_WRITE(ah, AR_PHY_TIMING9, pilotMask[0]); 1749185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING10, AR_PHY_TIMING10_PILOT_MASK_2, pilotMask[1]); 1750185377Ssam 1751185377Ssam /* Write magnitude masks */ 1752185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, binMagMask[0]); 1753185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, binMagMask[1]); 1754185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, binMagMask[2]); 1755185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_MASK_CTL, AR_PHY_MASK_CTL_MASK_4, binMagMask[3]); 1756185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, binMagMask[0]); 1757185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, binMagMask[1]); 1758185377Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, binMagMask[2]); 1759185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK2_4_MASK_4, binMagMask[3]); 1760185377Ssam } 1761185377Ssam#undef CHAN_TO_SPUR 1762185377Ssam} 1763185377Ssam 1764185377Ssam 1765185377Ssam/* 1766185377Ssam * Delta slope coefficient computation. 1767185377Ssam * Required for OFDM operation. 1768185377Ssam */ 1769185377Ssamvoid 1770187831Ssamar5212SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan) 1771185377Ssam{ 1772185377Ssam#define COEF_SCALE_S 24 1773185377Ssam#define INIT_CLOCKMHZSCALED 0x64000000 1774187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 1775185377Ssam unsigned long coef_scaled, coef_exp, coef_man, ds_coef_exp, ds_coef_man; 1776185377Ssam unsigned long clockMhzScaled = INIT_CLOCKMHZSCALED; 1777185377Ssam 1778187831Ssam if (IEEE80211_IS_CHAN_TURBO(chan)) 1779185377Ssam clockMhzScaled *= 2; 1780185377Ssam /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */ 1781185377Ssam /* scale for selected channel bandwidth */ 1782187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) { 1783185377Ssam clockMhzScaled = clockMhzScaled >> 1; 1784187831Ssam } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 1785185377Ssam clockMhzScaled = clockMhzScaled >> 2; 1786185377Ssam } 1787185377Ssam 1788185377Ssam /* 1789185377Ssam * ALGO -> coef = 1e8/fcarrier*fclock/40; 1790185377Ssam * scaled coef to provide precision for this floating calculation 1791185377Ssam */ 1792187831Ssam coef_scaled = clockMhzScaled / freq; 1793185377Ssam 1794185377Ssam /* 1795185377Ssam * ALGO -> coef_exp = 14-floor(log2(coef)); 1796185377Ssam * floor(log2(x)) is the highest set bit position 1797185377Ssam */ 1798185377Ssam for (coef_exp = 31; coef_exp > 0; coef_exp--) 1799185377Ssam if ((coef_scaled >> coef_exp) & 0x1) 1800185377Ssam break; 1801185377Ssam /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */ 1802185377Ssam HALASSERT(coef_exp); 1803185377Ssam coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1804185377Ssam 1805185377Ssam /* 1806185377Ssam * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5); 1807185377Ssam * The coefficient is already shifted up for scaling 1808185377Ssam */ 1809185377Ssam coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1810185377Ssam ds_coef_man = coef_man >> (COEF_SCALE_S - coef_exp); 1811185377Ssam ds_coef_exp = coef_exp - 16; 1812185377Ssam 1813185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1814185377Ssam AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 1815185377Ssam OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 1816185377Ssam AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 1817185377Ssam#undef INIT_CLOCKMHZSCALED 1818185377Ssam#undef COEF_SCALE_S 1819185377Ssam} 1820185377Ssam 1821185377Ssam/* 1822185377Ssam * Set a limit on the overall output power. Used for dynamic 1823185377Ssam * transmit power control and the like. 1824185377Ssam * 1825185377Ssam * NB: limit is in units of 0.5 dbM. 1826185377Ssam */ 1827185377SsamHAL_BOOL 1828185377Ssamar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 1829185377Ssam{ 1830187831Ssam /* XXX blech, construct local writable copy */ 1831187831Ssam struct ieee80211_channel dummy = *AH_PRIVATE(ah)->ah_curchan; 1832185377Ssam uint16_t dummyXpdGains[2]; 1833187831Ssam HAL_BOOL isBmode; 1834185377Ssam 1835187831Ssam SAVE_CCK(ah, &dummy, isBmode); 1836185377Ssam AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); 1837187831Ssam return ar5212SetTransmitPower(ah, &dummy, dummyXpdGains); 1838185377Ssam} 1839185377Ssam 1840185377Ssam/* 1841185377Ssam * Set the transmit power in the baseband for the given 1842185377Ssam * operating channel and mode. 1843185377Ssam */ 1844185377SsamHAL_BOOL 1845187831Ssamar5212SetTransmitPower(struct ath_hal *ah, 1846187831Ssam const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 1847185377Ssam{ 1848185377Ssam#define POW_OFDM(_r, _s) (((0 & 1)<< ((_s)+6)) | (((_r) & 0x3f) << (_s))) 1849185377Ssam#define POW_CCK(_r, _s) (((_r) & 0x3f) << (_s)) 1850185377Ssam#define N(a) (sizeof (a) / sizeof (a[0])) 1851185377Ssam static const uint16_t tpcScaleReductionTable[5] = 1852185377Ssam { 0, 3, 6, 9, MAX_RATE_POWER }; 1853185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 1854187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 1855185377Ssam const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1856185377Ssam int16_t minPower, maxPower, tpcInDb, powerLimit; 1857185377Ssam int i; 1858185377Ssam 1859185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 1860185377Ssam 1861185377Ssam OS_MEMZERO(ahp->ah_pcdacTable, ahp->ah_pcdacTableSize); 1862185377Ssam OS_MEMZERO(ahp->ah_ratesArray, sizeof(ahp->ah_ratesArray)); 1863185377Ssam 1864185377Ssam powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 1865185377Ssam if (powerLimit >= MAX_RATE_POWER || powerLimit == 0) 1866185377Ssam tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 1867185377Ssam else 1868185377Ssam tpcInDb = 0; 1869187831Ssam if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit, 1870185377Ssam AH_TRUE, &minPower, &maxPower)) { 1871185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set rate table\n", 1872185377Ssam __func__); 1873185377Ssam return AH_FALSE; 1874185377Ssam } 1875185377Ssam if (!ahp->ah_rfHal->setPowerTable(ah, 1876185377Ssam &minPower, &maxPower, chan, rfXpdGain)) { 1877185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 1878185377Ssam __func__); 1879185377Ssam return AH_FALSE; 1880185377Ssam } 1881185377Ssam 1882185377Ssam /* 1883185377Ssam * Adjust XR power/rate up by 2 dB to account for greater peak 1884185377Ssam * to avg ratio - except in newer avg power designs 1885185377Ssam */ 1886185377Ssam if (!IS_2413(ah) && !IS_5413(ah)) 1887185377Ssam ahp->ah_ratesArray[15] += 4; 1888185377Ssam /* 1889185377Ssam * txPowerIndexOffset is set by the SetPowerTable() call - 1890185377Ssam * adjust the rate table 1891185377Ssam */ 1892185377Ssam for (i = 0; i < N(ahp->ah_ratesArray); i++) { 1893185377Ssam ahp->ah_ratesArray[i] += ahp->ah_txPowerIndexOffset; 1894185377Ssam if (ahp->ah_ratesArray[i] > 63) 1895185377Ssam ahp->ah_ratesArray[i] = 63; 1896185377Ssam } 1897185377Ssam 1898185377Ssam if (ee->ee_eepMap < 2) { 1899185377Ssam /* 1900185377Ssam * Correct gain deltas for 5212 G operation - 1901185377Ssam * Removed with revised chipset 1902185377Ssam */ 1903185377Ssam if (AH_PRIVATE(ah)->ah_phyRev < AR_PHY_CHIP_ID_REV_2 && 1904187831Ssam IEEE80211_IS_CHAN_G(chan)) { 1905185377Ssam uint16_t cckOfdmPwrDelta; 1906185377Ssam 1907187831Ssam if (freq == 2484) 1908185377Ssam cckOfdmPwrDelta = SCALE_OC_DELTA( 1909185377Ssam ee->ee_cckOfdmPwrDelta - 1910185377Ssam ee->ee_scaledCh14FilterCckDelta); 1911185377Ssam else 1912185377Ssam cckOfdmPwrDelta = SCALE_OC_DELTA( 1913185377Ssam ee->ee_cckOfdmPwrDelta); 1914185377Ssam ar5212CorrectGainDelta(ah, cckOfdmPwrDelta); 1915185377Ssam } 1916185377Ssam /* 1917185377Ssam * Finally, write the power values into the 1918185377Ssam * baseband power table 1919185377Ssam */ 1920185377Ssam for (i = 0; i < (PWR_TABLE_SIZE/2); i++) { 1921185377Ssam OS_REG_WRITE(ah, AR_PHY_PCDAC_TX_POWER(i), 1922185377Ssam ((((ahp->ah_pcdacTable[2*i + 1] << 8) | 0xff) & 0xffff) << 16) 1923185377Ssam | (((ahp->ah_pcdacTable[2*i] << 8) | 0xff) & 0xffff) 1924185377Ssam ); 1925185377Ssam } 1926185377Ssam } 1927185377Ssam 1928185377Ssam /* Write the OFDM power per rate set */ 1929185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 1930185377Ssam POW_OFDM(ahp->ah_ratesArray[3], 24) 1931185377Ssam | POW_OFDM(ahp->ah_ratesArray[2], 16) 1932185377Ssam | POW_OFDM(ahp->ah_ratesArray[1], 8) 1933185377Ssam | POW_OFDM(ahp->ah_ratesArray[0], 0) 1934185377Ssam ); 1935185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 1936185377Ssam POW_OFDM(ahp->ah_ratesArray[7], 24) 1937185377Ssam | POW_OFDM(ahp->ah_ratesArray[6], 16) 1938185377Ssam | POW_OFDM(ahp->ah_ratesArray[5], 8) 1939185377Ssam | POW_OFDM(ahp->ah_ratesArray[4], 0) 1940185377Ssam ); 1941185377Ssam 1942185377Ssam /* Write the CCK power per rate set */ 1943185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 1944185377Ssam POW_CCK(ahp->ah_ratesArray[10], 24) 1945185377Ssam | POW_CCK(ahp->ah_ratesArray[9], 16) 1946185377Ssam | POW_CCK(ahp->ah_ratesArray[15], 8) /* XR target power */ 1947185377Ssam | POW_CCK(ahp->ah_ratesArray[8], 0) 1948185377Ssam ); 1949185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 1950185377Ssam POW_CCK(ahp->ah_ratesArray[14], 24) 1951185377Ssam | POW_CCK(ahp->ah_ratesArray[13], 16) 1952185377Ssam | POW_CCK(ahp->ah_ratesArray[12], 8) 1953185377Ssam | POW_CCK(ahp->ah_ratesArray[11], 0) 1954185377Ssam ); 1955185377Ssam 1956185377Ssam /* 1957185377Ssam * Set max power to 30 dBm and, optionally, 1958185377Ssam * enable TPC in tx descriptors. 1959185377Ssam */ 1960185377Ssam OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER | 1961185377Ssam (ahp->ah_tpcEnabled ? AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE : 0)); 1962185377Ssam 1963185377Ssam return AH_TRUE; 1964185377Ssam#undef N 1965185377Ssam#undef POW_CCK 1966185377Ssam#undef POW_OFDM 1967185377Ssam} 1968185377Ssam 1969185377Ssam/* 1970185377Ssam * Sets the transmit power in the baseband for the given 1971185377Ssam * operating channel and mode. 1972185377Ssam */ 1973185377Ssamstatic HAL_BOOL 1974187831Ssamar5212SetRateTable(struct ath_hal *ah, const struct ieee80211_channel *chan, 1975187831Ssam int16_t tpcScaleReduction, int16_t powerLimit, HAL_BOOL commit, 1976187831Ssam int16_t *pMinPower, int16_t *pMaxPower) 1977185377Ssam{ 1978185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 1979187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 1980185377Ssam const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 1981185377Ssam uint16_t *rpow = ahp->ah_ratesArray; 1982185377Ssam uint16_t twiceMaxEdgePower = MAX_RATE_POWER; 1983185377Ssam uint16_t twiceMaxEdgePowerCck = MAX_RATE_POWER; 1984185377Ssam uint16_t twiceMaxRDPower = MAX_RATE_POWER; 1985185377Ssam int i; 1986185377Ssam uint8_t cfgCtl; 1987185377Ssam int8_t twiceAntennaGain, twiceAntennaReduction; 1988185377Ssam const RD_EDGES_POWER *rep; 1989185377Ssam TRGT_POWER_INFO targetPowerOfdm, targetPowerCck; 1990185377Ssam int16_t scaledPower, maxAvailPower = 0; 1991185377Ssam int16_t r13, r9, r7, r0; 1992185377Ssam 1993185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 1994185377Ssam 1995187831Ssam twiceMaxRDPower = chan->ic_maxregpower * 2; 1996185377Ssam *pMaxPower = -MAX_RATE_POWER; 1997185377Ssam *pMinPower = MAX_RATE_POWER; 1998185377Ssam 1999185377Ssam /* Get conformance test limit maximum for this channel */ 2000185377Ssam cfgCtl = ath_hal_getctl(ah, chan); 2001185377Ssam for (i = 0; i < ee->ee_numCtls; i++) { 2002185377Ssam uint16_t twiceMinEdgePower; 2003185377Ssam 2004185377Ssam if (ee->ee_ctl[i] == 0) 2005185377Ssam continue; 2006185377Ssam if (ee->ee_ctl[i] == cfgCtl || 2007185377Ssam cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) { 2008185377Ssam rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 2009187831Ssam twiceMinEdgePower = ar5212GetMaxEdgePower(freq, rep); 2010185377Ssam if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 2011185377Ssam /* Find the minimum of all CTL edge powers that apply to this channel */ 2012185377Ssam twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 2013185377Ssam } else { 2014185377Ssam twiceMaxEdgePower = twiceMinEdgePower; 2015185377Ssam break; 2016185377Ssam } 2017185377Ssam } 2018185377Ssam } 2019185377Ssam 2020187831Ssam if (IEEE80211_IS_CHAN_G(chan)) { 2021185377Ssam /* Check for a CCK CTL for 11G CCK powers */ 2022185377Ssam cfgCtl = (cfgCtl & ~CTL_MODE_M) | CTL_11B; 2023185377Ssam for (i = 0; i < ee->ee_numCtls; i++) { 2024185377Ssam uint16_t twiceMinEdgePowerCck; 2025185377Ssam 2026185377Ssam if (ee->ee_ctl[i] == 0) 2027185377Ssam continue; 2028185377Ssam if (ee->ee_ctl[i] == cfgCtl || 2029185377Ssam cfgCtl == ((ee->ee_ctl[i] & CTL_MODE_M) | SD_NO_CTL)) { 2030185377Ssam rep = &ee->ee_rdEdgesPower[i * NUM_EDGES]; 2031187831Ssam twiceMinEdgePowerCck = ar5212GetMaxEdgePower(freq, rep); 2032185377Ssam if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 2033185377Ssam /* Find the minimum of all CTL edge powers that apply to this channel */ 2034185377Ssam twiceMaxEdgePowerCck = AH_MIN(twiceMaxEdgePowerCck, twiceMinEdgePowerCck); 2035185377Ssam } else { 2036185377Ssam twiceMaxEdgePowerCck = twiceMinEdgePowerCck; 2037185377Ssam break; 2038185377Ssam } 2039185377Ssam } 2040185377Ssam } 2041185377Ssam } else { 2042185377Ssam /* Set the 11B cck edge power to the one found before */ 2043185377Ssam twiceMaxEdgePowerCck = twiceMaxEdgePower; 2044185377Ssam } 2045185377Ssam 2046185377Ssam /* Get Antenna Gain reduction */ 2047187831Ssam if (IEEE80211_IS_CHAN_5GHZ(chan)) { 2048185377Ssam ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_5, &twiceAntennaGain); 2049185377Ssam } else { 2050185377Ssam ath_hal_eepromGet(ah, AR_EEP_ANTGAINMAX_2, &twiceAntennaGain); 2051185377Ssam } 2052185377Ssam twiceAntennaReduction = 2053185377Ssam ath_hal_getantennareduction(ah, chan, twiceAntennaGain); 2054185377Ssam 2055187831Ssam if (IEEE80211_IS_CHAN_OFDM(chan)) { 2056185377Ssam /* Get final OFDM target powers */ 2057187831Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 2058185377Ssam ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11g, 2059185377Ssam ee->ee_numTargetPwr_11g, &targetPowerOfdm); 2060185377Ssam } else { 2061185377Ssam ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11a, 2062185377Ssam ee->ee_numTargetPwr_11a, &targetPowerOfdm); 2063185377Ssam } 2064185377Ssam 2065185377Ssam /* Get Maximum OFDM power */ 2066185377Ssam /* Minimum of target and edge powers */ 2067185377Ssam scaledPower = AH_MIN(twiceMaxEdgePower, 2068185377Ssam twiceMaxRDPower - twiceAntennaReduction); 2069185377Ssam 2070185377Ssam /* 2071185377Ssam * If turbo is set, reduce power to keep power 2072185377Ssam * consumption under 2 Watts. Note that we always do 2073185377Ssam * this unless specially configured. Then we limit 2074185377Ssam * power only for non-AP operation. 2075185377Ssam */ 2076187831Ssam if (IEEE80211_IS_CHAN_TURBO(chan) 2077185377Ssam#ifdef AH_ENABLE_AP_SUPPORT 2078185377Ssam && AH_PRIVATE(ah)->ah_opmode != HAL_M_HOSTAP 2079185377Ssam#endif 2080185377Ssam ) { 2081185377Ssam /* 2082185377Ssam * If turbo is set, reduce power to keep power 2083185377Ssam * consumption under 2 Watts 2084185377Ssam */ 2085185377Ssam if (ee->ee_version >= AR_EEPROM_VER3_1) 2086185377Ssam scaledPower = AH_MIN(scaledPower, 2087185377Ssam ee->ee_turbo2WMaxPower5); 2088185377Ssam /* 2089185377Ssam * EEPROM version 4.0 added an additional 2090185377Ssam * constraint on 2.4GHz channels. 2091185377Ssam */ 2092185377Ssam if (ee->ee_version >= AR_EEPROM_VER4_0 && 2093187831Ssam IEEE80211_IS_CHAN_2GHZ(chan)) 2094185377Ssam scaledPower = AH_MIN(scaledPower, 2095185377Ssam ee->ee_turbo2WMaxPower2); 2096185377Ssam } 2097185377Ssam 2098185377Ssam maxAvailPower = AH_MIN(scaledPower, 2099185377Ssam targetPowerOfdm.twicePwr6_24); 2100185377Ssam 2101185377Ssam /* Reduce power by max regulatory domain allowed restrictions */ 2102185377Ssam scaledPower = maxAvailPower - (tpcScaleReduction * 2); 2103185377Ssam scaledPower = (scaledPower < 0) ? 0 : scaledPower; 2104185377Ssam scaledPower = AH_MIN(scaledPower, powerLimit); 2105185377Ssam 2106185377Ssam if (commit) { 2107185377Ssam /* Set OFDM rates 9, 12, 18, 24 */ 2108185377Ssam r0 = rpow[0] = rpow[1] = rpow[2] = rpow[3] = rpow[4] = scaledPower; 2109185377Ssam 2110185377Ssam /* Set OFDM rates 36, 48, 54, XR */ 2111185377Ssam rpow[5] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr36); 2112185377Ssam rpow[6] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr48); 2113185377Ssam r7 = rpow[7] = AH_MIN(rpow[0], targetPowerOfdm.twicePwr54); 2114185377Ssam 2115185377Ssam if (ee->ee_version >= AR_EEPROM_VER4_0) { 2116185377Ssam /* Setup XR target power from EEPROM */ 2117187831Ssam rpow[15] = AH_MIN(scaledPower, IEEE80211_IS_CHAN_2GHZ(chan) ? 2118185377Ssam ee->ee_xrTargetPower2 : ee->ee_xrTargetPower5); 2119185377Ssam } else { 2120185377Ssam /* XR uses 6mb power */ 2121185377Ssam rpow[15] = rpow[0]; 2122185377Ssam } 2123185377Ssam ahp->ah_ofdmTxPower = *pMaxPower; 2124185377Ssam 2125185377Ssam } else { 2126185377Ssam r0 = scaledPower; 2127185377Ssam r7 = AH_MIN(r0, targetPowerOfdm.twicePwr54); 2128185377Ssam } 2129185377Ssam *pMinPower = r7; 2130185377Ssam *pMaxPower = r0; 2131185377Ssam 2132185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2133185377Ssam "%s: MaxRD: %d TurboMax: %d MaxCTL: %d " 2134185377Ssam "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n", 2135185377Ssam __func__, twiceMaxRDPower, ee->ee_turbo2WMaxPower5, 2136185377Ssam twiceMaxEdgePower, tpcScaleReduction * 2, 2137187831Ssam chan->ic_freq, chan->ic_flags, 2138185377Ssam maxAvailPower, targetPowerOfdm.twicePwr6_24, *pMaxPower); 2139185377Ssam } 2140185377Ssam 2141187831Ssam if (IEEE80211_IS_CHAN_CCK(chan)) { 2142185377Ssam /* Get final CCK target powers */ 2143185377Ssam ar5212GetTargetPowers(ah, chan, ee->ee_trgtPwr_11b, 2144185377Ssam ee->ee_numTargetPwr_11b, &targetPowerCck); 2145185377Ssam 2146185377Ssam /* Reduce power by max regulatory domain allowed restrictions */ 2147185377Ssam scaledPower = AH_MIN(twiceMaxEdgePowerCck, 2148185377Ssam twiceMaxRDPower - twiceAntennaReduction); 2149185377Ssam if (maxAvailPower < AH_MIN(scaledPower, targetPowerCck.twicePwr6_24)) 2150185377Ssam maxAvailPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24); 2151185377Ssam 2152185377Ssam /* Reduce power by user selection */ 2153185377Ssam scaledPower = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24) - (tpcScaleReduction * 2); 2154185377Ssam scaledPower = (scaledPower < 0) ? 0 : scaledPower; 2155185377Ssam scaledPower = AH_MIN(scaledPower, powerLimit); 2156185377Ssam 2157185377Ssam if (commit) { 2158185377Ssam /* Set CCK rates 2L, 2S, 5.5L, 5.5S, 11L, 11S */ 2159185377Ssam rpow[8] = AH_MIN(scaledPower, targetPowerCck.twicePwr6_24); 2160185377Ssam r9 = rpow[9] = AH_MIN(scaledPower, targetPowerCck.twicePwr36); 2161185377Ssam rpow[10] = rpow[9]; 2162185377Ssam rpow[11] = AH_MIN(scaledPower, targetPowerCck.twicePwr48); 2163185377Ssam rpow[12] = rpow[11]; 2164185377Ssam r13 = rpow[13] = AH_MIN(scaledPower, targetPowerCck.twicePwr54); 2165185377Ssam rpow[14] = rpow[13]; 2166185377Ssam } else { 2167185377Ssam r9 = AH_MIN(scaledPower, targetPowerCck.twicePwr36); 2168185377Ssam r13 = AH_MIN(scaledPower, targetPowerCck.twicePwr54); 2169185377Ssam } 2170185377Ssam 2171185377Ssam /* Set min/max power based off OFDM values or initialization */ 2172185377Ssam if (r13 < *pMinPower) 2173185377Ssam *pMinPower = r13; 2174185377Ssam if (r9 > *pMaxPower) 2175185377Ssam *pMaxPower = r9; 2176185377Ssam 2177185377Ssam HALDEBUG(ah, HAL_DEBUG_RFPARAM, 2178185377Ssam "%s: cck: MaxRD: %d MaxCTL: %d " 2179185377Ssam "TPC_Reduction %d chan=%d (0x%x) maxAvailPower=%d pwr6_24=%d, maxPower=%d\n", 2180185377Ssam __func__, twiceMaxRDPower, twiceMaxEdgePowerCck, 2181187831Ssam tpcScaleReduction * 2, chan->ic_freq, chan->ic_flags, 2182185377Ssam maxAvailPower, targetPowerCck.twicePwr6_24, *pMaxPower); 2183185377Ssam } 2184185377Ssam if (commit) { 2185185377Ssam ahp->ah_tx6PowerInHalfDbm = *pMaxPower; 2186185377Ssam AH_PRIVATE(ah)->ah_maxPowerLevel = ahp->ah_tx6PowerInHalfDbm; 2187185377Ssam } 2188185377Ssam return AH_TRUE; 2189185377Ssam} 2190185377Ssam 2191185377SsamHAL_BOOL 2192187831Ssamar5212GetChipPowerLimits(struct ath_hal *ah, struct ieee80211_channel *chan) 2193185377Ssam{ 2194185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 2195187831Ssam#if 0 2196185377Ssam static const uint16_t tpcScaleReductionTable[5] = 2197185377Ssam { 0, 3, 6, 9, MAX_RATE_POWER }; 2198187831Ssam int16_t tpcInDb, powerLimit; 2199187831Ssam#endif 2200187831Ssam int16_t minPower, maxPower; 2201185377Ssam 2202185377Ssam /* 2203185377Ssam * Get Pier table max and min powers. 2204185377Ssam */ 2205187831Ssam if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) { 2206187831Ssam /* NB: rf code returns 1/4 dBm units, convert */ 2207187831Ssam chan->ic_maxpower = maxPower / 2; 2208187831Ssam chan->ic_minpower = minPower / 2; 2209187831Ssam } else { 2210187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 2211187831Ssam "%s: no min/max power for %u/0x%x\n", 2212187831Ssam __func__, chan->ic_freq, chan->ic_flags); 2213187831Ssam chan->ic_maxpower = MAX_RATE_POWER; 2214187831Ssam chan->ic_minpower = 0; 2215185377Ssam } 2216187831Ssam#if 0 2217185377Ssam /* 2218185377Ssam * Now adjust to reflect any global scale and/or CTL's. 2219185377Ssam * (XXX is that correct?) 2220185377Ssam */ 2221185377Ssam powerLimit = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 2222185377Ssam if (powerLimit >= MAX_RATE_POWER || powerLimit == 0) 2223185377Ssam tpcInDb = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale]; 2224185377Ssam else 2225185377Ssam tpcInDb = 0; 2226187831Ssam if (!ar5212SetRateTable(ah, chan, tpcInDb, powerLimit, 2227187831Ssam AH_FALSE, &minPower, &maxPower)) { 2228187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 2229187831Ssam "%s: unable to find max/min power\n",__func__); 2230187831Ssam return AH_FALSE; 2231185377Ssam } 2232187831Ssam if (maxPower < chan->ic_maxpower) 2233187831Ssam chan->ic_maxpower = maxPower; 2234187831Ssam if (minPower < chan->ic_minpower) 2235187831Ssam chan->ic_minpower = minPower; 2236187831Ssam HALDEBUG(ah, HAL_DEBUG_RESET, 2237187831Ssam "Chan %d: MaxPow = %d MinPow = %d\n", 2238187831Ssam chan->ic_freq, chan->ic_maxpower, chans->ic_minpower); 2239185377Ssam#endif 2240185377Ssam return AH_TRUE; 2241185377Ssam} 2242185377Ssam 2243185377Ssam/* 2244185377Ssam * Correct for the gain-delta between ofdm and cck mode target 2245185377Ssam * powers. Write the results to the rate table and the power table. 2246185377Ssam * 2247185377Ssam * Conventions : 2248185377Ssam * 1. rpow[ii] is the integer value of 2*(desired power 2249185377Ssam * for the rate ii in dBm) to provide 0.5dB resolution. rate 2250185377Ssam * mapping is as following : 2251185377Ssam * [0..7] --> ofdm 6, 9, .. 48, 54 2252185377Ssam * [8..14] --> cck 1L, 2L, 2S, .. 11L, 11S 2253185377Ssam * [15] --> XR (all rates get the same power) 2254185377Ssam * 2. powv[ii] is the pcdac corresponding to ii/2 dBm. 2255185377Ssam */ 2256185377Ssamstatic void 2257185377Ssamar5212CorrectGainDelta(struct ath_hal *ah, int twiceOfdmCckDelta) 2258185377Ssam{ 2259185377Ssam#define N(_a) (sizeof(_a) / sizeof(_a[0])) 2260185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 2261185377Ssam const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom; 2262185377Ssam int16_t ratesIndex[N(ahp->ah_ratesArray)]; 2263185377Ssam uint16_t ii, jj, iter; 2264185377Ssam int32_t cckIndex; 2265185377Ssam int16_t gainDeltaAdjust; 2266185377Ssam 2267185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 2268185377Ssam 2269185377Ssam gainDeltaAdjust = ee->ee_cckOfdmGainDelta; 2270185377Ssam 2271185377Ssam /* make a local copy of desired powers as initial indices */ 2272185377Ssam OS_MEMCPY(ratesIndex, ahp->ah_ratesArray, sizeof(ratesIndex)); 2273185377Ssam 2274185377Ssam /* fix only the CCK indices */ 2275185377Ssam for (ii = 8; ii < 15; ii++) { 2276185377Ssam /* apply a gain_delta correction of -15 for CCK */ 2277185377Ssam ratesIndex[ii] -= gainDeltaAdjust; 2278185377Ssam 2279185377Ssam /* Now check for contention with all ofdm target powers */ 2280185377Ssam jj = 0; 2281185377Ssam iter = 0; 2282185377Ssam /* indicates not all ofdm rates checked forcontention yet */ 2283185377Ssam while (jj < 16) { 2284185377Ssam if (ratesIndex[ii] < 0) 2285185377Ssam ratesIndex[ii] = 0; 2286185377Ssam if (jj == 8) { /* skip CCK rates */ 2287185377Ssam jj = 15; 2288185377Ssam continue; 2289185377Ssam } 2290185377Ssam if (ratesIndex[ii] == ahp->ah_ratesArray[jj]) { 2291185377Ssam if (ahp->ah_ratesArray[jj] == 0) 2292185377Ssam ratesIndex[ii]++; 2293185377Ssam else if (iter > 50) { 2294185377Ssam /* 2295185377Ssam * To avoid pathological case of of 2296185377Ssam * dm target powers 0 and 0.5dBm 2297185377Ssam */ 2298185377Ssam ratesIndex[ii]++; 2299185377Ssam } else 2300185377Ssam ratesIndex[ii]--; 2301185377Ssam /* check with all rates again */ 2302185377Ssam jj = 0; 2303185377Ssam iter++; 2304185377Ssam } else 2305185377Ssam jj++; 2306185377Ssam } 2307185377Ssam if (ratesIndex[ii] >= PWR_TABLE_SIZE) 2308185377Ssam ratesIndex[ii] = PWR_TABLE_SIZE -1; 2309185377Ssam cckIndex = ahp->ah_ratesArray[ii] - twiceOfdmCckDelta; 2310185377Ssam if (cckIndex < 0) 2311185377Ssam cckIndex = 0; 2312185377Ssam 2313185377Ssam /* 2314185377Ssam * Validate that the indexes for the powv are not 2315185377Ssam * out of bounds. 2316185377Ssam */ 2317185377Ssam HALASSERT(cckIndex < PWR_TABLE_SIZE); 2318185377Ssam HALASSERT(ratesIndex[ii] < PWR_TABLE_SIZE); 2319185377Ssam ahp->ah_pcdacTable[ratesIndex[ii]] = 2320185377Ssam ahp->ah_pcdacTable[cckIndex]; 2321185377Ssam } 2322185377Ssam /* Override rate per power table with new values */ 2323185377Ssam for (ii = 8; ii < 15; ii++) 2324185377Ssam ahp->ah_ratesArray[ii] = ratesIndex[ii]; 2325185377Ssam#undef N 2326185377Ssam} 2327185377Ssam 2328185377Ssam/* 2329185377Ssam * Find the maximum conformance test limit for the given channel and CTL info 2330185377Ssam */ 2331185377Ssamstatic uint16_t 2332185377Ssamar5212GetMaxEdgePower(uint16_t channel, const RD_EDGES_POWER *pRdEdgesPower) 2333185377Ssam{ 2334185377Ssam /* temp array for holding edge channels */ 2335185377Ssam uint16_t tempChannelList[NUM_EDGES]; 2336185377Ssam uint16_t clo, chi, twiceMaxEdgePower; 2337185377Ssam int i, numEdges; 2338185377Ssam 2339185377Ssam /* Get the edge power */ 2340185377Ssam for (i = 0; i < NUM_EDGES; i++) { 2341185377Ssam if (pRdEdgesPower[i].rdEdge == 0) 2342185377Ssam break; 2343185377Ssam tempChannelList[i] = pRdEdgesPower[i].rdEdge; 2344185377Ssam } 2345185377Ssam numEdges = i; 2346185377Ssam 2347185377Ssam ar5212GetLowerUpperValues(channel, tempChannelList, 2348185377Ssam numEdges, &clo, &chi); 2349185377Ssam /* Get the index for the lower channel */ 2350185377Ssam for (i = 0; i < numEdges && clo != tempChannelList[i]; i++) 2351185377Ssam ; 2352185377Ssam /* Is lower channel ever outside the rdEdge? */ 2353185377Ssam HALASSERT(i != numEdges); 2354185377Ssam 2355185377Ssam if ((clo == chi && clo == channel) || (pRdEdgesPower[i].flag)) { 2356185377Ssam /* 2357185377Ssam * If there's an exact channel match or an inband flag set 2358185377Ssam * on the lower channel use the given rdEdgePower 2359185377Ssam */ 2360185377Ssam twiceMaxEdgePower = pRdEdgesPower[i].twice_rdEdgePower; 2361185377Ssam HALASSERT(twiceMaxEdgePower > 0); 2362185377Ssam } else 2363185377Ssam twiceMaxEdgePower = MAX_RATE_POWER; 2364185377Ssam return twiceMaxEdgePower; 2365185377Ssam} 2366185377Ssam 2367185377Ssam/* 2368185377Ssam * Returns interpolated or the scaled up interpolated value 2369185377Ssam */ 2370185377Ssamstatic uint16_t 2371185377Ssaminterpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, 2372185377Ssam uint16_t targetLeft, uint16_t targetRight) 2373185377Ssam{ 2374185377Ssam uint16_t rv; 2375185377Ssam int16_t lRatio; 2376185377Ssam 2377185377Ssam /* to get an accurate ratio, always scale, if want to scale, then don't scale back down */ 2378185377Ssam if ((targetLeft * targetRight) == 0) 2379185377Ssam return 0; 2380185377Ssam 2381185377Ssam if (srcRight != srcLeft) { 2382185377Ssam /* 2383185377Ssam * Note the ratio always need to be scaled, 2384185377Ssam * since it will be a fraction. 2385185377Ssam */ 2386185377Ssam lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft); 2387185377Ssam if (lRatio < 0) { 2388185377Ssam /* Return as Left target if value would be negative */ 2389185377Ssam rv = targetLeft; 2390185377Ssam } else if (lRatio > EEP_SCALE) { 2391185377Ssam /* Return as Right target if Ratio is greater than 100% (SCALE) */ 2392185377Ssam rv = targetRight; 2393185377Ssam } else { 2394185377Ssam rv = (lRatio * targetRight + (EEP_SCALE - lRatio) * 2395185377Ssam targetLeft) / EEP_SCALE; 2396185377Ssam } 2397185377Ssam } else { 2398185377Ssam rv = targetLeft; 2399185377Ssam } 2400185377Ssam return rv; 2401185377Ssam} 2402185377Ssam 2403185377Ssam/* 2404185377Ssam * Return the four rates of target power for the given target power table 2405185377Ssam * channel, and number of channels 2406185377Ssam */ 2407185377Ssamstatic void 2408187831Ssamar5212GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, 2409185377Ssam const TRGT_POWER_INFO *powInfo, 2410185377Ssam uint16_t numChannels, TRGT_POWER_INFO *pNewPower) 2411185377Ssam{ 2412187831Ssam uint16_t freq = ath_hal_gethwchannel(ah, chan); 2413185377Ssam /* temp array for holding target power channels */ 2414185377Ssam uint16_t tempChannelList[NUM_TEST_FREQUENCIES]; 2415185377Ssam uint16_t clo, chi, ixlo, ixhi; 2416185377Ssam int i; 2417185377Ssam 2418185377Ssam /* Copy the target powers into the temp channel list */ 2419185377Ssam for (i = 0; i < numChannels; i++) 2420185377Ssam tempChannelList[i] = powInfo[i].testChannel; 2421185377Ssam 2422187831Ssam ar5212GetLowerUpperValues(freq, tempChannelList, 2423185377Ssam numChannels, &clo, &chi); 2424185377Ssam 2425185377Ssam /* Get the indices for the channel */ 2426185377Ssam ixlo = ixhi = 0; 2427185377Ssam for (i = 0; i < numChannels; i++) { 2428185377Ssam if (clo == tempChannelList[i]) { 2429185377Ssam ixlo = i; 2430185377Ssam } 2431185377Ssam if (chi == tempChannelList[i]) { 2432185377Ssam ixhi = i; 2433185377Ssam break; 2434185377Ssam } 2435185377Ssam } 2436185377Ssam 2437185377Ssam /* 2438185377Ssam * Get the lower and upper channels, target powers, 2439185377Ssam * and interpolate between them. 2440185377Ssam */ 2441187831Ssam pNewPower->twicePwr6_24 = interpolate(freq, clo, chi, 2442185377Ssam powInfo[ixlo].twicePwr6_24, powInfo[ixhi].twicePwr6_24); 2443187831Ssam pNewPower->twicePwr36 = interpolate(freq, clo, chi, 2444185377Ssam powInfo[ixlo].twicePwr36, powInfo[ixhi].twicePwr36); 2445187831Ssam pNewPower->twicePwr48 = interpolate(freq, clo, chi, 2446185377Ssam powInfo[ixlo].twicePwr48, powInfo[ixhi].twicePwr48); 2447187831Ssam pNewPower->twicePwr54 = interpolate(freq, clo, chi, 2448185377Ssam powInfo[ixlo].twicePwr54, powInfo[ixhi].twicePwr54); 2449185377Ssam} 2450185377Ssam 2451185377Ssam/* 2452185377Ssam * Search a list for a specified value v that is within 2453185377Ssam * EEP_DELTA of the search values. Return the closest 2454185377Ssam * values in the list above and below the desired value. 2455185377Ssam * EEP_DELTA is a factional value; everything is scaled 2456185377Ssam * so only integer arithmetic is used. 2457185377Ssam * 2458185377Ssam * NB: the input list is assumed to be sorted in ascending order 2459185377Ssam */ 2460185377Ssamvoid 2461185377Ssamar5212GetLowerUpperValues(uint16_t v, uint16_t *lp, uint16_t listSize, 2462185377Ssam uint16_t *vlo, uint16_t *vhi) 2463185377Ssam{ 2464185377Ssam uint32_t target = v * EEP_SCALE; 2465185377Ssam uint16_t *ep = lp+listSize; 2466185377Ssam 2467185377Ssam /* 2468185377Ssam * Check first and last elements for out-of-bounds conditions. 2469185377Ssam */ 2470185377Ssam if (target < (uint32_t)(lp[0] * EEP_SCALE - EEP_DELTA)) { 2471185377Ssam *vlo = *vhi = lp[0]; 2472185377Ssam return; 2473185377Ssam } 2474185377Ssam if (target > (uint32_t)(ep[-1] * EEP_SCALE + EEP_DELTA)) { 2475185377Ssam *vlo = *vhi = ep[-1]; 2476185377Ssam return; 2477185377Ssam } 2478185377Ssam 2479185377Ssam /* look for value being near or between 2 values in list */ 2480185377Ssam for (; lp < ep; lp++) { 2481185377Ssam /* 2482185377Ssam * If value is close to the current value of the list 2483185377Ssam * then target is not between values, it is one of the values 2484185377Ssam */ 2485185377Ssam if (abs(lp[0] * EEP_SCALE - target) < EEP_DELTA) { 2486185377Ssam *vlo = *vhi = lp[0]; 2487185377Ssam return; 2488185377Ssam } 2489185377Ssam /* 2490185377Ssam * Look for value being between current value and next value 2491185377Ssam * if so return these 2 values 2492185377Ssam */ 2493185377Ssam if (target < (uint32_t)(lp[1] * EEP_SCALE - EEP_DELTA)) { 2494185377Ssam *vlo = lp[0]; 2495185377Ssam *vhi = lp[1]; 2496185377Ssam return; 2497185377Ssam } 2498185377Ssam } 2499185377Ssam HALASSERT(AH_FALSE); /* should not reach here */ 2500185377Ssam} 2501185377Ssam 2502185377Ssam/* 2503185377Ssam * Perform analog "swizzling" of parameters into their location 2504185380Ssam * 2505185380Ssam * NB: used by RF backends 2506185377Ssam */ 2507185377Ssamvoid 2508185377Ssamar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32, uint32_t numBits, 2509185377Ssam uint32_t firstBit, uint32_t column) 2510185377Ssam{ 2511185380Ssam#define MAX_ANALOG_START 319 /* XXX */ 2512185377Ssam uint32_t tmp32, mask, arrayEntry, lastBit; 2513185377Ssam int32_t bitPosition, bitsLeft; 2514185377Ssam 2515185377Ssam HALASSERT(column <= 3); 2516185377Ssam HALASSERT(numBits <= 32); 2517185377Ssam HALASSERT(firstBit + numBits <= MAX_ANALOG_START); 2518185377Ssam 2519185377Ssam tmp32 = ath_hal_reverseBits(reg32, numBits); 2520185377Ssam arrayEntry = (firstBit - 1) / 8; 2521185377Ssam bitPosition = (firstBit - 1) % 8; 2522185377Ssam bitsLeft = numBits; 2523185377Ssam while (bitsLeft > 0) { 2524185377Ssam lastBit = (bitPosition + bitsLeft > 8) ? 2525185377Ssam 8 : bitPosition + bitsLeft; 2526185377Ssam mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << 2527185377Ssam (column * 8); 2528185377Ssam rfBuf[arrayEntry] &= ~mask; 2529185377Ssam rfBuf[arrayEntry] |= ((tmp32 << bitPosition) << 2530185377Ssam (column * 8)) & mask; 2531185377Ssam bitsLeft -= 8 - bitPosition; 2532185377Ssam tmp32 = tmp32 >> (8 - bitPosition); 2533185377Ssam bitPosition = 0; 2534185377Ssam arrayEntry++; 2535185377Ssam } 2536185380Ssam#undef MAX_ANALOG_START 2537185377Ssam} 2538185377Ssam 2539185377Ssam/* 2540185377Ssam * Sets the rate to duration values in MAC - used for multi- 2541185377Ssam * rate retry. 2542185377Ssam * The rate duration table needs to cover all valid rate codes; 2543185377Ssam * the 11g table covers all ofdm rates, while the 11b table 2544185377Ssam * covers all cck rates => all valid rates get covered between 2545185377Ssam * these two mode's ratetables! 2546185377Ssam * But if we're turbo, the ofdm phy is replaced by the turbo phy 2547185377Ssam * and cck is not valid with turbo => all rates get covered 2548185377Ssam * by the turbo ratetable only 2549185377Ssam */ 2550185377Ssamvoid 2551187831Ssamar5212SetRateDurationTable(struct ath_hal *ah, 2552187831Ssam const struct ieee80211_channel *chan) 2553185377Ssam{ 2554185377Ssam const HAL_RATE_TABLE *rt; 2555185377Ssam int i; 2556185377Ssam 2557185380Ssam /* NB: band doesn't matter for 1/2 and 1/4 rate */ 2558187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) { 2559185377Ssam rt = ar5212GetRateTable(ah, HAL_MODE_11A_HALF_RATE); 2560187831Ssam } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 2561185377Ssam rt = ar5212GetRateTable(ah, HAL_MODE_11A_QUARTER_RATE); 2562185377Ssam } else { 2563185377Ssam rt = ar5212GetRateTable(ah, 2564187831Ssam IEEE80211_IS_CHAN_TURBO(chan) ? HAL_MODE_TURBO : HAL_MODE_11G); 2565185377Ssam } 2566185377Ssam 2567185377Ssam for (i = 0; i < rt->rateCount; ++i) 2568185377Ssam OS_REG_WRITE(ah, 2569185377Ssam AR_RATE_DURATION(rt->info[i].rateCode), 2570185377Ssam ath_hal_computetxtime(ah, rt, 2571185377Ssam WLAN_CTRL_FRAME_SIZE, 2572185377Ssam rt->info[i].controlRate, AH_FALSE)); 2573187831Ssam if (!IEEE80211_IS_CHAN_TURBO(chan)) { 2574185377Ssam /* 11g Table is used to cover the CCK rates. */ 2575185377Ssam rt = ar5212GetRateTable(ah, HAL_MODE_11G); 2576185377Ssam for (i = 0; i < rt->rateCount; ++i) { 2577185377Ssam uint32_t reg = AR_RATE_DURATION(rt->info[i].rateCode); 2578185377Ssam 2579185377Ssam if (rt->info[i].phy != IEEE80211_T_CCK) 2580185377Ssam continue; 2581185377Ssam 2582185377Ssam OS_REG_WRITE(ah, reg, 2583185377Ssam ath_hal_computetxtime(ah, rt, 2584185377Ssam WLAN_CTRL_FRAME_SIZE, 2585185377Ssam rt->info[i].controlRate, AH_FALSE)); 2586185377Ssam /* cck rates have short preamble option also */ 2587185377Ssam if (rt->info[i].shortPreamble) { 2588185377Ssam reg += rt->info[i].shortPreamble << 2; 2589185377Ssam OS_REG_WRITE(ah, reg, 2590185377Ssam ath_hal_computetxtime(ah, rt, 2591185377Ssam WLAN_CTRL_FRAME_SIZE, 2592185377Ssam rt->info[i].controlRate, 2593185377Ssam AH_TRUE)); 2594185377Ssam } 2595185377Ssam } 2596185377Ssam } 2597185377Ssam} 2598185377Ssam 2599185377Ssam/* Adjust various register settings based on half/quarter rate clock setting. 2600185377Ssam * This includes: +USEC, TX/RX latency, 2601185377Ssam * + IFS params: slot, eifs, misc etc. 2602185377Ssam */ 2603185377Ssamvoid 2604187831Ssamar5212SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan) 2605185377Ssam{ 2606185377Ssam uint32_t txLat, rxLat, usec, slot, refClock, eifs, init_usec; 2607185377Ssam 2608187831Ssam HALASSERT(IEEE80211_IS_CHAN_HALF(chan) || 2609187831Ssam IEEE80211_IS_CHAN_QUARTER(chan)); 2610185380Ssam 2611185377Ssam refClock = OS_REG_READ(ah, AR_USEC) & AR_USEC_USEC32; 2612187831Ssam if (IEEE80211_IS_CHAN_HALF(chan)) { 2613185377Ssam slot = IFS_SLOT_HALF_RATE; 2614185377Ssam rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S; 2615185377Ssam txLat = TX_HALF_RATE_LATENCY << AR5212_USEC_TX_LAT_S; 2616185377Ssam usec = HALF_RATE_USEC; 2617185377Ssam eifs = IFS_EIFS_HALF_RATE; 2618185377Ssam init_usec = INIT_USEC >> 1; 2619185377Ssam } else { /* quarter rate */ 2620185377Ssam slot = IFS_SLOT_QUARTER_RATE; 2621185377Ssam rxLat = RX_NON_FULL_RATE_LATENCY << AR5212_USEC_RX_LAT_S; 2622185377Ssam txLat = TX_QUARTER_RATE_LATENCY << AR5212_USEC_TX_LAT_S; 2623185377Ssam usec = QUARTER_RATE_USEC; 2624185377Ssam eifs = IFS_EIFS_QUARTER_RATE; 2625185377Ssam init_usec = INIT_USEC >> 2; 2626185377Ssam } 2627185377Ssam 2628185377Ssam OS_REG_WRITE(ah, AR_USEC, (usec | refClock | txLat | rxLat)); 2629185377Ssam OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot); 2630185377Ssam OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs); 2631185377Ssam OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC, 2632185377Ssam AR_D_GBL_IFS_MISC_USEC_DURATION, init_usec); 2633185377Ssam} 2634