ar5210.h revision 185521
1193323Sed/* 2193323Sed * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3193323Sed * Copyright (c) 2002-2004 Atheros Communications, Inc. 4193323Sed * 5193323Sed * Permission to use, copy, modify, and/or distribute this software for any 6193323Sed * purpose with or without fee is hereby granted, provided that the above 7193323Sed * copyright notice and this permission notice appear in all copies. 8193323Sed * 9193323Sed * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10193323Sed * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11198090Srdivacky * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12234353Sdim * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13218893Sdim * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14234353Sdim * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15193323Sed * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16193323Sed * 17193323Sed * $Id: ar5210.h,v 1.8 2008/11/11 02:40:13 sam Exp $ 18193323Sed */ 19193323Sed#ifndef _ATH_AR5210_H_ 20193323Sed#define _ATH_AR5210_H_ 21218893Sdim 22198090Srdivacky#define AR5210_MAGIC 0x19980124 23198090Srdivacky 24234353Sdim#if 0 25198090Srdivacky/* 26198090Srdivacky * RTS_ENABLE includes LONG_PKT because they essentially 27226633Sdim * imply the same thing, and are set or not set together 28226633Sdim * for this chip 29198090Srdivacky */ 30198090Srdivacky#define AR5210_TXD_CTRL_A_HDR_LEN(_val) (((_val) ) & 0x0003f) 31198090Srdivacky#define AR5210_TXD_CTRL_A_TX_RATE(_val) (((_val) << 6) & 0x003c0) 32234353Sdim#define AR5210_TXD_CTRL_A_RTS_ENABLE ( 0x00c00) 33198090Srdivacky#define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000) 34203954Srdivacky#define AR5210_TXD_CTRL_A_ANT_MODE(_val) (((_val) << 13) & 0x02000) 35198090Srdivacky#define AR5210_TXD_CTRL_A_PKT_TYPE(_val) (((_val) << 14) & 0x1c000) 36198090Srdivacky#define AR5210_TXD_CTRL_A_INT_REQ ( 0x20000) 37198090Srdivacky#define AR5210_TXD_CTRL_A_KEY_VALID ( 0x40000) 38198090Srdivacky#define AR5210_TXD_CTRL_B_KEY_ID(_val) (((_val) ) & 0x0003f) 39198090Srdivacky#define AR5210_TXD_CTRL_B_RTS_DURATION(_val) (((_val) << 6) & 0x7ffc0) 40204642Srdivacky#endif 41221345Sdim 42221345Sdim#define INIT_CONFIG_STATUS 0x00000000 43226633Sdim#define INIT_ACKTOPS 0x00000008 44226633Sdim#define INIT_BCON_CNTRL_REG 0x00000000 45193323Sed#define INIT_SLOT_TIME 0x00000168 46193323Sed#define INIT_SLOT_TIME_TURBO 0x000001e0 /* More aggressive turbo slot timing = 6 us */ 47234353Sdim#define INIT_ACK_CTS_TIMEOUT 0x04000400 48193323Sed#define INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 49193323Sed 50198090Srdivacky#define INIT_USEC 0x27 51198090Srdivacky#define INIT_USEC_TURBO 0x4f 52198090Srdivacky#define INIT_USEC_32 0x1f 53198090Srdivacky#define INIT_TX_LATENCY 0x36 54198090Srdivacky#define INIT_RX_LATENCY 0x1D 55198090Srdivacky#define INIT_TRANSMIT_LATENCY \ 56198090Srdivacky ((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \ 57198090Srdivacky (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \ 58198090Srdivacky (INIT_USEC_32 << 7) | INIT_USEC ) 59198090Srdivacky#define INIT_TRANSMIT_LATENCY_TURBO \ 60198090Srdivacky ((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \ 61198090Srdivacky (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \ 62198090Srdivacky (INIT_USEC_32 << 7) | INIT_USEC_TURBO) 63204642Srdivacky 64204642Srdivacky#define INIT_SIFS 0x230 /* = 16 us - 2 us */ 65234353Sdim#define INIT_SIFS_TURBO 0x1E0 /* More aggressive turbo SIFS timing - 8 us - 2 us */ 66234353Sdim 67234353Sdim/* 68234353Sdim * Various fifo fill before Tx start, in 64-byte units 69203954Srdivacky * i.e. put the frame in the air while still DMAing 70198090Srdivacky */ 71198090Srdivacky#define MIN_TX_FIFO_THRESHOLD 0x1 72198090Srdivacky#define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1) 73198090Srdivacky 74218893Sdim#define INIT_NEXT_CFP_START 0xffffffff 75198090Srdivacky 76218893Sdim#define INIT_BEACON_PERIOD 0xffff 77221345Sdim#define INIT_BEACON_EN 0 /* this should be set by AP only when it's ready */ 78221345Sdim#define INIT_BEACON_CONTROL \ 79226633Sdim ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \ 80226633Sdim (INIT_TIM_OFFSET<<16) | INIT_BEACON_PERIOD) 81198090Srdivacky 82198090Srdivacky#define INIT_RSSI_THR 0x00000700 /* Missed beacon counter initialized to max value of 7 */ 83198090Srdivacky#define INIT_ProgIFS 0x398 /* PIFS - 2us */ 84193323Sed#define INIT_ProgIFS_TURBO 0x3C0 85193323Sed#define INIT_EIFS 0xd70 86193323Sed#define INIT_EIFS_TURBO 0x1ae0 87193323Sed#define INIT_CARR_SENSE_EN 1 88193323Sed#define INIT_PROTO_TIME_CNTRL ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS << 12) | \ 89198090Srdivacky (INIT_ProgIFS) ) 90221345Sdim#define INIT_PROTO_TIME_CNTRL_TURBO ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS_TURBO << 12) | \ 91234353Sdim (INIT_ProgIFS_TURBO) ) 92234353Sdim 93193323Sed#define AR5210_MAX_RATE_POWER 60 94193323Sed 95234353Sdim#undef HAL_NUM_TX_QUEUES /* from ah.h */ 96193323Sed#define HAL_NUM_TX_QUEUES 3 97193323Sed 98193323Sedstruct ath_hal_5210 { 99193323Sed struct ath_hal_private ah_priv; /* base definitions */ 100193323Sed 101193323Sed uint8_t ah_macaddr[IEEE80211_ADDR_LEN]; 102194612Sed /* 103198090Srdivacky * Runtime state. 104193323Sed */ 105193323Sed uint32_t ah_maskReg; /* shadow of IMR+IER regs */ 106193323Sed uint32_t ah_txOkInterruptMask; 107221345Sdim uint32_t ah_txErrInterruptMask; 108226633Sdim uint32_t ah_txDescInterruptMask; 109193323Sed uint32_t ah_txEolInterruptMask; 110199989Srdivacky uint32_t ah_txUrnInterruptMask; 111221345Sdim HAL_POWER_MODE ah_powerMode; 112198090Srdivacky uint8_t ah_bssid[IEEE80211_ADDR_LEN]; 113198090Srdivacky HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; /* beacon+cab+data */ 114195340Sed /* 115198090Srdivacky * Station mode support. 116198090Srdivacky */ 117198396Srdivacky uint32_t ah_staId1Defaults; /* STA_ID1 default settings */ 118210299Sed uint32_t ah_rssiThr; /* RSSI_THR settings */ 119224145Sdim 120226633Sdim u_int ah_sifstime; /* user-specified sifs time */ 121234353Sdim u_int ah_slottime; /* user-specified slot time */ 122193323Sed u_int ah_acktimeout; /* user-specified ack timeout */ 123193323Sed u_int ah_ctstimeout; /* user-specified cts timeout */ 124234353Sdim}; 125193323Sed#define AH5210(ah) ((struct ath_hal_5210 *)(ah)) 126193323Sed 127218893Sdimstruct ath_hal; 128218893Sdim 129218893Sdimextern void ar5210Detach(struct ath_hal *ah); 130218893Sdimextern HAL_BOOL ar5210Reset(struct ath_hal *, HAL_OPMODE, 131234353Sdim HAL_CHANNEL *, HAL_BOOL bChannelChange, HAL_STATUS *); 132218893Sdimextern void ar5210SetPCUConfig(struct ath_hal *); 133218893Sdimextern HAL_BOOL ar5210PhyDisable(struct ath_hal *); 134218893Sdimextern HAL_BOOL ar5210Disable(struct ath_hal *); 135234353Sdimextern HAL_BOOL ar5210ChipReset(struct ath_hal *, HAL_CHANNEL *); 136218893Sdimextern HAL_BOOL ar5210PerCalibration(struct ath_hal *, HAL_CHANNEL *, HAL_BOOL *); 137218893Sdimextern HAL_BOOL ar5210PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, 138234353Sdim u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone); 139218893Sdimextern HAL_BOOL ar5210ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan); 140218893Sdimextern int16_t ar5210GetNoiseFloor(struct ath_hal *); 141199481Srdivackyextern int16_t ar5210GetNfAdjust(struct ath_hal *, 142234353Sdim const HAL_CHANNEL_INTERNAL *); 143234353Sdimextern HAL_BOOL ar5210SetTxPowerLimit(struct ath_hal *, uint32_t limit); 144234353Sdimextern HAL_BOOL ar5210SetTransmitPower(struct ath_hal *, HAL_CHANNEL *); 145234353Sdimextern HAL_BOOL ar5210CalNoiseFloor(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 146234353Sdimextern HAL_BOOL ar5210ResetDma(struct ath_hal *, HAL_OPMODE); 147234353Sdim 148234353Sdimextern HAL_BOOL ar5210SetTxQueueProps(struct ath_hal *ah, int q, 149234353Sdim const HAL_TXQ_INFO *qInfo); 150234353Sdimextern HAL_BOOL ar5210GetTxQueueProps(struct ath_hal *ah, int q, 151234353Sdim HAL_TXQ_INFO *qInfo); 152234353Sdimextern int ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, 153234353Sdim const HAL_TXQ_INFO *qInfo); 154234353Sdimextern HAL_BOOL ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q); 155234353Sdimextern HAL_BOOL ar5210ResetTxQueue(struct ath_hal *ah, u_int q); 156234353Sdimextern uint32_t ar5210GetTxDP(struct ath_hal *, u_int); 157234353Sdimextern HAL_BOOL ar5210SetTxDP(struct ath_hal *, u_int, uint32_t txdp); 158234353Sdimextern HAL_BOOL ar5210UpdateTxTrigLevel(struct ath_hal *, HAL_BOOL); 159234353Sdimextern uint32_t ar5210NumTxPending(struct ath_hal *, u_int); 160234353Sdimextern HAL_BOOL ar5210StartTxDma(struct ath_hal *, u_int); 161234353Sdimextern HAL_BOOL ar5210StopTxDma(struct ath_hal *, u_int); 162234353Sdimextern HAL_BOOL ar5210SetupTxDesc(struct ath_hal *, struct ath_desc *, 163234353Sdim u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, 164234353Sdim u_int txRate0, u_int txRetries0, 165234353Sdim u_int keyIx, u_int antMode, u_int flags, 166234353Sdim u_int rtsctsRate, u_int rtsctsDuration, 167234353Sdim u_int compicvLen, u_int compivLen, u_int comp); 168198090Srdivackyextern HAL_BOOL ar5210SetupXTxDesc(struct ath_hal *, struct ath_desc *, 169198090Srdivacky u_int txRate1, u_int txRetries1, 170199481Srdivacky u_int txRate2, u_int txRetries2, 171198090Srdivacky u_int txRate3, u_int txRetries3); 172198090Srdivackyextern HAL_BOOL ar5210FillTxDesc(struct ath_hal *, struct ath_desc *, 173198090Srdivacky u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, 174198090Srdivacky const struct ath_desc *ds0); 175198090Srdivackyextern HAL_STATUS ar5210ProcTxDesc(struct ath_hal *, 176198090Srdivacky struct ath_desc *, struct ath_tx_status *); 177198090Srdivackyextern void ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *); 178198090Srdivackyextern void ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *); 179198090Srdivacky 180198090Srdivackyextern uint32_t ar5210GetRxDP(struct ath_hal *); 181198090Srdivackyextern void ar5210SetRxDP(struct ath_hal *, uint32_t rxdp); 182198090Srdivackyextern void ar5210EnableReceive(struct ath_hal *); 183234353Sdimextern HAL_BOOL ar5210StopDmaReceive(struct ath_hal *); 184234353Sdimextern void ar5210StartPcuReceive(struct ath_hal *); 185234353Sdimextern void ar5210StopPcuReceive(struct ath_hal *); 186234353Sdimextern void ar5210SetMulticastFilter(struct ath_hal *, 187234353Sdim uint32_t filter0, uint32_t filter1); 188234353Sdimextern HAL_BOOL ar5210ClrMulticastFilterIndex(struct ath_hal *, uint32_t); 189234353Sdimextern HAL_BOOL ar5210SetMulticastFilterIndex(struct ath_hal *, uint32_t); 190234353Sdimextern uint32_t ar5210GetRxFilter(struct ath_hal *); 191234353Sdimextern void ar5210SetRxFilter(struct ath_hal *, uint32_t); 192234353Sdimextern HAL_BOOL ar5210SetupRxDesc(struct ath_hal *, struct ath_desc *, 193234353Sdim uint32_t, u_int flags); 194234353Sdimextern HAL_STATUS ar5210ProcRxDesc(struct ath_hal *, struct ath_desc *, 195234353Sdim uint32_t, struct ath_desc *, uint64_t, 196234353Sdim struct ath_rx_status *); 197234353Sdim 198234353Sdimextern void ar5210GetMacAddress(struct ath_hal *, uint8_t *); 199198090Srdivackyextern HAL_BOOL ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *); 200198090Srdivackyextern void ar5210GetBssIdMask(struct ath_hal *, uint8_t *); 201206083Srdivackyextern HAL_BOOL ar5210SetBssIdMask(struct ath_hal *, const uint8_t *); 202199481Srdivackyextern HAL_BOOL ar5210EepromRead(struct ath_hal *, u_int off, uint16_t *data); 203221345Sdimextern HAL_BOOL ar5210EepromWrite(struct ath_hal *, u_int off, uint16_t data); 204199481Srdivackyextern HAL_BOOL ar5210SetRegulatoryDomain(struct ath_hal *, 205199481Srdivacky uint16_t, HAL_STATUS *); 206234353Sdimextern u_int ar5210GetWirelessModes(struct ath_hal *ah); 207234353Sdimextern void ar5210EnableRfKill(struct ath_hal *); 208234353Sdimextern HAL_BOOL ar5210GpioCfgInput(struct ath_hal *, uint32_t gpio); 209234353Sdimextern HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio); 210234353Sdimextern uint32_t ar5210GpioGet(struct ath_hal *, uint32_t gpio); 211234353Sdimextern HAL_BOOL ar5210GpioSet(struct ath_hal *, uint32_t gpio, uint32_t); 212234353Sdimextern void ar5210Gpio0SetIntr(struct ath_hal *, u_int, uint32_t ilevel); 213234353Sdimextern void ar5210SetLedState(struct ath_hal *, HAL_LED_STATE); 214234353Sdimextern u_int ar5210GetDefAntenna(struct ath_hal *); 215234353Sdimextern void ar5210SetDefAntenna(struct ath_hal *, u_int); 216234353Sdimextern HAL_ANT_SETTING ar5210GetAntennaSwitch(struct ath_hal *); 217234353Sdimextern HAL_BOOL ar5210SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); 218234353Sdimextern void ar5210WriteAssocid(struct ath_hal *, 219234353Sdim const uint8_t *bssid, uint16_t assocId); 220234353Sdimextern uint32_t ar5210GetTsf32(struct ath_hal *); 221234353Sdimextern uint64_t ar5210GetTsf64(struct ath_hal *); 222234353Sdimextern void ar5210ResetTsf(struct ath_hal *); 223199481Srdivackyextern uint32_t ar5210GetRandomSeed(struct ath_hal *); 224199481Srdivackyextern HAL_BOOL ar5210DetectCardPresent(struct ath_hal *); 225234353Sdimextern void ar5210UpdateMibCounters(struct ath_hal *, HAL_MIB_STATS *); 226234353Sdimextern void ar5210EnableHwEncryption(struct ath_hal *); 227234353Sdimextern void ar5210DisableHwEncryption(struct ath_hal *); 228234353Sdimextern HAL_RFGAIN ar5210GetRfgain(struct ath_hal *); 229234353Sdimextern HAL_BOOL ar5210SetSifsTime(struct ath_hal *, u_int); 230234353Sdimextern u_int ar5210GetSifsTime(struct ath_hal *); 231234353Sdimextern HAL_BOOL ar5210SetSlotTime(struct ath_hal *, u_int); 232234353Sdimextern u_int ar5210GetSlotTime(struct ath_hal *); 233234353Sdimextern HAL_BOOL ar5210SetAckTimeout(struct ath_hal *, u_int); 234234353Sdimextern u_int ar5210GetAckTimeout(struct ath_hal *); 235234353Sdimextern HAL_BOOL ar5210SetAckCTSRate(struct ath_hal *, u_int); 236234353Sdimextern u_int ar5210GetAckCTSRate(struct ath_hal *); 237234353Sdimextern HAL_BOOL ar5210SetCTSTimeout(struct ath_hal *, u_int); 238234353Sdimextern u_int ar5210GetCTSTimeout(struct ath_hal *); 239234353Sdimextern HAL_BOOL ar5210SetDecompMask(struct ath_hal *, uint16_t, int); 240234353Sdimvoid ar5210SetCoverageClass(struct ath_hal *, uint8_t, int); 241234353Sdimextern HAL_STATUS ar5210GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 242234353Sdim uint32_t, uint32_t *); 243234353Sdimextern HAL_BOOL ar5210SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 244234353Sdim uint32_t, uint32_t, HAL_STATUS *); 245234353Sdimextern HAL_BOOL ar5210GetDiagState(struct ath_hal *ah, int request, 246234353Sdim const void *args, uint32_t argsize, 247234353Sdim void **result, uint32_t *resultsize); 248234353Sdim 249234353Sdimextern u_int ar5210GetKeyCacheSize(struct ath_hal *); 250234353Sdimextern HAL_BOOL ar5210IsKeyCacheEntryValid(struct ath_hal *, uint16_t); 251234353Sdimextern HAL_BOOL ar5210ResetKeyCacheEntry(struct ath_hal *, uint16_t entry); 252234353Sdimextern HAL_BOOL ar5210SetKeyCacheEntry(struct ath_hal *, uint16_t entry, 253234353Sdim const HAL_KEYVAL *, const uint8_t *mac, int xorKey); 254234353Sdimextern HAL_BOOL ar5210SetKeyCacheEntryMac(struct ath_hal *, 255234353Sdim uint16_t, const uint8_t *); 256234353Sdim 257234353Sdimextern HAL_BOOL ar5210SetPowerMode(struct ath_hal *, uint32_t powerRequest, 258193323Sed int setChip); 259234353Sdimextern HAL_POWER_MODE ar5210GetPowerMode(struct ath_hal *); 260234353Sdim 261234353Sdimextern void ar5210SetBeaconTimers(struct ath_hal *, 262234353Sdim const HAL_BEACON_TIMERS *); 263234353Sdimextern void ar5210BeaconInit(struct ath_hal *, uint32_t, uint32_t); 264234353Sdimextern void ar5210SetStaBeaconTimers(struct ath_hal *, 265234353Sdim const HAL_BEACON_STATE *); 266234353Sdimextern void ar5210ResetStaBeaconTimers(struct ath_hal *); 267212904Sdim 268193323Sedextern HAL_BOOL ar5210IsInterruptPending(struct ath_hal *); 269234353Sdimextern HAL_BOOL ar5210GetPendingInterrupts(struct ath_hal *, HAL_INT *); 270234353Sdimextern HAL_INT ar5210GetInterrupts(struct ath_hal *); 271234353Sdimextern HAL_INT ar5210SetInterrupts(struct ath_hal *, HAL_INT ints); 272234353Sdim 273234353Sdimextern const HAL_RATE_TABLE *ar5210GetRateTable(struct ath_hal *, u_int mode); 274234353Sdim 275234353Sdimextern HAL_BOOL ar5210AniControl(struct ath_hal *, HAL_ANI_CMD, int ); 276234353Sdimextern void ar5210AniPoll(struct ath_hal *, const HAL_NODE_STATS *, HAL_CHANNEL *); 277234353Sdimextern void ar5210MibEvent(struct ath_hal *, const HAL_NODE_STATS *); 278234353Sdim#endif /* _ATH_AR5210_H_ */ 279234353Sdim