ah_regdomain.c revision 187831
1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2005-2006 Atheros Communications, Inc. 4185377Ssam * All rights reserved. 5185377Ssam * 6185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 7185377Ssam * purpose with or without fee is hereby granted, provided that the above 8185377Ssam * copyright notice and this permission notice appear in all copies. 9185377Ssam * 10185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17185377Ssam * 18187345Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ah_regdomain.c 187831 2009-01-28 18:00:22Z sam $ 19185377Ssam */ 20185377Ssam#include "opt_ah.h" 21185377Ssam 22185377Ssam#include "ah.h" 23187831Ssam 24187831Ssam#include <net80211/_ieee80211.h> 25187831Ssam#include <net80211/ieee80211_regdomain.h> 26187831Ssam 27185377Ssam#include "ah_internal.h" 28185377Ssam#include "ah_eeprom.h" 29185377Ssam#include "ah_devid.h" 30185377Ssam 31185377Ssam/* 32185377Ssam * XXX this code needs a audit+review 33185377Ssam */ 34185377Ssam 35185377Ssam/* used throughout this file... */ 36185377Ssam#define N(a) (sizeof (a) / sizeof (a[0])) 37185377Ssam 38185377Ssam#define HAL_MODE_11A_TURBO HAL_MODE_108A 39185377Ssam#define HAL_MODE_11G_TURBO HAL_MODE_108G 40185377Ssam 41185377Ssam/* 42185380Ssam * BMLEN defines the size of the bitmask used to hold frequency 43185380Ssam * band specifications. Note this must agree with the BM macro 44185380Ssam * definition that's used to setup initializers. See also further 45185380Ssam * comments below. 46185377Ssam */ 47185380Ssam#define BMLEN 2 /* 2 x 64 bits in each channel bitmask */ 48185380Ssamtypedef uint64_t chanbmask_t[BMLEN]; 49185377Ssam 50185380Ssam#define W0(_a) \ 51185380Ssam (((_a) >= 0 && (_a) < 64 ? (((uint64_t) 1)<<(_a)) : (uint64_t) 0)) 52185380Ssam#define W1(_a) \ 53185380Ssam (((_a) > 63 && (_a) < 128 ? (((uint64_t) 1)<<((_a)-64)) : (uint64_t) 0)) 54185380Ssam#define BM1(_fa) { W0(_fa), W1(_fa) } 55185380Ssam#define BM2(_fa, _fb) { W0(_fa) | W0(_fb), W1(_fa) | W1(_fb) } 56185380Ssam#define BM3(_fa, _fb, _fc) \ 57185380Ssam { W0(_fa) | W0(_fb) | W0(_fc), W1(_fa) | W1(_fb) | W1(_fc) } 58185380Ssam#define BM4(_fa, _fb, _fc, _fd) \ 59185380Ssam { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd), \ 60185380Ssam W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) } 61185380Ssam#define BM5(_fa, _fb, _fc, _fd, _fe) \ 62185380Ssam { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe), \ 63185380Ssam W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) } 64185380Ssam#define BM6(_fa, _fb, _fc, _fd, _fe, _ff) \ 65185380Ssam { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff), \ 66185380Ssam W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) } 67185380Ssam#define BM7(_fa, _fb, _fc, _fd, _fe, _ff, _fg) \ 68185380Ssam { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 69185380Ssam W0(_fg),\ 70185380Ssam W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 71185380Ssam W1(_fg) } 72185380Ssam#define BM8(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \ 73185380Ssam { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 74185380Ssam W0(_fg) | W0(_fh) , \ 75185380Ssam W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 76185380Ssam W1(_fg) | W1(_fh) } 77185377Ssam 78185377Ssam/* 79185380Ssam * Mask to check whether a domain is a multidomain or a single domain 80185380Ssam */ 81185377Ssam#define MULTI_DOMAIN_MASK 0xFF00 82185377Ssam 83185380Ssam/* 84185380Ssam * Enumerated Regulatory Domain Information 8 bit values indicate that 85185377Ssam * the regdomain is really a pair of unitary regdomains. 12 bit values 86185377Ssam * are the real unitary regdomains and are the only ones which have the 87185377Ssam * frequency bitmasks and flags set. 88185377Ssam */ 89185380Ssamenum { 90185377Ssam /* 91185377Ssam * The following regulatory domain definitions are 92185377Ssam * found in the EEPROM. Each regulatory domain 93185377Ssam * can operate in either a 5GHz or 2.4GHz wireless mode or 94185377Ssam * both 5GHz and 2.4GHz wireless modes. 95185377Ssam * In general, the value holds no special 96185377Ssam * meaning and is used to decode into either specific 97185377Ssam * 2.4GHz or 5GHz wireless mode for that particular 98185377Ssam * regulatory domain. 99185377Ssam */ 100185377Ssam NO_ENUMRD = 0x00, 101185377Ssam NULL1_WORLD = 0x03, /* For 11b-only countries (no 11a allowed) */ 102185377Ssam NULL1_ETSIB = 0x07, /* Israel */ 103185377Ssam NULL1_ETSIC = 0x08, 104185377Ssam FCC1_FCCA = 0x10, /* USA */ 105185377Ssam FCC1_WORLD = 0x11, /* Hong Kong */ 106185377Ssam FCC4_FCCA = 0x12, /* USA - Public Safety */ 107185380Ssam FCC5_FCCB = 0x13, /* USA w/ 1/2 and 1/4 width channels */ 108185377Ssam 109185377Ssam FCC2_FCCA = 0x20, /* Canada */ 110185377Ssam FCC2_WORLD = 0x21, /* Australia & HK */ 111185377Ssam FCC2_ETSIC = 0x22, 112185377Ssam FRANCE_RES = 0x31, /* Legacy France for OEM */ 113185377Ssam FCC3_FCCA = 0x3A, /* USA & Canada w/5470 band, 11h, DFS enabled */ 114185377Ssam FCC3_WORLD = 0x3B, /* USA & Canada w/5470 band, 11h, DFS enabled */ 115185377Ssam 116185377Ssam ETSI1_WORLD = 0x37, 117185377Ssam ETSI3_ETSIA = 0x32, /* France (optional) */ 118185377Ssam ETSI2_WORLD = 0x35, /* Hungary & others */ 119185377Ssam ETSI3_WORLD = 0x36, /* France & others */ 120185377Ssam ETSI4_WORLD = 0x30, 121185377Ssam ETSI4_ETSIC = 0x38, 122185377Ssam ETSI5_WORLD = 0x39, 123185377Ssam ETSI6_WORLD = 0x34, /* Bulgaria */ 124185377Ssam ETSI_RESERVED = 0x33, /* Reserved (Do not used) */ 125185377Ssam 126185377Ssam MKK1_MKKA = 0x40, /* Japan (JP1) */ 127185377Ssam MKK1_MKKB = 0x41, /* Japan (JP0) */ 128185377Ssam APL4_WORLD = 0x42, /* Singapore */ 129185377Ssam MKK2_MKKA = 0x43, /* Japan with 4.9G channels */ 130185377Ssam APL_RESERVED = 0x44, /* Reserved (Do not used) */ 131185377Ssam APL2_WORLD = 0x45, /* Korea */ 132185377Ssam APL2_APLC = 0x46, 133185377Ssam APL3_WORLD = 0x47, 134185377Ssam MKK1_FCCA = 0x48, /* Japan (JP1-1) */ 135185377Ssam APL2_APLD = 0x49, /* Korea with 2.3G channels */ 136185377Ssam MKK1_MKKA1 = 0x4A, /* Japan (JE1) */ 137185377Ssam MKK1_MKKA2 = 0x4B, /* Japan (JE2) */ 138185377Ssam MKK1_MKKC = 0x4C, /* Japan (MKK1_MKKA,except Ch14) */ 139185377Ssam 140185377Ssam APL3_FCCA = 0x50, 141185377Ssam APL1_WORLD = 0x52, /* Latin America */ 142185377Ssam APL1_FCCA = 0x53, 143185377Ssam APL1_APLA = 0x54, 144185377Ssam APL1_ETSIC = 0x55, 145185377Ssam APL2_ETSIC = 0x56, /* Venezuela */ 146185377Ssam APL5_WORLD = 0x58, /* Chile */ 147185377Ssam APL6_WORLD = 0x5B, /* Singapore */ 148187831Ssam APL7_FCCA = 0x5C, /* Taiwan 5.47 Band */ 149187831Ssam APL8_WORLD = 0x5D, /* Malaysia 5GHz */ 150187831Ssam APL9_WORLD = 0x5E, /* Korea 5GHz */ 151185377Ssam 152185377Ssam /* 153185377Ssam * World mode SKUs 154185377Ssam */ 155185377Ssam WOR0_WORLD = 0x60, /* World0 (WO0 SKU) */ 156185377Ssam WOR1_WORLD = 0x61, /* World1 (WO1 SKU) */ 157185377Ssam WOR2_WORLD = 0x62, /* World2 (WO2 SKU) */ 158185377Ssam WOR3_WORLD = 0x63, /* World3 (WO3 SKU) */ 159185377Ssam WOR4_WORLD = 0x64, /* World4 (WO4 SKU) */ 160185377Ssam WOR5_ETSIC = 0x65, /* World5 (WO5 SKU) */ 161185377Ssam 162185377Ssam WOR01_WORLD = 0x66, /* World0-1 (WW0-1 SKU) */ 163185377Ssam WOR02_WORLD = 0x67, /* World0-2 (WW0-2 SKU) */ 164185377Ssam EU1_WORLD = 0x68, /* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */ 165185377Ssam 166185377Ssam WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */ 167185377Ssam WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */ 168185377Ssam 169185377Ssam MKK3_MKKB = 0x80, /* Japan UNI-1 even + MKKB */ 170185377Ssam MKK3_MKKA2 = 0x81, /* Japan UNI-1 even + MKKA2 */ 171185377Ssam MKK3_MKKC = 0x82, /* Japan UNI-1 even + MKKC */ 172185377Ssam 173185377Ssam MKK4_MKKB = 0x83, /* Japan UNI-1 even + UNI-2 + MKKB */ 174185377Ssam MKK4_MKKA2 = 0x84, /* Japan UNI-1 even + UNI-2 + MKKA2 */ 175185377Ssam MKK4_MKKC = 0x85, /* Japan UNI-1 even + UNI-2 + MKKC */ 176185377Ssam 177185377Ssam MKK5_MKKB = 0x86, /* Japan UNI-1 even + UNI-2 + mid-band + MKKB */ 178185377Ssam MKK5_MKKA2 = 0x87, /* Japan UNI-1 even + UNI-2 + mid-band + MKKA2 */ 179185377Ssam MKK5_MKKC = 0x88, /* Japan UNI-1 even + UNI-2 + mid-band + MKKC */ 180185377Ssam 181185377Ssam MKK6_MKKB = 0x89, /* Japan UNI-1 even + UNI-1 odd MKKB */ 182185377Ssam MKK6_MKKA2 = 0x8A, /* Japan UNI-1 even + UNI-1 odd + MKKA2 */ 183185377Ssam MKK6_MKKC = 0x8B, /* Japan UNI-1 even + UNI-1 odd + MKKC */ 184185377Ssam 185185377Ssam MKK7_MKKB = 0x8C, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKB */ 186185377Ssam MKK7_MKKA2 = 0x8D, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKA2 */ 187185377Ssam MKK7_MKKC = 0x8E, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + MKKC */ 188185377Ssam 189185377Ssam MKK8_MKKB = 0x8F, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKB */ 190185377Ssam MKK8_MKKA2 = 0x90, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKA2 */ 191185377Ssam MKK8_MKKC = 0x91, /* Japan UNI-1 even + UNI-1 odd + UNI-2 + mid-band + MKKC */ 192185377Ssam 193185377Ssam /* Following definitions are used only by s/w to map old 194185377Ssam * Japan SKUs. 195185377Ssam */ 196185377Ssam MKK3_MKKA = 0xF0, /* Japan UNI-1 even + MKKA */ 197185377Ssam MKK3_MKKA1 = 0xF1, /* Japan UNI-1 even + MKKA1 */ 198185377Ssam MKK3_FCCA = 0xF2, /* Japan UNI-1 even + FCCA */ 199185377Ssam MKK4_MKKA = 0xF3, /* Japan UNI-1 even + UNI-2 + MKKA */ 200185377Ssam MKK4_MKKA1 = 0xF4, /* Japan UNI-1 even + UNI-2 + MKKA1 */ 201185377Ssam MKK4_FCCA = 0xF5, /* Japan UNI-1 even + UNI-2 + FCCA */ 202185377Ssam MKK9_MKKA = 0xF6, /* Japan UNI-1 even + 4.9GHz */ 203185377Ssam MKK10_MKKA = 0xF7, /* Japan UNI-1 even + UNI-2 + 4.9GHz */ 204185377Ssam 205185377Ssam /* 206185377Ssam * Regulator domains ending in a number (e.g. APL1, 207185377Ssam * MK1, ETSI4, etc) apply to 5GHz channel and power 208185377Ssam * information. Regulator domains ending in a letter 209185377Ssam * (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and 210185377Ssam * power information. 211185377Ssam */ 212185377Ssam APL1 = 0x0150, /* LAT & Asia */ 213185377Ssam APL2 = 0x0250, /* LAT & Asia */ 214185377Ssam APL3 = 0x0350, /* Taiwan */ 215185377Ssam APL4 = 0x0450, /* Jordan */ 216185377Ssam APL5 = 0x0550, /* Chile */ 217185377Ssam APL6 = 0x0650, /* Singapore */ 218185377Ssam APL8 = 0x0850, /* Malaysia */ 219185377Ssam APL9 = 0x0950, /* Korea (South) ROC 3 */ 220185377Ssam 221185377Ssam ETSI1 = 0x0130, /* Europe & others */ 222185377Ssam ETSI2 = 0x0230, /* Europe & others */ 223185377Ssam ETSI3 = 0x0330, /* Europe & others */ 224185377Ssam ETSI4 = 0x0430, /* Europe & others */ 225185377Ssam ETSI5 = 0x0530, /* Europe & others */ 226185377Ssam ETSI6 = 0x0630, /* Europe & others */ 227185377Ssam ETSIA = 0x0A30, /* France */ 228185377Ssam ETSIB = 0x0B30, /* Israel */ 229185377Ssam ETSIC = 0x0C30, /* Latin America */ 230185377Ssam 231185377Ssam FCC1 = 0x0110, /* US & others */ 232185377Ssam FCC2 = 0x0120, /* Canada, Australia & New Zealand */ 233185377Ssam FCC3 = 0x0160, /* US w/new middle band & DFS */ 234185377Ssam FCC4 = 0x0165, /* US Public Safety */ 235185380Ssam FCC5 = 0x0166, /* US w/ 1/2 and 1/4 width channels */ 236185377Ssam FCCA = 0x0A10, 237185380Ssam FCCB = 0x0A11, /* US w/ 1/2 and 1/4 width channels */ 238185377Ssam 239185377Ssam APLD = 0x0D50, /* South Korea */ 240185377Ssam 241185377Ssam MKK1 = 0x0140, /* Japan (UNI-1 odd)*/ 242185377Ssam MKK2 = 0x0240, /* Japan (4.9 GHz + UNI-1 odd) */ 243185377Ssam MKK3 = 0x0340, /* Japan (UNI-1 even) */ 244185377Ssam MKK4 = 0x0440, /* Japan (UNI-1 even + UNI-2) */ 245185377Ssam MKK5 = 0x0540, /* Japan (UNI-1 even + UNI-2 + mid-band) */ 246185377Ssam MKK6 = 0x0640, /* Japan (UNI-1 odd + UNI-1 even) */ 247185377Ssam MKK7 = 0x0740, /* Japan (UNI-1 odd + UNI-1 even + UNI-2 */ 248185377Ssam MKK8 = 0x0840, /* Japan (UNI-1 odd + UNI-1 even + UNI-2 + mid-band) */ 249185377Ssam MKK9 = 0x0940, /* Japan (UNI-1 even + 4.9 GHZ) */ 250185377Ssam MKK10 = 0x0B40, /* Japan (UNI-1 even + UNI-2 + 4.9 GHZ) */ 251185377Ssam MKKA = 0x0A40, /* Japan */ 252185377Ssam MKKC = 0x0A50, 253185377Ssam 254185377Ssam NULL1 = 0x0198, 255185377Ssam WORLD = 0x0199, 256185377Ssam DEBUG_REG_DMN = 0x01ff, 257185377Ssam}; 258185377Ssam 259185377Ssam#define WORLD_SKU_MASK 0x00F0 260185377Ssam#define WORLD_SKU_PREFIX 0x0060 261185377Ssam 262185377Ssamenum { /* conformance test limits */ 263185377Ssam FCC = 0x10, 264185377Ssam MKK = 0x40, 265185377Ssam ETSI = 0x30, 266185377Ssam}; 267185377Ssam 268185377Ssam/* 269185377Ssam * The following are flags for different requirements per reg domain. 270185377Ssam * These requirements are either inhereted from the reg domain pair or 271185380Ssam * from the unitary reg domain if the reg domain pair flags value is 0 272185377Ssam */ 273185377Ssamenum { 274185380Ssam NO_REQ = 0x00000000, /* NB: must be zero */ 275187831Ssam DISALLOW_ADHOC_11A = 0x00000001, /* adhoc not allowed in 5GHz */ 276187831Ssam DISALLOW_ADHOC_11A_TURB = 0x00000002, /* not allowed w/ 5GHz turbo */ 277187831Ssam NEED_NFC = 0x00000004, /* need noise floor check */ 278187831Ssam ADHOC_PER_11D = 0x00000008, /* must receive 11d beacon */ 279187831Ssam LIMIT_FRAME_4MS = 0x00000020, /* 4msec tx burst limit */ 280185380Ssam NO_HOSTAP = 0x00000040, /* No HOSTAP mode opereation */ 281185377Ssam}; 282185377Ssam 283185377Ssam/* 284185377Ssam * The following describe the bit masks for different passive scan 285185377Ssam * capability/requirements per regdomain. 286185377Ssam */ 287185380Ssam#define NO_PSCAN 0x0ULL /* NB: must be zero */ 288185377Ssam#define PSCAN_FCC 0x0000000000000001ULL 289185377Ssam#define PSCAN_FCC_T 0x0000000000000002ULL 290185377Ssam#define PSCAN_ETSI 0x0000000000000004ULL 291185377Ssam#define PSCAN_MKK1 0x0000000000000008ULL 292185377Ssam#define PSCAN_MKK2 0x0000000000000010ULL 293185377Ssam#define PSCAN_MKKA 0x0000000000000020ULL 294185377Ssam#define PSCAN_MKKA_G 0x0000000000000040ULL 295185377Ssam#define PSCAN_ETSIA 0x0000000000000080ULL 296185377Ssam#define PSCAN_ETSIB 0x0000000000000100ULL 297185377Ssam#define PSCAN_ETSIC 0x0000000000000200ULL 298185377Ssam#define PSCAN_WWR 0x0000000000000400ULL 299185377Ssam#define PSCAN_MKKA1 0x0000000000000800ULL 300185377Ssam#define PSCAN_MKKA1_G 0x0000000000001000ULL 301185377Ssam#define PSCAN_MKKA2 0x0000000000002000ULL 302185377Ssam#define PSCAN_MKKA2_G 0x0000000000004000ULL 303185377Ssam#define PSCAN_MKK3 0x0000000000008000ULL 304185377Ssam#define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL 305185377Ssam#define IS_ECM_CHAN 0x8000000000000000ULL 306185377Ssam 307185377Ssam/* 308185377Ssam * THE following table is the mapping of regdomain pairs specified by 309185377Ssam * an 8 bit regdomain value to the individual unitary reg domains 310185377Ssam */ 311187831Ssamtypedef struct regDomainPair { 312185377Ssam HAL_REG_DOMAIN regDmnEnum; /* 16 bit reg domain pair */ 313185377Ssam HAL_REG_DOMAIN regDmn5GHz; /* 5GHz reg domain */ 314185377Ssam HAL_REG_DOMAIN regDmn2GHz; /* 2GHz reg domain */ 315185377Ssam uint32_t flags5GHz; /* Requirements flags (AdHoc 316185377Ssam disallow, noise floor cal needed, 317185377Ssam etc) */ 318185377Ssam uint32_t flags2GHz; /* Requirements flags (AdHoc 319185377Ssam disallow, noise floor cal needed, 320185377Ssam etc) */ 321185377Ssam uint64_t pscanMask; /* Passive Scan flags which 322185377Ssam can override unitary domain 323185377Ssam passive scan flags. This 324185377Ssam value is used as a mask on 325185377Ssam the unitary flags*/ 326185377Ssam uint16_t singleCC; /* Country code of single country if 327185377Ssam a one-on-one mapping exists */ 328185377Ssam} REG_DMN_PAIR_MAPPING; 329185377Ssam 330185377Ssamstatic REG_DMN_PAIR_MAPPING regDomainPairs[] = { 331187831Ssam {NO_ENUMRD, DEBUG_REG_DMN, DEBUG_REG_DMN, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 332187831Ssam {NULL1_WORLD, NULL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 333187831Ssam {NULL1_ETSIB, NULL1, ETSIB, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 334187831Ssam {NULL1_ETSIC, NULL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 335185377Ssam 336187831Ssam {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 337187831Ssam {FCC2_WORLD, FCC2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 338187831Ssam {FCC2_ETSIC, FCC2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 339187831Ssam {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 340187831Ssam {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 341187831Ssam {FCC4_FCCA, FCC4, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 342187831Ssam {FCC5_FCCB, FCC5, FCCB, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 343185377Ssam 344187831Ssam {ETSI1_WORLD, ETSI1, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 345187831Ssam {ETSI2_WORLD, ETSI2, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 346187831Ssam {ETSI3_WORLD, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 347187831Ssam {ETSI4_WORLD, ETSI4, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 348187831Ssam {ETSI5_WORLD, ETSI5, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 349187831Ssam {ETSI6_WORLD, ETSI6, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 350185377Ssam 351187831Ssam {ETSI3_ETSIA, ETSI3, WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 352187831Ssam {FRANCE_RES, ETSI3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 353185377Ssam 354187831Ssam {FCC1_WORLD, FCC1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 355187831Ssam {FCC1_FCCA, FCC1, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 356187831Ssam {APL1_WORLD, APL1, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 357187831Ssam {APL2_WORLD, APL2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 358187831Ssam {APL3_WORLD, APL3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 359187831Ssam {APL4_WORLD, APL4, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 360187831Ssam {APL5_WORLD, APL5, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 361187831Ssam {APL6_WORLD, APL6, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 362187831Ssam {APL8_WORLD, APL8, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 363187831Ssam {APL9_WORLD, APL9, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 364185377Ssam 365187831Ssam {APL3_FCCA, APL3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 366187831Ssam {APL1_ETSIC, APL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 367187831Ssam {APL2_ETSIC, APL2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 368187831Ssam {APL2_APLD, APL2, APLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 369185377Ssam 370185377Ssam {MKK1_MKKA, MKK1, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA, CTRY_JAPAN }, 371185377Ssam {MKK1_MKKB, MKK1, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN1 }, 372185377Ssam {MKK1_FCCA, MKK1, FCCA, DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN2 }, 373185377Ssam {MKK1_MKKA1, MKK1, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_JAPAN4 }, 374185377Ssam {MKK1_MKKA2, MKK1, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN5 }, 375185377Ssam {MKK1_MKKC, MKK1, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN6 }, 376185377Ssam 377185377Ssam /* MKK2 */ 378185377Ssam {MKK2_MKKA, MKK2, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC| LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK2 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN3 }, 379185377Ssam 380185377Ssam /* MKK3 */ 381187831Ssam {MKK3_MKKA, MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC , PSCAN_MKKA, CTRY_DEFAULT }, 382185377Ssam {MKK3_MKKB, MKK3, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN7 }, 383187831Ssam {MKK3_MKKA1, MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_DEFAULT }, 384185377Ssam {MKK3_MKKA2,MKK3, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN8 }, 385185377Ssam {MKK3_MKKC, MKK3, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, NO_PSCAN, CTRY_JAPAN9 }, 386187831Ssam {MKK3_FCCA, MKK3, FCCA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, NO_PSCAN, CTRY_DEFAULT }, 387185377Ssam 388185377Ssam /* MKK4 */ 389185377Ssam {MKK4_MKKB, MKK4, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN10 }, 390187831Ssam {MKK4_MKKA1, MKK4, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA1 | PSCAN_MKKA1_G, CTRY_DEFAULT }, 391185377Ssam {MKK4_MKKA2, MKK4, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 |PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN11 }, 392185377Ssam {MKK4_MKKC, MKK4, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN12 }, 393187831Ssam {MKK4_FCCA, MKK4, FCCA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_DEFAULT }, 394185377Ssam 395185377Ssam /* MKK5 */ 396185377Ssam {MKK5_MKKB, MKK5, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN13 }, 397185377Ssam {MKK5_MKKA2,MKK5, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN14 }, 398185377Ssam {MKK5_MKKC, MKK5, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3, CTRY_JAPAN15 }, 399185377Ssam 400185377Ssam /* MKK6 */ 401185377Ssam {MKK6_MKKB, MKK6, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN16 }, 402185377Ssam {MKK6_MKKA2, MKK6, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN17 }, 403185377Ssam {MKK6_MKKC, MKK6, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1, CTRY_JAPAN18 }, 404185377Ssam 405185377Ssam /* MKK7 */ 406185377Ssam {MKK7_MKKB, MKK7, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN19 }, 407185377Ssam {MKK7_MKKA2, MKK7, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN20 }, 408185377Ssam {MKK7_MKKC, MKK7, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3, CTRY_JAPAN21 }, 409185377Ssam 410185377Ssam /* MKK8 */ 411185377Ssam {MKK8_MKKB, MKK8, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_JAPAN22 }, 412185377Ssam {MKK8_MKKA2,MKK8, MKKA, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 | PSCAN_MKKA2 | PSCAN_MKKA2_G, CTRY_JAPAN23 }, 413185377Ssam {MKK8_MKKC, MKK8, MKKC, DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK1 | PSCAN_MKK3 , CTRY_JAPAN24 }, 414185377Ssam 415187831Ssam {MKK9_MKKA, MKK9, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_DEFAULT }, 416187831Ssam {MKK10_MKKA, MKK10, MKKA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB | NEED_NFC | LIMIT_FRAME_4MS, NEED_NFC, PSCAN_MKK3 | PSCAN_MKKA | PSCAN_MKKA_G, CTRY_DEFAULT }, 417185377Ssam 418185377Ssam /* These are super domains */ 419187831Ssam {WOR0_WORLD, WOR0_WORLD, WOR0_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 420187831Ssam {WOR1_WORLD, WOR1_WORLD, WOR1_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 421187831Ssam {WOR2_WORLD, WOR2_WORLD, WOR2_WORLD, DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 422187831Ssam {WOR3_WORLD, WOR3_WORLD, WOR3_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 423187831Ssam {WOR4_WORLD, WOR4_WORLD, WOR4_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 424187831Ssam {WOR5_ETSIC, WOR5_ETSIC, WOR5_ETSIC, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 425187831Ssam {WOR01_WORLD, WOR01_WORLD, WOR01_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 426187831Ssam {WOR02_WORLD, WOR02_WORLD, WOR02_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 427187831Ssam {EU1_WORLD, EU1_WORLD, EU1_WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 428187831Ssam {WOR9_WORLD, WOR9_WORLD, WOR9_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 429187831Ssam {WORA_WORLD, WORA_WORLD, WORA_WORLD, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, CTRY_DEFAULT }, 430185377Ssam}; 431185377Ssam 432185377Ssam/* 433185380Ssam * The following tables are the master list for all different freqeuncy 434185377Ssam * bands with the complete matrix of all possible flags and settings 435185377Ssam * for each band if it is used in ANY reg domain. 436185377Ssam */ 437185377Ssam 438185377Ssam#define DEF_REGDMN FCC1_FCCA 439185377Ssam#define COUNTRY_ERD_FLAG 0x8000 440185377Ssam#define WORLDWIDE_ROAMING_FLAG 0x4000 441185377Ssam 442185377Ssamtypedef struct { 443185377Ssam HAL_CTRY_CODE countryCode; 444185377Ssam HAL_REG_DOMAIN regDmnEnum; 445185377Ssam} COUNTRY_CODE_TO_ENUM_RD; 446185377Ssam 447185377Ssamstatic COUNTRY_CODE_TO_ENUM_RD allCountries[] = { 448187831Ssam { CTRY_DEBUG, NO_ENUMRD }, 449187831Ssam { CTRY_DEFAULT, DEF_REGDMN }, 450187831Ssam { CTRY_ALBANIA, NULL1_WORLD }, 451187831Ssam { CTRY_ALGERIA, NULL1_WORLD }, 452187831Ssam { CTRY_ARGENTINA, APL3_WORLD }, 453187831Ssam { CTRY_ARMENIA, ETSI4_WORLD }, 454187831Ssam { CTRY_AUSTRALIA, FCC2_WORLD }, 455187831Ssam { CTRY_AUSTRIA, ETSI1_WORLD }, 456187831Ssam { CTRY_AZERBAIJAN, ETSI4_WORLD }, 457187831Ssam { CTRY_BAHRAIN, APL6_WORLD }, 458187831Ssam { CTRY_BELARUS, NULL1_WORLD }, 459187831Ssam { CTRY_BELGIUM, ETSI1_WORLD }, 460187831Ssam { CTRY_BELIZE, APL1_ETSIC }, 461187831Ssam { CTRY_BOLIVIA, APL1_ETSIC }, 462187831Ssam { CTRY_BRAZIL, FCC3_WORLD }, 463187831Ssam { CTRY_BRUNEI_DARUSSALAM,APL1_WORLD }, 464187831Ssam { CTRY_BULGARIA, ETSI6_WORLD }, 465187831Ssam { CTRY_CANADA, FCC2_FCCA }, 466187831Ssam { CTRY_CHILE, APL6_WORLD }, 467187831Ssam { CTRY_CHINA, APL1_WORLD }, 468187831Ssam { CTRY_COLOMBIA, FCC1_FCCA }, 469187831Ssam { CTRY_COSTA_RICA, NULL1_WORLD }, 470187831Ssam { CTRY_CROATIA, ETSI3_WORLD }, 471187831Ssam { CTRY_CYPRUS, ETSI1_WORLD }, 472187831Ssam { CTRY_CZECH, ETSI1_WORLD }, 473187831Ssam { CTRY_DENMARK, ETSI1_WORLD }, 474187831Ssam { CTRY_DOMINICAN_REPUBLIC,FCC1_FCCA }, 475187831Ssam { CTRY_ECUADOR, NULL1_WORLD }, 476187831Ssam { CTRY_EGYPT, ETSI3_WORLD }, 477187831Ssam { CTRY_EL_SALVADOR, NULL1_WORLD }, 478187831Ssam { CTRY_ESTONIA, ETSI1_WORLD }, 479187831Ssam { CTRY_FINLAND, ETSI1_WORLD }, 480187831Ssam { CTRY_FRANCE, ETSI1_WORLD }, 481187831Ssam { CTRY_FRANCE2, ETSI3_WORLD }, 482187831Ssam { CTRY_GEORGIA, ETSI4_WORLD }, 483187831Ssam { CTRY_GERMANY, ETSI1_WORLD }, 484187831Ssam { CTRY_GREECE, ETSI1_WORLD }, 485187831Ssam { CTRY_GUATEMALA, FCC1_FCCA }, 486187831Ssam { CTRY_HONDURAS, NULL1_WORLD }, 487187831Ssam { CTRY_HONG_KONG, FCC2_WORLD }, 488187831Ssam { CTRY_HUNGARY, ETSI1_WORLD }, 489187831Ssam { CTRY_ICELAND, ETSI1_WORLD }, 490187831Ssam { CTRY_INDIA, APL6_WORLD }, 491187831Ssam { CTRY_INDONESIA, APL1_WORLD }, 492187831Ssam { CTRY_IRAN, APL1_WORLD }, 493187831Ssam { CTRY_IRELAND, ETSI1_WORLD }, 494187831Ssam { CTRY_ISRAEL, NULL1_WORLD }, 495187831Ssam { CTRY_ITALY, ETSI1_WORLD }, 496187831Ssam { CTRY_JAPAN, MKK1_MKKA }, 497187831Ssam { CTRY_JAPAN1, MKK1_MKKB }, 498187831Ssam { CTRY_JAPAN2, MKK1_FCCA }, 499187831Ssam { CTRY_JAPAN3, MKK2_MKKA }, 500187831Ssam { CTRY_JAPAN4, MKK1_MKKA1 }, 501187831Ssam { CTRY_JAPAN5, MKK1_MKKA2 }, 502187831Ssam { CTRY_JAPAN6, MKK1_MKKC }, 503185377Ssam 504187831Ssam { CTRY_JAPAN7, MKK3_MKKB }, 505187831Ssam { CTRY_JAPAN8, MKK3_MKKA2 }, 506187831Ssam { CTRY_JAPAN9, MKK3_MKKC }, 507185377Ssam 508187831Ssam { CTRY_JAPAN10, MKK4_MKKB }, 509187831Ssam { CTRY_JAPAN11, MKK4_MKKA2 }, 510187831Ssam { CTRY_JAPAN12, MKK4_MKKC }, 511185377Ssam 512187831Ssam { CTRY_JAPAN13, MKK5_MKKB }, 513187831Ssam { CTRY_JAPAN14, MKK5_MKKA2 }, 514187831Ssam { CTRY_JAPAN15, MKK5_MKKC }, 515185377Ssam 516187831Ssam { CTRY_JAPAN16, MKK6_MKKB }, 517187831Ssam { CTRY_JAPAN17, MKK6_MKKA2 }, 518187831Ssam { CTRY_JAPAN18, MKK6_MKKC }, 519185377Ssam 520187831Ssam { CTRY_JAPAN19, MKK7_MKKB }, 521187831Ssam { CTRY_JAPAN20, MKK7_MKKA2 }, 522187831Ssam { CTRY_JAPAN21, MKK7_MKKC }, 523185377Ssam 524187831Ssam { CTRY_JAPAN22, MKK8_MKKB }, 525187831Ssam { CTRY_JAPAN23, MKK8_MKKA2 }, 526187831Ssam { CTRY_JAPAN24, MKK8_MKKC }, 527185377Ssam 528187831Ssam { CTRY_JORDAN, APL4_WORLD }, 529187831Ssam { CTRY_KAZAKHSTAN, NULL1_WORLD }, 530187831Ssam { CTRY_KOREA_NORTH, APL2_WORLD }, 531187831Ssam { CTRY_KOREA_ROC, APL2_WORLD }, 532187831Ssam { CTRY_KOREA_ROC2, APL2_WORLD }, 533187831Ssam { CTRY_KOREA_ROC3, APL9_WORLD }, 534187831Ssam { CTRY_KUWAIT, NULL1_WORLD }, 535187831Ssam { CTRY_LATVIA, ETSI1_WORLD }, 536187831Ssam { CTRY_LEBANON, NULL1_WORLD }, 537187831Ssam { CTRY_LIECHTENSTEIN,ETSI1_WORLD }, 538187831Ssam { CTRY_LITHUANIA, ETSI1_WORLD }, 539187831Ssam { CTRY_LUXEMBOURG, ETSI1_WORLD }, 540187831Ssam { CTRY_MACAU, FCC2_WORLD }, 541187831Ssam { CTRY_MACEDONIA, NULL1_WORLD }, 542187831Ssam { CTRY_MALAYSIA, APL8_WORLD }, 543187831Ssam { CTRY_MALTA, ETSI1_WORLD }, 544187831Ssam { CTRY_MEXICO, FCC1_FCCA }, 545187831Ssam { CTRY_MONACO, ETSI4_WORLD }, 546187831Ssam { CTRY_MOROCCO, NULL1_WORLD }, 547187831Ssam { CTRY_NETHERLANDS, ETSI1_WORLD }, 548187831Ssam { CTRY_NEW_ZEALAND, FCC2_ETSIC }, 549187831Ssam { CTRY_NORWAY, ETSI1_WORLD }, 550187831Ssam { CTRY_OMAN, APL6_WORLD }, 551187831Ssam { CTRY_PAKISTAN, NULL1_WORLD }, 552187831Ssam { CTRY_PANAMA, FCC1_FCCA }, 553187831Ssam { CTRY_PERU, APL1_WORLD }, 554187831Ssam { CTRY_PHILIPPINES, FCC3_WORLD }, 555187831Ssam { CTRY_POLAND, ETSI1_WORLD }, 556187831Ssam { CTRY_PORTUGAL, ETSI1_WORLD }, 557187831Ssam { CTRY_PUERTO_RICO, FCC1_FCCA }, 558187831Ssam { CTRY_QATAR, NULL1_WORLD }, 559187831Ssam { CTRY_ROMANIA, NULL1_WORLD }, 560187831Ssam { CTRY_RUSSIA, NULL1_WORLD }, 561187831Ssam { CTRY_SAUDI_ARABIA,FCC2_WORLD }, 562187831Ssam { CTRY_SINGAPORE, APL6_WORLD }, 563187831Ssam { CTRY_SLOVAKIA, ETSI1_WORLD }, 564187831Ssam { CTRY_SLOVENIA, ETSI1_WORLD }, 565187831Ssam { CTRY_SOUTH_AFRICA,FCC3_WORLD }, 566187831Ssam { CTRY_SPAIN, ETSI1_WORLD }, 567187831Ssam { CTRY_SWEDEN, ETSI1_WORLD }, 568187831Ssam { CTRY_SWITZERLAND, ETSI1_WORLD }, 569187831Ssam { CTRY_SYRIA, NULL1_WORLD }, 570187831Ssam { CTRY_TAIWAN, APL3_FCCA }, 571187831Ssam { CTRY_THAILAND, NULL1_WORLD }, 572187831Ssam { CTRY_TRINIDAD_Y_TOBAGO,ETSI4_WORLD }, 573187831Ssam { CTRY_TUNISIA, ETSI3_WORLD }, 574187831Ssam { CTRY_TURKEY, ETSI3_WORLD }, 575187831Ssam { CTRY_UKRAINE, NULL1_WORLD }, 576187831Ssam { CTRY_UAE, NULL1_WORLD }, 577187831Ssam { CTRY_UNITED_KINGDOM, ETSI1_WORLD }, 578187831Ssam { CTRY_UNITED_STATES, FCC1_FCCA }, 579187831Ssam { CTRY_UNITED_STATES_FCC49,FCC4_FCCA }, 580187831Ssam { CTRY_URUGUAY, FCC1_WORLD }, 581187831Ssam { CTRY_UZBEKISTAN, FCC3_FCCA }, 582187831Ssam { CTRY_VENEZUELA, APL2_ETSIC }, 583187831Ssam { CTRY_VIET_NAM, NULL1_WORLD }, 584187831Ssam { CTRY_ZIMBABWE, NULL1_WORLD } 585185377Ssam}; 586185377Ssam 587185380Ssam/* Bit masks for DFS per regdomain */ 588185380Ssamenum { 589185380Ssam NO_DFS = 0x0000000000000000ULL, /* NB: must be zero */ 590185380Ssam DFS_FCC3 = 0x0000000000000001ULL, 591185380Ssam DFS_ETSI = 0x0000000000000002ULL, 592185380Ssam DFS_MKK4 = 0x0000000000000004ULL, 593185380Ssam}; 594185380Ssam 595185380Ssam#define AFTER(x) ((x)+1) 596185380Ssam 597185380Ssam/* 598185380Ssam * Frequency band collections are defined using bitmasks. Each bit 599185380Ssam * in a mask is the index of an entry in one of the following tables. 600185380Ssam * Bitmasks are BMLEN*64 bits so if a table grows beyond that the bit 601185380Ssam * vectors must be enlarged or the tables split somehow (e.g. split 602185380Ssam * 1/2 and 1/4 rate channels into a separate table). 603185380Ssam * 604185380Ssam * Beware of ordering; the indices are defined relative to the preceding 605185380Ssam * entry so if things get off there will be confusion. A good way to 606185380Ssam * check the indices is to collect them in a switch statement in a stub 607185380Ssam * function so the compiler checks for duplicates. 608185380Ssam */ 609185380Ssam 610185380Ssamtypedef struct { 611185377Ssam uint16_t lowChannel; /* Low channel center in MHz */ 612185377Ssam uint16_t highChannel; /* High Channel center in MHz */ 613185377Ssam uint8_t powerDfs; /* Max power (dBm) for channel 614185377Ssam range when using DFS */ 615185377Ssam uint8_t antennaMax; /* Max allowed antenna gain */ 616185377Ssam uint8_t channelBW; /* Bandwidth of the channel */ 617185377Ssam uint8_t channelSep; /* Channel separation within 618185377Ssam the band */ 619185377Ssam uint64_t useDfs; /* Use DFS in the RegDomain 620185377Ssam if corresponding bit is set */ 621185377Ssam uint64_t usePassScan; /* Use Passive Scan in the RegDomain 622185377Ssam if corresponding bit is set */ 623185377Ssam} REG_DMN_FREQ_BAND; 624185377Ssam 625185377Ssam/* 626185377Ssam * 5GHz 11A channel tags 627185377Ssam */ 628185377Ssamstatic REG_DMN_FREQ_BAND regDmn5GhzFreq[] = { 629187831Ssam { 4915, 4925, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 }, 630185380Ssam#define F1_4915_4925 0 631187831Ssam { 4935, 4945, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 }, 632185380Ssam#define F1_4935_4945 AFTER(F1_4915_4925) 633187831Ssam { 4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2 }, 634185380Ssam#define F1_4920_4980 AFTER(F1_4935_4945) 635187831Ssam { 4942, 4987, 27, 6, 5, 5, NO_DFS, PSCAN_FCC }, 636185380Ssam#define F1_4942_4987 AFTER(F1_4920_4980) 637187831Ssam { 4945, 4985, 30, 6, 10, 5, NO_DFS, PSCAN_FCC }, 638185380Ssam#define F1_4945_4985 AFTER(F1_4942_4987) 639187831Ssam { 4950, 4980, 33, 6, 20, 5, NO_DFS, PSCAN_FCC }, 640185380Ssam#define F1_4950_4980 AFTER(F1_4945_4985) 641187831Ssam { 5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 }, 642185380Ssam#define F1_5035_5040 AFTER(F1_4950_4980) 643187831Ssam { 5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2 }, 644185380Ssam#define F1_5040_5080 AFTER(F1_5035_5040) 645187831Ssam { 5055, 5055, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 }, 646185380Ssam#define F1_5055_5055 AFTER(F1_5040_5080) 647185377Ssam 648187831Ssam { 5120, 5240, 5, 6, 20, 20, NO_DFS, NO_PSCAN }, 649185380Ssam#define F1_5120_5240 AFTER(F1_5055_5055) 650187831Ssam { 5120, 5240, 5, 6, 10, 10, NO_DFS, NO_PSCAN }, 651185380Ssam#define F2_5120_5240 AFTER(F1_5120_5240) 652187831Ssam { 5120, 5240, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 653185380Ssam#define F3_5120_5240 AFTER(F2_5120_5240) 654185377Ssam 655187831Ssam { 5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2 }, 656185380Ssam#define F1_5170_5230 AFTER(F3_5120_5240) 657187831Ssam { 5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2 }, 658185380Ssam#define F2_5170_5230 AFTER(F1_5170_5230) 659185377Ssam 660187831Ssam { 5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI }, 661185380Ssam#define F1_5180_5240 AFTER(F2_5170_5230) 662187831Ssam { 5180, 5240, 17, 6, 20, 20, NO_DFS, PSCAN_FCC }, 663185380Ssam#define F2_5180_5240 AFTER(F1_5180_5240) 664187831Ssam { 5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI }, 665185380Ssam#define F3_5180_5240 AFTER(F2_5180_5240) 666187831Ssam { 5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI }, 667185380Ssam#define F4_5180_5240 AFTER(F3_5180_5240) 668187831Ssam { 5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI }, 669185380Ssam#define F5_5180_5240 AFTER(F4_5180_5240) 670187831Ssam { 5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC }, 671185380Ssam#define F6_5180_5240 AFTER(F5_5180_5240) 672187831Ssam { 5180, 5240, 17, 6, 20, 10, NO_DFS, PSCAN_FCC }, 673185380Ssam#define F7_5180_5240 AFTER(F6_5180_5240) 674187831Ssam { 5180, 5240, 17, 6, 20, 5, NO_DFS, PSCAN_FCC }, 675185380Ssam#define F8_5180_5240 AFTER(F7_5180_5240) 676187831Ssam { 5180, 5320, 20, 6, 20, 20, DFS_ETSI, PSCAN_ETSI }, 677185377Ssam 678185380Ssam#define F1_5180_5320 AFTER(F8_5180_5240) 679187831Ssam { 5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI }, 680185377Ssam 681185380Ssam#define F1_5240_5280 AFTER(F1_5180_5320) 682187831Ssam { 5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI }, 683185377Ssam 684185380Ssam#define F1_5260_5280 AFTER(F1_5240_5280) 685187831Ssam { 5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI }, 686185377Ssam 687185380Ssam#define F1_5260_5320 AFTER(F1_5260_5280) 688187831Ssam { 5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3 }, 689185380Ssam#define F2_5260_5320 AFTER(F1_5260_5320) 690185377Ssam 691187831Ssam { 5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 692185380Ssam#define F3_5260_5320 AFTER(F2_5260_5320) 693187831Ssam { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 694185380Ssam#define F4_5260_5320 AFTER(F3_5260_5320) 695187831Ssam { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 696185380Ssam#define F5_5260_5320 AFTER(F4_5260_5320) 697187831Ssam { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN }, 698185380Ssam#define F6_5260_5320 AFTER(F5_5260_5320) 699187831Ssam { 5260, 5320, 23, 6, 20, 10, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 700185380Ssam#define F7_5260_5320 AFTER(F6_5260_5320) 701187831Ssam { 5260, 5320, 23, 6, 20, 5, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 702185380Ssam#define F8_5260_5320 AFTER(F7_5260_5320) 703185377Ssam 704187831Ssam { 5260, 5700, 5, 6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN }, 705185380Ssam#define F1_5260_5700 AFTER(F8_5260_5320) 706187831Ssam { 5260, 5700, 5, 6, 10, 10, DFS_FCC3 | DFS_ETSI, NO_PSCAN }, 707185380Ssam#define F2_5260_5700 AFTER(F1_5260_5700) 708187831Ssam { 5260, 5700, 5, 6, 5, 5, DFS_FCC3 | DFS_ETSI, NO_PSCAN }, 709185380Ssam#define F3_5260_5700 AFTER(F2_5260_5700) 710185377Ssam 711187831Ssam { 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 712185380Ssam#define F1_5280_5320 AFTER(F3_5260_5700) 713185377Ssam 714187831Ssam { 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI }, 715185380Ssam#define F1_5500_5620 AFTER(F1_5280_5320) 716185377Ssam 717187831Ssam { 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 718185380Ssam#define F1_5500_5700 AFTER(F1_5500_5620) 719187831Ssam { 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI }, 720185380Ssam#define F2_5500_5700 AFTER(F1_5500_5700) 721187831Ssam { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI }, 722185380Ssam#define F3_5500_5700 AFTER(F2_5500_5700) 723187831Ssam { 5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC }, 724185380Ssam#define F4_5500_5700 AFTER(F3_5500_5700) 725185377Ssam 726187831Ssam { 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN }, 727185380Ssam#define F1_5745_5805 AFTER(F4_5500_5700) 728187831Ssam { 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN }, 729185380Ssam#define F2_5745_5805 AFTER(F1_5745_5805) 730187831Ssam { 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI }, 731185380Ssam#define F3_5745_5805 AFTER(F2_5745_5805) 732187831Ssam { 5745, 5825, 5, 6, 20, 20, NO_DFS, NO_PSCAN }, 733185380Ssam#define F1_5745_5825 AFTER(F3_5745_5805) 734187831Ssam { 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN }, 735185380Ssam#define F2_5745_5825 AFTER(F1_5745_5825) 736187831Ssam { 5745, 5825, 20, 0, 20, 20, NO_DFS, NO_PSCAN }, 737185380Ssam#define F3_5745_5825 AFTER(F2_5745_5825) 738187831Ssam { 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN }, 739185380Ssam#define F4_5745_5825 AFTER(F3_5745_5825) 740187831Ssam { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN }, 741185380Ssam#define F5_5745_5825 AFTER(F4_5745_5825) 742187831Ssam { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN }, 743185380Ssam#define F6_5745_5825 AFTER(F5_5745_5825) 744187831Ssam { 5745, 5825, 5, 6, 10, 10, NO_DFS, NO_PSCAN }, 745185380Ssam#define F7_5745_5825 AFTER(F6_5745_5825) 746187831Ssam { 5745, 5825, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 747185380Ssam#define F8_5745_5825 AFTER(F7_5745_5825) 748187831Ssam { 5745, 5825, 30, 6, 20, 10, NO_DFS, NO_PSCAN }, 749185380Ssam#define F9_5745_5825 AFTER(F8_5745_5825) 750187831Ssam { 5745, 5825, 30, 6, 20, 5, NO_DFS, NO_PSCAN }, 751185380Ssam#define F10_5745_5825 AFTER(F9_5745_5825) 752185377Ssam 753185377Ssam /* 754185377Ssam * Below are the world roaming channels 755185377Ssam * All WWR domains have no power limit, instead use the card's CTL 756185377Ssam * or max power settings. 757185377Ssam */ 758187831Ssam { 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR }, 759185380Ssam#define W1_4920_4980 AFTER(F10_5745_5825) 760187831Ssam { 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR }, 761185380Ssam#define W1_5040_5080 AFTER(W1_4920_4980) 762187831Ssam { 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 763185380Ssam#define W1_5170_5230 AFTER(W1_5040_5080) 764187831Ssam { 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 765185380Ssam#define W1_5180_5240 AFTER(W1_5170_5230) 766187831Ssam { 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 767185380Ssam#define W1_5260_5320 AFTER(W1_5180_5240) 768187831Ssam { 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR }, 769185380Ssam#define W1_5745_5825 AFTER(W1_5260_5320) 770187831Ssam { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 771185380Ssam#define W1_5500_5700 AFTER(W1_5745_5825) 772187831Ssam { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN }, 773185380Ssam#define W2_5260_5320 AFTER(W1_5500_5700) 774187831Ssam { 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN }, 775185380Ssam#define W2_5180_5240 AFTER(W2_5260_5320) 776187831Ssam { 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR }, 777185380Ssam#define W2_5825_5825 AFTER(W2_5180_5240) 778185377Ssam}; 779185377Ssam 780185377Ssam/* 781185377Ssam * 5GHz Turbo (dynamic & static) tags 782185377Ssam */ 783185377Ssamstatic REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = { 784187831Ssam { 5130, 5210, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 785185380Ssam#define T1_5130_5210 0 786187831Ssam { 5250, 5330, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, 787185380Ssam#define T1_5250_5330 AFTER(T1_5130_5210) 788187831Ssam { 5370, 5490, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 789185380Ssam#define T1_5370_5490 AFTER(T1_5250_5330) 790187831Ssam { 5530, 5650, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, 791185380Ssam#define T1_5530_5650 AFTER(T1_5370_5490) 792185377Ssam 793187831Ssam { 5150, 5190, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 794185380Ssam#define T1_5150_5190 AFTER(T1_5530_5650) 795187831Ssam { 5230, 5310, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, 796185380Ssam#define T1_5230_5310 AFTER(T1_5150_5190) 797187831Ssam { 5350, 5470, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 798185380Ssam#define T1_5350_5470 AFTER(T1_5230_5310) 799187831Ssam { 5510, 5670, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, 800185380Ssam#define T1_5510_5670 AFTER(T1_5350_5470) 801185377Ssam 802187831Ssam { 5200, 5240, 17, 6, 40, 40, NO_DFS, NO_PSCAN }, 803185380Ssam#define T1_5200_5240 AFTER(T1_5510_5670) 804187831Ssam { 5200, 5240, 23, 6, 40, 40, NO_DFS, NO_PSCAN }, 805185380Ssam#define T2_5200_5240 AFTER(T1_5200_5240) 806187831Ssam { 5210, 5210, 17, 6, 40, 40, NO_DFS, NO_PSCAN }, 807185380Ssam#define T1_5210_5210 AFTER(T2_5200_5240) 808187831Ssam { 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN }, 809185380Ssam#define T2_5210_5210 AFTER(T1_5210_5210) 810185377Ssam 811187831Ssam { 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 812185380Ssam#define T1_5280_5280 AFTER(T2_5210_5210) 813187831Ssam { 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 814185380Ssam#define T2_5280_5280 AFTER(T1_5280_5280) 815187831Ssam { 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 816185380Ssam#define T1_5250_5250 AFTER(T2_5280_5280) 817187831Ssam { 5290, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 818185380Ssam#define T1_5290_5290 AFTER(T1_5250_5250) 819187831Ssam { 5250, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 820185380Ssam#define T1_5250_5290 AFTER(T1_5290_5290) 821187831Ssam { 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 822185380Ssam#define T2_5250_5290 AFTER(T1_5250_5290) 823185377Ssam 824187831Ssam { 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 825185380Ssam#define T1_5540_5660 AFTER(T2_5250_5290) 826187831Ssam { 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN }, 827185380Ssam#define T1_5760_5800 AFTER(T1_5540_5660) 828187831Ssam { 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN }, 829185380Ssam#define T2_5760_5800 AFTER(T1_5760_5800) 830185377Ssam 831187831Ssam { 5765, 5805, 30, 6, 40, 40, NO_DFS, NO_PSCAN }, 832185380Ssam#define T1_5765_5805 AFTER(T2_5760_5800) 833185377Ssam 834185377Ssam /* 835185377Ssam * Below are the WWR frequencies 836185377Ssam */ 837187831Ssam { 5210, 5250, 15, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 838185380Ssam#define WT1_5210_5250 AFTER(T1_5765_5805) 839187831Ssam { 5290, 5290, 18, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 840185380Ssam#define WT1_5290_5290 AFTER(WT1_5210_5250) 841187831Ssam { 5540, 5660, 20, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 842185380Ssam#define WT1_5540_5660 AFTER(WT1_5290_5290) 843187831Ssam { 5760, 5800, 20, 0, 40, 40, NO_DFS, PSCAN_WWR }, 844185380Ssam#define WT1_5760_5800 AFTER(WT1_5540_5660) 845185377Ssam}; 846185377Ssam 847185377Ssam/* 848185377Ssam * 2GHz 11b channel tags 849185377Ssam */ 850185380Ssamstatic REG_DMN_FREQ_BAND regDmn2GhzFreq[] = { 851187831Ssam { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 852185380Ssam#define F1_2312_2372 0 853187831Ssam { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 854185380Ssam#define F2_2312_2372 AFTER(F1_2312_2372) 855185377Ssam 856187831Ssam { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 857185380Ssam#define F1_2412_2472 AFTER(F2_2312_2372) 858187831Ssam { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA }, 859185380Ssam#define F2_2412_2472 AFTER(F1_2412_2472) 860187831Ssam { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN }, 861185380Ssam#define F3_2412_2472 AFTER(F2_2412_2472) 862185377Ssam 863187831Ssam { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN }, 864185380Ssam#define F1_2412_2462 AFTER(F3_2412_2472) 865187831Ssam { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA }, 866185380Ssam#define F2_2412_2462 AFTER(F1_2412_2462) 867185377Ssam 868187831Ssam { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 869185380Ssam#define F1_2432_2442 AFTER(F2_2412_2462) 870185377Ssam 871187831Ssam { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 872185380Ssam#define F1_2457_2472 AFTER(F1_2432_2442) 873185377Ssam 874187831Ssam { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA }, 875185380Ssam#define F1_2467_2472 AFTER(F1_2457_2472) 876185377Ssam 877187831Ssam { 2484, 2484, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 878185380Ssam#define F1_2484_2484 AFTER(F1_2467_2472) 879187831Ssam { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2 }, 880185380Ssam#define F2_2484_2484 AFTER(F1_2484_2484) 881185377Ssam 882187831Ssam { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 883185380Ssam#define F1_2512_2732 AFTER(F2_2484_2484) 884185377Ssam 885185377Ssam /* 886185380Ssam * WWR have powers opened up to 20dBm. 887185380Ssam * Limits should often come from CTL/Max powers 888185377Ssam */ 889187831Ssam { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 890185380Ssam#define W1_2312_2372 AFTER(F1_2512_2732) 891187831Ssam { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 892185380Ssam#define W1_2412_2412 AFTER(W1_2312_2372) 893187831Ssam { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 894185380Ssam#define W1_2417_2432 AFTER(W1_2412_2412) 895187831Ssam { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 896185380Ssam#define W1_2437_2442 AFTER(W1_2417_2432) 897187831Ssam { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 898185380Ssam#define W1_2447_2457 AFTER(W1_2437_2442) 899187831Ssam { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 900185380Ssam#define W1_2462_2462 AFTER(W1_2447_2457) 901187831Ssam { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 902185380Ssam#define W1_2467_2467 AFTER(W1_2462_2462) 903187831Ssam { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 904185380Ssam#define W2_2467_2467 AFTER(W1_2467_2467) 905187831Ssam { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 906185380Ssam#define W1_2472_2472 AFTER(W2_2467_2467) 907187831Ssam { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 908185380Ssam#define W2_2472_2472 AFTER(W1_2472_2472) 909187831Ssam { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 910185380Ssam#define W1_2484_2484 AFTER(W2_2472_2472) 911187831Ssam { 2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 912185380Ssam#define W2_2484_2484 AFTER(W1_2484_2484) 913185377Ssam}; 914185377Ssam 915185377Ssam/* 916185377Ssam * 2GHz 11g channel tags 917185377Ssam */ 918185377Ssamstatic REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = { 919187831Ssam { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 920185380Ssam#define G1_2312_2372 0 921187831Ssam { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 922185380Ssam#define G2_2312_2372 AFTER(G1_2312_2372) 923187831Ssam { 2312, 2372, 5, 6, 10, 5, NO_DFS, NO_PSCAN }, 924185380Ssam#define G3_2312_2372 AFTER(G2_2312_2372) 925187831Ssam { 2312, 2372, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 926185380Ssam#define G4_2312_2372 AFTER(G3_2312_2372) 927185377Ssam 928187831Ssam { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 929185380Ssam#define G1_2412_2472 AFTER(G4_2312_2372) 930187831Ssam { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G }, 931185380Ssam#define G2_2412_2472 AFTER(G1_2412_2472) 932187831Ssam { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN }, 933185380Ssam#define G3_2412_2472 AFTER(G2_2412_2472) 934187831Ssam { 2412, 2472, 5, 6, 10, 5, NO_DFS, NO_PSCAN }, 935185380Ssam#define G4_2412_2472 AFTER(G3_2412_2472) 936187831Ssam { 2412, 2472, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 937185380Ssam#define G5_2412_2472 AFTER(G4_2412_2472) 938185377Ssam 939187831Ssam { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN }, 940185380Ssam#define G1_2412_2462 AFTER(G5_2412_2472) 941187831Ssam { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G }, 942185380Ssam#define G2_2412_2462 AFTER(G1_2412_2462) 943187831Ssam { 2412, 2462, 27, 6, 10, 5, NO_DFS, NO_PSCAN }, 944185380Ssam#define G3_2412_2462 AFTER(G2_2412_2462) 945187831Ssam { 2412, 2462, 27, 6, 5, 5, NO_DFS, NO_PSCAN }, 946185380Ssam#define G4_2412_2462 AFTER(G3_2412_2462) 947185377Ssam 948187831Ssam { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 949185380Ssam#define G1_2432_2442 AFTER(G4_2412_2462) 950185377Ssam 951187831Ssam { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 952185380Ssam#define G1_2457_2472 AFTER(G1_2432_2442) 953185377Ssam 954187831Ssam { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 955185380Ssam#define G1_2512_2732 AFTER(G1_2457_2472) 956187831Ssam { 2512, 2732, 5, 6, 10, 5, NO_DFS, NO_PSCAN }, 957185380Ssam#define G2_2512_2732 AFTER(G1_2512_2732) 958187831Ssam { 2512, 2732, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 959185380Ssam#define G3_2512_2732 AFTER(G2_2512_2732) 960185377Ssam 961187831Ssam { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA }, 962185380Ssam#define G1_2467_2472 AFTER(G3_2512_2732) 963185377Ssam 964185377Ssam /* 965185377Ssam * WWR open up the power to 20dBm 966185377Ssam */ 967187831Ssam { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 968185380Ssam#define WG1_2312_2372 AFTER(G1_2467_2472) 969187831Ssam { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 970185380Ssam#define WG1_2412_2412 AFTER(WG1_2312_2372) 971187831Ssam { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 972185380Ssam#define WG1_2417_2432 AFTER(WG1_2412_2412) 973187831Ssam { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 974185380Ssam#define WG1_2437_2442 AFTER(WG1_2417_2432) 975187831Ssam { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 976185380Ssam#define WG1_2447_2457 AFTER(WG1_2437_2442) 977187831Ssam { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 978185380Ssam#define WG1_2462_2462 AFTER(WG1_2447_2457) 979187831Ssam { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 980185380Ssam#define WG1_2467_2467 AFTER(WG1_2462_2462) 981187831Ssam { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 982185380Ssam#define WG2_2467_2467 AFTER(WG1_2467_2467) 983187831Ssam { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 984185380Ssam#define WG1_2472_2472 AFTER(WG2_2467_2467) 985187831Ssam { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 986185380Ssam#define WG2_2472_2472 AFTER(WG1_2472_2472) 987185377Ssam}; 988185377Ssam 989185377Ssam/* 990185377Ssam * 2GHz Dynamic turbo tags 991185377Ssam */ 992185377Ssamstatic REG_DMN_FREQ_BAND regDmn2Ghz11gTurboFreq[] = { 993187831Ssam { 2312, 2372, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 994185380Ssam#define T1_2312_2372 0 995187831Ssam { 2437, 2437, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 996185380Ssam#define T1_2437_2437 AFTER(T1_2312_2372) 997187831Ssam { 2437, 2437, 20, 6, 40, 40, NO_DFS, NO_PSCAN }, 998185380Ssam#define T2_2437_2437 AFTER(T1_2437_2437) 999187831Ssam { 2437, 2437, 18, 6, 40, 40, NO_DFS, PSCAN_WWR }, 1000185380Ssam#define T3_2437_2437 AFTER(T2_2437_2437) 1001187831Ssam { 2512, 2732, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 1002185380Ssam#define T1_2512_2732 AFTER(T3_2437_2437) 1003185377Ssam}; 1004185377Ssam 1005185377Ssamtypedef struct regDomain { 1006185380Ssam uint16_t regDmnEnum; /* value from EnumRd table */ 1007185377Ssam uint8_t conformanceTestLimit; 1008185380Ssam uint32_t flags; /* Requirement flags (AdHoc disallow, 1009185380Ssam noise floor cal needed, etc) */ 1010185380Ssam uint64_t dfsMask; /* DFS bitmask for 5Ghz tables */ 1011185380Ssam uint64_t pscan; /* Bitmask for passive scan */ 1012185380Ssam chanbmask_t chan11a; /* 11a channels */ 1013185380Ssam chanbmask_t chan11a_turbo; /* 11a static turbo channels */ 1014185380Ssam chanbmask_t chan11a_dyn_turbo; /* 11a dynamic turbo channels */ 1015185380Ssam chanbmask_t chan11a_half; /* 11a 1/2 width channels */ 1016185380Ssam chanbmask_t chan11a_quarter; /* 11a 1/4 width channels */ 1017185380Ssam chanbmask_t chan11b; /* 11b channels */ 1018185380Ssam chanbmask_t chan11g; /* 11g channels */ 1019185380Ssam chanbmask_t chan11g_turbo; /* 11g dynamic turbo channels */ 1020185380Ssam chanbmask_t chan11g_half; /* 11g 1/2 width channels */ 1021185380Ssam chanbmask_t chan11g_quarter; /* 11g 1/4 width channels */ 1022185377Ssam} REG_DOMAIN; 1023185377Ssam 1024185377Ssamstatic REG_DOMAIN regDomains[] = { 1025185377Ssam 1026185380Ssam {.regDmnEnum = DEBUG_REG_DMN, 1027185380Ssam .conformanceTestLimit = FCC, 1028185380Ssam .dfsMask = DFS_FCC3, 1029187831Ssam .chan11a = BM3(F1_5120_5240, F1_5260_5700, F1_5745_5825), 1030187831Ssam .chan11a_half = BM3(F2_5120_5240, F2_5260_5700, F7_5745_5825), 1031187831Ssam .chan11a_quarter = BM3(F3_5120_5240, F3_5260_5700, F8_5745_5825), 1032185380Ssam .chan11a_turbo = BM8(T1_5130_5210, 1033185380Ssam T1_5250_5330, 1034185380Ssam T1_5370_5490, 1035185380Ssam T1_5530_5650, 1036185380Ssam T1_5150_5190, 1037185380Ssam T1_5230_5310, 1038185380Ssam T1_5350_5470, 1039185380Ssam T1_5510_5670), 1040185380Ssam .chan11a_dyn_turbo = BM4(T1_5200_5240, 1041185380Ssam T1_5280_5280, 1042185380Ssam T1_5540_5660, 1043185380Ssam T1_5765_5805), 1044185380Ssam .chan11b = BM4(F1_2312_2372, 1045185380Ssam F1_2412_2472, 1046185380Ssam F1_2484_2484, 1047185380Ssam F1_2512_2732), 1048185380Ssam .chan11g = BM3(G1_2312_2372, G1_2412_2472, G1_2512_2732), 1049185380Ssam .chan11g_turbo = BM3(T1_2312_2372, T1_2437_2437, T1_2512_2732), 1050185380Ssam .chan11g_half = BM3(G2_2312_2372, G4_2412_2472, G2_2512_2732), 1051185380Ssam .chan11g_quarter = BM3(G3_2312_2372, G5_2412_2472, G3_2512_2732), 1052185380Ssam }, 1053185377Ssam 1054185380Ssam {.regDmnEnum = APL1, 1055185380Ssam .conformanceTestLimit = FCC, 1056185380Ssam .chan11a = BM1(F4_5745_5825), 1057185380Ssam }, 1058185377Ssam 1059185380Ssam {.regDmnEnum = APL2, 1060185380Ssam .conformanceTestLimit = FCC, 1061185380Ssam .chan11a = BM1(F1_5745_5805), 1062185380Ssam }, 1063185377Ssam 1064185380Ssam {.regDmnEnum = APL3, 1065185380Ssam .conformanceTestLimit = FCC, 1066185380Ssam .chan11a = BM2(F1_5280_5320, F2_5745_5805), 1067185380Ssam }, 1068185377Ssam 1069185380Ssam {.regDmnEnum = APL4, 1070185380Ssam .conformanceTestLimit = FCC, 1071185380Ssam .chan11a = BM2(F4_5180_5240, F3_5745_5825), 1072185380Ssam }, 1073185377Ssam 1074185380Ssam {.regDmnEnum = APL5, 1075185380Ssam .conformanceTestLimit = FCC, 1076185380Ssam .chan11a = BM1(F2_5745_5825), 1077185380Ssam }, 1078185377Ssam 1079185380Ssam {.regDmnEnum = APL6, 1080185380Ssam .conformanceTestLimit = ETSI, 1081185380Ssam .dfsMask = DFS_ETSI, 1082185380Ssam .pscan = PSCAN_FCC_T | PSCAN_FCC, 1083185380Ssam .chan11a = BM3(F4_5180_5240, F2_5260_5320, F3_5745_5825), 1084185380Ssam .chan11a_turbo = BM3(T2_5210_5210, T1_5250_5290, T1_5760_5800), 1085185380Ssam }, 1086185377Ssam 1087185380Ssam {.regDmnEnum = APL8, 1088185380Ssam .conformanceTestLimit = ETSI, 1089185380Ssam .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 1090185380Ssam .chan11a = BM2(F6_5260_5320, F4_5745_5825), 1091185380Ssam }, 1092185377Ssam 1093185380Ssam {.regDmnEnum = APL9, 1094185380Ssam .conformanceTestLimit = ETSI, 1095185380Ssam .dfsMask = DFS_ETSI, 1096185380Ssam .pscan = PSCAN_ETSI, 1097185380Ssam .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 1098185380Ssam .chan11a = BM3(F1_5180_5320, F1_5500_5620, F3_5745_5805), 1099185380Ssam }, 1100185377Ssam 1101185380Ssam {.regDmnEnum = ETSI1, 1102185380Ssam .conformanceTestLimit = ETSI, 1103185380Ssam .dfsMask = DFS_ETSI, 1104185380Ssam .pscan = PSCAN_ETSI, 1105185380Ssam .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1106185380Ssam .chan11a = BM3(W2_5180_5240, F2_5260_5320, F2_5500_5700), 1107185380Ssam }, 1108185377Ssam 1109185380Ssam {.regDmnEnum = ETSI2, 1110185380Ssam .conformanceTestLimit = ETSI, 1111185380Ssam .dfsMask = DFS_ETSI, 1112185380Ssam .pscan = PSCAN_ETSI, 1113185380Ssam .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1114185380Ssam .chan11a = BM1(F3_5180_5240), 1115185380Ssam }, 1116185377Ssam 1117185380Ssam {.regDmnEnum = ETSI3, 1118185380Ssam .conformanceTestLimit = ETSI, 1119185380Ssam .dfsMask = DFS_ETSI, 1120185380Ssam .pscan = PSCAN_ETSI, 1121185380Ssam .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1122185380Ssam .chan11a = BM2(W2_5180_5240, F2_5260_5320), 1123185380Ssam }, 1124185377Ssam 1125185380Ssam {.regDmnEnum = ETSI4, 1126185380Ssam .conformanceTestLimit = ETSI, 1127185380Ssam .dfsMask = DFS_ETSI, 1128185380Ssam .pscan = PSCAN_ETSI, 1129185380Ssam .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1130185380Ssam .chan11a = BM2(F3_5180_5240, F1_5260_5320), 1131185380Ssam }, 1132185377Ssam 1133185380Ssam {.regDmnEnum = ETSI5, 1134185380Ssam .conformanceTestLimit = ETSI, 1135185380Ssam .dfsMask = DFS_ETSI, 1136185380Ssam .pscan = PSCAN_ETSI, 1137185380Ssam .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1138185380Ssam .chan11a = BM1(F1_5180_5240), 1139185380Ssam }, 1140185377Ssam 1141185380Ssam {.regDmnEnum = ETSI6, 1142185380Ssam .conformanceTestLimit = ETSI, 1143185380Ssam .dfsMask = DFS_ETSI, 1144185380Ssam .pscan = PSCAN_ETSI, 1145185380Ssam .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1146185380Ssam .chan11a = BM3(F5_5180_5240, F1_5260_5280, F3_5500_5700), 1147185380Ssam }, 1148185377Ssam 1149185380Ssam {.regDmnEnum = FCC1, 1150185380Ssam .conformanceTestLimit = FCC, 1151185380Ssam .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 1152185380Ssam .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 1153185380Ssam .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 1154185380Ssam }, 1155185377Ssam 1156185380Ssam {.regDmnEnum = FCC2, 1157185380Ssam .conformanceTestLimit = FCC, 1158185380Ssam .chan11a = BM3(F6_5180_5240, F5_5260_5320, F6_5745_5825), 1159185380Ssam .chan11a_dyn_turbo = BM3(T2_5200_5240, T1_5280_5280, T1_5765_5805), 1160185380Ssam }, 1161185377Ssam 1162185380Ssam {.regDmnEnum = FCC3, 1163185380Ssam .conformanceTestLimit = FCC, 1164185380Ssam .dfsMask = DFS_FCC3, 1165185380Ssam .pscan = PSCAN_FCC | PSCAN_FCC_T, 1166185380Ssam .chan11a = BM4(F2_5180_5240, 1167185380Ssam F3_5260_5320, 1168185380Ssam F1_5500_5700, 1169185380Ssam F5_5745_5825), 1170185380Ssam .chan11a_turbo = BM4(T1_5210_5210, 1171185380Ssam T1_5250_5250, 1172185380Ssam T1_5290_5290, 1173185380Ssam T2_5760_5800), 1174185380Ssam .chan11a_dyn_turbo = BM3(T1_5200_5240, T2_5280_5280, T1_5540_5660), 1175185380Ssam }, 1176185377Ssam 1177185380Ssam {.regDmnEnum = FCC4, 1178185380Ssam .conformanceTestLimit = FCC, 1179185380Ssam .dfsMask = DFS_FCC3, 1180185380Ssam .pscan = PSCAN_FCC | PSCAN_FCC_T, 1181185380Ssam .chan11a = BM1(F1_4950_4980), 1182185380Ssam .chan11a_half = BM1(F1_4945_4985), 1183185380Ssam .chan11a_quarter = BM1(F1_4942_4987), 1184185380Ssam }, 1185185377Ssam 1186185380Ssam /* FCC1 w/ 1/2 and 1/4 width channels */ 1187185380Ssam {.regDmnEnum = FCC5, 1188185380Ssam .conformanceTestLimit = FCC, 1189185380Ssam .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 1190185380Ssam .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 1191185380Ssam .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 1192185380Ssam .chan11a_half = BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825), 1193185380Ssam .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825), 1194185380Ssam }, 1195185377Ssam 1196185380Ssam {.regDmnEnum = MKK1, 1197185380Ssam .conformanceTestLimit = MKK, 1198185380Ssam .pscan = PSCAN_MKK1, 1199185380Ssam .flags = DISALLOW_ADHOC_11A_TURB, 1200185380Ssam .chan11a = BM1(F1_5170_5230), 1201185380Ssam }, 1202185377Ssam 1203185380Ssam {.regDmnEnum = MKK2, 1204185380Ssam .conformanceTestLimit = MKK, 1205185380Ssam .pscan = PSCAN_MKK2, 1206185380Ssam .flags = DISALLOW_ADHOC_11A_TURB, 1207185380Ssam .chan11a = BM3(F1_4920_4980, F1_5040_5080, F1_5170_5230), 1208187831Ssam .chan11a_half = BM4(F1_4915_4925, 1209185380Ssam F1_4935_4945, 1210185380Ssam F1_5035_5040, 1211185380Ssam F1_5055_5055), 1212185380Ssam }, 1213185380Ssam 1214185377Ssam /* UNI-1 even */ 1215185380Ssam {.regDmnEnum = MKK3, 1216185380Ssam .conformanceTestLimit = MKK, 1217185380Ssam .pscan = PSCAN_MKK3, 1218185380Ssam .flags = DISALLOW_ADHOC_11A_TURB, 1219185380Ssam .chan11a = BM1(F4_5180_5240), 1220185380Ssam }, 1221185377Ssam 1222185377Ssam /* UNI-1 even + UNI-2 */ 1223185380Ssam {.regDmnEnum = MKK4, 1224185380Ssam .conformanceTestLimit = MKK, 1225185380Ssam .dfsMask = DFS_MKK4, 1226185380Ssam .pscan = PSCAN_MKK3, 1227185380Ssam .flags = DISALLOW_ADHOC_11A_TURB, 1228185380Ssam .chan11a = BM2(F4_5180_5240, F2_5260_5320), 1229185380Ssam }, 1230185377Ssam 1231185377Ssam /* UNI-1 even + UNI-2 + mid-band */ 1232185380Ssam {.regDmnEnum = MKK5, 1233185380Ssam .conformanceTestLimit = MKK, 1234185380Ssam .dfsMask = DFS_MKK4, 1235185380Ssam .pscan = PSCAN_MKK3, 1236185380Ssam .flags = DISALLOW_ADHOC_11A_TURB, 1237185380Ssam .chan11a = BM3(F4_5180_5240, F2_5260_5320, F4_5500_5700), 1238185380Ssam }, 1239185377Ssam 1240185377Ssam /* UNI-1 odd + even */ 1241185380Ssam {.regDmnEnum = MKK6, 1242185380Ssam .conformanceTestLimit = MKK, 1243185380Ssam .pscan = PSCAN_MKK1, 1244185380Ssam .flags = DISALLOW_ADHOC_11A_TURB, 1245185380Ssam .chan11a = BM2(F2_5170_5230, F4_5180_5240), 1246185380Ssam }, 1247185377Ssam 1248185377Ssam /* UNI-1 odd + UNI-1 even + UNI-2 */ 1249185380Ssam {.regDmnEnum = MKK7, 1250185380Ssam .conformanceTestLimit = MKK, 1251185380Ssam .dfsMask = DFS_MKK4, 1252185380Ssam .pscan = PSCAN_MKK1 | PSCAN_MKK3, 1253185380Ssam .flags = DISALLOW_ADHOC_11A_TURB, 1254185380Ssam .chan11a = BM3(F1_5170_5230, F4_5180_5240, F2_5260_5320), 1255185380Ssam }, 1256185377Ssam 1257185377Ssam /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */ 1258185380Ssam {.regDmnEnum = MKK8, 1259185380Ssam .conformanceTestLimit = MKK, 1260185380Ssam .dfsMask = DFS_MKK4, 1261185380Ssam .pscan = PSCAN_MKK1 | PSCAN_MKK3, 1262185380Ssam .flags = DISALLOW_ADHOC_11A_TURB, 1263185380Ssam .chan11a = BM4(F1_5170_5230, 1264185380Ssam F4_5180_5240, 1265185380Ssam F2_5260_5320, 1266185380Ssam F4_5500_5700), 1267185380Ssam }, 1268185377Ssam 1269185377Ssam /* UNI-1 even + 4.9 GHZ */ 1270185380Ssam {.regDmnEnum = MKK9, 1271185380Ssam .conformanceTestLimit = MKK, 1272185380Ssam .pscan = PSCAN_MKK3, 1273185380Ssam .flags = DISALLOW_ADHOC_11A_TURB, 1274185380Ssam .chan11a = BM7(F1_4915_4925, 1275185380Ssam F1_4935_4945, 1276185380Ssam F1_4920_4980, 1277185380Ssam F1_5035_5040, 1278185380Ssam F1_5055_5055, 1279185380Ssam F1_5040_5080, 1280185380Ssam F4_5180_5240), 1281185380Ssam }, 1282185377Ssam 1283185377Ssam /* UNI-1 even + UNI-2 + 4.9 GHZ */ 1284185380Ssam {.regDmnEnum = MKK10, 1285185380Ssam .conformanceTestLimit = MKK, 1286185380Ssam .dfsMask = DFS_MKK4, 1287185380Ssam .pscan = PSCAN_MKK3, 1288185380Ssam .flags = DISALLOW_ADHOC_11A_TURB, 1289185380Ssam .chan11a = BM8(F1_4915_4925, 1290185380Ssam F1_4935_4945, 1291185380Ssam F1_4920_4980, 1292185380Ssam F1_5035_5040, 1293185380Ssam F1_5055_5055, 1294185380Ssam F1_5040_5080, 1295185380Ssam F4_5180_5240, 1296185380Ssam F2_5260_5320), 1297185380Ssam }, 1298185377Ssam 1299185377Ssam /* Defined here to use when 2G channels are authorised for country K2 */ 1300185380Ssam {.regDmnEnum = APLD, 1301185380Ssam .conformanceTestLimit = NO_CTL, 1302185380Ssam .chan11b = BM2(F2_2312_2372,F2_2412_2472), 1303185380Ssam .chan11g = BM2(G2_2312_2372,G2_2412_2472), 1304185380Ssam }, 1305185377Ssam 1306185380Ssam {.regDmnEnum = ETSIA, 1307185380Ssam .conformanceTestLimit = NO_CTL, 1308185380Ssam .pscan = PSCAN_ETSIA, 1309185380Ssam .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1310185380Ssam .chan11b = BM1(F1_2457_2472), 1311185380Ssam .chan11g = BM1(G1_2457_2472), 1312185380Ssam .chan11g_turbo = BM1(T2_2437_2437) 1313185380Ssam }, 1314185377Ssam 1315185380Ssam {.regDmnEnum = ETSIB, 1316185380Ssam .conformanceTestLimit = ETSI, 1317185380Ssam .pscan = PSCAN_ETSIB, 1318185380Ssam .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1319185380Ssam .chan11b = BM1(F1_2432_2442), 1320185380Ssam .chan11g = BM1(G1_2432_2442), 1321185380Ssam .chan11g_turbo = BM1(T2_2437_2437) 1322185380Ssam }, 1323185377Ssam 1324185380Ssam {.regDmnEnum = ETSIC, 1325185380Ssam .conformanceTestLimit = ETSI, 1326185380Ssam .pscan = PSCAN_ETSIC, 1327185380Ssam .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 1328185380Ssam .chan11b = BM1(F3_2412_2472), 1329185380Ssam .chan11g = BM1(G3_2412_2472), 1330185380Ssam .chan11g_turbo = BM1(T2_2437_2437) 1331185380Ssam }, 1332185377Ssam 1333185380Ssam {.regDmnEnum = FCCA, 1334185380Ssam .conformanceTestLimit = FCC, 1335185380Ssam .chan11b = BM1(F1_2412_2462), 1336185380Ssam .chan11g = BM1(G1_2412_2462), 1337185380Ssam .chan11g_turbo = BM1(T2_2437_2437), 1338185380Ssam }, 1339185377Ssam 1340185380Ssam /* FCCA w/ 1/2 and 1/4 width channels */ 1341185380Ssam {.regDmnEnum = FCCB, 1342185380Ssam .conformanceTestLimit = FCC, 1343185380Ssam .chan11b = BM1(F1_2412_2462), 1344185380Ssam .chan11g = BM1(G1_2412_2462), 1345185380Ssam .chan11g_turbo = BM1(T2_2437_2437), 1346185380Ssam .chan11g_half = BM1(G3_2412_2462), 1347185380Ssam .chan11g_quarter = BM1(G4_2412_2462), 1348185380Ssam }, 1349185377Ssam 1350185380Ssam {.regDmnEnum = MKKA, 1351185380Ssam .conformanceTestLimit = MKK, 1352185380Ssam .pscan = PSCAN_MKKA | PSCAN_MKKA_G 1353185380Ssam | PSCAN_MKKA1 | PSCAN_MKKA1_G 1354185380Ssam | PSCAN_MKKA2 | PSCAN_MKKA2_G, 1355185380Ssam .flags = DISALLOW_ADHOC_11A_TURB, 1356185380Ssam .chan11b = BM3(F2_2412_2462, F1_2467_2472, F2_2484_2484), 1357185380Ssam .chan11g = BM2(G2_2412_2462, G1_2467_2472), 1358185380Ssam .chan11g_turbo = BM1(T2_2437_2437) 1359185380Ssam }, 1360185377Ssam 1361185380Ssam {.regDmnEnum = MKKC, 1362185380Ssam .conformanceTestLimit = MKK, 1363185380Ssam .chan11b = BM1(F2_2412_2472), 1364185380Ssam .chan11g = BM1(G2_2412_2472), 1365185380Ssam .chan11g_turbo = BM1(T2_2437_2437) 1366185380Ssam }, 1367185377Ssam 1368185380Ssam {.regDmnEnum = WORLD, 1369185380Ssam .conformanceTestLimit = ETSI, 1370185380Ssam .chan11b = BM1(F2_2412_2472), 1371185380Ssam .chan11g = BM1(G2_2412_2472), 1372185380Ssam .chan11g_turbo = BM1(T2_2437_2437) 1373185380Ssam }, 1374185377Ssam 1375185380Ssam {.regDmnEnum = WOR0_WORLD, 1376185380Ssam .conformanceTestLimit = NO_CTL, 1377185380Ssam .dfsMask = DFS_FCC3 | DFS_ETSI, 1378185380Ssam .pscan = PSCAN_WWR, 1379185380Ssam .flags = ADHOC_PER_11D, 1380185380Ssam .chan11a = BM5(W1_5260_5320, 1381185380Ssam W1_5180_5240, 1382185380Ssam W1_5170_5230, 1383185380Ssam W1_5745_5825, 1384185380Ssam W1_5500_5700), 1385185380Ssam .chan11a_turbo = BM3(WT1_5210_5250, 1386185380Ssam WT1_5290_5290, 1387185380Ssam WT1_5760_5800), 1388185380Ssam .chan11b = BM8(W1_2412_2412, 1389185380Ssam W1_2437_2442, 1390185380Ssam W1_2462_2462, 1391185380Ssam W1_2472_2472, 1392185380Ssam W1_2417_2432, 1393185380Ssam W1_2447_2457, 1394185380Ssam W1_2467_2467, 1395185380Ssam W1_2484_2484), 1396185380Ssam .chan11g = BM7(WG1_2412_2412, 1397185380Ssam WG1_2437_2442, 1398185380Ssam WG1_2462_2462, 1399185380Ssam WG1_2472_2472, 1400185380Ssam WG1_2417_2432, 1401185380Ssam WG1_2447_2457, 1402185380Ssam WG1_2467_2467), 1403185380Ssam .chan11g_turbo = BM1(T3_2437_2437) 1404185380Ssam }, 1405185377Ssam 1406185380Ssam {.regDmnEnum = WOR01_WORLD, 1407185380Ssam .conformanceTestLimit = NO_CTL, 1408185380Ssam .dfsMask = DFS_FCC3 | DFS_ETSI, 1409185380Ssam .pscan = PSCAN_WWR, 1410185380Ssam .flags = ADHOC_PER_11D, 1411185380Ssam .chan11a = BM5(W1_5260_5320, 1412185380Ssam W1_5180_5240, 1413185380Ssam W1_5170_5230, 1414185380Ssam W1_5745_5825, 1415185380Ssam W1_5500_5700), 1416185380Ssam .chan11a_turbo = BM3(WT1_5210_5250, 1417185380Ssam WT1_5290_5290, 1418185380Ssam WT1_5760_5800), 1419185380Ssam .chan11b = BM5(W1_2412_2412, 1420185380Ssam W1_2437_2442, 1421185380Ssam W1_2462_2462, 1422185380Ssam W1_2417_2432, 1423185380Ssam W1_2447_2457), 1424185380Ssam .chan11g = BM5(WG1_2412_2412, 1425185380Ssam WG1_2437_2442, 1426185380Ssam WG1_2462_2462, 1427185380Ssam WG1_2417_2432, 1428185380Ssam WG1_2447_2457), 1429185380Ssam .chan11g_turbo = BM1(T3_2437_2437)}, 1430185377Ssam 1431185380Ssam {.regDmnEnum = WOR02_WORLD, 1432185380Ssam .conformanceTestLimit = NO_CTL, 1433185380Ssam .dfsMask = DFS_FCC3 | DFS_ETSI, 1434185380Ssam .pscan = PSCAN_WWR, 1435185380Ssam .flags = ADHOC_PER_11D, 1436185380Ssam .chan11a = BM5(W1_5260_5320, 1437185380Ssam W1_5180_5240, 1438185380Ssam W1_5170_5230, 1439185380Ssam W1_5745_5825, 1440185380Ssam W1_5500_5700), 1441185380Ssam .chan11a_turbo = BM3(WT1_5210_5250, 1442185380Ssam WT1_5290_5290, 1443185380Ssam WT1_5760_5800), 1444185380Ssam .chan11b = BM7(W1_2412_2412, 1445185380Ssam W1_2437_2442, 1446185380Ssam W1_2462_2462, 1447185380Ssam W1_2472_2472, 1448185380Ssam W1_2417_2432, 1449185380Ssam W1_2447_2457, 1450185380Ssam W1_2467_2467), 1451185380Ssam .chan11g = BM7(WG1_2412_2412, 1452185380Ssam WG1_2437_2442, 1453185380Ssam WG1_2462_2462, 1454185380Ssam WG1_2472_2472, 1455185380Ssam WG1_2417_2432, 1456185380Ssam WG1_2447_2457, 1457185380Ssam WG1_2467_2467), 1458185380Ssam .chan11g_turbo = BM1(T3_2437_2437)}, 1459185377Ssam 1460185380Ssam {.regDmnEnum = EU1_WORLD, 1461185380Ssam .conformanceTestLimit = NO_CTL, 1462185380Ssam .dfsMask = DFS_FCC3 | DFS_ETSI, 1463185380Ssam .pscan = PSCAN_WWR, 1464185380Ssam .flags = ADHOC_PER_11D, 1465185380Ssam .chan11a = BM5(W1_5260_5320, 1466185380Ssam W1_5180_5240, 1467185380Ssam W1_5170_5230, 1468185380Ssam W1_5745_5825, 1469185380Ssam W1_5500_5700), 1470185380Ssam .chan11a_turbo = BM3(WT1_5210_5250, 1471185380Ssam WT1_5290_5290, 1472185380Ssam WT1_5760_5800), 1473185380Ssam .chan11b = BM7(W1_2412_2412, 1474185380Ssam W1_2437_2442, 1475185380Ssam W1_2462_2462, 1476185380Ssam W2_2472_2472, 1477185380Ssam W1_2417_2432, 1478185380Ssam W1_2447_2457, 1479185380Ssam W2_2467_2467), 1480185380Ssam .chan11g = BM7(WG1_2412_2412, 1481185380Ssam WG1_2437_2442, 1482185380Ssam WG1_2462_2462, 1483185380Ssam WG2_2472_2472, 1484185380Ssam WG1_2417_2432, 1485185380Ssam WG1_2447_2457, 1486185380Ssam WG2_2467_2467), 1487185380Ssam .chan11g_turbo = BM1(T3_2437_2437)}, 1488185377Ssam 1489185380Ssam {.regDmnEnum = WOR1_WORLD, 1490185380Ssam .conformanceTestLimit = NO_CTL, 1491185380Ssam .dfsMask = DFS_FCC3 | DFS_ETSI, 1492185380Ssam .pscan = PSCAN_WWR, 1493187831Ssam .flags = DISALLOW_ADHOC_11A, 1494185380Ssam .chan11a = BM5(W1_5260_5320, 1495185380Ssam W1_5180_5240, 1496185380Ssam W1_5170_5230, 1497185380Ssam W1_5745_5825, 1498185380Ssam W1_5500_5700), 1499185380Ssam .chan11b = BM8(W1_2412_2412, 1500185380Ssam W1_2437_2442, 1501185380Ssam W1_2462_2462, 1502185380Ssam W1_2472_2472, 1503185380Ssam W1_2417_2432, 1504185380Ssam W1_2447_2457, 1505185380Ssam W1_2467_2467, 1506185380Ssam W1_2484_2484), 1507185380Ssam .chan11g = BM7(WG1_2412_2412, 1508185380Ssam WG1_2437_2442, 1509185380Ssam WG1_2462_2462, 1510185380Ssam WG1_2472_2472, 1511185380Ssam WG1_2417_2432, 1512185380Ssam WG1_2447_2457, 1513185380Ssam WG1_2467_2467), 1514185380Ssam .chan11g_turbo = BM1(T3_2437_2437) 1515185380Ssam }, 1516185377Ssam 1517185380Ssam {.regDmnEnum = WOR2_WORLD, 1518185380Ssam .conformanceTestLimit = NO_CTL, 1519185380Ssam .dfsMask = DFS_FCC3 | DFS_ETSI, 1520185380Ssam .pscan = PSCAN_WWR, 1521187831Ssam .flags = DISALLOW_ADHOC_11A, 1522185380Ssam .chan11a = BM5(W1_5260_5320, 1523185380Ssam W1_5180_5240, 1524185380Ssam W1_5170_5230, 1525185380Ssam W1_5745_5825, 1526185380Ssam W1_5500_5700), 1527185380Ssam .chan11a_turbo = BM3(WT1_5210_5250, 1528185380Ssam WT1_5290_5290, 1529185380Ssam WT1_5760_5800), 1530185380Ssam .chan11b = BM8(W1_2412_2412, 1531185380Ssam W1_2437_2442, 1532185380Ssam W1_2462_2462, 1533185380Ssam W1_2472_2472, 1534185380Ssam W1_2417_2432, 1535185380Ssam W1_2447_2457, 1536185380Ssam W1_2467_2467, 1537185380Ssam W1_2484_2484), 1538185380Ssam .chan11g = BM7(WG1_2412_2412, 1539185380Ssam WG1_2437_2442, 1540185380Ssam WG1_2462_2462, 1541185380Ssam WG1_2472_2472, 1542185380Ssam WG1_2417_2432, 1543185380Ssam WG1_2447_2457, 1544185380Ssam WG1_2467_2467), 1545185380Ssam .chan11g_turbo = BM1(T3_2437_2437)}, 1546185377Ssam 1547185380Ssam {.regDmnEnum = WOR3_WORLD, 1548185380Ssam .conformanceTestLimit = NO_CTL, 1549185380Ssam .dfsMask = DFS_FCC3 | DFS_ETSI, 1550185380Ssam .pscan = PSCAN_WWR, 1551185380Ssam .flags = ADHOC_PER_11D, 1552185380Ssam .chan11a = BM4(W1_5260_5320, 1553185380Ssam W1_5180_5240, 1554185380Ssam W1_5170_5230, 1555185380Ssam W1_5745_5825), 1556185380Ssam .chan11a_turbo = BM3(WT1_5210_5250, 1557185380Ssam WT1_5290_5290, 1558185380Ssam WT1_5760_5800), 1559185380Ssam .chan11b = BM7(W1_2412_2412, 1560185380Ssam W1_2437_2442, 1561185380Ssam W1_2462_2462, 1562185380Ssam W1_2472_2472, 1563185380Ssam W1_2417_2432, 1564185380Ssam W1_2447_2457, 1565185380Ssam W1_2467_2467), 1566185380Ssam .chan11g = BM7(WG1_2412_2412, 1567185380Ssam WG1_2437_2442, 1568185380Ssam WG1_2462_2462, 1569185380Ssam WG1_2472_2472, 1570185380Ssam WG1_2417_2432, 1571185380Ssam WG1_2447_2457, 1572185380Ssam WG1_2467_2467), 1573185380Ssam .chan11g_turbo = BM1(T3_2437_2437)}, 1574185377Ssam 1575185380Ssam {.regDmnEnum = WOR4_WORLD, 1576185380Ssam .conformanceTestLimit = NO_CTL, 1577185380Ssam .dfsMask = DFS_FCC3 | DFS_ETSI, 1578185380Ssam .pscan = PSCAN_WWR, 1579187831Ssam .flags = DISALLOW_ADHOC_11A, 1580185380Ssam .chan11a = BM4(W2_5260_5320, 1581185380Ssam W2_5180_5240, 1582185380Ssam F2_5745_5805, 1583185380Ssam W2_5825_5825), 1584185380Ssam .chan11a_turbo = BM3(WT1_5210_5250, 1585185380Ssam WT1_5290_5290, 1586185380Ssam WT1_5760_5800), 1587185380Ssam .chan11b = BM5(W1_2412_2412, 1588185380Ssam W1_2437_2442, 1589185380Ssam W1_2462_2462, 1590185380Ssam W1_2417_2432, 1591185380Ssam W1_2447_2457), 1592185380Ssam .chan11g = BM5(WG1_2412_2412, 1593185380Ssam WG1_2437_2442, 1594185380Ssam WG1_2462_2462, 1595185380Ssam WG1_2417_2432, 1596185380Ssam WG1_2447_2457), 1597185380Ssam .chan11g_turbo = BM1(T3_2437_2437)}, 1598185377Ssam 1599185380Ssam {.regDmnEnum = WOR5_ETSIC, 1600185380Ssam .conformanceTestLimit = NO_CTL, 1601185380Ssam .dfsMask = DFS_FCC3 | DFS_ETSI, 1602185380Ssam .pscan = PSCAN_WWR, 1603187831Ssam .flags = DISALLOW_ADHOC_11A, 1604185380Ssam .chan11a = BM3(W1_5260_5320, W2_5180_5240, F6_5745_5825), 1605185380Ssam .chan11b = BM7(W1_2412_2412, 1606185380Ssam W1_2437_2442, 1607185380Ssam W1_2462_2462, 1608185380Ssam W2_2472_2472, 1609185380Ssam W1_2417_2432, 1610185380Ssam W1_2447_2457, 1611185380Ssam W2_2467_2467), 1612185380Ssam .chan11g = BM7(WG1_2412_2412, 1613185380Ssam WG1_2437_2442, 1614185380Ssam WG1_2462_2462, 1615185380Ssam WG2_2472_2472, 1616185380Ssam WG1_2417_2432, 1617185380Ssam WG1_2447_2457, 1618185380Ssam WG2_2467_2467), 1619185380Ssam .chan11g_turbo = BM1(T3_2437_2437)}, 1620185377Ssam 1621185380Ssam {.regDmnEnum = WOR9_WORLD, 1622185380Ssam .conformanceTestLimit = NO_CTL, 1623185380Ssam .dfsMask = DFS_FCC3 | DFS_ETSI, 1624185380Ssam .pscan = PSCAN_WWR, 1625187831Ssam .flags = DISALLOW_ADHOC_11A, 1626185380Ssam .chan11a = BM4(W1_5260_5320, 1627185380Ssam W1_5180_5240, 1628185380Ssam W1_5745_5825, 1629185380Ssam W1_5500_5700), 1630185380Ssam .chan11a_turbo = BM3(WT1_5210_5250, 1631185380Ssam WT1_5290_5290, 1632185380Ssam WT1_5760_5800), 1633185380Ssam .chan11b = BM5(W1_2412_2412, 1634185380Ssam W1_2437_2442, 1635185380Ssam W1_2462_2462, 1636185380Ssam W1_2417_2432, 1637185380Ssam W1_2447_2457), 1638185380Ssam .chan11g = BM5(WG1_2412_2412, 1639185380Ssam WG1_2437_2442, 1640185380Ssam WG1_2462_2462, 1641185380Ssam WG1_2417_2432, 1642185380Ssam WG1_2447_2457), 1643185380Ssam .chan11g_turbo = BM1(T3_2437_2437)}, 1644185377Ssam 1645185380Ssam {.regDmnEnum = WORA_WORLD, 1646185380Ssam .conformanceTestLimit = NO_CTL, 1647185380Ssam .dfsMask = DFS_FCC3 | DFS_ETSI, 1648185380Ssam .pscan = PSCAN_WWR, 1649187831Ssam .flags = DISALLOW_ADHOC_11A, 1650185380Ssam .chan11a = BM4(W1_5260_5320, 1651185380Ssam W1_5180_5240, 1652185380Ssam W1_5745_5825, 1653185380Ssam W1_5500_5700), 1654185380Ssam .chan11b = BM7(W1_2412_2412, 1655185380Ssam W1_2437_2442, 1656185380Ssam W1_2462_2462, 1657185380Ssam W1_2472_2472, 1658185380Ssam W1_2417_2432, 1659185380Ssam W1_2447_2457, 1660185380Ssam W1_2467_2467), 1661185380Ssam .chan11g = BM7(WG1_2412_2412, 1662185380Ssam WG1_2437_2442, 1663185380Ssam WG1_2462_2462, 1664185380Ssam WG1_2472_2472, 1665185380Ssam WG1_2417_2432, 1666185380Ssam WG1_2447_2457, 1667185380Ssam WG1_2467_2467), 1668185380Ssam .chan11g_turbo = BM1(T3_2437_2437)}, 1669185380Ssam 1670185380Ssam {.regDmnEnum = NULL1, 1671185380Ssam .conformanceTestLimit = NO_CTL, 1672185380Ssam } 1673185377Ssam}; 1674185377Ssam 1675185377Ssamstruct cmode { 1676185377Ssam u_int mode; 1677185377Ssam u_int flags; 1678185377Ssam}; 1679185377Ssam 1680185377Ssamstatic const struct cmode modes[] = { 1681187831Ssam { HAL_MODE_TURBO, IEEE80211_CHAN_ST }, 1682187831Ssam { HAL_MODE_11A, IEEE80211_CHAN_A }, 1683187831Ssam { HAL_MODE_11B, IEEE80211_CHAN_B }, 1684187831Ssam { HAL_MODE_11G, IEEE80211_CHAN_G }, 1685187831Ssam { HAL_MODE_11G_TURBO, IEEE80211_CHAN_108G }, 1686187831Ssam { HAL_MODE_11A_TURBO, IEEE80211_CHAN_108A }, 1687187831Ssam { HAL_MODE_11A_QUARTER_RATE, 1688187831Ssam IEEE80211_CHAN_A | IEEE80211_CHAN_QUARTER }, 1689187831Ssam { HAL_MODE_11A_HALF_RATE, 1690187831Ssam IEEE80211_CHAN_A | IEEE80211_CHAN_HALF }, 1691187831Ssam { HAL_MODE_11G_QUARTER_RATE, 1692187831Ssam IEEE80211_CHAN_G | IEEE80211_CHAN_QUARTER }, 1693187831Ssam { HAL_MODE_11G_HALF_RATE, 1694187831Ssam IEEE80211_CHAN_G | IEEE80211_CHAN_HALF }, 1695187831Ssam { HAL_MODE_11NG_HT20, IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_HT20 }, 1696187831Ssam { HAL_MODE_11NG_HT40PLUS, 1697187831Ssam IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_HT40U }, 1698187831Ssam { HAL_MODE_11NG_HT40MINUS, 1699187831Ssam IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_HT40D }, 1700187831Ssam { HAL_MODE_11NA_HT20, IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_HT20 }, 1701187831Ssam { HAL_MODE_11NA_HT40PLUS, 1702187831Ssam IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_HT40U }, 1703187831Ssam { HAL_MODE_11NA_HT40MINUS, 1704187831Ssam IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_HT40D }, 1705185377Ssam}; 1706185377Ssam 1707187831Ssamstatic OS_INLINE uint16_t 1708185377SsamgetEepromRD(struct ath_hal *ah) 1709185377Ssam{ 1710185377Ssam return AH_PRIVATE(ah)->ah_currentRD &~ WORLDWIDE_ROAMING_FLAG; 1711185377Ssam} 1712185377Ssam 1713185377Ssam/* 1714185377Ssam * Test to see if the bitmask array is all zeros 1715185377Ssam */ 1716185377Ssamstatic HAL_BOOL 1717185380SsamisChanBitMaskZero(const uint64_t *bitmask) 1718185377Ssam{ 1719185377Ssam#if BMLEN > 2 1720185377Ssam#error "add more cases" 1721185377Ssam#endif 1722185377Ssam#if BMLEN > 1 1723185377Ssam if (bitmask[1] != 0) 1724185377Ssam return AH_FALSE; 1725185377Ssam#endif 1726185377Ssam return (bitmask[0] == 0); 1727185377Ssam} 1728185377Ssam 1729185377Ssam/* 1730185377Ssam * Return whether or not the regulatory domain/country in EEPROM 1731185377Ssam * is acceptable. 1732185377Ssam */ 1733185377Ssamstatic HAL_BOOL 1734185377SsamisEepromValid(struct ath_hal *ah) 1735185377Ssam{ 1736185377Ssam uint16_t rd = getEepromRD(ah); 1737185377Ssam int i; 1738185377Ssam 1739185377Ssam if (rd & COUNTRY_ERD_FLAG) { 1740185377Ssam uint16_t cc = rd &~ COUNTRY_ERD_FLAG; 1741185377Ssam for (i = 0; i < N(allCountries); i++) 1742185377Ssam if (allCountries[i].countryCode == cc) 1743185377Ssam return AH_TRUE; 1744185377Ssam } else { 1745185377Ssam for (i = 0; i < N(regDomainPairs); i++) 1746185377Ssam if (regDomainPairs[i].regDmnEnum == rd) 1747185377Ssam return AH_TRUE; 1748185377Ssam } 1749185377Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 1750185377Ssam "%s: invalid regulatory domain/country code 0x%x\n", __func__, rd); 1751185377Ssam return AH_FALSE; 1752185377Ssam} 1753185377Ssam 1754185377Ssam/* 1755187831Ssam * Find the pointer to the country element in the country table 1756187831Ssam * corresponding to the country code 1757185377Ssam */ 1758187831Ssamstatic COUNTRY_CODE_TO_ENUM_RD* 1759187831SsamfindCountry(HAL_CTRY_CODE countryCode) 1760185377Ssam{ 1761187831Ssam int i; 1762185377Ssam 1763187831Ssam for (i = 0; i < N(allCountries); i++) { 1764187831Ssam if (allCountries[i].countryCode == countryCode) 1765187831Ssam return &allCountries[i]; 1766185377Ssam } 1767187831Ssam return AH_NULL; 1768185377Ssam} 1769185377Ssam 1770187831Ssamstatic REG_DOMAIN * 1771187831SsamfindRegDmn(int regDmn) 1772185377Ssam{ 1773187831Ssam int i; 1774185377Ssam 1775187831Ssam for (i = 0; i < N(regDomains); i++) { 1776187831Ssam if (regDomains[i].regDmnEnum == regDmn) 1777187831Ssam return ®Domains[i]; 1778185380Ssam } 1779187831Ssam return AH_NULL; 1780185377Ssam} 1781185377Ssam 1782187831Ssamstatic REG_DMN_PAIR_MAPPING * 1783187831SsamfindRegDmnPair(int regDmnPair) 1784185377Ssam{ 1785185377Ssam int i; 1786185377Ssam 1787187831Ssam if (regDmnPair != NO_ENUMRD) { 1788187831Ssam for (i = 0; i < N(regDomainPairs); i++) { 1789187831Ssam if (regDomainPairs[i].regDmnEnum == regDmnPair) 1790187831Ssam return ®DomainPairs[i]; 1791187831Ssam } 1792185377Ssam } 1793187831Ssam return AH_NULL; 1794185377Ssam} 1795185377Ssam 1796185377Ssam/* 1797185377Ssam * Calculate a default country based on the EEPROM setting. 1798185377Ssam */ 1799185377Ssamstatic HAL_CTRY_CODE 1800185377SsamgetDefaultCountry(struct ath_hal *ah) 1801185377Ssam{ 1802187831Ssam REG_DMN_PAIR_MAPPING *regpair; 1803185377Ssam uint16_t rd; 1804185377Ssam 1805185377Ssam rd = getEepromRD(ah); 1806185377Ssam if (rd & COUNTRY_ERD_FLAG) { 1807187831Ssam COUNTRY_CODE_TO_ENUM_RD *country; 1808185377Ssam uint16_t cc = rd & ~COUNTRY_ERD_FLAG; 1809185377Ssam country = findCountry(cc); 1810185377Ssam if (country != AH_NULL) 1811185377Ssam return cc; 1812185377Ssam } 1813185377Ssam /* 1814185377Ssam * Check reg domains that have only one country 1815185377Ssam */ 1816187831Ssam regpair = findRegDmnPair(rd); 1817187831Ssam return (regpair != AH_NULL) ? regpair->singleCC : CTRY_DEFAULT; 1818185377Ssam} 1819185377Ssam 1820185377Ssamstatic HAL_BOOL 1821187831SsamIS_BIT_SET(int bit, const uint64_t bitmask[]) 1822185377Ssam{ 1823187831Ssam int byteOffset, bitnum; 1824187831Ssam uint64_t val; 1825185377Ssam 1826187831Ssam byteOffset = bit/64; 1827187831Ssam bitnum = bit - byteOffset*64; 1828187831Ssam val = ((uint64_t) 1) << bitnum; 1829187831Ssam return (bitmask[byteOffset] & val) != 0; 1830185377Ssam} 1831185377Ssam 1832187831Ssamstatic HAL_STATUS 1833187831Ssamgetregstate(struct ath_hal *ah, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1834187831Ssam COUNTRY_CODE_TO_ENUM_RD **pcountry, 1835187831Ssam REG_DOMAIN **prd2GHz, REG_DOMAIN **prd5GHz) 1836185377Ssam{ 1837187831Ssam COUNTRY_CODE_TO_ENUM_RD *country; 1838187831Ssam REG_DOMAIN *rd5GHz, *rd2GHz; 1839185377Ssam 1840187831Ssam if (cc == CTRY_DEFAULT && regDmn == SKU_NONE) { 1841187831Ssam /* 1842187831Ssam * Validate the EEPROM setting and setup defaults 1843187831Ssam */ 1844187831Ssam if (!isEepromValid(ah)) { 1845187831Ssam /* 1846187831Ssam * Don't return any channels if the EEPROM has an 1847187831Ssam * invalid regulatory domain/country code setting. 1848187831Ssam */ 1849187831Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 1850187831Ssam "%s: invalid EEPROM contents\n",__func__); 1851187831Ssam return HAL_EEBADREG; 1852187831Ssam } 1853185377Ssam 1854187831Ssam cc = getDefaultCountry(ah); 1855187831Ssam country = findCountry(cc); 1856187831Ssam if (country == AH_NULL) { 1857187831Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 1858187831Ssam "NULL Country!, cc %d\n", cc); 1859187831Ssam return HAL_EEBADCC; 1860187831Ssam } 1861187831Ssam regDmn = country->regDmnEnum; 1862187831Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: EEPROM cc %u rd 0x%x\n", 1863187831Ssam __func__, cc, regDmn); 1864185377Ssam 1865187831Ssam if (country->countryCode == CTRY_DEFAULT) { 1866187831Ssam /* 1867187831Ssam * Check EEPROM; SKU may be for a country, single 1868187831Ssam * domain, or multiple domains (WWR). 1869187831Ssam */ 1870187831Ssam uint16_t rdnum = getEepromRD(ah); 1871187831Ssam if ((rdnum & COUNTRY_ERD_FLAG) == 0 && 1872187831Ssam (findRegDmn(rdnum) != AH_NULL || 1873187831Ssam findRegDmnPair(rdnum) != AH_NULL)) { 1874185377Ssam regDmn = rdnum; 1875187831Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 1876187831Ssam "%s: EEPROM rd 0x%x\n", __func__, rdnum); 1877185377Ssam } 1878185377Ssam } 1879187831Ssam } else { 1880187831Ssam country = findCountry(cc); 1881187831Ssam if (country == AH_NULL) { 1882185377Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 1883187831Ssam "unknown country, cc %d\n", cc); 1884187831Ssam return HAL_EINVAL; 1885185377Ssam } 1886187831Ssam if (regDmn == SKU_NONE) 1887187831Ssam regDmn = country->regDmnEnum; 1888187831Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u rd 0x%x\n", 1889187831Ssam __func__, cc, regDmn); 1890185377Ssam } 1891185377Ssam 1892185377Ssam /* 1893187831Ssam * Setup per-band state. 1894185377Ssam */ 1895187831Ssam if ((regDmn & MULTI_DOMAIN_MASK) == 0) { 1896187831Ssam REG_DMN_PAIR_MAPPING *regpair = findRegDmnPair(regDmn); 1897187831Ssam if (regpair == AH_NULL) { 1898187831Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 1899187831Ssam "%s: no reg domain pair %u for country %u\n", 1900187831Ssam __func__, regDmn, country->countryCode); 1901187831Ssam return HAL_EINVAL; 1902187831Ssam } 1903187831Ssam rd5GHz = findRegDmn(regpair->regDmn5GHz); 1904187831Ssam if (rd5GHz == AH_NULL) { 1905187831Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 1906187831Ssam "%s: no 5GHz reg domain %u for country %u\n", 1907187831Ssam __func__, regpair->regDmn5GHz, country->countryCode); 1908187831Ssam return HAL_EINVAL; 1909187831Ssam } 1910187831Ssam rd2GHz = findRegDmn(regpair->regDmn2GHz); 1911187831Ssam if (rd2GHz == AH_NULL) { 1912187831Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 1913187831Ssam "%s: no 2GHz reg domain %u for country %u\n", 1914187831Ssam __func__, regpair->regDmn2GHz, country->countryCode); 1915187831Ssam return HAL_EINVAL; 1916187831Ssam } 1917185377Ssam } else { 1918187831Ssam rd5GHz = rd2GHz = findRegDmn(regDmn); 1919187831Ssam if (rd2GHz == AH_NULL) { 1920187831Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 1921187831Ssam "%s: no unitary reg domain %u for country %u\n", 1922187831Ssam __func__, regDmn, country->countryCode); 1923187831Ssam return HAL_EINVAL; 1924185377Ssam } 1925185377Ssam } 1926187831Ssam if (pcountry != AH_NULL) 1927187831Ssam *pcountry = country; 1928187831Ssam *prd2GHz = rd2GHz; 1929187831Ssam *prd5GHz = rd5GHz; 1930187831Ssam return HAL_OK; 1931185377Ssam} 1932185377Ssam 1933185377Ssam/* 1934187831Ssam * Construct the channel list for the specified regulatory config. 1935185377Ssam */ 1936187831Ssamstatic HAL_STATUS 1937187831Ssamgetchannels(struct ath_hal *ah, 1938187831Ssam struct ieee80211_channel chans[], u_int maxchans, int *nchans, 1939187831Ssam u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1940187831Ssam HAL_BOOL enableExtendedChannels, 1941187831Ssam COUNTRY_CODE_TO_ENUM_RD **pcountry, 1942187831Ssam REG_DOMAIN **prd2GHz, REG_DOMAIN **prd5GHz) 1943185377Ssam{ 1944185377Ssam#define CHANNEL_HALF_BW 10 1945185377Ssam#define CHANNEL_QUARTER_BW 5 1946187831Ssam#define HAL_MODE_11A_ALL \ 1947187831Ssam (HAL_MODE_11A | HAL_MODE_11A_TURBO | HAL_MODE_TURBO | \ 1948187831Ssam HAL_MODE_11A_QUARTER_RATE | HAL_MODE_11A_HALF_RATE) 1949187831Ssam REG_DOMAIN *rd5GHz, *rd2GHz; 1950185377Ssam u_int modesAvail; 1951185377Ssam const struct cmode *cm; 1952187831Ssam struct ieee80211_channel *ic; 1953185377Ssam int next, b; 1954187831Ssam HAL_STATUS status; 1955185377Ssam 1956187831Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u regDmn 0x%x mode 0x%x%s\n", 1957187831Ssam __func__, cc, regDmn, modeSelect, 1958187831Ssam enableExtendedChannels ? " ecm" : ""); 1959185377Ssam 1960187831Ssam status = getregstate(ah, cc, regDmn, pcountry, &rd2GHz, &rd5GHz); 1961187831Ssam if (status != HAL_OK) 1962187831Ssam return status; 1963185377Ssam 1964187831Ssam /* get modes that HW is capable of */ 1965187831Ssam modesAvail = ath_hal_getWirelessModes(ah); 1966187831Ssam /* optimize work below if no 11a channels */ 1967187831Ssam if (isChanBitMaskZero(rd5GHz->chan11a) && 1968187831Ssam (modesAvail & HAL_MODE_11A_ALL)) { 1969185377Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 1970187831Ssam "%s: disallow all 11a\n", __func__); 1971187831Ssam modesAvail &= ~HAL_MODE_11A_ALL; 1972185377Ssam } 1973185377Ssam 1974185377Ssam next = 0; 1975187831Ssam ic = &chans[0]; 1976185377Ssam for (cm = modes; cm < &modes[N(modes)]; cm++) { 1977185377Ssam uint16_t c, c_hi, c_lo; 1978185377Ssam uint64_t *channelBM = AH_NULL; 1979185377Ssam REG_DMN_FREQ_BAND *fband = AH_NULL,*freqs; 1980185377Ssam int low_adj, hi_adj, channelSep, lastc; 1981187831Ssam uint32_t rdflags; 1982187831Ssam uint64_t dfsMask; 1983187831Ssam uint64_t pscan; 1984185377Ssam 1985185377Ssam if ((cm->mode & modeSelect) == 0) { 1986185377Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 1987185377Ssam "%s: skip mode 0x%x flags 0x%x\n", 1988185377Ssam __func__, cm->mode, cm->flags); 1989185377Ssam continue; 1990185377Ssam } 1991185377Ssam if ((cm->mode & modesAvail) == 0) { 1992185377Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 1993185377Ssam "%s: !avail mode 0x%x (0x%x) flags 0x%x\n", 1994185377Ssam __func__, modesAvail, cm->mode, cm->flags); 1995185377Ssam continue; 1996185377Ssam } 1997185377Ssam if (!ath_hal_getChannelEdges(ah, cm->flags, &c_lo, &c_hi)) { 1998185377Ssam /* channel not supported by hardware, skip it */ 1999185377Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2000185377Ssam "%s: channels 0x%x not supported by hardware\n", 2001185377Ssam __func__,cm->flags); 2002185377Ssam continue; 2003185377Ssam } 2004185377Ssam switch (cm->mode) { 2005185377Ssam case HAL_MODE_TURBO: 2006187831Ssam case HAL_MODE_11A_TURBO: 2007187831Ssam rdflags = rd5GHz->flags; 2008187831Ssam dfsMask = rd5GHz->dfsMask; 2009187831Ssam pscan = rd5GHz->pscan; 2010187831Ssam if (cm->mode == HAL_MODE_TURBO) 2011187831Ssam channelBM = rd5GHz->chan11a_turbo; 2012187831Ssam else 2013187831Ssam channelBM = rd5GHz->chan11a_dyn_turbo; 2014185377Ssam freqs = ®Dmn5GhzTurboFreq[0]; 2015185377Ssam break; 2016187831Ssam case HAL_MODE_11G_TURBO: 2017187831Ssam rdflags = rd2GHz->flags; 2018187831Ssam dfsMask = rd2GHz->dfsMask; 2019187831Ssam pscan = rd2GHz->pscan; 2020187831Ssam channelBM = rd2GHz->chan11g_turbo; 2021187831Ssam freqs = ®Dmn2Ghz11gTurboFreq[0]; 2022187831Ssam break; 2023185377Ssam case HAL_MODE_11A: 2024185380Ssam case HAL_MODE_11A_HALF_RATE: 2025185380Ssam case HAL_MODE_11A_QUARTER_RATE: 2026185377Ssam case HAL_MODE_11NA_HT20: 2027185377Ssam case HAL_MODE_11NA_HT40PLUS: 2028185377Ssam case HAL_MODE_11NA_HT40MINUS: 2029187831Ssam rdflags = rd5GHz->flags; 2030187831Ssam dfsMask = rd5GHz->dfsMask; 2031187831Ssam pscan = rd5GHz->pscan; 2032185380Ssam if (cm->mode == HAL_MODE_11A_HALF_RATE) 2033187831Ssam channelBM = rd5GHz->chan11a_half; 2034185380Ssam else if (cm->mode == HAL_MODE_11A_QUARTER_RATE) 2035187831Ssam channelBM = rd5GHz->chan11a_quarter; 2036185380Ssam else 2037187831Ssam channelBM = rd5GHz->chan11a; 2038185377Ssam freqs = ®Dmn5GhzFreq[0]; 2039185377Ssam break; 2040185377Ssam case HAL_MODE_11B: 2041185377Ssam case HAL_MODE_11G: 2042185380Ssam case HAL_MODE_11G_HALF_RATE: 2043185380Ssam case HAL_MODE_11G_QUARTER_RATE: 2044185377Ssam case HAL_MODE_11NG_HT20: 2045185377Ssam case HAL_MODE_11NG_HT40PLUS: 2046185377Ssam case HAL_MODE_11NG_HT40MINUS: 2047187831Ssam rdflags = rd2GHz->flags; 2048187831Ssam dfsMask = rd2GHz->dfsMask; 2049187831Ssam pscan = rd2GHz->pscan; 2050185380Ssam if (cm->mode == HAL_MODE_11G_HALF_RATE) 2051187831Ssam channelBM = rd2GHz->chan11g_half; 2052185380Ssam else if (cm->mode == HAL_MODE_11G_QUARTER_RATE) 2053187831Ssam channelBM = rd2GHz->chan11g_quarter; 2054187831Ssam else if (cm->mode == HAL_MODE_11B) 2055187831Ssam channelBM = rd2GHz->chan11b; 2056185380Ssam else 2057187831Ssam channelBM = rd2GHz->chan11g; 2058187831Ssam if (cm->mode == HAL_MODE_11B) 2059187831Ssam freqs = ®Dmn2GhzFreq[0]; 2060187831Ssam else 2061187831Ssam freqs = ®Dmn2Ghz11gFreq[0]; 2062185377Ssam break; 2063185377Ssam default: 2064185377Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2065185377Ssam "%s: Unkonwn HAL mode 0x%x\n", __func__, cm->mode); 2066185377Ssam continue; 2067185377Ssam } 2068185377Ssam if (isChanBitMaskZero(channelBM)) 2069185377Ssam continue; 2070185377Ssam /* 2071185377Ssam * Setup special handling for HT40 channels; e.g. 2072185377Ssam * 5G HT40 channels require 40Mhz channel separation. 2073185377Ssam */ 2074185377Ssam hi_adj = (cm->mode == HAL_MODE_11NA_HT40PLUS || 2075185377Ssam cm->mode == HAL_MODE_11NG_HT40PLUS) ? -20 : 0; 2076185377Ssam low_adj = (cm->mode == HAL_MODE_11NA_HT40MINUS || 2077185377Ssam cm->mode == HAL_MODE_11NG_HT40MINUS) ? 20 : 0; 2078185377Ssam channelSep = (cm->mode == HAL_MODE_11NA_HT40PLUS || 2079185377Ssam cm->mode == HAL_MODE_11NA_HT40MINUS) ? 40 : 0; 2080185377Ssam 2081185377Ssam for (b = 0; b < 64*BMLEN; b++) { 2082185377Ssam if (!IS_BIT_SET(b, channelBM)) 2083185377Ssam continue; 2084185377Ssam fband = &freqs[b]; 2085185377Ssam lastc = 0; 2086185377Ssam 2087185377Ssam for (c = fband->lowChannel + low_adj; 2088185377Ssam c <= fband->highChannel + hi_adj; 2089185377Ssam c += fband->channelSep) { 2090185377Ssam if (!(c_lo <= c && c <= c_hi)) { 2091185377Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2092185377Ssam "%s: c %u out of range [%u..%u]\n", 2093185377Ssam __func__, c, c_lo, c_hi); 2094185377Ssam continue; 2095185377Ssam } 2096185377Ssam if (next >= maxchans){ 2097185377Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2098185377Ssam "%s: too many channels for channel table\n", 2099185377Ssam __func__); 2100185377Ssam goto done; 2101185377Ssam } 2102185377Ssam if ((fband->usePassScan & IS_ECM_CHAN) && 2103185377Ssam !enableExtendedChannels) { 2104185377Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2105187831Ssam "skip ecm channel\n"); 2106185377Ssam continue; 2107185377Ssam } 2108187831Ssam if ((fband->useDfs & dfsMask) && 2109187831Ssam (cm->flags & IEEE80211_CHAN_HT40)) { 2110187831Ssam /* NB: DFS and HT40 don't mix */ 2111185377Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2112187831Ssam "skip HT40 chan, DFS required\n"); 2113185377Ssam continue; 2114185377Ssam } 2115185377Ssam /* 2116185377Ssam * Make sure that channel separation 2117185377Ssam * meets the requirement. 2118185377Ssam */ 2119185377Ssam if (lastc && channelSep && 2120185377Ssam (c-lastc) < channelSep) 2121185377Ssam continue; 2122185377Ssam lastc = c; 2123185377Ssam 2124187831Ssam OS_MEMZERO(ic, sizeof(*ic)); 2125187831Ssam ic->ic_freq = c; 2126187831Ssam ic->ic_flags = cm->flags; 2127187831Ssam ic->ic_maxregpower = fband->powerDfs; 2128187831Ssam ath_hal_getpowerlimits(ah, ic); 2129187831Ssam ic->ic_maxantgain = fband->antennaMax; 2130187831Ssam if (fband->usePassScan & pscan) 2131187831Ssam ic->ic_flags |= IEEE80211_CHAN_PASSIVE; 2132187831Ssam if (fband->useDfs & dfsMask) 2133187831Ssam ic->ic_flags |= IEEE80211_CHAN_DFS; 2134187831Ssam if (IEEE80211_IS_CHAN_5GHZ(ic) && 2135187831Ssam (rdflags & DISALLOW_ADHOC_11A)) 2136187831Ssam ic->ic_flags |= IEEE80211_CHAN_NOADHOC; 2137187831Ssam if (IEEE80211_IS_CHAN_TURBO(ic) && 2138187831Ssam (rdflags & DISALLOW_ADHOC_11A_TURB)) 2139187831Ssam ic->ic_flags |= IEEE80211_CHAN_NOADHOC; 2140187831Ssam if (rdflags & NO_HOSTAP) 2141187831Ssam ic->ic_flags |= IEEE80211_CHAN_NOHOSTAP; 2142187831Ssam if (rdflags & LIMIT_FRAME_4MS) 2143187831Ssam ic->ic_flags |= IEEE80211_CHAN_4MSXMIT; 2144187831Ssam if (rdflags & NEED_NFC) 2145187831Ssam ic->ic_flags |= CHANNEL_NFCREQUIRED; 2146187831Ssam 2147187831Ssam ic++, next++; 2148185377Ssam } 2149185377Ssam } 2150185377Ssam } 2151185377Ssamdone: 2152185377Ssam *nchans = next; 2153187831Ssam /* NB: pcountry set above by getregstate */ 2154187831Ssam if (prd2GHz != AH_NULL) 2155187831Ssam *prd2GHz = rd2GHz; 2156187831Ssam if (prd5GHz != AH_NULL) 2157187831Ssam *prd5GHz = rd5GHz; 2158187831Ssam return HAL_OK; 2159187831Ssam#undef HAL_MODE_11A_ALL 2160185377Ssam#undef CHANNEL_HALF_BW 2161185377Ssam#undef CHANNEL_QUARTER_BW 2162185377Ssam} 2163185377Ssam 2164185377Ssam/* 2165187831Ssam * Retrieve a channel list without affecting runtime state. 2166185377Ssam */ 2167187831SsamHAL_STATUS 2168187831Ssamath_hal_getchannels(struct ath_hal *ah, 2169187831Ssam struct ieee80211_channel chans[], u_int maxchans, int *nchans, 2170187831Ssam u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 2171187831Ssam HAL_BOOL enableExtendedChannels) 2172185377Ssam{ 2173187831Ssam return getchannels(ah, chans, maxchans, nchans, modeSelect, 2174187831Ssam cc, regDmn, enableExtendedChannels, AH_NULL, AH_NULL, AH_NULL); 2175187831Ssam} 2176185377Ssam 2177187831Ssam/* 2178187831Ssam * Handle frequency mapping from 900Mhz range to 2.4GHz range 2179187831Ssam * for GSM radios. This is done when we need the h/w frequency 2180187831Ssam * and the channel is marked IEEE80211_CHAN_GSM. 2181187831Ssam */ 2182187831Ssamstatic int 2183187831Ssamath_hal_mapgsm(int sku, int freq) 2184187831Ssam{ 2185187831Ssam if (sku == SKU_XR9) 2186187831Ssam return 1520 + freq; 2187187831Ssam if (sku == SKU_GZ901) 2188187831Ssam return 1544 + freq; 2189187831Ssam if (sku == SKU_SR9) 2190187831Ssam return 3344 - freq; 2191187831Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 2192187831Ssam "%s: cannot map freq %u unknown gsm sku %u\n", 2193187831Ssam __func__, freq, sku); 2194187831Ssam return freq; 2195187831Ssam} 2196185377Ssam 2197187831Ssam/* 2198187831Ssam * Setup the internal/private channel state given a table of 2199187831Ssam * net80211 channels. We collapse entries for the same frequency 2200187831Ssam * and record the frequency for doing noise floor processing 2201187831Ssam * where we don't have net80211 channel context. 2202187831Ssam */ 2203187831Ssamstatic HAL_BOOL 2204187831SsamassignPrivateChannels(struct ath_hal *ah, 2205187831Ssam struct ieee80211_channel chans[], int nchans, int sku) 2206187831Ssam{ 2207187831Ssam HAL_CHANNEL_INTERNAL *ic; 2208187831Ssam int i, j, next, freq; 2209187831Ssam 2210187831Ssam next = 0; 2211187831Ssam for (i = 0; i < nchans; i++) { 2212187831Ssam struct ieee80211_channel *c = &chans[i]; 2213187831Ssam for (j = i-1; j >= 0; j--) 2214187831Ssam if (chans[j].ic_freq == c->ic_freq) { 2215187831Ssam c->ic_devdata = chans[j].ic_devdata; 2216187831Ssam break; 2217185377Ssam } 2218187831Ssam if (j < 0) { 2219187831Ssam /* new entry, assign a private channel entry */ 2220187831Ssam if (next >= N(AH_PRIVATE(ah)->ah_channels)) { 2221187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 2222187831Ssam "%s: too many channels, max %u\n", 2223187831Ssam __func__, N(AH_PRIVATE(ah)->ah_channels)); 2224187831Ssam return AH_FALSE; 2225187831Ssam } 2226187831Ssam /* 2227187831Ssam * Handle frequency mapping for 900MHz devices. 2228187831Ssam * The hardware uses 2.4GHz frequencies that are 2229187831Ssam * down-converted. The 802.11 layer uses the 2230187831Ssam * true frequencies. 2231187831Ssam */ 2232187831Ssam freq = IEEE80211_IS_CHAN_GSM(c) ? 2233187831Ssam ath_hal_mapgsm(sku, c->ic_freq) : c->ic_freq; 2234187831Ssam 2235187831Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, 2236187831Ssam "%s: private[%3u] %u/0x%x -> channel %u\n", 2237187831Ssam __func__, next, c->ic_freq, c->ic_flags, freq); 2238187831Ssam 2239187831Ssam ic = &AH_PRIVATE(ah)->ah_channels[next]; 2240187831Ssam /* 2241187831Ssam * NB: This clears privFlags which means ancillary 2242187831Ssam * code like ANI and IQ calibration will be 2243187831Ssam * restarted and re-setup any per-channel state. 2244187831Ssam */ 2245187831Ssam OS_MEMZERO(ic, sizeof(*ic)); 2246187831Ssam ic->channel = freq; 2247187831Ssam c->ic_devdata = next; 2248187831Ssam next++; 2249185377Ssam } 2250185377Ssam } 2251187831Ssam AH_PRIVATE(ah)->ah_nchan = next; 2252187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: %u public, %u private channels\n", 2253187831Ssam __func__, nchans, next); 2254187831Ssam return AH_TRUE; 2255185377Ssam} 2256185377Ssam 2257185377Ssam/* 2258187831Ssam * Setup the channel list based on the information in the EEPROM. 2259185377Ssam */ 2260187831SsamHAL_STATUS 2261187831Ssamath_hal_init_channels(struct ath_hal *ah, 2262187831Ssam struct ieee80211_channel chans[], u_int maxchans, int *nchans, 2263187831Ssam u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 2264187831Ssam HAL_BOOL enableExtendedChannels) 2265185377Ssam{ 2266187831Ssam COUNTRY_CODE_TO_ENUM_RD *country; 2267187831Ssam REG_DOMAIN *rd5GHz, *rd2GHz; 2268187831Ssam HAL_STATUS status; 2269185377Ssam 2270187831Ssam status = getchannels(ah, chans, maxchans, nchans, modeSelect, 2271187831Ssam cc, regDmn, enableExtendedChannels, &country, &rd2GHz, &rd5GHz); 2272187831Ssam if (status == HAL_OK && 2273187831Ssam assignPrivateChannels(ah, chans, *nchans, AH_PRIVATE(ah)->ah_currentRD)) { 2274187831Ssam AH_PRIVATE(ah)->ah_rd2GHz = rd2GHz; 2275187831Ssam AH_PRIVATE(ah)->ah_rd5GHz = rd5GHz; 2276187831Ssam 2277187831Ssam ah->ah_countryCode = country->countryCode; 2278187831Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u\n", 2279187831Ssam __func__, ah->ah_countryCode); 2280187831Ssam } else 2281187831Ssam status = HAL_EINVAL; 2282187831Ssam return status; 2283185377Ssam} 2284185377Ssam 2285187831Ssam/* 2286187831Ssam * Set the channel list. 2287187831Ssam */ 2288187831SsamHAL_STATUS 2289187831Ssamath_hal_set_channels(struct ath_hal *ah, 2290187831Ssam struct ieee80211_channel chans[], int nchans, 2291187831Ssam HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd) 2292187831Ssam{ 2293187831Ssam COUNTRY_CODE_TO_ENUM_RD *country; 2294187831Ssam REG_DOMAIN *rd5GHz, *rd2GHz; 2295187831Ssam HAL_STATUS status; 2296185377Ssam 2297187831Ssam switch (rd) { 2298187831Ssam case SKU_SR9: 2299187831Ssam case SKU_XR9: 2300187831Ssam case SKU_GZ901: 2301187831Ssam /* 2302187831Ssam * Map 900MHz sku's. The frequencies will be mapped 2303187831Ssam * according to the sku to compensate for the down-converter. 2304187831Ssam * We use the FCC for these sku's as the mapped channel 2305187831Ssam * list is known compatible (will need to change if/when 2306187831Ssam * vendors do different mapping in different locales). 2307187831Ssam */ 2308187831Ssam status = getregstate(ah, CTRY_DEFAULT, SKU_FCC, 2309187831Ssam &country, &rd2GHz, &rd5GHz); 2310187831Ssam break; 2311187831Ssam default: 2312187831Ssam status = getregstate(ah, cc, rd, 2313187831Ssam &country, &rd2GHz, &rd5GHz); 2314187831Ssam rd = AH_PRIVATE(ah)->ah_currentRD; 2315187831Ssam break; 2316187831Ssam } 2317187831Ssam if (status == HAL_OK && assignPrivateChannels(ah, chans, nchans, rd)) { 2318187831Ssam AH_PRIVATE(ah)->ah_rd2GHz = rd2GHz; 2319187831Ssam AH_PRIVATE(ah)->ah_rd5GHz = rd5GHz; 2320185377Ssam 2321187831Ssam ah->ah_countryCode = country->countryCode; 2322187831Ssam HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s: cc %u\n", 2323187831Ssam __func__, ah->ah_countryCode); 2324187831Ssam } else 2325187831Ssam status = HAL_EINVAL; 2326187831Ssam return status; 2327187831Ssam} 2328185377Ssam 2329187831Ssam#ifdef AH_DEBUG 2330185377Ssam/* 2331187831Ssam * Return the internal channel corresponding to a public channel. 2332187831Ssam * NB: normally this routine is inline'd (see ah_internal.h) 2333185377Ssam */ 2334187831SsamHAL_CHANNEL_INTERNAL * 2335187831Ssamath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c) 2336185377Ssam{ 2337187831Ssam HAL_CHANNEL_INTERNAL *cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata]; 2338185377Ssam 2339187831Ssam if (c->ic_devdata < AH_PRIVATE(ah)->ah_nchan && 2340187831Ssam (c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c))) 2341187831Ssam return cc; 2342187831Ssam if (c->ic_devdata >= AH_PRIVATE(ah)->ah_nchan) { 2343187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 2344187831Ssam "%s: bad mapping, devdata %u nchans %u\n", 2345187831Ssam __func__, c->ic_devdata, AH_PRIVATE(ah)->ah_nchan); 2346187831Ssam HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan); 2347185377Ssam } else { 2348187831Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 2349187831Ssam "%s: no match for %u/0x%x devdata %u channel %u\n", 2350187831Ssam __func__, c->ic_freq, c->ic_flags, c->ic_devdata, 2351187831Ssam cc->channel); 2352187831Ssam HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c)); 2353185377Ssam } 2354187831Ssam return AH_NULL; 2355185377Ssam} 2356187831Ssam#endif /* AH_DEBUG */ 2357185377Ssam 2358187831Ssam#define isWwrSKU(_ah) \ 2359187831Ssam ((getEepromRD((_ah)) & WORLD_SKU_MASK) == WORLD_SKU_PREFIX || \ 2360187831Ssam getEepromRD(_ah) == WORLD) 2361187831Ssam 2362185377Ssam/* 2363187831Ssam * Return the test group for the specific channel based on 2364187831Ssam * the current regulatory setup. 2365185377Ssam */ 2366187831Ssamu_int 2367187831Ssamath_hal_getctl(struct ath_hal *ah, const struct ieee80211_channel *c) 2368185377Ssam{ 2369187831Ssam u_int ctl; 2370185377Ssam 2371187831Ssam if (AH_PRIVATE(ah)->ah_rd2GHz == AH_PRIVATE(ah)->ah_rd5GHz || 2372187831Ssam (ah->ah_countryCode == CTRY_DEFAULT && isWwrSKU(ah))) 2373187831Ssam ctl = SD_NO_CTL; 2374187831Ssam else if (IEEE80211_IS_CHAN_2GHZ(c)) 2375187831Ssam ctl = AH_PRIVATE(ah)->ah_rd2GHz->conformanceTestLimit; 2376187831Ssam else 2377187831Ssam ctl = AH_PRIVATE(ah)->ah_rd5GHz->conformanceTestLimit; 2378187831Ssam if (IEEE80211_IS_CHAN_B(c)) 2379187831Ssam return ctl | CTL_11B; 2380187831Ssam if (IEEE80211_IS_CHAN_G(c)) 2381187831Ssam return ctl | CTL_11G; 2382187831Ssam if (IEEE80211_IS_CHAN_108G(c)) 2383187831Ssam return ctl | CTL_108G; 2384187831Ssam if (IEEE80211_IS_CHAN_TURBO(c)) 2385187831Ssam return ctl | CTL_TURBO; 2386187831Ssam if (IEEE80211_IS_CHAN_A(c)) 2387187831Ssam return ctl | CTL_11A; 2388187831Ssam return ctl; 2389185377Ssam} 2390185377Ssam 2391185377Ssam/* 2392187831Ssam * Return the max allowed antenna gain and apply any regulatory 2393187831Ssam * domain specific changes. 2394187831Ssam * 2395187831Ssam * NOTE: a negative reduction is possible in RD's that only 2396187831Ssam * measure radiated power (e.g., ETSI) which would increase 2397187831Ssam * that actual conducted output power (though never beyond 2398187831Ssam * the calibrated target power). 2399185377Ssam */ 2400187831Ssamu_int 2401187831Ssamath_hal_getantennareduction(struct ath_hal *ah, 2402187831Ssam const struct ieee80211_channel *chan, u_int twiceGain) 2403185377Ssam{ 2404187831Ssam int8_t antennaMax = twiceGain - chan->ic_maxantgain*2; 2405187831Ssam return (antennaMax < 0) ? 0 : antennaMax; 2406185377Ssam} 2407