ata-promise.c revision 227000
1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-promise.c 227000 2011-11-01 17:57:21Z marius $"); 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_promise_chipinit(device_t dev); 56static int ata_promise_ch_attach(device_t dev); 57static int ata_promise_status(device_t dev); 58static int ata_promise_dmastart(struct ata_request *request); 59static int ata_promise_dmastop(struct ata_request *request); 60static void ata_promise_dmareset(device_t dev); 61static int ata_promise_setmode(device_t dev, int target, int mode); 62static int ata_promise_tx2_ch_attach(device_t dev); 63static int ata_promise_tx2_status(device_t dev); 64static int ata_promise_mio_ch_attach(device_t dev); 65static int ata_promise_mio_ch_detach(device_t dev); 66static void ata_promise_mio_intr(void *data); 67static int ata_promise_mio_status(device_t dev); 68static int ata_promise_mio_command(struct ata_request *request); 69static void ata_promise_mio_reset(device_t dev); 70static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result); 71static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result); 72static u_int32_t ata_promise_mio_softreset(device_t dev, int port); 73static void ata_promise_mio_dmainit(device_t dev); 74static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 75static int ata_promise_mio_setmode(device_t dev, int target, int mode); 76static int ata_promise_mio_getrev(device_t dev, int target); 77static void ata_promise_sx4_intr(void *data); 78static int ata_promise_sx4_command(struct ata_request *request); 79static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 80static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 81static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 82 83/* misc defines */ 84#define PR_OLD 0 85#define PR_NEW 1 86#define PR_TX 2 87#define PR_MIO 3 88#define PR_TX4 0x01 89#define PR_SX4X 0x02 90#define PR_SX6K 0x04 91#define PR_PATA 0x08 92#define PR_CMBO 0x10 93#define PR_CMBO2 0x20 94#define PR_SATA 0x40 95#define PR_SATA2 0x80 96 97/* 98 * Promise chipset support functions 99 */ 100#define ATA_PDC_APKT_OFFSET 0x00000010 101#define ATA_PDC_HPKT_OFFSET 0x00000040 102#define ATA_PDC_ASG_OFFSET 0x00000080 103#define ATA_PDC_LSG_OFFSET 0x000000c0 104#define ATA_PDC_HSG_OFFSET 0x00000100 105#define ATA_PDC_CHN_OFFSET 0x00000400 106#define ATA_PDC_BUF_BASE 0x00400000 107#define ATA_PDC_BUF_OFFSET 0x00100000 108#define ATA_PDC_MAX_HPKT 8 109#define ATA_PDC_WRITE_REG 0x00 110#define ATA_PDC_WRITE_CTL 0x0e 111#define ATA_PDC_WRITE_END 0x08 112#define ATA_PDC_WAIT_NBUSY 0x10 113#define ATA_PDC_WAIT_READY 0x18 114#define ATA_PDC_1B 0x20 115#define ATA_PDC_2B 0x40 116 117struct host_packet { 118 u_int32_t addr; 119 TAILQ_ENTRY(host_packet) chain; 120}; 121 122struct ata_promise_sx4 { 123 struct mtx mtx; 124 TAILQ_HEAD(, host_packet) queue; 125 int busy; 126}; 127 128static int 129ata_promise_probe(device_t dev) 130{ 131 struct ata_pci_controller *ctlr = device_get_softc(dev); 132 struct ata_chip_id *idx; 133 static struct ata_chip_id ids[] = 134 {{ ATA_PDC20246, 0, PR_OLD, 0x00, ATA_UDMA2, "PDC20246" }, 135 { ATA_PDC20262, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20262" }, 136 { ATA_PDC20263, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20263" }, 137 { ATA_PDC20265, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20265" }, 138 { ATA_PDC20267, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20267" }, 139 { ATA_PDC20268, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20268" }, 140 { ATA_PDC20269, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20269" }, 141 { ATA_PDC20270, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20270" }, 142 { ATA_PDC20271, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20271" }, 143 { ATA_PDC20275, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20275" }, 144 { ATA_PDC20276, 0, PR_TX, PR_SX6K, ATA_UDMA6, "PDC20276" }, 145 { ATA_PDC20277, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20277" }, 146 { ATA_PDC20318, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20318" }, 147 { ATA_PDC20319, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20319" }, 148 { ATA_PDC20371, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20371" }, 149 { ATA_PDC20375, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20375" }, 150 { ATA_PDC20376, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20376" }, 151 { ATA_PDC20377, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20377" }, 152 { ATA_PDC20378, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20378" }, 153 { ATA_PDC20379, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20379" }, 154 { ATA_PDC20571, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20571" }, 155 { ATA_PDC20575, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20575" }, 156 { ATA_PDC20579, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20579" }, 157 { ATA_PDC20771, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC20771" }, 158 { ATA_PDC40775, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC40775" }, 159 { ATA_PDC20617, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20617" }, 160 { ATA_PDC20618, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20618" }, 161 { ATA_PDC20619, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20619" }, 162 { ATA_PDC20620, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20620" }, 163 { ATA_PDC20621, 0, PR_MIO, PR_SX4X, ATA_UDMA5, "PDC20621" }, 164 { ATA_PDC20622, 0, PR_MIO, PR_SX4X, ATA_SA150, "PDC20622" }, 165 { ATA_PDC40518, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40518" }, 166 { ATA_PDC40519, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40519" }, 167 { ATA_PDC40718, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40718" }, 168 { ATA_PDC40719, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40719" }, 169 { ATA_PDC40779, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40779" }, 170 { 0, 0, 0, 0, 0, 0}}; 171 char buffer[64]; 172 uintptr_t devid = 0; 173 174 if (pci_get_vendor(dev) != ATA_PROMISE_ID) 175 return ENXIO; 176 177 if (!(idx = ata_match_chip(dev, ids))) 178 return ENXIO; 179 180 /* if we are on a SuperTrak SX6000 dont attach */ 181 if ((idx->cfg2 & PR_SX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 182 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 183 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 184 devid == ATA_I960RM) 185 return ENXIO; 186 187 strcpy(buffer, "Promise "); 188 strcat(buffer, idx->text); 189 190 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 191 if ((idx->cfg2 & PR_TX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 192 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 193 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 194 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 195 static long start = 0, end = 0; 196 197 if (pci_get_slot(dev) == 1) { 198 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 199 strcat(buffer, " (channel 0+1)"); 200 } 201 else if (pci_get_slot(dev) == 2 && start && end) { 202 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 203 strcat(buffer, " (channel 2+3)"); 204 } 205 else { 206 start = end = 0; 207 } 208 } 209 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 210 device_set_desc_copy(dev, buffer); 211 ctlr->chip = idx; 212 ctlr->chipinit = ata_promise_chipinit; 213 return (BUS_PROBE_DEFAULT); 214} 215 216static int 217ata_promise_chipinit(device_t dev) 218{ 219 struct ata_pci_controller *ctlr = device_get_softc(dev); 220 int stat_reg; 221 222 if (ata_setup_interrupt(dev, ata_generic_intr)) 223 return ENXIO; 224 225 switch (ctlr->chip->cfg1) { 226 case PR_NEW: 227 /* setup clocks */ 228 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 229 /* FALLTHROUGH */ 230 231 case PR_OLD: 232 /* enable burst mode */ 233 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 234 ctlr->ch_attach = ata_promise_ch_attach; 235 ctlr->ch_detach = ata_pci_ch_detach; 236 ctlr->setmode = ata_promise_setmode; 237 return 0; 238 239 case PR_TX: 240 ctlr->ch_attach = ata_promise_tx2_ch_attach; 241 ctlr->ch_detach = ata_pci_ch_detach; 242 ctlr->setmode = ata_promise_setmode; 243 return 0; 244 245 case PR_MIO: 246 ctlr->r_type1 = SYS_RES_MEMORY; 247 ctlr->r_rid1 = PCIR_BAR(4); 248 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 249 &ctlr->r_rid1, RF_ACTIVE))) 250 goto failnfree; 251 252#ifdef __sparc64__ 253 if (ctlr->chip->cfg2 == PR_SX4X && 254 !bus_space_map(rman_get_bustag(ctlr->r_res1), 255 rman_get_bushandle(ctlr->r_res1), rman_get_size(ctlr->r_res1), 256 BUS_SPACE_MAP_LINEAR, NULL)) 257 goto failnfree; 258#endif 259 260 ctlr->r_type2 = SYS_RES_MEMORY; 261 ctlr->r_rid2 = PCIR_BAR(3); 262 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 263 &ctlr->r_rid2, RF_ACTIVE))) 264 goto failnfree; 265 266 if (ctlr->chip->cfg2 == PR_SX4X) { 267 struct ata_promise_sx4 *hpkt; 268 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 269 270 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 271 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 272 ata_promise_sx4_intr, ctlr, &ctlr->handle)) { 273 device_printf(dev, "unable to setup interrupt\n"); 274 goto failnfree; 275 } 276 277 /* print info about cache memory */ 278 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 279 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 280 ((dimm >> 24) & 0xff), 281 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 282 " ECC enabled" : "" ); 283 284 /* adjust cache memory parameters */ 285 ATA_OUTL(ctlr->r_res2, 0x000c000c, 286 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 287 288 /* setup host packet controls */ 289 hpkt = malloc(sizeof(struct ata_promise_sx4), 290 M_ATAPCI, M_NOWAIT | M_ZERO); 291 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF); 292 TAILQ_INIT(&hpkt->queue); 293 hpkt->busy = 0; 294 ctlr->chipset_data = hpkt; 295 ctlr->ch_attach = ata_promise_mio_ch_attach; 296 ctlr->ch_detach = ata_promise_mio_ch_detach; 297 ctlr->reset = ata_promise_mio_reset; 298 ctlr->setmode = ata_promise_setmode; 299 ctlr->channels = 4; 300 return 0; 301 } 302 303 /* mio type controllers need an interrupt intercept */ 304 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 305 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 306 ata_promise_mio_intr, ctlr, &ctlr->handle)) { 307 device_printf(dev, "unable to setup interrupt\n"); 308 goto failnfree; 309 } 310 311 switch (ctlr->chip->cfg2) { 312 case PR_PATA: 313 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 314 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 315 goto sata150; 316 case PR_CMBO: 317 ctlr->channels = 3; 318 goto sata150; 319 case PR_SATA: 320 ctlr->channels = 4; 321sata150: 322 stat_reg = 0x6c; 323 break; 324 325 case PR_CMBO2: 326 ctlr->channels = 3; 327 goto sataii; 328 case PR_SATA2: 329 default: 330 ctlr->channels = 4; 331sataii: 332 stat_reg = 0x60; 333 break; 334 } 335 336 /* prime fake interrupt register */ 337 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 338 339 /* clear SATA status and unmask interrupts */ 340 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 341 342 /* enable "long burst length" on gen2 chips */ 343 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) 344 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000); 345 346 ctlr->ch_attach = ata_promise_mio_ch_attach; 347 ctlr->ch_detach = ata_promise_mio_ch_detach; 348 ctlr->reset = ata_promise_mio_reset; 349 ctlr->setmode = ata_promise_mio_setmode; 350 ctlr->getrev = ata_promise_mio_getrev; 351 352 return 0; 353 } 354 355failnfree: 356 if (ctlr->r_res2) 357 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 358 if (ctlr->r_res1) 359 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 360 return ENXIO; 361} 362 363static int 364ata_promise_ch_attach(device_t dev) 365{ 366 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 367 struct ata_channel *ch = device_get_softc(dev); 368 369 if (ata_pci_ch_attach(dev)) 370 return ENXIO; 371 372 if (ctlr->chip->cfg1 == PR_NEW) { 373 ch->dma.start = ata_promise_dmastart; 374 ch->dma.stop = ata_promise_dmastop; 375 ch->dma.reset = ata_promise_dmareset; 376 } 377 378 ch->hw.status = ata_promise_status; 379 ch->flags |= ATA_NO_ATAPI_DMA; 380 ch->flags |= ATA_CHECKS_CABLE; 381 return 0; 382} 383 384static int 385ata_promise_status(device_t dev) 386{ 387 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 388 struct ata_channel *ch = device_get_softc(dev); 389 390 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 391 return ata_pci_status(dev); 392 } 393 return 0; 394} 395 396static int 397ata_promise_dmastart(struct ata_request *request) 398{ 399 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 400 struct ata_channel *ch = device_get_softc(request->parent); 401 402 if (request->flags & ATA_R_48BIT) { 403 ATA_OUTB(ctlr->r_res1, 0x11, 404 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 405 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 406 ((request->flags & ATA_R_READ) ? 0x05000000 : 0x06000000) | 407 (request->bytecount >> 1)); 408 } 409 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 410 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 411 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, request->dma->sg_bus); 412 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 413 ((request->flags & ATA_R_READ) ? ATA_BMCMD_WRITE_READ : 0) | 414 ATA_BMCMD_START_STOP); 415 ch->dma.flags |= ATA_DMA_ACTIVE; 416 return 0; 417} 418 419static int 420ata_promise_dmastop(struct ata_request *request) 421{ 422 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 423 struct ata_channel *ch = device_get_softc(request->parent); 424 int error; 425 426 if (request->flags & ATA_R_48BIT) { 427 ATA_OUTB(ctlr->r_res1, 0x11, 428 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 429 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 430 } 431 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 432 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 433 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 434 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 435 ch->dma.flags &= ~ATA_DMA_ACTIVE; 436 return error; 437} 438 439static void 440ata_promise_dmareset(device_t dev) 441{ 442 struct ata_channel *ch = device_get_softc(dev); 443 444 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 445 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 446 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 447 ch->flags &= ~ATA_DMA_ACTIVE; 448} 449 450static int 451ata_promise_setmode(device_t dev, int target, int mode) 452{ 453 device_t parent = device_get_parent(dev); 454 struct ata_pci_controller *ctlr = device_get_softc(parent); 455 struct ata_channel *ch = device_get_softc(dev); 456 int devno = (ch->unit << 1) + target; 457 u_int32_t timings[][2] = { 458 /* PR_OLD PR_NEW mode */ 459 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 460 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 461 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 462 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 463 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 464 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 465 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 466 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 467 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 468 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 469 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 470 { 0, 0x00424ef6 }, /* UDMA 3 */ 471 { 0, 0x004127f3 }, /* UDMA 4 */ 472 { 0, 0x004127f3 } /* UDMA 5 */ 473 }; 474 475 mode = min(mode, ctlr->chip->max_dma); 476 477 switch (ctlr->chip->cfg1) { 478 case PR_OLD: 479 case PR_NEW: 480 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 481 (pci_read_config(parent, 0x50, 2) & 482 (ch->unit ? 1 << 11 : 1 << 10))) { 483 ata_print_cable(dev, "controller"); 484 mode = ATA_UDMA2; 485 } 486 break; 487 488 case PR_TX: 489 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 490 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 491 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 492 ata_print_cable(dev, "controller"); 493 mode = ATA_UDMA2; 494 } 495 break; 496 497 case PR_MIO: 498 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 499 (ATA_INL(ctlr->r_res2, 500 (ctlr->chip->cfg2 & PR_SX4X ? 0x000c0260 : 0x0260) + 501 (ch->unit << 7)) & 0x01000000)) { 502 ata_print_cable(dev, "controller"); 503 mode = ATA_UDMA2; 504 } 505 break; 506 } 507 508 if (ctlr->chip->cfg1 < PR_TX) 509 pci_write_config(parent, 0x60 + (devno << 2), 510 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 511 return (mode); 512} 513 514static int 515ata_promise_tx2_ch_attach(device_t dev) 516{ 517 struct ata_channel *ch = device_get_softc(dev); 518 519 if (ata_pci_ch_attach(dev)) 520 return ENXIO; 521 522 ch->hw.status = ata_promise_tx2_status; 523 ch->flags |= ATA_CHECKS_CABLE; 524 return 0; 525} 526 527static int 528ata_promise_tx2_status(device_t dev) 529{ 530 struct ata_channel *ch = device_get_softc(dev); 531 532 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 533 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 534 return ata_pci_status(dev); 535 } 536 return 0; 537} 538 539static int 540ata_promise_mio_ch_attach(device_t dev) 541{ 542 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 543 struct ata_channel *ch = device_get_softc(dev); 544 int offset = (ctlr->chip->cfg2 & PR_SX4X) ? 0x000c0000 : 0; 545 int i; 546 547 ata_promise_mio_dmainit(dev); 548 549 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 550 ch->r_io[i].res = ctlr->r_res2; 551 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 552 } 553 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 554 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 555 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 556 ata_default_registers(dev); 557 if ((ctlr->chip->cfg2 & (PR_SATA | PR_SATA2)) || 558 ((ctlr->chip->cfg2 & (PR_CMBO | PR_CMBO2)) && ch->unit < 2)) { 559 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 560 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 561 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 562 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 563 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 564 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 565 ch->flags |= ATA_NO_SLAVE; 566 ch->flags |= ATA_SATA; 567 } 568 ch->flags |= ATA_USE_16BIT; 569 ch->flags |= ATA_CHECKS_CABLE; 570 571 ata_generic_hw(dev); 572 if (ctlr->chip->cfg2 & PR_SX4X) { 573 ch->hw.command = ata_promise_sx4_command; 574 } 575 else { 576 ch->hw.command = ata_promise_mio_command; 577 ch->hw.status = ata_promise_mio_status; 578 ch->hw.softreset = ata_promise_mio_softreset; 579 ch->hw.pm_read = ata_promise_mio_pm_read; 580 ch->hw.pm_write = ata_promise_mio_pm_write; 581 } 582 return 0; 583} 584 585static int 586ata_promise_mio_ch_detach(device_t dev) 587{ 588 589 ata_dmafini(dev); 590 return (0); 591} 592 593static void 594ata_promise_mio_intr(void *data) 595{ 596 struct ata_pci_controller *ctlr = data; 597 struct ata_channel *ch; 598 u_int32_t vector; 599 int unit; 600 601 /* 602 * since reading interrupt status register on early "mio" chips 603 * clears the status bits we cannot read it for each channel later on 604 * in the generic interrupt routine. 605 */ 606 vector = ATA_INL(ctlr->r_res2, 0x040); 607 ATA_OUTL(ctlr->r_res2, 0x040, vector); 608 ctlr->chipset_data = (void *)(uintptr_t)vector; 609 610 for (unit = 0; unit < ctlr->channels; unit++) { 611 if ((ch = ctlr->interrupt[unit].argument)) 612 ctlr->interrupt[unit].function(ch); 613 } 614 615 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 616} 617 618static int 619ata_promise_mio_status(device_t dev) 620{ 621 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 622 struct ata_channel *ch = device_get_softc(dev); 623 u_int32_t stat_reg, vector, status; 624 625 switch (ctlr->chip->cfg2) { 626 case PR_PATA: 627 case PR_CMBO: 628 case PR_SATA: 629 stat_reg = 0x6c; 630 break; 631 case PR_CMBO2: 632 case PR_SATA2: 633 default: 634 stat_reg = 0x60; 635 break; 636 } 637 638 /* read and acknowledge interrupt */ 639 vector = (uint32_t)(uintptr_t)ctlr->chipset_data; 640 641 /* read and clear interface status */ 642 status = ATA_INL(ctlr->r_res2, stat_reg); 643 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 644 645 /* check for and handle disconnect events */ 646 if (status & (0x00000001 << ch->unit)) { 647 if (bootverbose) 648 device_printf(dev, "DISCONNECT requested\n"); 649 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 650 } 651 652 /* check for and handle connect events */ 653 if (status & (0x00000010 << ch->unit)) { 654 if (bootverbose) 655 device_printf(dev, "CONNECT requested\n"); 656 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 657 } 658 659 /* do we have any device action ? */ 660 return (vector & (1 << (ch->unit + 1))); 661} 662 663static int 664ata_promise_mio_command(struct ata_request *request) 665{ 666 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 667 struct ata_channel *ch = device_get_softc(request->parent); 668 669 u_int32_t *wordp = (u_int32_t *)ch->dma.work; 670 671 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 672 673 if ((ctlr->chip->cfg2 == PR_SATA2) || 674 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 675 /* set portmultiplier port */ 676 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), request->unit & 0x0f); 677 } 678 679 /* XXX SOS add ATAPI commands support later */ 680 switch (request->u.ata.command) { 681 default: 682 return ata_generic_command(request); 683 684 case ATA_READ_DMA: 685 case ATA_READ_DMA48: 686 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 687 break; 688 689 case ATA_WRITE_DMA: 690 case ATA_WRITE_DMA48: 691 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 692 break; 693 } 694 wordp[1] = htole32(request->dma->sg_bus); 695 wordp[2] = 0; 696 ata_promise_apkt((u_int8_t*)wordp, request); 697 698 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma.work_bus); 699 return 0; 700} 701 702static void 703ata_promise_mio_reset(device_t dev) 704{ 705 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 706 struct ata_channel *ch = device_get_softc(dev); 707 struct ata_promise_sx4 *hpktp; 708 709 switch (ctlr->chip->cfg2) { 710 case PR_SX4X: 711 712 /* softreset channel ATA module */ 713 hpktp = ctlr->chipset_data; 714 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 715 ata_udelay(1000); 716 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 717 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 718 ~0x00003f9f) | (ch->unit + 1)); 719 720 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 721 mtx_lock(&hpktp->mtx); 722 ATA_OUTL(ctlr->r_res2, 0xc012c, 723 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 724 DELAY(10); 725 ATA_OUTL(ctlr->r_res2, 0xc012c, 726 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 727 hpktp->busy = 0; 728 mtx_unlock(&hpktp->mtx); 729 ata_generic_reset(dev); 730 break; 731 732 case PR_PATA: 733 case PR_CMBO: 734 case PR_SATA: 735 if ((ctlr->chip->cfg2 == PR_SATA) || 736 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 737 738 /* mask plug/unplug intr */ 739 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 740 } 741 742 /* softreset channels ATA module */ 743 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 744 ata_udelay(10000); 745 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 746 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 747 ~0x00003f9f) | (ch->unit + 1)); 748 749 if ((ctlr->chip->cfg2 == PR_SATA) || 750 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 751 752 if (ata_sata_phy_reset(dev, -1, 1)) 753 ata_generic_reset(dev); 754 else 755 ch->devices = 0; 756 757 /* reset and enable plug/unplug intr */ 758 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 759 } 760 else 761 ata_generic_reset(dev); 762 break; 763 764 case PR_CMBO2: 765 case PR_SATA2: 766 if ((ctlr->chip->cfg2 == PR_SATA2) || 767 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 768 /* set portmultiplier port */ 769 //ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 770 771 /* mask plug/unplug intr */ 772 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 773 } 774 775 /* softreset channels ATA module */ 776 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 777 ata_udelay(10000); 778 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 779 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 780 ~0x00003f9f) | (ch->unit + 1)); 781 782 if ((ctlr->chip->cfg2 == PR_SATA2) || 783 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 784 785 /* set PHY mode to "improved" */ 786 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 787 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 788 ~0x00000003) | 0x00000001); 789 790 if (ata_sata_phy_reset(dev, -1, 1)) { 791 u_int32_t signature = ch->hw.softreset(dev, ATA_PM); 792 793 if (1 | bootverbose) 794 device_printf(dev, "SIGNATURE: %08x\n", signature); 795 796 switch (signature >> 16) { 797 case 0x0000: 798 ch->devices = ATA_ATA_MASTER; 799 break; 800 case 0x9669: 801 ch->devices = ATA_PORTMULTIPLIER; 802 ata_pm_identify(dev); 803 break; 804 case 0xeb14: 805 ch->devices = ATA_ATAPI_MASTER; 806 break; 807 default: /* SOS XXX */ 808 if (bootverbose) 809 device_printf(dev, 810 "No signature, assuming disk device\n"); 811 ch->devices = ATA_ATA_MASTER; 812 } 813 if (bootverbose) 814 device_printf(dev, "promise_mio_reset devices=%08x\n", 815 ch->devices); 816 817 } else 818 ch->devices = 0; 819 820 /* reset and enable plug/unplug intr */ 821 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 822 823 ///* set portmultiplier port */ 824 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 825 } 826 else 827 ata_generic_reset(dev); 828 break; 829 830 } 831} 832 833static int 834ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result) 835{ 836 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 837 struct ata_channel *ch = device_get_softc(dev); 838 int timeout = 0; 839 840 if (port < 0) { 841 *result = ATA_IDX_INL(ch, reg); 842 return (0); 843 } 844 if (port < ATA_PM) { 845 switch (reg) { 846 case ATA_SSTATUS: 847 reg = 0; 848 break; 849 case ATA_SERROR: 850 reg = 1; 851 break; 852 case ATA_SCONTROL: 853 reg = 2; 854 break; 855 default: 856 return (EINVAL); 857 } 858 } 859 /* set portmultiplier port */ 860 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 861 862 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 863 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 864 865 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_READ_PM); 866 867 while (timeout < 1000000) { 868 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 869 if (!(status & ATA_S_BUSY)) 870 break; 871 timeout += 1000; 872 DELAY(1000); 873 } 874 if (timeout >= 1000000) 875 return ATA_E_ABORT; 876 877 *result = ATA_IDX_INB(ch, ATA_COUNT) | 878 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 879 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 880 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 881 return 0; 882} 883 884static int 885ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value) 886{ 887 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 888 struct ata_channel *ch = device_get_softc(dev); 889 int timeout = 0; 890 891 if (port < 0) { 892 ATA_IDX_OUTL(ch, reg, value); 893 return (0); 894 } 895 if (port < ATA_PM) { 896 switch (reg) { 897 case ATA_SSTATUS: 898 reg = 0; 899 break; 900 case ATA_SERROR: 901 reg = 1; 902 break; 903 case ATA_SCONTROL: 904 reg = 2; 905 break; 906 default: 907 return (EINVAL); 908 } 909 } 910 /* set portmultiplier port */ 911 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 912 913 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 914 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 915 ATA_IDX_OUTB(ch, ATA_COUNT, value & 0xff); 916 ATA_IDX_OUTB(ch, ATA_SECTOR, (value >> 8) & 0xff); 917 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff); 918 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (value >> 24) & 0xff); 919 920 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_WRITE_PM); 921 922 while (timeout < 1000000) { 923 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 924 if (!(status & ATA_S_BUSY)) 925 break; 926 timeout += 1000; 927 DELAY(1000); 928 } 929 if (timeout >= 1000000) 930 return ATA_E_ABORT; 931 932 return ATA_IDX_INB(ch, ATA_ERROR); 933} 934 935/* must be called with ATA channel locked and state_mtx held */ 936static u_int32_t 937ata_promise_mio_softreset(device_t dev, int port) 938{ 939 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 940 struct ata_channel *ch = device_get_softc(dev); 941 int timeout; 942 943 /* set portmultiplier port */ 944 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), port & 0x0f); 945 946 /* softreset device on this channel */ 947 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 948 DELAY(10); 949 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 950 ata_udelay(10000); 951 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 952 ata_udelay(150000); 953 ATA_IDX_INB(ch, ATA_ERROR); 954 955 /* wait for BUSY to go inactive */ 956 for (timeout = 0; timeout < 100; timeout++) { 957 u_int8_t err, stat; 958 959 err = ATA_IDX_INB(ch, ATA_ERROR); 960 stat = ATA_IDX_INB(ch, ATA_STATUS); 961 962 //if (stat == err && timeout > (stat & ATA_S_BUSY ? 100 : 10)) 963 //break; 964 965 if (!(stat & ATA_S_BUSY)) { 966 //if ((err & 0x7f) == ATA_E_ILI) { 967 return ATA_IDX_INB(ch, ATA_COUNT) | 968 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 969 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 970 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 971 //} 972 //else if (stat & 0x0f) { 973 //stat |= ATA_S_BUSY; 974 //} 975 } 976 977 if (!(stat & ATA_S_BUSY) || (stat == 0xff && timeout > 10)) 978 break; 979 ata_udelay(100000); 980 } 981 return -1; 982} 983 984static void 985ata_promise_mio_dmainit(device_t dev) 986{ 987 struct ata_channel *ch = device_get_softc(dev); 988 989 /* note start and stop are not used here */ 990 ch->dma.setprd = ata_promise_mio_setprd; 991 ch->dma.max_iosize = 65536; 992 ata_dmainit(dev); 993} 994 995#define MAXLASTSGSIZE (32 * sizeof(u_int32_t)) 996static void 997ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 998{ 999 struct ata_dmasetprd_args *args = xsc; 1000 struct ata_dma_prdentry *prd = args->dmatab; 1001 int i; 1002 1003 if ((args->error = error)) 1004 return; 1005 1006 for (i = 0; i < nsegs; i++) { 1007 prd[i].addr = htole32(segs[i].ds_addr); 1008 prd[i].count = htole32(segs[i].ds_len); 1009 } 1010 if (segs[i - 1].ds_len > MAXLASTSGSIZE) { 1011 //printf("split last SG element of %u\n", segs[i - 1].ds_len); 1012 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE); 1013 prd[i].count = htole32(MAXLASTSGSIZE); 1014 prd[i].addr = htole32(segs[i - 1].ds_addr + 1015 (segs[i - 1].ds_len - MAXLASTSGSIZE)); 1016 nsegs++; 1017 i++; 1018 } 1019 prd[i - 1].count |= htole32(ATA_DMA_EOT); 1020 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 1021 args->nsegs = nsegs; 1022} 1023 1024static int 1025ata_promise_mio_setmode(device_t dev, int target, int mode) 1026{ 1027 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1028 struct ata_channel *ch = device_get_softc(dev); 1029 1030 if ( (ctlr->chip->cfg2 == PR_SATA) || 1031 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1032 (ctlr->chip->cfg2 == PR_SATA2) || 1033 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1034 mode = ata_sata_setmode(dev, target, mode); 1035 else 1036 mode = ata_promise_setmode(dev, target, mode); 1037 return (mode); 1038} 1039 1040static int 1041ata_promise_mio_getrev(device_t dev, int target) 1042{ 1043 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1044 struct ata_channel *ch = device_get_softc(dev); 1045 1046 if ( (ctlr->chip->cfg2 == PR_SATA) || 1047 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1048 (ctlr->chip->cfg2 == PR_SATA2) || 1049 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1050 return (ata_sata_getrev(dev, target)); 1051 else 1052 return (0); 1053} 1054 1055static void 1056ata_promise_sx4_intr(void *data) 1057{ 1058 struct ata_pci_controller *ctlr = data; 1059 struct ata_channel *ch; 1060 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 1061 int unit; 1062 1063 for (unit = 0; unit < ctlr->channels; unit++) { 1064 if (vector & (1 << (unit + 1))) 1065 if ((ch = ctlr->interrupt[unit].argument)) 1066 ctlr->interrupt[unit].function(ch); 1067 if (vector & (1 << (unit + 5))) 1068 if ((ch = ctlr->interrupt[unit].argument)) 1069 ata_promise_queue_hpkt(ctlr, 1070 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1071 ATA_PDC_HPKT_OFFSET)); 1072 if (vector & (1 << (unit + 9))) { 1073 ata_promise_next_hpkt(ctlr); 1074 if ((ch = ctlr->interrupt[unit].argument)) 1075 ctlr->interrupt[unit].function(ch); 1076 } 1077 if (vector & (1 << (unit + 13))) { 1078 ata_promise_next_hpkt(ctlr); 1079 if ((ch = ctlr->interrupt[unit].argument)) 1080 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1081 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1082 ATA_PDC_APKT_OFFSET)); 1083 } 1084 } 1085} 1086 1087static int 1088ata_promise_sx4_command(struct ata_request *request) 1089{ 1090 device_t gparent = device_get_parent(request->parent); 1091 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1092 struct ata_channel *ch = device_get_softc(request->parent); 1093 struct ata_dma_prdentry *prd; 1094 caddr_t window = rman_get_virtual(ctlr->r_res1); 1095 u_int32_t *wordp; 1096 int i, idx, length = 0; 1097 1098 /* XXX SOS add ATAPI commands support later */ 1099 switch (request->u.ata.command) { 1100 1101 default: 1102 return -1; 1103 1104 case ATA_ATA_IDENTIFY: 1105 case ATA_READ: 1106 case ATA_READ48: 1107 case ATA_READ_MUL: 1108 case ATA_READ_MUL48: 1109 case ATA_WRITE: 1110 case ATA_WRITE48: 1111 case ATA_WRITE_MUL: 1112 case ATA_WRITE_MUL48: 1113 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1114 return ata_generic_command(request); 1115 1116 case ATA_SETFEATURES: 1117 case ATA_FLUSHCACHE: 1118 case ATA_FLUSHCACHE48: 1119 case ATA_SLEEP: 1120 case ATA_SET_MULTI: 1121 wordp = (u_int32_t *) 1122 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1123 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 1124 wordp[1] = 0; 1125 wordp[2] = 0; 1126 ata_promise_apkt((u_int8_t *)wordp, request); 1127 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1128 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1129 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1130 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 1131 return 0; 1132 1133 case ATA_READ_DMA: 1134 case ATA_READ_DMA48: 1135 case ATA_WRITE_DMA: 1136 case ATA_WRITE_DMA48: 1137 prd = request->dma->sg; 1138 wordp = (u_int32_t *) 1139 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 1140 i = idx = 0; 1141 do { 1142 wordp[idx++] = prd[i].addr; 1143 wordp[idx++] = prd[i].count; 1144 length += (prd[i].count & ~ATA_DMA_EOT); 1145 } while (!(prd[i++].count & ATA_DMA_EOT)); 1146 1147 wordp = (u_int32_t *) 1148 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 1149 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1150 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1151 1152 wordp = (u_int32_t *) 1153 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 1154 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1155 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1156 1157 wordp = (u_int32_t *) 1158 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 1159 if (request->flags & ATA_R_READ) 1160 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 1161 if (request->flags & ATA_R_WRITE) 1162 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 1163 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 1164 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 1165 wordp[3] = 0; 1166 1167 wordp = (u_int32_t *) 1168 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1169 if (request->flags & ATA_R_READ) 1170 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 1171 if (request->flags & ATA_R_WRITE) 1172 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 1173 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 1174 wordp[2] = 0; 1175 ata_promise_apkt((u_int8_t *)wordp, request); 1176 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1177 1178 if (request->flags & ATA_R_READ) { 1179 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 1180 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 1181 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1182 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 1183 } 1184 if (request->flags & ATA_R_WRITE) { 1185 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 1186 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 1187 ata_promise_queue_hpkt(ctlr, 1188 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 1189 } 1190 return 0; 1191 } 1192} 1193 1194static int 1195ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 1196{ 1197 int i = 12; 1198 1199 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 1200 bytep[i++] = ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit); 1201 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 1202 bytep[i++] = ATA_A_4BIT; 1203 1204 if (request->flags & ATA_R_48BIT) { 1205 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1206 bytep[i++] = request->u.ata.feature >> 8; 1207 bytep[i++] = request->u.ata.feature; 1208 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 1209 bytep[i++] = request->u.ata.count >> 8; 1210 bytep[i++] = request->u.ata.count; 1211 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1212 bytep[i++] = request->u.ata.lba >> 24; 1213 bytep[i++] = request->u.ata.lba; 1214 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1215 bytep[i++] = request->u.ata.lba >> 32; 1216 bytep[i++] = request->u.ata.lba >> 8; 1217 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1218 bytep[i++] = request->u.ata.lba >> 40; 1219 bytep[i++] = request->u.ata.lba >> 16; 1220 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1221 bytep[i++] = ATA_D_LBA | ATA_DEV(request->unit); 1222 } 1223 else { 1224 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1225 bytep[i++] = request->u.ata.feature; 1226 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 1227 bytep[i++] = request->u.ata.count; 1228 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1229 bytep[i++] = request->u.ata.lba; 1230 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1231 bytep[i++] = request->u.ata.lba >> 8; 1232 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1233 bytep[i++] = request->u.ata.lba >> 16; 1234 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1235 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ATA_DEV(request->unit) | 1236 ((request->u.ata.lba >> 24)&0xf); 1237 } 1238 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 1239 bytep[i++] = request->u.ata.command; 1240 return i; 1241} 1242 1243static void 1244ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 1245{ 1246 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1247 1248 mtx_lock(&hpktp->mtx); 1249 if (hpktp->busy) { 1250 struct host_packet *hp = 1251 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO); 1252 hp->addr = hpkt; 1253 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 1254 } 1255 else { 1256 hpktp->busy = 1; 1257 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 1258 } 1259 mtx_unlock(&hpktp->mtx); 1260} 1261 1262static void 1263ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 1264{ 1265 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1266 struct host_packet *hp; 1267 1268 mtx_lock(&hpktp->mtx); 1269 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 1270 TAILQ_REMOVE(&hpktp->queue, hp, chain); 1271 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 1272 free(hp, M_TEMP); 1273 } 1274 else 1275 hpktp->busy = 0; 1276 mtx_unlock(&hpktp->mtx); 1277} 1278 1279ATA_DECLARE_DRIVER(ata_promise); 1280