ata-promise.c revision 216013
1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-promise.c 216013 2010-11-28 18:53:29Z marius $"); 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_promise_chipinit(device_t dev); 56static int ata_promise_ch_attach(device_t dev); 57static int ata_promise_status(device_t dev); 58static int ata_promise_dmastart(struct ata_request *request); 59static int ata_promise_dmastop(struct ata_request *request); 60static void ata_promise_dmareset(device_t dev); 61static int ata_promise_setmode(device_t dev, int target, int mode); 62static int ata_promise_tx2_ch_attach(device_t dev); 63static int ata_promise_tx2_status(device_t dev); 64static int ata_promise_mio_ch_attach(device_t dev); 65static int ata_promise_mio_ch_detach(device_t dev); 66static void ata_promise_mio_intr(void *data); 67static int ata_promise_mio_status(device_t dev); 68static int ata_promise_mio_command(struct ata_request *request); 69static void ata_promise_mio_reset(device_t dev); 70static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result); 71static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result); 72static u_int32_t ata_promise_mio_softreset(device_t dev, int port); 73static void ata_promise_mio_dmainit(device_t dev); 74static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 75static int ata_promise_mio_setmode(device_t dev, int target, int mode); 76static int ata_promise_mio_getrev(device_t dev, int target); 77static void ata_promise_sx4_intr(void *data); 78static int ata_promise_sx4_command(struct ata_request *request); 79static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 80static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 81static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 82 83/* misc defines */ 84#define PR_OLD 0 85#define PR_NEW 1 86#define PR_TX 2 87#define PR_MIO 3 88#define PR_TX4 0x01 89#define PR_SX4X 0x02 90#define PR_SX6K 0x04 91#define PR_PATA 0x08 92#define PR_CMBO 0x10 93#define PR_CMBO2 0x20 94#define PR_SATA 0x40 95#define PR_SATA2 0x80 96 97 98/* 99 * Promise chipset support functions 100 */ 101#define ATA_PDC_APKT_OFFSET 0x00000010 102#define ATA_PDC_HPKT_OFFSET 0x00000040 103#define ATA_PDC_ASG_OFFSET 0x00000080 104#define ATA_PDC_LSG_OFFSET 0x000000c0 105#define ATA_PDC_HSG_OFFSET 0x00000100 106#define ATA_PDC_CHN_OFFSET 0x00000400 107#define ATA_PDC_BUF_BASE 0x00400000 108#define ATA_PDC_BUF_OFFSET 0x00100000 109#define ATA_PDC_MAX_HPKT 8 110#define ATA_PDC_WRITE_REG 0x00 111#define ATA_PDC_WRITE_CTL 0x0e 112#define ATA_PDC_WRITE_END 0x08 113#define ATA_PDC_WAIT_NBUSY 0x10 114#define ATA_PDC_WAIT_READY 0x18 115#define ATA_PDC_1B 0x20 116#define ATA_PDC_2B 0x40 117 118struct host_packet { 119 u_int32_t addr; 120 TAILQ_ENTRY(host_packet) chain; 121}; 122 123struct ata_promise_sx4 { 124 struct mtx mtx; 125 TAILQ_HEAD(, host_packet) queue; 126 int busy; 127}; 128 129static int 130ata_promise_probe(device_t dev) 131{ 132 struct ata_pci_controller *ctlr = device_get_softc(dev); 133 struct ata_chip_id *idx; 134 static struct ata_chip_id ids[] = 135 {{ ATA_PDC20246, 0, PR_OLD, 0x00, ATA_UDMA2, "PDC20246" }, 136 { ATA_PDC20262, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20262" }, 137 { ATA_PDC20263, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20263" }, 138 { ATA_PDC20265, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20265" }, 139 { ATA_PDC20267, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20267" }, 140 { ATA_PDC20268, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20268" }, 141 { ATA_PDC20269, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20269" }, 142 { ATA_PDC20270, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20270" }, 143 { ATA_PDC20271, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20271" }, 144 { ATA_PDC20275, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20275" }, 145 { ATA_PDC20276, 0, PR_TX, PR_SX6K, ATA_UDMA6, "PDC20276" }, 146 { ATA_PDC20277, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20277" }, 147 { ATA_PDC20318, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20318" }, 148 { ATA_PDC20319, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20319" }, 149 { ATA_PDC20371, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20371" }, 150 { ATA_PDC20375, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20375" }, 151 { ATA_PDC20376, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20376" }, 152 { ATA_PDC20377, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20377" }, 153 { ATA_PDC20378, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20378" }, 154 { ATA_PDC20379, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20379" }, 155 { ATA_PDC20571, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20571" }, 156 { ATA_PDC20575, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20575" }, 157 { ATA_PDC20579, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20579" }, 158 { ATA_PDC20771, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC20771" }, 159 { ATA_PDC40775, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC40775" }, 160 { ATA_PDC20617, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20617" }, 161 { ATA_PDC20618, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20618" }, 162 { ATA_PDC20619, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20619" }, 163 { ATA_PDC20620, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20620" }, 164 { ATA_PDC20621, 0, PR_MIO, PR_SX4X, ATA_UDMA5, "PDC20621" }, 165 { ATA_PDC20622, 0, PR_MIO, PR_SX4X, ATA_SA150, "PDC20622" }, 166 { ATA_PDC40518, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40518" }, 167 { ATA_PDC40519, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40519" }, 168 { ATA_PDC40718, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40718" }, 169 { ATA_PDC40719, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40719" }, 170 { ATA_PDC40779, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40779" }, 171 { 0, 0, 0, 0, 0, 0}}; 172 char buffer[64]; 173 uintptr_t devid = 0; 174 175 if (pci_get_vendor(dev) != ATA_PROMISE_ID) 176 return ENXIO; 177 178 if (!(idx = ata_match_chip(dev, ids))) 179 return ENXIO; 180 181 /* if we are on a SuperTrak SX6000 dont attach */ 182 if ((idx->cfg2 & PR_SX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 183 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 184 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 185 devid == ATA_I960RM) 186 return ENXIO; 187 188 strcpy(buffer, "Promise "); 189 strcat(buffer, idx->text); 190 191 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 192 if ((idx->cfg2 & PR_TX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 193 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 194 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 195 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 196 static long start = 0, end = 0; 197 198 if (pci_get_slot(dev) == 1) { 199 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 200 strcat(buffer, " (channel 0+1)"); 201 } 202 else if (pci_get_slot(dev) == 2 && start && end) { 203 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 204 strcat(buffer, " (channel 2+3)"); 205 } 206 else { 207 start = end = 0; 208 } 209 } 210 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma)); 211 device_set_desc_copy(dev, buffer); 212 ctlr->chip = idx; 213 ctlr->chipinit = ata_promise_chipinit; 214 return (BUS_PROBE_DEFAULT); 215} 216 217static int 218ata_promise_chipinit(device_t dev) 219{ 220 struct ata_pci_controller *ctlr = device_get_softc(dev); 221 int stat_reg; 222 223 if (ata_setup_interrupt(dev, ata_generic_intr)) 224 return ENXIO; 225 226 switch (ctlr->chip->cfg1) { 227 case PR_NEW: 228 /* setup clocks */ 229 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 230 /* FALLTHROUGH */ 231 232 case PR_OLD: 233 /* enable burst mode */ 234 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 235 ctlr->ch_attach = ata_promise_ch_attach; 236 ctlr->ch_detach = ata_pci_ch_detach; 237 ctlr->setmode = ata_promise_setmode; 238 return 0; 239 240 case PR_TX: 241 ctlr->ch_attach = ata_promise_tx2_ch_attach; 242 ctlr->ch_detach = ata_pci_ch_detach; 243 ctlr->setmode = ata_promise_setmode; 244 return 0; 245 246 case PR_MIO: 247 ctlr->r_type1 = SYS_RES_MEMORY; 248 ctlr->r_rid1 = PCIR_BAR(4); 249 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 250 &ctlr->r_rid1, RF_ACTIVE))) 251 goto failnfree; 252 253 ctlr->r_type2 = SYS_RES_MEMORY; 254 ctlr->r_rid2 = PCIR_BAR(3); 255 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 256 &ctlr->r_rid2, RF_ACTIVE))) 257 goto failnfree; 258 259 if (ctlr->chip->cfg2 == PR_SX4X) { 260 struct ata_promise_sx4 *hpkt; 261 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 262 263 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 264 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 265 ata_promise_sx4_intr, ctlr, &ctlr->handle)) { 266 device_printf(dev, "unable to setup interrupt\n"); 267 goto failnfree; 268 } 269 270 /* print info about cache memory */ 271 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 272 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 273 ((dimm >> 24) & 0xff), 274 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 275 " ECC enabled" : "" ); 276 277 /* adjust cache memory parameters */ 278 ATA_OUTL(ctlr->r_res2, 0x000c000c, 279 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 280 281 /* setup host packet controls */ 282 hpkt = malloc(sizeof(struct ata_promise_sx4), 283 M_TEMP, M_NOWAIT | M_ZERO); 284 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF); 285 TAILQ_INIT(&hpkt->queue); 286 hpkt->busy = 0; 287 ctlr->chipset_data = hpkt; 288 ctlr->ch_attach = ata_promise_mio_ch_attach; 289 ctlr->ch_detach = ata_promise_mio_ch_detach; 290 ctlr->reset = ata_promise_mio_reset; 291 ctlr->setmode = ata_promise_setmode; 292 ctlr->channels = 4; 293 return 0; 294 } 295 296 /* mio type controllers need an interrupt intercept */ 297 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 298 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 299 ata_promise_mio_intr, ctlr, &ctlr->handle)) { 300 device_printf(dev, "unable to setup interrupt\n"); 301 goto failnfree; 302 } 303 304 switch (ctlr->chip->cfg2) { 305 case PR_PATA: 306 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 307 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 308 goto sata150; 309 case PR_CMBO: 310 ctlr->channels = 3; 311 goto sata150; 312 case PR_SATA: 313 ctlr->channels = 4; 314sata150: 315 stat_reg = 0x6c; 316 break; 317 318 case PR_CMBO2: 319 ctlr->channels = 3; 320 goto sataii; 321 case PR_SATA2: 322 default: 323 ctlr->channels = 4; 324sataii: 325 stat_reg = 0x60; 326 break; 327 } 328 329 /* prime fake interrupt register */ 330 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 331 332 /* clear SATA status and unmask interrupts */ 333 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 334 335 /* enable "long burst length" on gen2 chips */ 336 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) 337 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000); 338 339 ctlr->ch_attach = ata_promise_mio_ch_attach; 340 ctlr->ch_detach = ata_promise_mio_ch_detach; 341 ctlr->reset = ata_promise_mio_reset; 342 ctlr->setmode = ata_promise_mio_setmode; 343 ctlr->getrev = ata_promise_mio_getrev; 344 345 return 0; 346 } 347 348failnfree: 349 if (ctlr->r_res2) 350 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 351 if (ctlr->r_res1) 352 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 353 return ENXIO; 354} 355 356static int 357ata_promise_ch_attach(device_t dev) 358{ 359 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 360 struct ata_channel *ch = device_get_softc(dev); 361 362 if (ata_pci_ch_attach(dev)) 363 return ENXIO; 364 365 if (ctlr->chip->cfg1 == PR_NEW) { 366 ch->dma.start = ata_promise_dmastart; 367 ch->dma.stop = ata_promise_dmastop; 368 ch->dma.reset = ata_promise_dmareset; 369 } 370 371 ch->hw.status = ata_promise_status; 372 ch->flags |= ATA_NO_ATAPI_DMA; 373 ch->flags |= ATA_CHECKS_CABLE; 374 return 0; 375} 376 377static int 378ata_promise_status(device_t dev) 379{ 380 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 381 struct ata_channel *ch = device_get_softc(dev); 382 383 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 384 return ata_pci_status(dev); 385 } 386 return 0; 387} 388 389static int 390ata_promise_dmastart(struct ata_request *request) 391{ 392 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 393 struct ata_channel *ch = device_get_softc(request->parent); 394 395 if (request->flags & ATA_R_48BIT) { 396 ATA_OUTB(ctlr->r_res1, 0x11, 397 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 398 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 399 ((request->flags & ATA_R_READ) ? 0x05000000 : 0x06000000) | 400 (request->bytecount >> 1)); 401 } 402 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 403 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 404 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, request->dma->sg_bus); 405 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 406 ((request->flags & ATA_R_READ) ? ATA_BMCMD_WRITE_READ : 0) | 407 ATA_BMCMD_START_STOP); 408 ch->dma.flags |= ATA_DMA_ACTIVE; 409 return 0; 410} 411 412static int 413ata_promise_dmastop(struct ata_request *request) 414{ 415 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 416 struct ata_channel *ch = device_get_softc(request->parent); 417 int error; 418 419 if (request->flags & ATA_R_48BIT) { 420 ATA_OUTB(ctlr->r_res1, 0x11, 421 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 422 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 423 } 424 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 425 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 426 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 427 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 428 ch->dma.flags &= ~ATA_DMA_ACTIVE; 429 return error; 430} 431 432static void 433ata_promise_dmareset(device_t dev) 434{ 435 struct ata_channel *ch = device_get_softc(dev); 436 437 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 438 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 439 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 440 ch->flags &= ~ATA_DMA_ACTIVE; 441} 442 443static int 444ata_promise_setmode(device_t dev, int target, int mode) 445{ 446 device_t parent = device_get_parent(dev); 447 struct ata_pci_controller *ctlr = device_get_softc(parent); 448 struct ata_channel *ch = device_get_softc(dev); 449 int devno = (ch->unit << 1) + target; 450 u_int32_t timings[][2] = { 451 /* PR_OLD PR_NEW mode */ 452 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 453 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 454 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 455 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 456 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 457 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 458 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 459 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 460 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 461 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 462 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 463 { 0, 0x00424ef6 }, /* UDMA 3 */ 464 { 0, 0x004127f3 }, /* UDMA 4 */ 465 { 0, 0x004127f3 } /* UDMA 5 */ 466 }; 467 468 mode = min(mode, ctlr->chip->max_dma); 469 470 switch (ctlr->chip->cfg1) { 471 case PR_OLD: 472 case PR_NEW: 473 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 474 (pci_read_config(parent, 0x50, 2) & 475 (ch->unit ? 1 << 11 : 1 << 10))) { 476 ata_print_cable(dev, "controller"); 477 mode = ATA_UDMA2; 478 } 479 break; 480 481 case PR_TX: 482 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 483 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 484 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 485 ata_print_cable(dev, "controller"); 486 mode = ATA_UDMA2; 487 } 488 break; 489 490 case PR_MIO: 491 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 492 (ATA_INL(ctlr->r_res2, 493 (ctlr->chip->cfg2 & PR_SX4X ? 0x000c0260 : 0x0260) + 494 (ch->unit << 7)) & 0x01000000)) { 495 ata_print_cable(dev, "controller"); 496 mode = ATA_UDMA2; 497 } 498 break; 499 } 500 501 if (ctlr->chip->cfg1 < PR_TX) 502 pci_write_config(parent, 0x60 + (devno << 2), 503 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 504 return (mode); 505} 506 507static int 508ata_promise_tx2_ch_attach(device_t dev) 509{ 510 struct ata_channel *ch = device_get_softc(dev); 511 512 if (ata_pci_ch_attach(dev)) 513 return ENXIO; 514 515 ch->hw.status = ata_promise_tx2_status; 516 ch->flags |= ATA_CHECKS_CABLE; 517 return 0; 518} 519 520static int 521ata_promise_tx2_status(device_t dev) 522{ 523 struct ata_channel *ch = device_get_softc(dev); 524 525 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 526 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 527 return ata_pci_status(dev); 528 } 529 return 0; 530} 531 532static int 533ata_promise_mio_ch_attach(device_t dev) 534{ 535 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 536 struct ata_channel *ch = device_get_softc(dev); 537 int offset = (ctlr->chip->cfg2 & PR_SX4X) ? 0x000c0000 : 0; 538 int i; 539 540 ata_promise_mio_dmainit(dev); 541 542 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 543 ch->r_io[i].res = ctlr->r_res2; 544 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 545 } 546 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 547 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 548 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 549 ata_default_registers(dev); 550 if ((ctlr->chip->cfg2 & (PR_SATA | PR_SATA2)) || 551 ((ctlr->chip->cfg2 & (PR_CMBO | PR_CMBO2)) && ch->unit < 2)) { 552 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 553 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 554 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 555 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 556 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 557 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 558 ch->flags |= ATA_NO_SLAVE; 559 ch->flags |= ATA_SATA; 560 } 561 ch->flags |= ATA_USE_16BIT; 562 ch->flags |= ATA_CHECKS_CABLE; 563 564 ata_generic_hw(dev); 565 if (ctlr->chip->cfg2 & PR_SX4X) { 566 ch->hw.command = ata_promise_sx4_command; 567 } 568 else { 569 ch->hw.command = ata_promise_mio_command; 570 ch->hw.status = ata_promise_mio_status; 571 ch->hw.softreset = ata_promise_mio_softreset; 572 ch->hw.pm_read = ata_promise_mio_pm_read; 573 ch->hw.pm_write = ata_promise_mio_pm_write; 574 } 575 return 0; 576} 577 578static int 579ata_promise_mio_ch_detach(device_t dev) 580{ 581 582 ata_dmafini(dev); 583 return (0); 584} 585 586static void 587ata_promise_mio_intr(void *data) 588{ 589 struct ata_pci_controller *ctlr = data; 590 struct ata_channel *ch; 591 u_int32_t vector; 592 int unit; 593 594 /* 595 * since reading interrupt status register on early "mio" chips 596 * clears the status bits we cannot read it for each channel later on 597 * in the generic interrupt routine. 598 */ 599 vector = ATA_INL(ctlr->r_res2, 0x040); 600 ATA_OUTL(ctlr->r_res2, 0x040, vector); 601 ctlr->chipset_data = (void *)(uintptr_t)vector; 602 603 for (unit = 0; unit < ctlr->channels; unit++) { 604 if ((ch = ctlr->interrupt[unit].argument)) 605 ctlr->interrupt[unit].function(ch); 606 } 607 608 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 609} 610 611static int 612ata_promise_mio_status(device_t dev) 613{ 614 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 615 struct ata_channel *ch = device_get_softc(dev); 616 u_int32_t stat_reg, vector, status; 617 618 switch (ctlr->chip->cfg2) { 619 case PR_PATA: 620 case PR_CMBO: 621 case PR_SATA: 622 stat_reg = 0x6c; 623 break; 624 case PR_CMBO2: 625 case PR_SATA2: 626 default: 627 stat_reg = 0x60; 628 break; 629 } 630 631 /* read and acknowledge interrupt */ 632 vector = (uint32_t)(uintptr_t)ctlr->chipset_data; 633 634 /* read and clear interface status */ 635 status = ATA_INL(ctlr->r_res2, stat_reg); 636 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 637 638 /* check for and handle disconnect events */ 639 if (status & (0x00000001 << ch->unit)) { 640 if (bootverbose) 641 device_printf(dev, "DISCONNECT requested\n"); 642 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 643 } 644 645 /* check for and handle connect events */ 646 if (status & (0x00000010 << ch->unit)) { 647 if (bootverbose) 648 device_printf(dev, "CONNECT requested\n"); 649 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 650 } 651 652 /* do we have any device action ? */ 653 return (vector & (1 << (ch->unit + 1))); 654} 655 656static int 657ata_promise_mio_command(struct ata_request *request) 658{ 659 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 660 struct ata_channel *ch = device_get_softc(request->parent); 661 662 u_int32_t *wordp = (u_int32_t *)ch->dma.work; 663 664 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 665 666 if ((ctlr->chip->cfg2 == PR_SATA2) || 667 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 668 /* set portmultiplier port */ 669 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), request->unit & 0x0f); 670 } 671 672 /* XXX SOS add ATAPI commands support later */ 673 switch (request->u.ata.command) { 674 default: 675 return ata_generic_command(request); 676 677 case ATA_READ_DMA: 678 case ATA_READ_DMA48: 679 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 680 break; 681 682 case ATA_WRITE_DMA: 683 case ATA_WRITE_DMA48: 684 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 685 break; 686 } 687 wordp[1] = htole32(request->dma->sg_bus); 688 wordp[2] = 0; 689 ata_promise_apkt((u_int8_t*)wordp, request); 690 691 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma.work_bus); 692 return 0; 693} 694 695static void 696ata_promise_mio_reset(device_t dev) 697{ 698 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 699 struct ata_channel *ch = device_get_softc(dev); 700 struct ata_promise_sx4 *hpktp; 701 702 switch (ctlr->chip->cfg2) { 703 case PR_SX4X: 704 705 /* softreset channel ATA module */ 706 hpktp = ctlr->chipset_data; 707 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 708 ata_udelay(1000); 709 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 710 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 711 ~0x00003f9f) | (ch->unit + 1)); 712 713 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 714 mtx_lock(&hpktp->mtx); 715 ATA_OUTL(ctlr->r_res2, 0xc012c, 716 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 717 DELAY(10); 718 ATA_OUTL(ctlr->r_res2, 0xc012c, 719 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 720 hpktp->busy = 0; 721 mtx_unlock(&hpktp->mtx); 722 ata_generic_reset(dev); 723 break; 724 725 case PR_PATA: 726 case PR_CMBO: 727 case PR_SATA: 728 if ((ctlr->chip->cfg2 == PR_SATA) || 729 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 730 731 /* mask plug/unplug intr */ 732 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 733 } 734 735 /* softreset channels ATA module */ 736 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 737 ata_udelay(10000); 738 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 739 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 740 ~0x00003f9f) | (ch->unit + 1)); 741 742 if ((ctlr->chip->cfg2 == PR_SATA) || 743 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 744 745 if (ata_sata_phy_reset(dev, -1, 1)) 746 ata_generic_reset(dev); 747 else 748 ch->devices = 0; 749 750 /* reset and enable plug/unplug intr */ 751 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 752 } 753 else 754 ata_generic_reset(dev); 755 break; 756 757 case PR_CMBO2: 758 case PR_SATA2: 759 if ((ctlr->chip->cfg2 == PR_SATA2) || 760 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 761 /* set portmultiplier port */ 762 //ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 763 764 /* mask plug/unplug intr */ 765 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 766 } 767 768 /* softreset channels ATA module */ 769 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 770 ata_udelay(10000); 771 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 772 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 773 ~0x00003f9f) | (ch->unit + 1)); 774 775 if ((ctlr->chip->cfg2 == PR_SATA2) || 776 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 777 778 /* set PHY mode to "improved" */ 779 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 780 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 781 ~0x00000003) | 0x00000001); 782 783 if (ata_sata_phy_reset(dev, -1, 1)) { 784 u_int32_t signature = ch->hw.softreset(dev, ATA_PM); 785 786 if (1 | bootverbose) 787 device_printf(dev, "SIGNATURE: %08x\n", signature); 788 789 switch (signature >> 16) { 790 case 0x0000: 791 ch->devices = ATA_ATA_MASTER; 792 break; 793 case 0x9669: 794 ch->devices = ATA_PORTMULTIPLIER; 795 ata_pm_identify(dev); 796 break; 797 case 0xeb14: 798 ch->devices = ATA_ATAPI_MASTER; 799 break; 800 default: /* SOS XXX */ 801 if (bootverbose) 802 device_printf(dev, 803 "No signature, assuming disk device\n"); 804 ch->devices = ATA_ATA_MASTER; 805 } 806 if (bootverbose) 807 device_printf(dev, "promise_mio_reset devices=%08x\n", 808 ch->devices); 809 810 } else 811 ch->devices = 0; 812 813 /* reset and enable plug/unplug intr */ 814 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 815 816 ///* set portmultiplier port */ 817 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 818 } 819 else 820 ata_generic_reset(dev); 821 break; 822 823 } 824} 825 826static int 827ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result) 828{ 829 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 830 struct ata_channel *ch = device_get_softc(dev); 831 int timeout = 0; 832 833 if (port < 0) { 834 *result = ATA_IDX_INL(ch, reg); 835 return (0); 836 } 837 if (port < ATA_PM) { 838 switch (reg) { 839 case ATA_SSTATUS: 840 reg = 0; 841 break; 842 case ATA_SERROR: 843 reg = 1; 844 break; 845 case ATA_SCONTROL: 846 reg = 2; 847 break; 848 default: 849 return (EINVAL); 850 } 851 } 852 /* set portmultiplier port */ 853 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 854 855 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 856 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 857 858 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_READ_PM); 859 860 while (timeout < 1000000) { 861 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 862 if (!(status & ATA_S_BUSY)) 863 break; 864 timeout += 1000; 865 DELAY(1000); 866 } 867 if (timeout >= 1000000) 868 return ATA_E_ABORT; 869 870 *result = ATA_IDX_INB(ch, ATA_COUNT) | 871 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 872 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 873 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 874 return 0; 875} 876 877static int 878ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value) 879{ 880 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 881 struct ata_channel *ch = device_get_softc(dev); 882 int timeout = 0; 883 884 if (port < 0) { 885 ATA_IDX_OUTL(ch, reg, value); 886 return (0); 887 } 888 if (port < ATA_PM) { 889 switch (reg) { 890 case ATA_SSTATUS: 891 reg = 0; 892 break; 893 case ATA_SERROR: 894 reg = 1; 895 break; 896 case ATA_SCONTROL: 897 reg = 2; 898 break; 899 default: 900 return (EINVAL); 901 } 902 } 903 /* set portmultiplier port */ 904 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 905 906 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 907 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 908 ATA_IDX_OUTB(ch, ATA_COUNT, value & 0xff); 909 ATA_IDX_OUTB(ch, ATA_SECTOR, (value >> 8) & 0xff); 910 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff); 911 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (value >> 24) & 0xff); 912 913 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_WRITE_PM); 914 915 while (timeout < 1000000) { 916 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 917 if (!(status & ATA_S_BUSY)) 918 break; 919 timeout += 1000; 920 DELAY(1000); 921 } 922 if (timeout >= 1000000) 923 return ATA_E_ABORT; 924 925 return ATA_IDX_INB(ch, ATA_ERROR); 926} 927 928/* must be called with ATA channel locked and state_mtx held */ 929static u_int32_t 930ata_promise_mio_softreset(device_t dev, int port) 931{ 932 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 933 struct ata_channel *ch = device_get_softc(dev); 934 int timeout; 935 936 /* set portmultiplier port */ 937 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), port & 0x0f); 938 939 /* softreset device on this channel */ 940 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 941 DELAY(10); 942 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 943 ata_udelay(10000); 944 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 945 ata_udelay(150000); 946 ATA_IDX_INB(ch, ATA_ERROR); 947 948 /* wait for BUSY to go inactive */ 949 for (timeout = 0; timeout < 100; timeout++) { 950 u_int8_t err, stat; 951 952 err = ATA_IDX_INB(ch, ATA_ERROR); 953 stat = ATA_IDX_INB(ch, ATA_STATUS); 954 955 //if (stat == err && timeout > (stat & ATA_S_BUSY ? 100 : 10)) 956 //break; 957 958 if (!(stat & ATA_S_BUSY)) { 959 //if ((err & 0x7f) == ATA_E_ILI) { 960 return ATA_IDX_INB(ch, ATA_COUNT) | 961 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 962 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 963 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 964 //} 965 //else if (stat & 0x0f) { 966 //stat |= ATA_S_BUSY; 967 //} 968 } 969 970 if (!(stat & ATA_S_BUSY) || (stat == 0xff && timeout > 10)) 971 break; 972 ata_udelay(100000); 973 } 974 return -1; 975} 976 977static void 978ata_promise_mio_dmainit(device_t dev) 979{ 980 struct ata_channel *ch = device_get_softc(dev); 981 982 /* note start and stop are not used here */ 983 ch->dma.setprd = ata_promise_mio_setprd; 984 ch->dma.max_iosize = 65536; 985 ata_dmainit(dev); 986} 987 988#define MAXLASTSGSIZE (32 * sizeof(u_int32_t)) 989static void 990ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 991{ 992 struct ata_dmasetprd_args *args = xsc; 993 struct ata_dma_prdentry *prd = args->dmatab; 994 int i; 995 996 if ((args->error = error)) 997 return; 998 999 for (i = 0; i < nsegs; i++) { 1000 prd[i].addr = htole32(segs[i].ds_addr); 1001 prd[i].count = htole32(segs[i].ds_len); 1002 } 1003 if (segs[i - 1].ds_len > MAXLASTSGSIZE) { 1004 //printf("split last SG element of %u\n", segs[i - 1].ds_len); 1005 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE); 1006 prd[i].count = htole32(MAXLASTSGSIZE); 1007 prd[i].addr = htole32(segs[i - 1].ds_addr + 1008 (segs[i - 1].ds_len - MAXLASTSGSIZE)); 1009 nsegs++; 1010 i++; 1011 } 1012 prd[i - 1].count |= htole32(ATA_DMA_EOT); 1013 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 1014 args->nsegs = nsegs; 1015} 1016 1017static int 1018ata_promise_mio_setmode(device_t dev, int target, int mode) 1019{ 1020 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1021 struct ata_channel *ch = device_get_softc(dev); 1022 1023 if ( (ctlr->chip->cfg2 == PR_SATA) || 1024 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1025 (ctlr->chip->cfg2 == PR_SATA2) || 1026 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1027 mode = ata_sata_setmode(dev, target, mode); 1028 else 1029 mode = ata_promise_setmode(dev, target, mode); 1030 return (mode); 1031} 1032 1033static int 1034ata_promise_mio_getrev(device_t dev, int target) 1035{ 1036 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1037 struct ata_channel *ch = device_get_softc(dev); 1038 1039 if ( (ctlr->chip->cfg2 == PR_SATA) || 1040 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1041 (ctlr->chip->cfg2 == PR_SATA2) || 1042 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1043 return (ata_sata_getrev(dev, target)); 1044 else 1045 return (0); 1046} 1047 1048static void 1049ata_promise_sx4_intr(void *data) 1050{ 1051 struct ata_pci_controller *ctlr = data; 1052 struct ata_channel *ch; 1053 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 1054 int unit; 1055 1056 for (unit = 0; unit < ctlr->channels; unit++) { 1057 if (vector & (1 << (unit + 1))) 1058 if ((ch = ctlr->interrupt[unit].argument)) 1059 ctlr->interrupt[unit].function(ch); 1060 if (vector & (1 << (unit + 5))) 1061 if ((ch = ctlr->interrupt[unit].argument)) 1062 ata_promise_queue_hpkt(ctlr, 1063 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1064 ATA_PDC_HPKT_OFFSET)); 1065 if (vector & (1 << (unit + 9))) { 1066 ata_promise_next_hpkt(ctlr); 1067 if ((ch = ctlr->interrupt[unit].argument)) 1068 ctlr->interrupt[unit].function(ch); 1069 } 1070 if (vector & (1 << (unit + 13))) { 1071 ata_promise_next_hpkt(ctlr); 1072 if ((ch = ctlr->interrupt[unit].argument)) 1073 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1074 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1075 ATA_PDC_APKT_OFFSET)); 1076 } 1077 } 1078} 1079 1080static int 1081ata_promise_sx4_command(struct ata_request *request) 1082{ 1083 device_t gparent = device_get_parent(request->parent); 1084 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1085 struct ata_channel *ch = device_get_softc(request->parent); 1086 struct ata_dma_prdentry *prd; 1087 caddr_t window = rman_get_virtual(ctlr->r_res1); 1088 u_int32_t *wordp; 1089 int i, idx, length = 0; 1090 1091 /* XXX SOS add ATAPI commands support later */ 1092 switch (request->u.ata.command) { 1093 1094 default: 1095 return -1; 1096 1097 case ATA_ATA_IDENTIFY: 1098 case ATA_READ: 1099 case ATA_READ48: 1100 case ATA_READ_MUL: 1101 case ATA_READ_MUL48: 1102 case ATA_WRITE: 1103 case ATA_WRITE48: 1104 case ATA_WRITE_MUL: 1105 case ATA_WRITE_MUL48: 1106 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1107 return ata_generic_command(request); 1108 1109 case ATA_SETFEATURES: 1110 case ATA_FLUSHCACHE: 1111 case ATA_FLUSHCACHE48: 1112 case ATA_SLEEP: 1113 case ATA_SET_MULTI: 1114 wordp = (u_int32_t *) 1115 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1116 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 1117 wordp[1] = 0; 1118 wordp[2] = 0; 1119 ata_promise_apkt((u_int8_t *)wordp, request); 1120 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1121 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1122 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1123 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 1124 return 0; 1125 1126 case ATA_READ_DMA: 1127 case ATA_READ_DMA48: 1128 case ATA_WRITE_DMA: 1129 case ATA_WRITE_DMA48: 1130 prd = request->dma->sg; 1131 wordp = (u_int32_t *) 1132 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 1133 i = idx = 0; 1134 do { 1135 wordp[idx++] = prd[i].addr; 1136 wordp[idx++] = prd[i].count; 1137 length += (prd[i].count & ~ATA_DMA_EOT); 1138 } while (!(prd[i++].count & ATA_DMA_EOT)); 1139 1140 wordp = (u_int32_t *) 1141 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 1142 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1143 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1144 1145 wordp = (u_int32_t *) 1146 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 1147 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1148 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1149 1150 wordp = (u_int32_t *) 1151 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 1152 if (request->flags & ATA_R_READ) 1153 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 1154 if (request->flags & ATA_R_WRITE) 1155 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 1156 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 1157 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 1158 wordp[3] = 0; 1159 1160 wordp = (u_int32_t *) 1161 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1162 if (request->flags & ATA_R_READ) 1163 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 1164 if (request->flags & ATA_R_WRITE) 1165 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 1166 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 1167 wordp[2] = 0; 1168 ata_promise_apkt((u_int8_t *)wordp, request); 1169 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1170 1171 if (request->flags & ATA_R_READ) { 1172 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 1173 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 1174 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1175 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 1176 } 1177 if (request->flags & ATA_R_WRITE) { 1178 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 1179 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 1180 ata_promise_queue_hpkt(ctlr, 1181 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 1182 } 1183 return 0; 1184 } 1185} 1186 1187static int 1188ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 1189{ 1190 int i = 12; 1191 1192 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 1193 bytep[i++] = ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit); 1194 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 1195 bytep[i++] = ATA_A_4BIT; 1196 1197 if (request->flags & ATA_R_48BIT) { 1198 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1199 bytep[i++] = request->u.ata.feature >> 8; 1200 bytep[i++] = request->u.ata.feature; 1201 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 1202 bytep[i++] = request->u.ata.count >> 8; 1203 bytep[i++] = request->u.ata.count; 1204 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1205 bytep[i++] = request->u.ata.lba >> 24; 1206 bytep[i++] = request->u.ata.lba; 1207 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1208 bytep[i++] = request->u.ata.lba >> 32; 1209 bytep[i++] = request->u.ata.lba >> 8; 1210 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1211 bytep[i++] = request->u.ata.lba >> 40; 1212 bytep[i++] = request->u.ata.lba >> 16; 1213 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1214 bytep[i++] = ATA_D_LBA | ATA_DEV(request->unit); 1215 } 1216 else { 1217 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1218 bytep[i++] = request->u.ata.feature; 1219 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 1220 bytep[i++] = request->u.ata.count; 1221 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1222 bytep[i++] = request->u.ata.lba; 1223 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1224 bytep[i++] = request->u.ata.lba >> 8; 1225 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1226 bytep[i++] = request->u.ata.lba >> 16; 1227 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1228 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ATA_DEV(request->unit) | 1229 ((request->u.ata.lba >> 24)&0xf); 1230 } 1231 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 1232 bytep[i++] = request->u.ata.command; 1233 return i; 1234} 1235 1236static void 1237ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 1238{ 1239 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1240 1241 mtx_lock(&hpktp->mtx); 1242 if (hpktp->busy) { 1243 struct host_packet *hp = 1244 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO); 1245 hp->addr = hpkt; 1246 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 1247 } 1248 else { 1249 hpktp->busy = 1; 1250 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 1251 } 1252 mtx_unlock(&hpktp->mtx); 1253} 1254 1255static void 1256ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 1257{ 1258 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1259 struct host_packet *hp; 1260 1261 mtx_lock(&hpktp->mtx); 1262 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 1263 TAILQ_REMOVE(&hpktp->queue, hp, chain); 1264 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 1265 free(hp, M_TEMP); 1266 } 1267 else 1268 hpktp->busy = 0; 1269 mtx_unlock(&hpktp->mtx); 1270} 1271 1272ATA_DECLARE_DRIVER(ata_promise); 1273