ata-ite.c revision 237107
1/*- 2 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-ite.c 237107 2012-06-14 22:19:23Z marius $"); 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_ite_chipinit(device_t dev); 56static int ata_ite_ch_attach(device_t dev); 57static int ata_ite_821x_setmode(device_t dev, int target, int mode); 58static int ata_ite_8213_setmode(device_t dev, int target, int mode); 59 60/* 61 * Integrated Technology Express Inc. (ITE) chipset support functions 62 */ 63static int 64ata_ite_probe(device_t dev) 65{ 66 struct ata_pci_controller *ctlr = device_get_softc(dev); 67 static const struct ata_chip_id const ids[] = 68 {{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" }, 69 { ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 70 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 71 { 0, 0, 0, 0, 0, 0}}; 72 73 if (pci_get_vendor(dev) != ATA_ITE_ID) 74 return ENXIO; 75 76 if (!(ctlr->chip = ata_match_chip(dev, ids))) 77 return ENXIO; 78 79 ata_set_desc(dev); 80 ctlr->chipinit = ata_ite_chipinit; 81 return (BUS_PROBE_DEFAULT); 82} 83 84static int 85ata_ite_chipinit(device_t dev) 86{ 87 struct ata_pci_controller *ctlr = device_get_softc(dev); 88 89 if (ata_setup_interrupt(dev, ata_generic_intr)) 90 return ENXIO; 91 92 if (ctlr->chip->chipid == ATA_IT8213F) { 93 /* the ITE 8213F only has one channel */ 94 ctlr->channels = 1; 95 96 ctlr->setmode = ata_ite_8213_setmode; 97 } 98 else { 99 /* set PCI mode and 66Mhz reference clock */ 100 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 101 102 /* set default active & recover timings */ 103 pci_write_config(dev, 0x54, 0x31, 1); 104 pci_write_config(dev, 0x56, 0x31, 1); 105 106 ctlr->setmode = ata_ite_821x_setmode; 107 /* No timing restrictions initally. */ 108 ctlr->chipset_data = NULL; 109 } 110 ctlr->ch_attach = ata_ite_ch_attach; 111 return (0); 112} 113 114static int 115ata_ite_ch_attach(device_t dev) 116{ 117 struct ata_channel *ch = device_get_softc(dev); 118 int error; 119 120 error = ata_pci_ch_attach(dev); 121 ch->flags |= ATA_CHECKS_CABLE; 122#ifdef ATA_CAM 123 ch->flags |= ATA_NO_ATAPI_DMA; 124#endif 125 return (error); 126} 127 128static int 129ata_ite_821x_setmode(device_t dev, int target, int mode) 130{ 131 device_t parent = device_get_parent(dev); 132 struct ata_pci_controller *ctlr = device_get_softc(parent); 133 struct ata_channel *ch = device_get_softc(dev); 134 int devno = (ch->unit << 1) + target; 135 int piomode; 136 uint8_t *timings = (uint8_t*)(&ctlr->chipset_data); 137 static const uint8_t udmatiming[] = 138 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 139 static const uint8_t chtiming[] = 140 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 141 142 mode = min(mode, ctlr->chip->max_dma); 143 /* check the CBLID bits for 80 conductor cable detection */ 144 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 145 (pci_read_config(parent, 0x40, 2) & 146 (ch->unit ? (1<<3) : (1<<2)))) { 147 ata_print_cable(dev, "controller"); 148 mode = ATA_UDMA2; 149 } 150 if (mode >= ATA_UDMA0) { 151 /* enable UDMA mode */ 152 pci_write_config(parent, 0x50, 153 pci_read_config(parent, 0x50, 1) & 154 ~(1 << (devno + 3)), 1); 155 /* set UDMA timing */ 156 pci_write_config(parent, 157 0x56 + (ch->unit << 2) + target, 158 udmatiming[mode & ATA_MODE_MASK], 1); 159 piomode = ATA_PIO4; 160 } else { 161 /* disable UDMA mode */ 162 pci_write_config(parent, 0x50, 163 pci_read_config(parent, 0x50, 1) | 164 (1 << (devno + 3)), 1); 165 piomode = mode; 166 } 167 timings[devno] = chtiming[ata_mode2idx(piomode)]; 168 /* set active and recover timing (shared between master & slave) */ 169 pci_write_config(parent, 0x54 + (ch->unit << 2), 170 max(timings[ch->unit << 1], timings[(ch->unit << 1) + 1]), 1); 171 return (mode); 172} 173 174static int 175ata_ite_8213_setmode(device_t dev, int target, int mode) 176{ 177 device_t parent = device_get_parent(dev); 178 struct ata_pci_controller *ctlr = device_get_softc(parent); 179 int piomode; 180 u_int16_t reg40 = pci_read_config(parent, 0x40, 2); 181 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 182 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 183 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 184 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 185 u_int16_t mask40 = 0, new40 = 0; 186 u_int8_t mask44 = 0, new44 = 0; 187 static const uint8_t timings[] = 188 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 189 static const uint8_t utimings[] = 190 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 191 192 mode = min(mode, ctlr->chip->max_dma); 193 194 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 195 !(reg54 & (0x10 << target))) { 196 ata_print_cable(dev, "controller"); 197 mode = ATA_UDMA2; 198 } 199 /* Enable/disable UDMA and set timings. */ 200 if (mode >= ATA_UDMA0) { 201 pci_write_config(parent, 0x48, reg48 | (0x0001 << target), 2); 202 pci_write_config(parent, 0x4a, 203 (reg4a & ~(0x3 << (target << 2))) | 204 (utimings[mode & ATA_MODE_MASK] << (target<<2)), 2); 205 piomode = ATA_PIO4; 206 } else { 207 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << target), 2); 208 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (target << 2))),2); 209 piomode = mode; 210 } 211 /* Set UDMA reference clock (33/66/133MHz). */ 212 reg54 &= ~(0x1001 << target); 213 if (mode >= ATA_UDMA5) 214 reg54 |= (0x1000 << target); 215 else if (mode >= ATA_UDMA3) 216 reg54 |= (0x1 << target); 217 pci_write_config(parent, 0x54, reg54, 2); 218 /* Allow PIO/WDMA timing controls. */ 219 reg40 &= 0xff00; 220 reg40 |= 0x4033; 221 /* Set PIO/WDMA timings. */ 222 if (target == 0) { 223 reg40 |= (ata_atapi(dev, target) ? 0x04 : 0x00); 224 mask40 = 0x3300; 225 new40 = timings[ata_mode2idx(piomode)] << 8; 226 } 227 else { 228 reg40 |= (ata_atapi(dev, target) ? 0x40 : 0x00); 229 mask44 = 0x0f; 230 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 231 (timings[ata_mode2idx(piomode)] & 0x03); 232 } 233 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 234 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 235 return (mode); 236} 237 238ATA_DECLARE_DRIVER(ata_ite); 239