ata-ite.c revision 242625
1183724Ssos/*- 2230132Suqs * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3183724Ssos * All rights reserved. 4183724Ssos * 5183724Ssos * Redistribution and use in source and binary forms, with or without 6183724Ssos * modification, are permitted provided that the following conditions 7183724Ssos * are met: 8183724Ssos * 1. Redistributions of source code must retain the above copyright 9183724Ssos * notice, this list of conditions and the following disclaimer, 10183724Ssos * without modification, immediately at the beginning of the file. 11183724Ssos * 2. Redistributions in binary form must reproduce the above copyright 12183724Ssos * notice, this list of conditions and the following disclaimer in the 13183724Ssos * documentation and/or other materials provided with the distribution. 14183724Ssos * 15183724Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16183724Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17183724Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18183724Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19183724Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20183724Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21183724Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22183724Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23183724Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24183724Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25183724Ssos */ 26183724Ssos 27183724Ssos#include <sys/cdefs.h> 28183724Ssos__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-ite.c 242625 2012-11-05 19:16:27Z dim $"); 29183724Ssos 30183724Ssos#include "opt_ata.h" 31183724Ssos#include <sys/param.h> 32183724Ssos#include <sys/module.h> 33183724Ssos#include <sys/systm.h> 34183724Ssos#include <sys/kernel.h> 35183724Ssos#include <sys/ata.h> 36183724Ssos#include <sys/bus.h> 37183724Ssos#include <sys/endian.h> 38183724Ssos#include <sys/malloc.h> 39183724Ssos#include <sys/lock.h> 40183724Ssos#include <sys/mutex.h> 41183724Ssos#include <sys/sema.h> 42183724Ssos#include <sys/taskqueue.h> 43183724Ssos#include <vm/uma.h> 44183724Ssos#include <machine/stdarg.h> 45183724Ssos#include <machine/resource.h> 46183724Ssos#include <machine/bus.h> 47183724Ssos#include <sys/rman.h> 48183724Ssos#include <dev/pci/pcivar.h> 49183724Ssos#include <dev/pci/pcireg.h> 50183724Ssos#include <dev/ata/ata-all.h> 51183724Ssos#include <dev/ata/ata-pci.h> 52183724Ssos#include <ata_if.h> 53183724Ssos 54183724Ssos/* local prototypes */ 55183724Ssosstatic int ata_ite_chipinit(device_t dev); 56200171Smavstatic int ata_ite_ch_attach(device_t dev); 57200171Smavstatic int ata_ite_821x_setmode(device_t dev, int target, int mode); 58200171Smavstatic int ata_ite_8213_setmode(device_t dev, int target, int mode); 59183724Ssos 60183724Ssos/* 61183724Ssos * Integrated Technology Express Inc. (ITE) chipset support functions 62183724Ssos */ 63183724Ssosstatic int 64183724Ssosata_ite_probe(device_t dev) 65183724Ssos{ 66183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 67242625Sdim static const struct ata_chip_id ids[] = 68183724Ssos {{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" }, 69183724Ssos { ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 70183724Ssos { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 71183724Ssos { 0, 0, 0, 0, 0, 0}}; 72183724Ssos 73183724Ssos if (pci_get_vendor(dev) != ATA_ITE_ID) 74183724Ssos return ENXIO; 75183724Ssos 76183724Ssos if (!(ctlr->chip = ata_match_chip(dev, ids))) 77183724Ssos return ENXIO; 78183724Ssos 79183724Ssos ata_set_desc(dev); 80183724Ssos ctlr->chipinit = ata_ite_chipinit; 81194893Smav return (BUS_PROBE_DEFAULT); 82183724Ssos} 83183724Ssos 84183724Ssosstatic int 85183724Ssosata_ite_chipinit(device_t dev) 86183724Ssos{ 87183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 88183724Ssos 89183724Ssos if (ata_setup_interrupt(dev, ata_generic_intr)) 90183724Ssos return ENXIO; 91183724Ssos 92183724Ssos if (ctlr->chip->chipid == ATA_IT8213F) { 93183724Ssos /* the ITE 8213F only has one channel */ 94183724Ssos ctlr->channels = 1; 95183724Ssos 96183724Ssos ctlr->setmode = ata_ite_8213_setmode; 97183724Ssos } 98183724Ssos else { 99183724Ssos /* set PCI mode and 66Mhz reference clock */ 100183724Ssos pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 101183724Ssos 102183724Ssos /* set default active & recover timings */ 103183724Ssos pci_write_config(dev, 0x54, 0x31, 1); 104183724Ssos pci_write_config(dev, 0x56, 0x31, 1); 105183724Ssos 106183724Ssos ctlr->setmode = ata_ite_821x_setmode; 107200753Smav /* No timing restrictions initally. */ 108237107Smarius ctlr->chipset_data = NULL; 109183724Ssos } 110200171Smav ctlr->ch_attach = ata_ite_ch_attach; 111237107Smarius return (0); 112183724Ssos} 113200171Smav 114200171Smavstatic int 115200171Smavata_ite_ch_attach(device_t dev) 116200171Smav{ 117200171Smav struct ata_channel *ch = device_get_softc(dev); 118200171Smav int error; 119183724Ssos 120200171Smav error = ata_pci_ch_attach(dev); 121200171Smav ch->flags |= ATA_CHECKS_CABLE; 122237107Smarius#ifdef ATA_CAM 123237107Smarius ch->flags |= ATA_NO_ATAPI_DMA; 124237107Smarius#endif 125200171Smav return (error); 126200171Smav} 127200171Smav 128200171Smavstatic int 129200171Smavata_ite_821x_setmode(device_t dev, int target, int mode) 130183724Ssos{ 131200171Smav device_t parent = device_get_parent(dev); 132200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 133200171Smav struct ata_channel *ch = device_get_softc(dev); 134200171Smav int devno = (ch->unit << 1) + target; 135200171Smav int piomode; 136200753Smav uint8_t *timings = (uint8_t*)(&ctlr->chipset_data); 137233282Smarius static const uint8_t udmatiming[] = 138200171Smav { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 139233282Smarius static const uint8_t chtiming[] = 140200171Smav { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 141183724Ssos 142200171Smav mode = min(mode, ctlr->chip->max_dma); 143200171Smav /* check the CBLID bits for 80 conductor cable detection */ 144209872Smav if (ata_dma_check_80pin && mode > ATA_UDMA2 && 145209872Smav (pci_read_config(parent, 0x40, 2) & 146183724Ssos (ch->unit ? (1<<3) : (1<<2)))) { 147200171Smav ata_print_cable(dev, "controller"); 148200171Smav mode = ATA_UDMA2; 149200171Smav } 150183724Ssos if (mode >= ATA_UDMA0) { 151200171Smav /* enable UDMA mode */ 152200171Smav pci_write_config(parent, 0x50, 153200171Smav pci_read_config(parent, 0x50, 1) & 154183724Ssos ~(1 << (devno + 3)), 1); 155200171Smav /* set UDMA timing */ 156200171Smav pci_write_config(parent, 157200171Smav 0x56 + (ch->unit << 2) + target, 158183724Ssos udmatiming[mode & ATA_MODE_MASK], 1); 159200171Smav piomode = ATA_PIO4; 160200171Smav } else { 161200171Smav /* disable UDMA mode */ 162200171Smav pci_write_config(parent, 0x50, 163200171Smav pci_read_config(parent, 0x50, 1) | 164183724Ssos (1 << (devno + 3)), 1); 165200171Smav piomode = mode; 166183724Ssos } 167200753Smav timings[devno] = chtiming[ata_mode2idx(piomode)]; 168200171Smav /* set active and recover timing (shared between master & slave) */ 169200753Smav pci_write_config(parent, 0x54 + (ch->unit << 2), 170200753Smav max(timings[ch->unit << 1], timings[(ch->unit << 1) + 1]), 1); 171200171Smav return (mode); 172183724Ssos} 173183724Ssos 174200171Smavstatic int 175200171Smavata_ite_8213_setmode(device_t dev, int target, int mode) 176183724Ssos{ 177200171Smav device_t parent = device_get_parent(dev); 178200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 179200171Smav int piomode; 180200171Smav u_int16_t reg40 = pci_read_config(parent, 0x40, 2); 181200171Smav u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 182200171Smav u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 183200171Smav u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 184200171Smav u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 185200171Smav u_int16_t mask40 = 0, new40 = 0; 186200171Smav u_int8_t mask44 = 0, new44 = 0; 187233282Smarius static const uint8_t timings[] = 188233282Smarius { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 189233282Smarius static const uint8_t utimings[] = 190233282Smarius { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 191183724Ssos 192200171Smav mode = min(mode, ctlr->chip->max_dma); 193183724Ssos 194209872Smav if (ata_dma_check_80pin && mode > ATA_UDMA2 && 195209872Smav !(reg54 & (0x10 << target))) { 196200171Smav ata_print_cable(dev, "controller"); 197200171Smav mode = ATA_UDMA2; 198200171Smav } 199200171Smav /* Enable/disable UDMA and set timings. */ 200183724Ssos if (mode >= ATA_UDMA0) { 201200171Smav pci_write_config(parent, 0x48, reg48 | (0x0001 << target), 2); 202200171Smav pci_write_config(parent, 0x4a, 203200171Smav (reg4a & ~(0x3 << (target << 2))) | 204200171Smav (utimings[mode & ATA_MODE_MASK] << (target<<2)), 2); 205200171Smav piomode = ATA_PIO4; 206200171Smav } else { 207200171Smav pci_write_config(parent, 0x48, reg48 & ~(0x0001 << target), 2); 208200171Smav pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (target << 2))),2); 209200171Smav piomode = mode; 210183724Ssos } 211200171Smav /* Set UDMA reference clock (33/66/133MHz). */ 212200171Smav reg54 &= ~(0x1001 << target); 213183724Ssos if (mode >= ATA_UDMA5) 214200171Smav reg54 |= (0x1000 << target); 215200171Smav else if (mode >= ATA_UDMA3) 216200171Smav reg54 |= (0x1 << target); 217200171Smav pci_write_config(parent, 0x54, reg54, 2); 218200171Smav /* Allow PIO/WDMA timing controls. */ 219183724Ssos reg40 &= 0xff00; 220183724Ssos reg40 |= 0x4033; 221200171Smav /* Set PIO/WDMA timings. */ 222200171Smav if (target == 0) { 223200459Smarius reg40 |= (ata_atapi(dev, target) ? 0x04 : 0x00); 224183724Ssos mask40 = 0x3300; 225200171Smav new40 = timings[ata_mode2idx(piomode)] << 8; 226183724Ssos } 227183724Ssos else { 228200459Smarius reg40 |= (ata_atapi(dev, target) ? 0x40 : 0x00); 229183724Ssos mask44 = 0x0f; 230200171Smav new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 231200171Smav (timings[ata_mode2idx(piomode)] & 0x03); 232183724Ssos } 233200171Smav pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 234200171Smav pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 235200171Smav return (mode); 236183724Ssos} 237183724Ssos 238183724SsosATA_DECLARE_DRIVER(ata_ite); 239