ata-ite.c revision 230132
1183724Ssos/*- 2230132Suqs * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3183724Ssos * All rights reserved. 4183724Ssos * 5183724Ssos * Redistribution and use in source and binary forms, with or without 6183724Ssos * modification, are permitted provided that the following conditions 7183724Ssos * are met: 8183724Ssos * 1. Redistributions of source code must retain the above copyright 9183724Ssos * notice, this list of conditions and the following disclaimer, 10183724Ssos * without modification, immediately at the beginning of the file. 11183724Ssos * 2. Redistributions in binary form must reproduce the above copyright 12183724Ssos * notice, this list of conditions and the following disclaimer in the 13183724Ssos * documentation and/or other materials provided with the distribution. 14183724Ssos * 15183724Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16183724Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17183724Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18183724Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19183724Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20183724Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21183724Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22183724Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23183724Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24183724Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25183724Ssos */ 26183724Ssos 27183724Ssos#include <sys/cdefs.h> 28183724Ssos__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-ite.c 230132 2012-01-15 13:23:18Z uqs $"); 29183724Ssos 30183724Ssos#include "opt_ata.h" 31183724Ssos#include <sys/param.h> 32183724Ssos#include <sys/module.h> 33183724Ssos#include <sys/systm.h> 34183724Ssos#include <sys/kernel.h> 35183724Ssos#include <sys/ata.h> 36183724Ssos#include <sys/bus.h> 37183724Ssos#include <sys/endian.h> 38183724Ssos#include <sys/malloc.h> 39183724Ssos#include <sys/lock.h> 40183724Ssos#include <sys/mutex.h> 41183724Ssos#include <sys/sema.h> 42183724Ssos#include <sys/taskqueue.h> 43183724Ssos#include <vm/uma.h> 44183724Ssos#include <machine/stdarg.h> 45183724Ssos#include <machine/resource.h> 46183724Ssos#include <machine/bus.h> 47183724Ssos#include <sys/rman.h> 48183724Ssos#include <dev/pci/pcivar.h> 49183724Ssos#include <dev/pci/pcireg.h> 50183724Ssos#include <dev/ata/ata-all.h> 51183724Ssos#include <dev/ata/ata-pci.h> 52183724Ssos#include <ata_if.h> 53183724Ssos 54183724Ssos/* local prototypes */ 55183724Ssosstatic int ata_ite_chipinit(device_t dev); 56200171Smavstatic int ata_ite_ch_attach(device_t dev); 57200171Smavstatic int ata_ite_821x_setmode(device_t dev, int target, int mode); 58200171Smavstatic int ata_ite_8213_setmode(device_t dev, int target, int mode); 59183724Ssos 60183724Ssos 61183724Ssos/* 62183724Ssos * Integrated Technology Express Inc. (ITE) chipset support functions 63183724Ssos */ 64183724Ssosstatic int 65183724Ssosata_ite_probe(device_t dev) 66183724Ssos{ 67183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 68183724Ssos static struct ata_chip_id ids[] = 69183724Ssos {{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" }, 70183724Ssos { ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 71183724Ssos { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 72183724Ssos { 0, 0, 0, 0, 0, 0}}; 73183724Ssos 74183724Ssos if (pci_get_vendor(dev) != ATA_ITE_ID) 75183724Ssos return ENXIO; 76183724Ssos 77183724Ssos if (!(ctlr->chip = ata_match_chip(dev, ids))) 78183724Ssos return ENXIO; 79183724Ssos 80183724Ssos ata_set_desc(dev); 81183724Ssos ctlr->chipinit = ata_ite_chipinit; 82194893Smav return (BUS_PROBE_DEFAULT); 83183724Ssos} 84183724Ssos 85183724Ssosstatic int 86183724Ssosata_ite_chipinit(device_t dev) 87183724Ssos{ 88183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 89183724Ssos 90183724Ssos if (ata_setup_interrupt(dev, ata_generic_intr)) 91183724Ssos return ENXIO; 92183724Ssos 93183724Ssos if (ctlr->chip->chipid == ATA_IT8213F) { 94183724Ssos /* the ITE 8213F only has one channel */ 95183724Ssos ctlr->channels = 1; 96183724Ssos 97183724Ssos ctlr->setmode = ata_ite_8213_setmode; 98183724Ssos } 99183724Ssos else { 100183724Ssos /* set PCI mode and 66Mhz reference clock */ 101183724Ssos pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 102183724Ssos 103183724Ssos /* set default active & recover timings */ 104183724Ssos pci_write_config(dev, 0x54, 0x31, 1); 105183724Ssos pci_write_config(dev, 0x56, 0x31, 1); 106183724Ssos 107183724Ssos ctlr->setmode = ata_ite_821x_setmode; 108200753Smav /* No timing restrictions initally. */ 109200753Smav ctlr->chipset_data = (void *)0; 110183724Ssos } 111200171Smav ctlr->ch_attach = ata_ite_ch_attach; 112183724Ssos return 0; 113183724Ssos} 114200171Smav 115200171Smavstatic int 116200171Smavata_ite_ch_attach(device_t dev) 117200171Smav{ 118200171Smav struct ata_channel *ch = device_get_softc(dev); 119200171Smav int error; 120183724Ssos 121200171Smav error = ata_pci_ch_attach(dev); 122200171Smav ch->flags |= ATA_CHECKS_CABLE; 123200171Smav return (error); 124200171Smav} 125200171Smav 126200171Smavstatic int 127200171Smavata_ite_821x_setmode(device_t dev, int target, int mode) 128183724Ssos{ 129200171Smav device_t parent = device_get_parent(dev); 130200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 131200171Smav struct ata_channel *ch = device_get_softc(dev); 132200171Smav int devno = (ch->unit << 1) + target; 133200171Smav int piomode; 134200753Smav uint8_t *timings = (uint8_t*)(&ctlr->chipset_data); 135200171Smav u_int8_t udmatiming[] = 136200171Smav { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 137200171Smav u_int8_t chtiming[] = 138200171Smav { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 139183724Ssos 140200171Smav mode = min(mode, ctlr->chip->max_dma); 141200171Smav /* check the CBLID bits for 80 conductor cable detection */ 142209872Smav if (ata_dma_check_80pin && mode > ATA_UDMA2 && 143209872Smav (pci_read_config(parent, 0x40, 2) & 144183724Ssos (ch->unit ? (1<<3) : (1<<2)))) { 145200171Smav ata_print_cable(dev, "controller"); 146200171Smav mode = ATA_UDMA2; 147200171Smav } 148183724Ssos if (mode >= ATA_UDMA0) { 149200171Smav /* enable UDMA mode */ 150200171Smav pci_write_config(parent, 0x50, 151200171Smav pci_read_config(parent, 0x50, 1) & 152183724Ssos ~(1 << (devno + 3)), 1); 153200171Smav /* set UDMA timing */ 154200171Smav pci_write_config(parent, 155200171Smav 0x56 + (ch->unit << 2) + target, 156183724Ssos udmatiming[mode & ATA_MODE_MASK], 1); 157200171Smav piomode = ATA_PIO4; 158200171Smav } else { 159200171Smav /* disable UDMA mode */ 160200171Smav pci_write_config(parent, 0x50, 161200171Smav pci_read_config(parent, 0x50, 1) | 162183724Ssos (1 << (devno + 3)), 1); 163200171Smav piomode = mode; 164183724Ssos } 165200753Smav timings[devno] = chtiming[ata_mode2idx(piomode)]; 166200171Smav /* set active and recover timing (shared between master & slave) */ 167200753Smav pci_write_config(parent, 0x54 + (ch->unit << 2), 168200753Smav max(timings[ch->unit << 1], timings[(ch->unit << 1) + 1]), 1); 169200171Smav return (mode); 170183724Ssos} 171183724Ssos 172200171Smavstatic int 173200171Smavata_ite_8213_setmode(device_t dev, int target, int mode) 174183724Ssos{ 175200171Smav device_t parent = device_get_parent(dev); 176200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 177200171Smav int piomode; 178200171Smav u_int16_t reg40 = pci_read_config(parent, 0x40, 2); 179200171Smav u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 180200171Smav u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 181200171Smav u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 182200171Smav u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 183200171Smav u_int16_t mask40 = 0, new40 = 0; 184200171Smav u_int8_t mask44 = 0, new44 = 0; 185200171Smav u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 186200171Smav u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 187183724Ssos 188200171Smav mode = min(mode, ctlr->chip->max_dma); 189183724Ssos 190209872Smav if (ata_dma_check_80pin && mode > ATA_UDMA2 && 191209872Smav !(reg54 & (0x10 << target))) { 192200171Smav ata_print_cable(dev, "controller"); 193200171Smav mode = ATA_UDMA2; 194200171Smav } 195200171Smav /* Enable/disable UDMA and set timings. */ 196183724Ssos if (mode >= ATA_UDMA0) { 197200171Smav pci_write_config(parent, 0x48, reg48 | (0x0001 << target), 2); 198200171Smav pci_write_config(parent, 0x4a, 199200171Smav (reg4a & ~(0x3 << (target << 2))) | 200200171Smav (utimings[mode & ATA_MODE_MASK] << (target<<2)), 2); 201200171Smav piomode = ATA_PIO4; 202200171Smav } else { 203200171Smav pci_write_config(parent, 0x48, reg48 & ~(0x0001 << target), 2); 204200171Smav pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (target << 2))),2); 205200171Smav piomode = mode; 206183724Ssos } 207200171Smav /* Set UDMA reference clock (33/66/133MHz). */ 208200171Smav reg54 &= ~(0x1001 << target); 209183724Ssos if (mode >= ATA_UDMA5) 210200171Smav reg54 |= (0x1000 << target); 211200171Smav else if (mode >= ATA_UDMA3) 212200171Smav reg54 |= (0x1 << target); 213200171Smav pci_write_config(parent, 0x54, reg54, 2); 214200171Smav /* Allow PIO/WDMA timing controls. */ 215183724Ssos reg40 &= 0xff00; 216183724Ssos reg40 |= 0x4033; 217200171Smav /* Set PIO/WDMA timings. */ 218200171Smav if (target == 0) { 219200459Smarius reg40 |= (ata_atapi(dev, target) ? 0x04 : 0x00); 220183724Ssos mask40 = 0x3300; 221200171Smav new40 = timings[ata_mode2idx(piomode)] << 8; 222183724Ssos } 223183724Ssos else { 224200459Smarius reg40 |= (ata_atapi(dev, target) ? 0x40 : 0x00); 225183724Ssos mask44 = 0x0f; 226200171Smav new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 227200171Smav (timings[ata_mode2idx(piomode)] & 0x03); 228183724Ssos } 229200171Smav pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 230200171Smav pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 231200171Smav return (mode); 232183724Ssos} 233183724Ssos 234183724SsosATA_DECLARE_DRIVER(ata_ite); 235