ata-ite.c revision 200171
1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-ite.c 200171 2009-12-06 00:10:13Z mav $"); 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_ite_chipinit(device_t dev); 56static int ata_ite_ch_attach(device_t dev); 57static int ata_ite_821x_setmode(device_t dev, int target, int mode); 58static int ata_ite_8213_setmode(device_t dev, int target, int mode); 59 60 61/* 62 * Integrated Technology Express Inc. (ITE) chipset support functions 63 */ 64static int 65ata_ite_probe(device_t dev) 66{ 67 struct ata_pci_controller *ctlr = device_get_softc(dev); 68 static struct ata_chip_id ids[] = 69 {{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" }, 70 { ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 71 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 72 { 0, 0, 0, 0, 0, 0}}; 73 74 if (pci_get_vendor(dev) != ATA_ITE_ID) 75 return ENXIO; 76 77 if (!(ctlr->chip = ata_match_chip(dev, ids))) 78 return ENXIO; 79 80 ata_set_desc(dev); 81 ctlr->chipinit = ata_ite_chipinit; 82 return (BUS_PROBE_DEFAULT); 83} 84 85static int 86ata_ite_chipinit(device_t dev) 87{ 88 struct ata_pci_controller *ctlr = device_get_softc(dev); 89 90 if (ata_setup_interrupt(dev, ata_generic_intr)) 91 return ENXIO; 92 93 if (ctlr->chip->chipid == ATA_IT8213F) { 94 /* the ITE 8213F only has one channel */ 95 ctlr->channels = 1; 96 97 ctlr->setmode = ata_ite_8213_setmode; 98 } 99 else { 100 /* set PCI mode and 66Mhz reference clock */ 101 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 102 103 /* set default active & recover timings */ 104 pci_write_config(dev, 0x54, 0x31, 1); 105 pci_write_config(dev, 0x56, 0x31, 1); 106 107 ctlr->setmode = ata_ite_821x_setmode; 108 } 109 ctlr->ch_attach = ata_ite_ch_attach; 110 return 0; 111} 112 113static int 114ata_ite_ch_attach(device_t dev) 115{ 116 struct ata_channel *ch = device_get_softc(dev); 117 int error; 118 119 error = ata_pci_ch_attach(dev); 120 ch->flags |= ATA_CHECKS_CABLE; 121 return (error); 122} 123 124static int 125ata_ite_821x_setmode(device_t dev, int target, int mode) 126{ 127 device_t parent = device_get_parent(dev); 128 struct ata_pci_controller *ctlr = device_get_softc(parent); 129 struct ata_channel *ch = device_get_softc(dev); 130 int devno = (ch->unit << 1) + target; 131 int piomode; 132 u_int8_t udmatiming[] = 133 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 134 u_int8_t chtiming[] = 135 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 136 137 mode = min(mode, ctlr->chip->max_dma); 138 /* check the CBLID bits for 80 conductor cable detection */ 139 if (mode > ATA_UDMA2 && (pci_read_config(parent, 0x40, 2) & 140 (ch->unit ? (1<<3) : (1<<2)))) { 141 ata_print_cable(dev, "controller"); 142 mode = ATA_UDMA2; 143 } 144 if (mode >= ATA_UDMA0) { 145 /* enable UDMA mode */ 146 pci_write_config(parent, 0x50, 147 pci_read_config(parent, 0x50, 1) & 148 ~(1 << (devno + 3)), 1); 149 /* set UDMA timing */ 150 pci_write_config(parent, 151 0x56 + (ch->unit << 2) + target, 152 udmatiming[mode & ATA_MODE_MASK], 1); 153 piomode = ATA_PIO4; 154 } else { 155 /* disable UDMA mode */ 156 pci_write_config(parent, 0x50, 157 pci_read_config(parent, 0x50, 1) | 158 (1 << (devno + 3)), 1); 159 piomode = mode; 160 } 161 /* set active and recover timing (shared between master & slave) */ 162 if (pci_read_config(parent, 0x54 + (ch->unit << 2), 1) < 163 chtiming[ata_mode2idx(piomode)]) 164 pci_write_config(parent, 0x54 + (ch->unit << 2), 165 chtiming[ata_mode2idx(piomode)], 1); 166 return (mode); 167} 168 169static int 170ata_ite_8213_setmode(device_t dev, int target, int mode) 171{ 172 device_t parent = device_get_parent(dev); 173 struct ata_pci_controller *ctlr = device_get_softc(parent); 174 int piomode; 175 u_int16_t reg40 = pci_read_config(parent, 0x40, 2); 176 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 177 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 178 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 179 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 180 u_int16_t mask40 = 0, new40 = 0; 181 u_int8_t mask44 = 0, new44 = 0; 182 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 183 u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 184 185 mode = min(mode, ctlr->chip->max_dma); 186 187 if (mode > ATA_UDMA2 && !(reg54 & (0x10 << target))) { 188 ata_print_cable(dev, "controller"); 189 mode = ATA_UDMA2; 190 } 191 /* Enable/disable UDMA and set timings. */ 192 if (mode >= ATA_UDMA0) { 193 pci_write_config(parent, 0x48, reg48 | (0x0001 << target), 2); 194 pci_write_config(parent, 0x4a, 195 (reg4a & ~(0x3 << (target << 2))) | 196 (utimings[mode & ATA_MODE_MASK] << (target<<2)), 2); 197 piomode = ATA_PIO4; 198 } else { 199 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << target), 2); 200 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (target << 2))),2); 201 piomode = mode; 202 } 203 /* Set UDMA reference clock (33/66/133MHz). */ 204 reg54 &= ~(0x1001 << target); 205 if (mode >= ATA_UDMA5) 206 reg54 |= (0x1000 << target); 207 else if (mode >= ATA_UDMA3) 208 reg54 |= (0x1 << target); 209 pci_write_config(parent, 0x54, reg54, 2); 210 /* Allow PIO/WDMA timing controls. */ 211 reg40 &= 0xff00; 212 reg40 |= 0x4033; 213 /* Set PIO/WDMA timings. */ 214 if (target == 0) { 215 reg40 |= (ata_atapi(dev) ? 0x04 : 0x00); 216 mask40 = 0x3300; 217 new40 = timings[ata_mode2idx(piomode)] << 8; 218 } 219 else { 220 reg40 |= (ata_atapi(dev) ? 0x40 : 0x00); 221 mask44 = 0x0f; 222 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 223 (timings[ata_mode2idx(piomode)] & 0x03); 224 } 225 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 226 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 227 return (mode); 228} 229 230ATA_DECLARE_DRIVER(ata_ite); 231