aic7xxx.reg revision 65953
1/* 2 * Aic7xxx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2000 Justin Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id$ 32 * 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.reg 65953 2000-09-16 21:55:31Z gibbs $ 34 */ 35 36/* 37 * This file is processed by the aic7xxx_asm utility for use in assembling 38 * firmware for the aic7xxx family of SCSI host adapters as well as to generate 39 * a C header file for use in the kernel portion of the Aic7xxx driver. 40 * 41 * All page numbers refer to the Adaptec AIC-7770 Data Book available from 42 * Adaptec's Technical Documents Department 1-800-934-2766 43 */ 44 45/* 46 * SCSI Sequence Control (p. 3-11). 47 * Each bit, when set starts a specific SCSI sequence on the bus 48 */ 49register SCSISEQ { 50 address 0x000 51 access_mode RW 52 bit TEMODE 0x80 53 bit ENSELO 0x40 54 bit ENSELI 0x20 55 bit ENRSELI 0x10 56 bit ENAUTOATNO 0x08 57 bit ENAUTOATNI 0x04 58 bit ENAUTOATNP 0x02 59 bit SCSIRSTO 0x01 60} 61 62/* 63 * SCSI Transfer Control 0 Register (pp. 3-13). 64 * Controls the SCSI module data path. 65 */ 66register SXFRCTL0 { 67 address 0x001 68 access_mode RW 69 bit DFON 0x80 70 bit DFPEXP 0x40 71 bit FAST20 0x20 72 bit CLRSTCNT 0x10 73 bit SPIOEN 0x08 74 bit SCAMEN 0x04 75 bit CLRCHN 0x02 76} 77 78/* 79 * SCSI Transfer Control 1 Register (pp. 3-14,15). 80 * Controls the SCSI module data path. 81 */ 82register SXFRCTL1 { 83 address 0x002 84 access_mode RW 85 bit BITBUCKET 0x80 86 bit SWRAPEN 0x40 87 bit ENSPCHK 0x20 88 mask STIMESEL 0x18 89 bit ENSTIMER 0x04 90 bit ACTNEGEN 0x02 91 bit STPWEN 0x01 /* Powered Termination */ 92} 93 94/* 95 * SCSI Control Signal Read Register (p. 3-15). 96 * Reads the actual state of the SCSI bus pins 97 */ 98register SCSISIGI { 99 address 0x003 100 access_mode RO 101 bit CDI 0x80 102 bit IOI 0x40 103 bit MSGI 0x20 104 bit ATNI 0x10 105 bit SELI 0x08 106 bit BSYI 0x04 107 bit REQI 0x02 108 bit ACKI 0x01 109/* 110 * Possible phases in SCSISIGI 111 */ 112 mask PHASE_MASK CDI|IOI|MSGI 113 mask P_DATAOUT 0x00 114 mask P_DATAIN IOI 115 mask P_DATAOUT_DT P_DATAOUT|MSGI 116 mask P_DATAIN_DT P_DATAIN|MSGI 117 mask P_COMMAND CDI 118 mask P_MESGOUT CDI|MSGI 119 mask P_STATUS CDI|IOI 120 mask P_MESGIN CDI|IOI|MSGI 121} 122 123/* 124 * SCSI Control Signal Write Register (p. 3-16). 125 * Writing to this register modifies the control signals on the bus. Only 126 * those signals that are allowed in the current mode (Initiator/Target) are 127 * asserted. 128 */ 129register SCSISIGO { 130 address 0x003 131 access_mode WO 132 bit CDO 0x80 133 bit IOO 0x40 134 bit MSGO 0x20 135 bit ATNO 0x10 136 bit SELO 0x08 137 bit BSYO 0x04 138 bit REQO 0x02 139 bit ACKO 0x01 140/* 141 * Possible phases to write into SCSISIG0 142 */ 143 mask PHASE_MASK CDI|IOI|MSGI 144 mask P_DATAOUT 0x00 145 mask P_DATAIN IOI 146 mask P_COMMAND CDI 147 mask P_MESGOUT CDI|MSGI 148 mask P_STATUS CDI|IOI 149 mask P_MESGIN CDI|IOI|MSGI 150} 151 152/* 153 * SCSI Rate Control (p. 3-17). 154 * Contents of this register determine the Synchronous SCSI data transfer 155 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the 156 * SOFS (3:0) bits disables synchronous data transfers. Any offset value 157 * greater than 0 enables synchronous transfers. 158 */ 159register SCSIRATE { 160 address 0x004 161 access_mode RW 162 bit WIDEXFER 0x80 /* Wide transfer control */ 163 bit ENABLE_CRC 0x40 /* CRC for D-Phases */ 164 bit SINGLE_EDGE 0x10 /* Disable DT Transfers */ 165 mask SXFR 0x70 /* Sync transfer rate */ 166 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */ 167 mask SOFS 0x0f /* Sync offset */ 168} 169 170/* 171 * SCSI ID (p. 3-18). 172 * Contains the ID of the board and the current target on the 173 * selected channel. 174 */ 175register SCSIID { 176 address 0x005 177 access_mode RW 178 mask TID 0xf0 /* Target ID mask */ 179 mask TWIN_TID 0x70 180 bit TWIN_CHNLB 0x80 181 mask OID 0x0f /* Our ID mask */ 182 /* 183 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book) 184 * The aic7890/91 allow an offset of up to 127 transfers in both wide 185 * and narrow mode. 186 */ 187 alias SCSIOFFSET 188 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */ 189} 190 191/* 192 * SCSI Latched Data (p. 3-19). 193 * Read/Write latches used to transfer data on the SCSI bus during 194 * Automatic or Manual PIO mode. SCSIDATH can be used for the 195 * upper byte of a 16bit wide asynchronouse data phase transfer. 196 */ 197register SCSIDATL { 198 address 0x006 199 access_mode RW 200} 201 202register SCSIDATH { 203 address 0x007 204 access_mode RW 205} 206 207/* 208 * SCSI Transfer Count (pp. 3-19,20) 209 * These registers count down the number of bytes transferred 210 * across the SCSI bus. The counter is decremented only once 211 * the data has been safely transferred. SDONE in SSTAT0 is 212 * set when STCNT goes to 0 213 */ 214register STCNT { 215 address 0x008 216 size 3 217 access_mode RW 218} 219 220/* ALT_MODE register on Ultra160 chips */ 221register OPTIONMODE { 222 address 0x008 223 access_mode RW 224 bit AUTORATEEN 0x80 225 bit AUTOACKEN 0x40 226 bit ATNMGMNTEN 0x20 227 bit BUSFREEREV 0x10 228 bit EXPPHASEDIS 0x08 229 bit SCSIDATL_IMGEN 0x04 230 bit AUTO_MSGOUT_DE 0x02 231 bit DIS_MSGIN_DUALEDGE 0x01 232 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE 233} 234 235/* ALT_MODE register on Ultra160 chips */ 236register TARGCRCCNT { 237 address 0x00a 238 size 2 239 access_mode RW 240} 241 242/* 243 * Clear SCSI Interrupt 0 (p. 3-20) 244 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 245 */ 246register CLRSINT0 { 247 address 0x00b 248 access_mode WO 249 bit CLRSELDO 0x40 250 bit CLRSELDI 0x20 251 bit CLRSELINGO 0x10 252 bit CLRSWRAP 0x08 253 bit CLRSPIORDY 0x02 254} 255 256/* 257 * SCSI Status 0 (p. 3-21) 258 * Contains one set of SCSI Interrupt codes 259 * These are most likely of interest to the sequencer 260 */ 261register SSTAT0 { 262 address 0x00b 263 access_mode RO 264 bit TARGET 0x80 /* Board acting as target */ 265 bit SELDO 0x40 /* Selection Done */ 266 bit SELDI 0x20 /* Board has been selected */ 267 bit SELINGO 0x10 /* Selection In Progress */ 268 bit SWRAP 0x08 /* 24bit counter wrap */ 269 bit IOERR 0x08 /* LVD Tranceiver mode changed */ 270 bit SDONE 0x04 /* STCNT = 0x000000 */ 271 bit SPIORDY 0x02 /* SCSI PIO Ready */ 272 bit DMADONE 0x01 /* DMA transfer completed */ 273} 274 275/* 276 * Clear SCSI Interrupt 1 (p. 3-23) 277 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 278 */ 279register CLRSINT1 { 280 address 0x00c 281 access_mode WO 282 bit CLRSELTIMEO 0x80 283 bit CLRATNO 0x40 284 bit CLRSCSIRSTI 0x20 285 bit CLRBUSFREE 0x08 286 bit CLRSCSIPERR 0x04 287 bit CLRPHASECHG 0x02 288 bit CLRREQINIT 0x01 289} 290 291/* 292 * SCSI Status 1 (p. 3-24) 293 */ 294register SSTAT1 { 295 address 0x00c 296 access_mode RO 297 bit SELTO 0x80 298 bit ATNTARG 0x40 299 bit SCSIRSTI 0x20 300 bit PHASEMIS 0x10 301 bit BUSFREE 0x08 302 bit SCSIPERR 0x04 303 bit PHASECHG 0x02 304 bit REQINIT 0x01 305} 306 307/* 308 * SCSI Status 2 (pp. 3-25,26) 309 */ 310register SSTAT2 { 311 address 0x00d 312 access_mode RO 313 bit OVERRUN 0x80 314 bit SHVALID 0x40 /* Shaddow Layer non-zero */ 315 bit EXP_ACTIVE 0x10 /* SCSI Expander Active */ 316 bit CRCVALERR 0x08 /* CRC doesn't match (U3 only) */ 317 bit CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */ 318 bit CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */ 319 bit DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */ 320 mask SFCNT 0x1f 321} 322 323/* 324 * SCSI Status 3 (p. 3-26) 325 */ 326register SSTAT3 { 327 address 0x00e 328 access_mode RO 329 mask SCSICNT 0xf0 330 mask OFFCNT 0x0f 331} 332 333/* 334 * SCSI ID for the aic7890/91 chips 335 */ 336register SCSIID_ULTRA2 { 337 address 0x00f 338 access_mode RW 339 mask TID 0xf0 /* Target ID mask */ 340 mask OID 0x0f /* Our ID mask */ 341} 342 343/* 344 * SCSI Interrupt Mode 1 (p. 3-28) 345 * Setting any bit will enable the corresponding function 346 * in SIMODE0 to interrupt via the IRQ pin. 347 */ 348register SIMODE0 { 349 address 0x010 350 access_mode RW 351 bit ENSELDO 0x40 352 bit ENSELDI 0x20 353 bit ENSELINGO 0x10 354 bit ENSWRAP 0x08 355 bit ENIOERR 0x08 /* LVD Tranceiver mode changes */ 356 bit ENSDONE 0x04 357 bit ENSPIORDY 0x02 358 bit ENDMADONE 0x01 359} 360 361/* 362 * SCSI Interrupt Mode 1 (pp. 3-28,29) 363 * Setting any bit will enable the corresponding function 364 * in SIMODE1 to interrupt via the IRQ pin. 365 */ 366register SIMODE1 { 367 address 0x011 368 access_mode RW 369 bit ENSELTIMO 0x80 370 bit ENATNTARG 0x40 371 bit ENSCSIRST 0x20 372 bit ENPHASEMIS 0x10 373 bit ENBUSFREE 0x08 374 bit ENSCSIPERR 0x04 375 bit ENPHASECHG 0x02 376 bit ENREQINIT 0x01 377} 378 379/* 380 * SCSI Data Bus (High) (p. 3-29) 381 * This register reads data on the SCSI Data bus directly. 382 */ 383register SCSIBUSL { 384 address 0x012 385 access_mode RO 386} 387 388register SCSIBUSH { 389 address 0x013 390 access_mode RO 391} 392 393/* 394 * SCSI/Host Address (p. 3-30) 395 * These registers hold the host address for the byte about to be 396 * transferred on the SCSI bus. They are counted up in the same 397 * manner as STCNT is counted down. SHADDR should always be used 398 * to determine the address of the last byte transferred since HADDR 399 * can be skewed by write ahead. 400 */ 401register SHADDR { 402 address 0x014 403 size 4 404 access_mode RO 405} 406 407/* 408 * Selection Timeout Timer (p. 3-30) 409 */ 410register SELTIMER { 411 address 0x018 412 access_mode RW 413 bit STAGE6 0x20 414 bit STAGE5 0x10 415 bit STAGE4 0x08 416 bit STAGE3 0x04 417 bit STAGE2 0x02 418 bit STAGE1 0x01 419 alias TARGIDIN 420} 421 422/* 423 * Selection/Reselection ID (p. 3-31) 424 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 425 * device did not set its own ID. 426 */ 427register SELID { 428 address 0x019 429 access_mode RW 430 mask SELID_MASK 0xf0 431 bit ONEBIT 0x08 432} 433 434register SCAMCTL { 435 address 0x01a 436 access_mode RW 437 bit ENSCAMSELO 0x80 438 bit CLRSCAMSELID 0x40 439 bit ALTSTIM 0x20 440 bit DFLTTID 0x10 441 mask SCAMLVL 0x03 442} 443 444/* 445 * Target Mode Selecting in ID bitmask (aic7890/91/96/97) 446 */ 447register TARGID { 448 address 0x01b 449 size 2 450 access_mode RW 451} 452 453/* 454 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book) 455 * Indicates if external logic has been attached to the chip to 456 * perform the tasks of accessing a serial eeprom, testing termination 457 * strength, and performing cable detection. On the aic7860, most of 458 * these features are handled on chip, but on the aic7855 an attached 459 * aic3800 does the grunt work. 460 */ 461register SPIOCAP { 462 address 0x01b 463 access_mode RW 464 bit SOFT1 0x80 465 bit SOFT0 0x40 466 bit SOFTCMDEN 0x20 467 bit HAS_BRDCTL 0x10 /* External Board control */ 468 bit SEEPROM 0x08 /* External serial eeprom logic */ 469 bit EEPROM 0x04 /* Writable external BIOS ROM */ 470 bit ROM 0x02 /* Logic for accessing external ROM */ 471 bit SSPIOCPS 0x01 /* Termination and cable detection */ 472} 473 474register BRDCTL { 475 address 0x01d 476 bit BRDDAT7 0x80 477 bit BRDDAT6 0x40 478 bit BRDDAT5 0x20 479 bit BRDSTB 0x10 480 bit BRDCS 0x08 481 bit BRDRW 0x04 482 bit BRDCTL1 0x02 483 bit BRDCTL0 0x01 484 /* 7890 Definitions */ 485 bit BRDDAT4 0x10 486 bit BRDDAT3 0x08 487 bit BRDDAT2 0x04 488 bit BRDRW_ULTRA2 0x02 489 bit BRDSTB_ULTRA2 0x01 490} 491 492/* 493 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 494 * Controls the reading and writing of an external serial 1-bit 495 * EEPROM Device. In order to access the serial EEPROM, you must 496 * first set the SEEMS bit that generates a request to the memory 497 * port for access to the serial EEPROM device. When the memory 498 * port is not busy servicing another request, it reconfigures 499 * to allow access to the serial EEPROM. When this happens, SEERDY 500 * gets set high to verify that the memory port access has been 501 * granted. 502 * 503 * After successful arbitration for the memory port, the SEECS bit of 504 * the SEECTL register is connected to the chip select. The SEECK, 505 * SEEDO, and SEEDI are connected to the clock, data out, and data in 506 * lines respectively. The SEERDY bit of SEECTL is useful in that it 507 * gives us an 800 nsec timer. After a write to the SEECTL register, 508 * the SEERDY goes high 800 nsec later. The one exception to this is 509 * when we first request access to the memory port. The SEERDY goes 510 * high to signify that access has been granted and, for this case, has 511 * no implied timing. 512 * 513 * See 93cx6.c for detailed information on the protocol necessary to 514 * read the serial EEPROM. 515 */ 516register SEECTL { 517 address 0x01e 518 bit EXTARBACK 0x80 519 bit EXTARBREQ 0x40 520 bit SEEMS 0x20 521 bit SEERDY 0x10 522 bit SEECS 0x08 523 bit SEECK 0x04 524 bit SEEDO 0x02 525 bit SEEDI 0x01 526} 527/* 528 * SCSI Block Control (p. 3-32) 529 * Controls Bus type and channel selection. In a twin channel configuration 530 * addresses 0x00-0x1e are gated to the appropriate channel based on this 531 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 532 * on a wide bus. 533 */ 534register SBLKCTL { 535 address 0x01f 536 access_mode RW 537 bit DIAGLEDEN 0x80 /* Aic78X0 only */ 538 bit DIAGLEDON 0x40 /* Aic78X0 only */ 539 bit AUTOFLUSHDIS 0x20 540 bit SELBUSB 0x08 541 bit ENAB40 0x08 /* LVD transceiver active */ 542 bit ENAB20 0x04 /* SE/HVD transceiver active */ 543 bit SELWIDE 0x02 544 bit XCVR 0x01 /* External transceiver active */ 545} 546 547/* 548 * Sequencer Control (p. 3-33) 549 * Error detection mode and speed configuration 550 */ 551register SEQCTL { 552 address 0x060 553 access_mode RW 554 bit PERRORDIS 0x80 555 bit PAUSEDIS 0x40 556 bit FAILDIS 0x20 557 bit FASTMODE 0x10 558 bit BRKADRINTEN 0x08 559 bit STEP 0x04 560 bit SEQRESET 0x02 561 bit LOADRAM 0x01 562} 563 564/* 565 * Sequencer RAM Data (p. 3-34) 566 * Single byte window into the Scratch Ram area starting at the address 567 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 568 * four bytes in succession. The SEQADDRs will increment after the most 569 * significant byte is written 570 */ 571register SEQRAM { 572 address 0x061 573 access_mode RW 574} 575 576/* 577 * Sequencer Address Registers (p. 3-35) 578 * Only the first bit of SEQADDR1 holds addressing information 579 */ 580register SEQADDR0 { 581 address 0x062 582 access_mode RW 583} 584 585register SEQADDR1 { 586 address 0x063 587 access_mode RW 588 mask SEQADDR1_MASK 0x01 589} 590 591/* 592 * Accumulator 593 * We cheat by passing arguments in the Accumulator up to the kernel driver 594 */ 595register ACCUM { 596 address 0x064 597 access_mode RW 598 accumulator 599} 600 601register SINDEX { 602 address 0x065 603 access_mode RW 604 sindex 605} 606 607register DINDEX { 608 address 0x066 609 access_mode RW 610} 611 612register ALLONES { 613 address 0x069 614 access_mode RO 615 allones 616} 617 618register ALLZEROS { 619 address 0x06a 620 access_mode RO 621 allzeros 622} 623 624register NONE { 625 address 0x06a 626 access_mode WO 627 none 628} 629 630register FLAGS { 631 address 0x06b 632 access_mode RO 633 bit ZERO 0x02 634 bit CARRY 0x01 635} 636 637register SINDIR { 638 address 0x06c 639 access_mode RO 640} 641 642register DINDIR { 643 address 0x06d 644 access_mode WO 645} 646 647register FUNCTION1 { 648 address 0x06e 649 access_mode RW 650} 651 652register STACK { 653 address 0x06f 654 access_mode RO 655} 656 657/* 658 * Board Control (p. 3-43) 659 */ 660register BCTL { 661 address 0x084 662 access_mode RW 663 bit ACE 0x08 664 bit ENABLE 0x01 665} 666 667/* 668 * On the aic78X0 chips, Board Control is replaced by the DSCommand 669 * register (p. 4-64) 670 */ 671register DSCOMMAND0 { 672 address 0x084 673 access_mode RW 674 bit CACHETHEN 0x80 /* Cache Threshold enable */ 675 bit DPARCKEN 0x40 /* Data Parity Check Enable */ 676 bit MPARCKEN 0x20 /* Memory Parity Check Enable */ 677 bit EXTREQLCK 0x10 /* External Request Lock */ 678 /* aic7890/91/96/97 only */ 679 bit INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */ 680 bit RAMPS 0x04 /* External SCB RAM Present */ 681 bit USCBSIZE32 0x02 /* Use 32byte SCB Page Size */ 682 bit CIOPARCKEN 0x01 /* Internal bus parity error enable */ 683} 684 685/* 686 * Bus On/Off Time (p. 3-44) 687 */ 688register BUSTIME { 689 address 0x085 690 access_mode RW 691 mask BOFF 0xf0 692 mask BON 0x0f 693} 694 695/* 696 * Bus Speed (p. 3-45) aic7770 only 697 */ 698register BUSSPD { 699 address 0x086 700 access_mode RW 701 mask DFTHRSH 0xc0 702 mask STBOFF 0x38 703 mask STBON 0x07 704 mask DFTHRSH_100 0xc0 705} 706 707/* aic7850/55/60/70/80/95 only */ 708register DSPCISTATUS { 709 address 0x086 710 mask DFTHRSH_100 0xc0 711} 712 713/* aic7890/91/96/97 only */ 714register HS_MAILBOX { 715 address 0x086 716 mask HOST_MAILBOX 0xF0 717 mask SEQ_MAILBOX 0x0F 718 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 719} 720 721const HOST_MAILBOX_SHIFT 4 722const SEQ_MAILBOX_SHIFT 0 723 724/* 725 * Host Control (p. 3-47) R/W 726 * Overall host control of the device. 727 */ 728register HCNTRL { 729 address 0x087 730 access_mode RW 731 bit POWRDN 0x40 732 bit SWINT 0x10 733 bit IRQMS 0x08 734 bit PAUSE 0x04 735 bit INTEN 0x02 736 bit CHIPRST 0x01 737 bit CHIPRSTACK 0x01 738} 739 740/* 741 * Host Address (p. 3-48) 742 * This register contains the address of the byte about 743 * to be transferred across the host bus. 744 */ 745register HADDR { 746 address 0x088 747 size 4 748 access_mode RW 749} 750 751register HCNT { 752 address 0x08c 753 size 3 754 access_mode RW 755} 756 757/* 758 * SCB Pointer (p. 3-49) 759 * Gate one of the SCBs into the SCBARRAY window. 760 */ 761register SCBPTR { 762 address 0x090 763 access_mode RW 764} 765 766/* 767 * Interrupt Status (p. 3-50) 768 * Status for system interrupts 769 */ 770register INTSTAT { 771 address 0x091 772 access_mode RW 773 bit BRKADRINT 0x08 774 bit SCSIINT 0x04 775 bit CMDCMPLT 0x02 776 bit SEQINT 0x01 777 mask BAD_PHASE SEQINT /* unknown scsi bus phase */ 778 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ 779 mask NO_IDENT 0x20|SEQINT /* no IDENTIFY after reconnect*/ 780 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ 781 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */ 782 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */ 783 mask RESIDUAL 0x80|SEQINT /* Residual byte count != 0 */ 784 mask TRACEPOINT2 0x90|SEQINT 785 mask HOST_MSG_LOOP 0xa0|SEQINT /* 786 * The bus is ready for the 787 * host to perform another 788 * message transaction. This 789 * mechanism is used for things 790 * like sync/wide negotiation 791 * that require a kernel based 792 * message state engine. 793 */ 794 mask PERR_DETECTED 0xb0|SEQINT /* 795 * Either the phase_lock 796 * or inb_next routine has 797 * noticed a parity error. 798 */ 799 mask TRACEPOINT 0xd0|SEQINT 800 mask DATA_OVERRUN 0xf0|SEQINT /* 801 * Target attempted to write 802 * beyond the bounds of its 803 * command. 804 */ 805 806 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */ 807 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT) 808} 809 810/* 811 * Hard Error (p. 3-53) 812 * Reporting of catastrophic errors. You usually cannot recover from 813 * these without a full board reset. 814 */ 815register ERROR { 816 address 0x092 817 access_mode RO 818 bit CIOPARERR 0x80 /* Ultra2 only */ 819 bit PCIERRSTAT 0x40 /* PCI only */ 820 bit MPARERR 0x20 /* PCI only */ 821 bit DPARERR 0x10 /* PCI only */ 822 bit SQPARERR 0x08 823 bit ILLOPCODE 0x04 824 bit ILLSADDR 0x02 825 bit ILLHADDR 0x01 826} 827 828/* 829 * Clear Interrupt Status (p. 3-52) 830 */ 831register CLRINT { 832 address 0x092 833 access_mode WO 834 bit CLRPARERR 0x10 /* PCI only */ 835 bit CLRBRKADRINT 0x08 836 bit CLRSCSIINT 0x04 837 bit CLRCMDINT 0x02 838 bit CLRSEQINT 0x01 839} 840 841register DFCNTRL { 842 address 0x093 843 access_mode RW 844 bit PRELOADEN 0x80 /* aic7890 only */ 845 bit WIDEODD 0x40 846 bit SCSIEN 0x20 847 bit SDMAEN 0x10 848 bit SDMAENACK 0x10 849 bit HDMAEN 0x08 850 bit HDMAENACK 0x08 851 bit DIRECTION 0x04 852 bit FIFOFLUSH 0x02 853 bit FIFORESET 0x01 854} 855 856register DFSTATUS { 857 address 0x094 858 access_mode RO 859 bit PRELOAD_AVAIL 0x80 860 bit DWORDEMP 0x20 861 bit MREQPEND 0x10 862 bit HDONE 0x08 863 bit DFTHRESH 0x04 864 bit FIFOFULL 0x02 865 bit FIFOEMP 0x01 866} 867 868register DFWADDR { 869 address 0x95 870 access_mode RW 871} 872 873register DFRADDR { 874 address 0x97 875 access_mode RW 876} 877 878register DFDAT { 879 address 0x099 880 access_mode RW 881} 882 883/* 884 * SCB Auto Increment (p. 3-59) 885 * Byte offset into the SCB Array and an optional bit to allow auto 886 * incrementing of the address during download and upload operations 887 */ 888register SCBCNT { 889 address 0x09a 890 access_mode RW 891 bit SCBAUTO 0x80 892 mask SCBCNT_MASK 0x1f 893} 894 895/* 896 * Queue In FIFO (p. 3-60) 897 * Input queue for queued SCBs (commands that the seqencer has yet to start) 898 */ 899register QINFIFO { 900 address 0x09b 901 access_mode RW 902} 903 904/* 905 * Queue In Count (p. 3-60) 906 * Number of queued SCBs 907 */ 908register QINCNT { 909 address 0x09c 910 access_mode RO 911} 912 913/* 914 * Queue Out FIFO (p. 3-61) 915 * Queue of SCBs that have completed and await the host 916 */ 917register QOUTFIFO { 918 address 0x09d 919 access_mode WO 920} 921 922register CRCCONTROL1 { 923 address 0x09d 924 access_mode RW 925 bit CRCONSEEN 0x80 926 bit CRCVALCHKEN 0x40 927 bit CRCENDCHKEN 0x20 928 bit CRCREQCHKEN 0x10 929 bit TARGCRCENDEN 0x08 930 bit TARGCRCCNTEN 0x04 931} 932 933 934/* 935 * Queue Out Count (p. 3-61) 936 * Number of queued SCBs in the Out FIFO 937 */ 938register QOUTCNT { 939 address 0x09e 940 access_mode RO 941} 942 943register SCSIPHASE { 944 address 0x09e 945 access_mode RO 946 bit STATUS_PHASE 0x20 947 bit COMMAND_PHASE 0x10 948 bit MSG_IN_PHASE 0x08 949 bit MSG_OUT_PHASE 0x04 950 bit DATA_IN_PHASE 0x02 951 bit DATA_OUT_PHASE 0x01 952} 953 954/* 955 * Special Function 956 */ 957register SFUNCT { 958 address 0x09f 959 access_mode RW 960 bit ALT_MODE 0x80 961} 962 963/* 964 * SCB Definition (p. 5-4) 965 */ 966scb { 967 address 0x0a0 968 SCB_CDB_PTR { 969 size 4 970 alias SCB_RESIDUAL_DATACNT 971 alias SCB_CDB_STORE 972 alias SCB_TARGET_INFO 973 } 974 SCB_RESIDUAL_SGPTR { 975 size 4 976 } 977 SCB_SCSI_STATUS { 978 size 1 979 } 980 SCB_CDB_STORE_PAD { 981 size 3 982 } 983 SCB_DATAPTR { 984 size 4 985 } 986 SCB_DATACNT { 987 /* 988 * The last byte is really the high address bits for 989 * the data address. 990 */ 991 size 4 992 bit SG_LAST_SEG 0x80 /* In the fourth byte */ 993 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 994 } 995 SCB_SGPTR { 996 size 4 997 bit SG_RESID_VALID 0x04 /* In the first byte */ 998 bit SG_FULL_RESID 0x02 /* In the first byte */ 999 bit SG_LIST_NULL 0x01 /* In the first byte */ 1000 } 1001 SCB_CONTROL { 1002 size 1 1003 bit TARGET_SCB 0x80 1004 bit DISCENB 0x40 1005 bit TAG_ENB 0x20 1006 bit MK_MESSAGE 0x10 1007 bit ULTRAENB 0x08 1008 bit DISCONNECTED 0x04 1009 mask SCB_TAG_TYPE 0x03 1010 } 1011 SCB_SCSIID { 1012 size 1 1013 bit TWIN_CHNLB 0x80 1014 mask TWIN_TID 0x70 1015 mask TID 0xf0 1016 mask OID 0x0f 1017 } 1018 SCB_LUN { 1019 mask LID 0xff 1020 size 1 1021 } 1022 SCB_TAG { 1023 size 1 1024 } 1025 SCB_CDB_LEN { 1026 size 1 1027 } 1028 SCB_SCSIRATE { 1029 size 1 1030 } 1031 SCB_SCSIOFFSET { 1032 size 1 1033 } 1034 SCB_NEXT { 1035 size 1 1036 } 1037 SCB_64_SPARE { 1038 size 16 1039 } 1040 SCB_64_BTT { 1041 size 16 1042 } 1043} 1044 1045const SCB_UPLOAD_SIZE 32 1046const SCB_DOWNLOAD_SIZE 32 1047const SCB_DOWNLOAD_SIZE_64 48 1048 1049const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */ 1050 1051/* --------------------- AHA-2840-only definitions -------------------- */ 1052 1053register SEECTL_2840 { 1054 address 0x0c0 1055 access_mode RW 1056 bit CS_2840 0x04 1057 bit CK_2840 0x02 1058 bit DO_2840 0x01 1059} 1060 1061register STATUS_2840 { 1062 address 0x0c1 1063 access_mode RW 1064 bit EEPROM_TF 0x80 1065 mask BIOS_SEL 0x60 1066 mask ADSEL 0x1e 1067 bit DI_2840 0x01 1068} 1069 1070/* --------------------- AIC-7870-only definitions -------------------- */ 1071 1072register CCHADDR { 1073 address 0x0E0 1074 size 8 1075} 1076 1077register CCHCNT { 1078 address 0x0E8 1079} 1080 1081register CCSGRAM { 1082 address 0x0E9 1083} 1084 1085register CCSGADDR { 1086 address 0x0EA 1087} 1088 1089register CCSGCTL { 1090 address 0x0EB 1091 bit CCSGDONE 0x80 1092 bit CCSGEN 0x08 1093 bit SG_FETCH_NEEDED 0x02 /* Bit used for software state */ 1094 bit CCSGRESET 0x01 1095} 1096 1097register CCSCBCNT { 1098 address 0xEF 1099} 1100 1101register CCSCBCTL { 1102 address 0x0EE 1103 bit CCSCBDONE 0x80 1104 bit ARRDONE 0x40 /* SCB Array prefetch done */ 1105 bit CCARREN 0x10 1106 bit CCSCBEN 0x08 1107 bit CCSCBDIR 0x04 1108 bit CCSCBRESET 0x01 1109} 1110 1111register CCSCBADDR { 1112 address 0x0ED 1113} 1114 1115register CCSCBRAM { 1116 address 0xEC 1117} 1118 1119/* 1120 * SCB bank address (7895/7896/97 only) 1121 */ 1122register SCBBADDR { 1123 address 0x0F0 1124 access_mode RW 1125} 1126 1127register CCSCBPTR { 1128 address 0x0F1 1129} 1130 1131register HNSCB_QOFF { 1132 address 0x0F4 1133} 1134 1135register SNSCB_QOFF { 1136 address 0x0F6 1137} 1138 1139register SDSCB_QOFF { 1140 address 0x0F8 1141} 1142 1143register QOFF_CTLSTA { 1144 address 0x0FA 1145 bit SCB_AVAIL 0x40 1146 bit SNSCB_ROLLOVER 0x20 1147 bit SDSCB_ROLLOVER 0x10 1148 mask SCB_QSIZE 0x07 1149 mask SCB_QSIZE_256 0x06 1150} 1151 1152register DFF_THRSH { 1153 address 0x0FB 1154 mask WR_DFTHRSH 0x70 1155 mask RD_DFTHRSH 0x07 1156 mask RD_DFTHRSH_MIN 0x00 1157 mask RD_DFTHRSH_25 0x01 1158 mask RD_DFTHRSH_50 0x02 1159 mask RD_DFTHRSH_63 0x03 1160 mask RD_DFTHRSH_75 0x04 1161 mask RD_DFTHRSH_85 0x05 1162 mask RD_DFTHRSH_90 0x06 1163 mask RD_DFTHRSH_MAX 0x07 1164 mask WR_DFTHRSH_MIN 0x00 1165 mask WR_DFTHRSH_25 0x10 1166 mask WR_DFTHRSH_50 0x20 1167 mask WR_DFTHRSH_63 0x30 1168 mask WR_DFTHRSH_75 0x40 1169 mask WR_DFTHRSH_85 0x50 1170 mask WR_DFTHRSH_90 0x60 1171 mask WR_DFTHRSH_MAX 0x70 1172} 1173 1174register SG_CACHE_PRE { 1175 access_mode WO 1176 address 0x0fc 1177 mask SG_ADDR_MASK 0xf8 1178 bit ODD_SEG 0x04 1179 bit LAST_SEG 0x02 1180 bit LAST_SEG_DONE 0x01 1181} 1182 1183register SG_CACHE_SHADOW { 1184 access_mode RO 1185 address 0x0fc 1186 mask SG_ADDR_MASK 0xf8 1187 bit ODD_SEG 0x04 1188 bit LAST_SEG 0x02 1189 bit LAST_SEG_DONE 0x01 1190} 1191/* ---------------------- Scratch RAM Offsets ------------------------- */ 1192/* These offsets are either to values that are initialized by the board's 1193 * BIOS or are specified by the sequencer code. 1194 * 1195 * The host adapter card (at least the BIOS) uses 20-2f for SCSI 1196 * device information, 32-33 and 5a-5f as well. As it turns out, the 1197 * BIOS trashes 20-2f, writing the synchronous negotiation results 1198 * on top of the BIOS values, so we re-use those for our per-target 1199 * scratchspace (actually a value that can be copied directly into 1200 * SCSIRATE). The kernel driver will enable synchronous negotiation 1201 * for all targets that have a value other than 0 in the lower four 1202 * bits of the target scratch space. This should work regardless of 1203 * whether the bios has been installed. 1204 */ 1205 1206scratch_ram { 1207 address 0x020 1208 1209 /* 1210 * 1 byte per target starting at this address for configuration values 1211 */ 1212 CMDSIZE_TABLE { 1213 alias TARG_SCSIRATE 1214 size 8 1215 } 1216 BUSY_TARGETS { 1217 size 16 1218 } 1219 /* 1220 * Bit vector of targets that have ULTRA enabled as set by the BIOS. 1221 * The Sequencer relies in a per-SCB field to control the disconnect 1222 * priveldge. 1223 */ 1224 ULTRA_ENB { 1225 size 2 1226 /* 1227 * Partial transfer past cacheline end to be 1228 * transferred using an extra S/G. 1229 */ 1230 alias MWI_RESIDUAL 1231 } 1232 /* 1233 * Bit vector of targets that have disconnection disabled as set by 1234 * the BIOS. The Sequencer relies in a per-SCB field to control the 1235 * disconnect priveldge. 1236 */ 1237 DISC_DSB { 1238 size 2 1239 } 1240 /* 1241 * Single byte buffer used to designate the type or message 1242 * to send to a target. 1243 */ 1244 MSG_OUT { 1245 size 1 1246 } 1247 /* Parameters for DMA Logic */ 1248 DMAPARAMS { 1249 size 1 1250 bit PRELOADEN 0x80 1251 bit WIDEODD 0x40 1252 bit SCSIEN 0x20 1253 bit SDMAEN 0x10 1254 bit SDMAENACK 0x10 1255 bit HDMAEN 0x08 1256 bit HDMAENACK 0x08 1257 bit DIRECTION 0x04 1258 bit FIFOFLUSH 0x02 1259 bit FIFORESET 0x01 1260 } 1261 SEQ_FLAGS { 1262 size 1 1263 bit IDENTIFY_SEEN 0x80 1264 bit SCBPTR_VALID 0x40 1265 bit TARGET_CMD_IS_TAGGED 0x40 1266 bit DPHASE 0x20 1267 /* Target flags */ 1268 bit TARG_CMD_PENDING 0x10 1269 bit CMDPHASE_PENDING 0x08 1270 bit DPHASE_PENDING 0x04 1271 bit SPHASE_PENDING 0x02 1272 bit NO_DISCONNECT 0x01 1273 } 1274 /* 1275 * Temporary storage for the 1276 * target/channel/lun of a 1277 * reconnecting target 1278 */ 1279 SAVED_SCSIID { 1280 size 1 1281 } 1282 SAVED_LUN { 1283 size 1 1284 } 1285 /* 1286 * The last bus phase as seen by the sequencer. 1287 */ 1288 LASTPHASE { 1289 size 1 1290 bit CDI 0x80 1291 bit IOI 0x40 1292 bit MSGI 0x20 1293 mask PHASE_MASK CDI|IOI|MSGI 1294 mask P_DATAOUT 0x00 1295 mask P_DATAIN IOI 1296 mask P_COMMAND CDI 1297 mask P_MESGOUT CDI|MSGI 1298 mask P_STATUS CDI|IOI 1299 mask P_MESGIN CDI|IOI|MSGI 1300 mask P_BUSFREE 0x01 1301 } 1302 /* 1303 * head of list of SCBs awaiting 1304 * selection 1305 */ 1306 WAITING_SCBH { 1307 size 1 1308 } 1309 /* 1310 * head of list of SCBs that are 1311 * disconnected. Used for SCB 1312 * paging. 1313 */ 1314 DISCONNECTED_SCBH { 1315 size 1 1316 } 1317 /* 1318 * head of list of SCBs that are 1319 * not in use. Used for SCB paging. 1320 */ 1321 FREE_SCBH { 1322 size 1 1323 } 1324 /* 1325 * Address of the hardware scb array in the host. 1326 */ 1327 HSCB_ADDR { 1328 size 4 1329 } 1330 /* 1331 * Base address of our shared data with the kernel driver in host 1332 * memory. This includes the qinfifo, qoutfifo, and target mode 1333 * incoming command queue. 1334 */ 1335 SHARED_DATA_ADDR { 1336 size 4 1337 } 1338 KERNEL_QINPOS { 1339 size 1 1340 } 1341 QINPOS { 1342 size 1 1343 } 1344 QOUTPOS { 1345 size 1 1346 } 1347 /* 1348 * Kernel and sequencer offsets into the queue of 1349 * incoming target mode command descriptors. The 1350 * queue is full when the KERNEL_TQINPOS == TQINPOS. 1351 */ 1352 KERNEL_TQINPOS { 1353 size 1 1354 } 1355 TQINPOS { 1356 size 1 1357 } 1358 ARG_1 { 1359 size 1 1360 mask SEND_MSG 0x80 1361 mask SEND_SENSE 0x40 1362 mask SEND_REJ 0x20 1363 mask MSGOUT_PHASEMIS 0x10 1364 mask EXIT_MSG_LOOP 0x08 1365 mask CONT_MSG_LOOP 0x04 1366 mask CONT_TARG_SESSION 0x02 1367 alias RETURN_1 1368 } 1369 ARG_2 { 1370 size 1 1371 alias RETURN_2 1372 } 1373 1374 /* 1375 * Snapshot of MSG_OUT taken after each message is sent. 1376 */ 1377 LAST_MSG { 1378 size 1 1379 } 1380 1381 /* 1382 * Interrupt kernel for a message to this target on 1383 * the next transaction. This is usually used for 1384 * negotiation requests. 1385 */ 1386 TARGET_MSG_REQUEST { 1387 size 2 1388 } 1389 1390 /* 1391 * Sequences the kernel driver has okayed for us. This allows 1392 * the driver to do things like prevent initiator or target 1393 * operations. 1394 */ 1395 SCSISEQ_TEMPLATE { 1396 size 1 1397 bit ENSELO 0x40 1398 bit ENSELI 0x20 1399 bit ENRSELI 0x10 1400 bit ENAUTOATNO 0x08 1401 bit ENAUTOATNI 0x04 1402 bit ENAUTOATNP 0x02 1403 } 1404 1405 /* 1406 * Track whether the transfer byte count for 1407 * the current data phase is odd. 1408 */ 1409 DATA_COUNT_ODD { 1410 size 1 1411 } 1412 1413 /* 1414 * The initiator specified tag for this target mode transaction. 1415 */ 1416 INITIATOR_TAG { 1417 size 1 1418 } 1419 1420 /* 1421 * These are reserved registers in the card's scratch ram. Some of 1422 * the values are specified in the AHA2742 technical reference manual 1423 * and are initialized by the BIOS at boot time. 1424 */ 1425 SCSICONF { 1426 address 0x05a 1427 size 1 1428 bit TERM_ENB 0x80 1429 bit RESET_SCSI 0x40 1430 bit ENSPCHK 0x20 1431 mask HSCSIID 0x07 /* our SCSI ID */ 1432 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */ 1433 } 1434 INTDEF { 1435 address 0x05c 1436 size 1 1437 bit EDGE_TRIG 0x80 1438 mask VECTOR 0x0f 1439 } 1440 HOSTCONF { 1441 address 0x05d 1442 size 1 1443 } 1444 HA_274_BIOSCTRL { 1445 address 0x05f 1446 size 1 1447 mask BIOSMODE 0x30 1448 mask BIOSDISABLED 0x30 1449 bit CHANNEL_B_PRIMARY 0x08 1450 } 1451 /* 1452 * Per target SCSI offset values for Ultra2 controllers. 1453 */ 1454 TARG_OFFSET { 1455 address 0x070 1456 size 16 1457 } 1458} 1459 1460const TID_SHIFT 4 1461const SCB_LIST_NULL 0xff 1462const TARGET_CMD_CMPLT 0xfe 1463 1464const CCSGADDR_MAX 0x80 1465const CCSGRAM_MAXSEGS 16 1466 1467/* WDTR Message values */ 1468const BUS_8_BIT 0x00 1469const BUS_16_BIT 0x01 1470const BUS_32_BIT 0x02 1471 1472/* Offset maximums */ 1473const MAX_OFFSET_8BIT 0x0f 1474const MAX_OFFSET_16BIT 0x08 1475const MAX_OFFSET_ULTRA2 0x7f 1476const HOST_MSG 0xff 1477 1478/* Target mode command processing constants */ 1479const CMD_GROUP_CODE_SHIFT 0x05 1480 1481const STATUS_BUSY 0x08 1482const STATUS_QUEUE_FULL 0x28 1483const SCB_TARGET_PHASES 0 1484const SCB_TARGET_DATA_DIR 1 1485const SCB_TARGET_STATUS 2 1486const SCB_INITIATOR_TAG 3 1487const TARGET_DATA_IN 1 1488 1489/* 1490 * Downloaded (kernel inserted) constants 1491 */ 1492/* Offsets into the SCBID array where different data is stored */ 1493const QOUTFIFO_OFFSET download 1494const QINFIFO_OFFSET download 1495const CACHESIZE_MASK download 1496const INVERTED_CACHESIZE_MASK download 1497