aic7xxx.c revision 75048
1/* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: //depot/src/aic7xxx/aic7xxx.c#35 $ 32 * 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.c 75048 2001-04-01 00:00:09Z gibbs $ 34 */ 35 36#ifdef __linux__ 37#include "aic7xxx_linux.h" 38#include "aic7xxx_inline.h" 39#include "aicasm/aicasm_insformat.h" 40#endif 41 42#ifdef __FreeBSD__ 43#include <dev/aic7xxx/aic7xxx_freebsd.h> 44#include <dev/aic7xxx/aic7xxx_inline.h> 45#include <dev/aic7xxx/aicasm/aicasm_insformat.h> 46#endif 47 48/****************************** Softc Data ************************************/ 49struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); 50 51/***************************** Lookup Tables **********************************/ 52char *ahc_chip_names[] = 53{ 54 "NONE", 55 "aic7770", 56 "aic7850", 57 "aic7855", 58 "aic7859", 59 "aic7860", 60 "aic7870", 61 "aic7880", 62 "aic7895", 63 "aic7895C", 64 "aic7890/91", 65 "aic7896/97", 66 "aic7892", 67 "aic7899" 68}; 69static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names); 70 71/* 72 * Hardware error codes. 73 */ 74struct ahc_hard_error_entry { 75 uint8_t errno; 76 char *errmesg; 77}; 78 79static struct ahc_hard_error_entry ahc_hard_errors[] = { 80 { ILLHADDR, "Illegal Host Access" }, 81 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 82 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 83 { SQPARERR, "Sequencer Parity Error" }, 84 { DPARERR, "Data-path Parity Error" }, 85 { MPARERR, "Scratch or SCB Memory Parity Error" }, 86 { PCIERRSTAT, "PCI Error detected" }, 87 { CIOPARERR, "CIOBUS Parity Error" }, 88}; 89static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors); 90 91static struct ahc_phase_table_entry ahc_phase_table[] = 92{ 93 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 94 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 95 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 96 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 97 { P_COMMAND, MSG_NOOP, "in Command phase" }, 98 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 99 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 100 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 101 { P_BUSFREE, MSG_NOOP, "while idle" }, 102 { 0, MSG_NOOP, "in unknown phase" } 103}; 104 105/* 106 * In most cases we only wish to itterate over real phases, so 107 * exclude the last element from the count. 108 */ 109static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1; 110 111/* 112 * Valid SCSIRATE values. (p. 3-17) 113 * Provides a mapping of tranfer periods in ns to the proper value to 114 * stick in the scsixfer reg. 115 */ 116static struct ahc_syncrate ahc_syncrates[] = 117{ 118 /* ultra2 fast/ultra period rate */ 119 { 0x42, 0x000, 9, "80.0" }, 120 { 0x03, 0x000, 10, "40.0" }, 121 { 0x04, 0x000, 11, "33.0" }, 122 { 0x05, 0x100, 12, "20.0" }, 123 { 0x06, 0x110, 15, "16.0" }, 124 { 0x07, 0x120, 18, "13.4" }, 125 { 0x08, 0x000, 25, "10.0" }, 126 { 0x19, 0x010, 31, "8.0" }, 127 { 0x1a, 0x020, 37, "6.67" }, 128 { 0x1b, 0x030, 43, "5.7" }, 129 { 0x1c, 0x040, 50, "5.0" }, 130 { 0x00, 0x050, 56, "4.4" }, 131 { 0x00, 0x060, 62, "4.0" }, 132 { 0x00, 0x070, 68, "3.6" }, 133 { 0x00, 0x000, 0, NULL } 134}; 135 136/* Our Sequencer Program */ 137#include "aic7xxx_seq.h" 138 139/**************************** Function Declarations ***************************/ 140static struct ahc_tmode_tstate* 141 ahc_alloc_tstate(struct ahc_softc *ahc, 142 u_int scsi_id, char channel); 143#ifdef AHC_TARGET_MODE 144static void ahc_free_tstate(struct ahc_softc *ahc, 145 u_int scsi_id, char channel, int force); 146#endif 147static struct ahc_syncrate* 148 ahc_devlimited_syncrate(struct ahc_softc *ahc, 149 struct ahc_initiator_tinfo *, 150 u_int *period, 151 u_int *ppr_options, 152 role_t role); 153static void ahc_update_pending_scbs(struct ahc_softc *ahc); 154static void ahc_fetch_devinfo(struct ahc_softc *ahc, 155 struct ahc_devinfo *devinfo); 156static void ahc_scb_devinfo(struct ahc_softc *ahc, 157 struct ahc_devinfo *devinfo, 158 struct scb *scb); 159static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 160 struct ahc_devinfo *devinfo, 161 struct scb *scb); 162static void ahc_build_transfer_msg(struct ahc_softc *ahc, 163 struct ahc_devinfo *devinfo); 164static void ahc_construct_sdtr(struct ahc_softc *ahc, 165 struct ahc_devinfo *devinfo, 166 u_int period, u_int offset); 167static void ahc_construct_wdtr(struct ahc_softc *ahc, 168 struct ahc_devinfo *devinfo, 169 u_int bus_width); 170static void ahc_construct_ppr(struct ahc_softc *ahc, 171 struct ahc_devinfo *devinfo, 172 u_int period, u_int offset, 173 u_int bus_width, u_int ppr_options); 174static void ahc_clear_msg_state(struct ahc_softc *ahc); 175static void ahc_handle_message_phase(struct ahc_softc *ahc); 176typedef enum { 177 AHCMSG_1B, 178 AHCMSG_2B, 179 AHCMSG_EXT 180} ahc_msgtype; 181static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 182 u_int msgval, int full); 183static int ahc_parse_msg(struct ahc_softc *ahc, 184 struct ahc_devinfo *devinfo); 185static int ahc_handle_msg_reject(struct ahc_softc *ahc, 186 struct ahc_devinfo *devinfo); 187static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 188 struct ahc_devinfo *devinfo); 189static void ahc_handle_devreset(struct ahc_softc *ahc, 190 struct ahc_devinfo *devinfo, 191 cam_status status, char *message, 192 int verbose_level); 193static void ahc_setup_target_msgin(struct ahc_softc *ahc, 194 struct ahc_devinfo *devinfo, 195 struct scb *scb); 196 197static bus_dmamap_callback_t ahc_dmamap_cb; 198static void ahc_build_free_scb_list(struct ahc_softc *ahc); 199static int ahc_init_scbdata(struct ahc_softc *ahc); 200static void ahc_fini_scbdata(struct ahc_softc *ahc); 201static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 202 struct scb *prev_scb, 203 struct scb *scb); 204static int ahc_qinfifo_count(struct ahc_softc *ahc); 205static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 206 u_int prev, u_int scbptr); 207static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 208static u_int ahc_rem_wscb(struct ahc_softc *ahc, 209 u_int scbpos, u_int prev); 210static int ahc_abort_scbs(struct ahc_softc *ahc, int target, 211 char channel, int lun, u_int tag, 212 role_t role, uint32_t status); 213static void ahc_reset_current_bus(struct ahc_softc *ahc); 214static void ahc_calc_residual(struct scb *scb); 215#ifdef AHC_DUMP_SEQ 216static void ahc_dumpseq(struct ahc_softc *ahc); 217#endif 218static void ahc_loadseq(struct ahc_softc *ahc); 219static int ahc_check_patch(struct ahc_softc *ahc, 220 struct patch **start_patch, 221 u_int start_instr, u_int *skip_addr); 222static void ahc_download_instr(struct ahc_softc *ahc, 223 u_int instrptr, uint8_t *dconsts); 224#ifdef AHC_TARGET_MODE 225static void ahc_queue_lstate_event(struct ahc_softc *ahc, 226 struct ahc_tmode_lstate *lstate, 227 u_int initiator_id, 228 u_int event_type, 229 u_int event_arg); 230static void ahc_update_scsiid(struct ahc_softc *ahc, 231 u_int targid_mask); 232static int ahc_handle_target_cmd(struct ahc_softc *ahc, 233 struct target_cmd *cmd); 234#endif 235/************************* Sequencer Execution Control ************************/ 236/* 237 * Restart the sequencer program from address zero 238 */ 239void 240ahc_restart(struct ahc_softc *ahc) 241{ 242 243 ahc_pause(ahc); 244 245 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 246 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 247 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 248 249 /* 250 * Ensure that the sequencer's idea of TQINPOS 251 * matches our own. The sequencer increments TQINPOS 252 * only after it sees a DMA complete and a reset could 253 * occur before the increment leaving the kernel to believe 254 * the command arrived but the sequencer to not. 255 */ 256 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 257 258 /* Always allow reselection */ 259 ahc_outb(ahc, SCSISEQ, 260 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 261 if ((ahc->features & AHC_CMD_CHAN) != 0) { 262 /* Ensure that no DMA operations are in progress */ 263 ahc_outb(ahc, CCSCBCNT, 0); 264 ahc_outb(ahc, CCSGCTL, 0); 265 ahc_outb(ahc, CCSCBCTL, 0); 266 } 267 /* 268 * If we were in the process of DMA'ing SCB data into 269 * an SCB, replace that SCB on the free list. This prevents 270 * an SCB leak. 271 */ 272 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 273 ahc_add_curscb_to_free_list(ahc); 274 ahc_outb(ahc, SEQ_FLAGS2, 275 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 276 } 277 ahc_outb(ahc, MWI_RESIDUAL, 0); 278 ahc_outb(ahc, SEQCTL, FASTMODE); 279 ahc_outb(ahc, SEQADDR0, 0); 280 ahc_outb(ahc, SEQADDR1, 0); 281 ahc_unpause(ahc); 282} 283 284/************************* Input/Output Queues ********************************/ 285void 286ahc_run_qoutfifo(struct ahc_softc *ahc) 287{ 288 struct scb *scb; 289 u_int scb_index; 290 291 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 292 293 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 294 if ((ahc->qoutfifonext & 0x03) == 0x03) { 295 u_int modnext; 296 297 /* 298 * Clear 32bits of QOUTFIFO at a time 299 * so that we don't clobber an incomming 300 * byte DMA to the array on architectures 301 * that only support 32bit load and store 302 * operations. 303 */ 304 modnext = ahc->qoutfifonext & ~0x3; 305 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 306 } 307 ahc->qoutfifonext++; 308 309 scb = ahc_lookup_scb(ahc, scb_index); 310 if (scb == NULL) { 311 printf("%s: WARNING no command for scb %d " 312 "(cmdcmplt)\nQOUTPOS = %d\n", 313 ahc_name(ahc), scb_index, 314 ahc->qoutfifonext - 1); 315 continue; 316 } 317 318 /* 319 * Save off the residual 320 * if there is one. 321 */ 322 if (ahc_check_residual(scb) != 0) 323 ahc_calc_residual(scb); 324 else 325 ahc_set_residual(scb, 0); 326 ahc_done(ahc, scb); 327 } 328} 329 330void 331ahc_run_untagged_queues(struct ahc_softc *ahc) 332{ 333 int i; 334 335 for (i = 0; i < 16; i++) 336 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 337} 338 339void 340ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 341{ 342 struct scb *scb; 343 344 if (ahc->untagged_queue_lock != 0) 345 return; 346 347 if ((scb = TAILQ_FIRST(queue)) != NULL 348 && (scb->flags & SCB_ACTIVE) == 0) { 349 scb->flags |= SCB_ACTIVE; 350 ahc_queue_scb(ahc, scb); 351 } 352} 353 354/************************* Interrupt Handling *********************************/ 355void 356ahc_handle_brkadrint(struct ahc_softc *ahc) 357{ 358 /* 359 * We upset the sequencer :-( 360 * Lookup the error message 361 */ 362 int i; 363 int error; 364 365 error = ahc_inb(ahc, ERROR); 366 for (i = 0; error != 1 && i < num_errors; i++) 367 error >>= 1; 368 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 369 ahc_name(ahc), ahc_hard_errors[i].errmesg, 370 ahc_inb(ahc, SEQADDR0) | 371 (ahc_inb(ahc, SEQADDR1) << 8)); 372 373 ahc_dump_card_state(ahc); 374 375 /* Tell everyone that this HBA is no longer availible */ 376 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 377 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 378 CAM_NO_HBA); 379 380 /* Disable all interrupt sources by resetting the controller */ 381 ahc_shutdown(ahc); 382} 383 384void 385ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 386{ 387 struct scb *scb; 388 struct ahc_devinfo devinfo; 389 390 ahc_fetch_devinfo(ahc, &devinfo); 391 392 /* 393 * Clear the upper byte that holds SEQINT status 394 * codes and clear the SEQINT bit. We will unpause 395 * the sequencer, if appropriate, after servicing 396 * the request. 397 */ 398 ahc_outb(ahc, CLRINT, CLRSEQINT); 399 switch (intstat & SEQINT_MASK) { 400 case BAD_STATUS: 401 { 402 u_int scb_index; 403 struct hardware_scb *hscb; 404 405 /* 406 * Set the default return value to 0 (don't 407 * send sense). The sense code will change 408 * this if needed. 409 */ 410 ahc_outb(ahc, RETURN_1, 0); 411 412 /* 413 * The sequencer will notify us when a command 414 * has an error that would be of interest to 415 * the kernel. This allows us to leave the sequencer 416 * running in the common case of command completes 417 * without error. The sequencer will already have 418 * dma'd the SCB back up to us, so we can reference 419 * the in kernel copy directly. 420 */ 421 scb_index = ahc_inb(ahc, SCB_TAG); 422 scb = ahc_lookup_scb(ahc, scb_index); 423 if (scb == NULL) { 424 printf("%s:%c:%d: ahc_intr - referenced scb " 425 "not valid during seqint 0x%x scb(%d)\n", 426 ahc_name(ahc), devinfo.channel, 427 devinfo.target, intstat, scb_index); 428 ahc_dump_card_state(ahc); 429 panic("for safety"); 430 goto unpause; 431 } 432 433 hscb = scb->hscb; 434 435 /* Don't want to clobber the original sense code */ 436 if ((scb->flags & SCB_SENSE) != 0) { 437 /* 438 * Clear the SCB_SENSE Flag and have 439 * the sequencer do a normal command 440 * complete. 441 */ 442 scb->flags &= ~SCB_SENSE; 443 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 444 break; 445 } 446 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 447 /* Freeze the queue until the client sees the error. */ 448 ahc_freeze_devq(ahc, scb); 449 ahc_freeze_scb(scb); 450 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 451 switch (hscb->shared_data.status.scsi_status) { 452 case SCSI_STATUS_OK: 453 printf("%s: Interrupted for staus of 0???\n", 454 ahc_name(ahc)); 455 break; 456 case SCSI_STATUS_CMD_TERMINATED: 457 case SCSI_STATUS_CHECK_COND: 458 { 459 struct ahc_dma_seg *sg; 460 struct scsi_sense *sc; 461 struct ahc_initiator_tinfo *targ_info; 462 struct ahc_tmode_tstate *tstate; 463 struct ahc_transinfo *tinfo; 464#ifdef AHC_DEBUG 465 if (ahc_debug & AHC_SHOWSENSE) { 466 ahc_print_path(ahc, scb); 467 printf("SCB %d: requests Check Status\n", 468 scb->hscb->tag); 469 } 470#endif 471 472 if (ahc_perform_autosense(scb) == 0) 473 break; 474 475 targ_info = ahc_fetch_transinfo(ahc, 476 devinfo.channel, 477 devinfo.our_scsiid, 478 devinfo.target, 479 &tstate); 480 tinfo = &targ_info->current; 481 sg = scb->sg_list; 482 sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 483 /* 484 * Save off the residual if there is one. 485 */ 486 if (ahc_check_residual(scb)) 487 ahc_calc_residual(scb); 488 else 489 ahc_set_residual(scb, 0); 490#ifdef AHC_DEBUG 491 if (ahc_debug & AHC_SHOWSENSE) { 492 ahc_print_path(ahc, scb); 493 printf("Sending Sense\n"); 494 } 495#endif 496 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 497 sg->len = ahc_get_sense_bufsize(ahc, scb); 498 sg->len |= AHC_DMA_LAST_SEG; 499 500 /* Fixup byte order */ 501 sg->addr = ahc_htole32(sg->addr); 502 sg->len = ahc_htole32(sg->len); 503 504 sc->opcode = REQUEST_SENSE; 505 sc->byte2 = 0; 506 if (tinfo->protocol_version <= SCSI_REV_2 507 && SCB_GET_LUN(scb) < 8) 508 sc->byte2 = SCB_GET_LUN(scb) << 5; 509 sc->unused[0] = 0; 510 sc->unused[1] = 0; 511 sc->length = sg->len; 512 sc->control = 0; 513 514 /* 515 * We can't allow the target to disconnect. 516 * This will be an untagged transaction and 517 * having the target disconnect will make this 518 * transaction indestinguishable from outstanding 519 * tagged transactions. 520 */ 521 hscb->control = 0; 522 523 /* 524 * This request sense could be because the 525 * the device lost power or in some other 526 * way has lost our transfer negotiations. 527 * Renegotiate if appropriate. Unit attention 528 * errors will be reported before any data 529 * phases occur. 530 */ 531 if (ahc_get_residual(scb) 532 == ahc_get_transfer_length(scb)) { 533 ahc_update_neg_request(ahc, &devinfo, 534 tstate, targ_info, 535 /*force*/TRUE); 536 } 537 if (tstate->auto_negotiate & devinfo.target_mask) { 538 hscb->control |= MK_MESSAGE; 539 scb->flags &= ~SCB_NEGOTIATE; 540 scb->flags |= SCB_AUTO_NEGOTIATE; 541 } 542 hscb->cdb_len = sizeof(*sc); 543 hscb->dataptr = sg->addr; 544 hscb->datacnt = sg->len; 545 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 546 hscb->sgptr = ahc_htole32(hscb->sgptr); 547 scb->sg_count = 1; 548 scb->flags |= SCB_SENSE; 549 ahc_qinfifo_requeue_tail(ahc, scb); 550 ahc_outb(ahc, RETURN_1, SEND_SENSE); 551#ifdef __FreeBSD__ 552 /* 553 * Ensure we have enough time to actually 554 * retrieve the sense. 555 */ 556 untimeout(ahc_timeout, (caddr_t)scb, 557 scb->io_ctx->ccb_h.timeout_ch); 558 scb->io_ctx->ccb_h.timeout_ch = 559 timeout(ahc_timeout, (caddr_t)scb, 5 * hz); 560#endif 561 break; 562 } 563 default: 564 break; 565 } 566 break; 567 } 568 case NO_MATCH: 569 { 570 /* Ensure we don't leave the selection hardware on */ 571 ahc_outb(ahc, SCSISEQ, 572 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 573 574 printf("%s:%c:%d: no active SCB for reconnecting " 575 "target - issuing BUS DEVICE RESET\n", 576 ahc_name(ahc), devinfo.channel, devinfo.target); 577 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 578 "ARG_1 == 0x%x ACCUM = 0x%x\n", 579 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 580 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 581 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 582 "SINDEX == 0x%x\n", 583 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 584 ahc_index_busy_tcl(ahc, 585 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 586 ahc_inb(ahc, SAVED_LUN))), 587 ahc_inb(ahc, SINDEX)); 588 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 589 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 590 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 591 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 592 ahc_inb(ahc, SCB_CONTROL)); 593 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 594 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 595 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 596 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 597 ahc_dump_card_state(ahc); 598 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 599 ahc->msgout_len = 1; 600 ahc->msgout_index = 0; 601 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 602 ahc_outb(ahc, MSG_OUT, HOST_MSG); 603 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, LASTPHASE) | ATNO); 604 break; 605 } 606 case SEND_REJECT: 607 { 608 u_int rejbyte = ahc_inb(ahc, ACCUM); 609 printf("%s:%c:%d: Warning - unknown message received from " 610 "target (0x%x). Rejecting\n", 611 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 612 break; 613 } 614 case NO_IDENT: 615 { 616 /* 617 * The reconnecting target either did not send an identify 618 * message, or did, but we didn't find an SCB to match and 619 * before it could respond to our ATN/abort, it hit a dataphase. 620 * The only safe thing to do is to blow it away with a bus 621 * reset. 622 */ 623 int found; 624 625 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 626 "LASTPHASE = 0x%x, SAVED_SCSIID == 0x%x\n", 627 ahc_name(ahc), devinfo.channel, devinfo.target, 628 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_SCSIID)); 629 found = ahc_reset_channel(ahc, devinfo.channel, 630 /*initiate reset*/TRUE); 631 printf("%s: Issued Channel %c Bus Reset. " 632 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 633 found); 634 return; 635 } 636 case IGN_WIDE_RES: 637 ahc_handle_ign_wide_residue(ahc, &devinfo); 638 break; 639 case BAD_PHASE: 640 { 641 u_int lastphase; 642 643 lastphase = ahc_inb(ahc, LASTPHASE); 644 printf("%s:%c:%d: unknown scsi bus phase %x, " 645 "lastphase = 0x%x. Attempting to continue\n", 646 ahc_name(ahc), devinfo.channel, devinfo.target, 647 lastphase, ahc_inb(ahc, SCSISIGI)); 648 break; 649 } 650 case MISSED_BUSFREE: 651 { 652 u_int lastphase; 653 654 lastphase = ahc_inb(ahc, LASTPHASE); 655 printf("%s:%c:%d: Missed busfree. " 656 "Lastphase = 0x%x, Curphase = 0x%x\n", 657 ahc_name(ahc), devinfo.channel, devinfo.target, 658 lastphase, ahc_inb(ahc, SCSISIGI)); 659 ahc_restart(ahc); 660 return; 661 } 662 case HOST_MSG_LOOP: 663 { 664 /* 665 * The sequencer has encountered a message phase 666 * that requires host assistance for completion. 667 * While handling the message phase(s), we will be 668 * notified by the sequencer after each byte is 669 * transfered so we can track bus phase changes. 670 * 671 * If this is the first time we've seen a HOST_MSG_LOOP 672 * interrupt, initialize the state of the host message 673 * loop. 674 */ 675 if (ahc->msg_type == MSG_TYPE_NONE) { 676 struct scb *scb; 677 u_int scb_index; 678 u_int bus_phase; 679 680 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 681 if (bus_phase != P_MESGIN 682 && bus_phase != P_MESGOUT) { 683 printf("ahc_intr: HOST_MSG_LOOP bad " 684 "phase 0x%x\n", 685 bus_phase); 686 /* 687 * Probably transitioned to bus free before 688 * we got here. Just punt the message. 689 */ 690 ahc_clear_intstat(ahc); 691 ahc_restart(ahc); 692 return; 693 } 694 695 scb_index = ahc_inb(ahc, SCB_TAG); 696 scb = ahc_lookup_scb(ahc, scb_index); 697 if (devinfo.role == ROLE_INITIATOR) { 698 if (scb == NULL) 699 panic("HOST_MSG_LOOP with " 700 "invalid SCB %x\n", scb_index); 701 702 if (bus_phase == P_MESGOUT) 703 ahc_setup_initiator_msgout(ahc, 704 &devinfo, 705 scb); 706 else { 707 ahc->msg_type = 708 MSG_TYPE_INITIATOR_MSGIN; 709 ahc->msgin_index = 0; 710 } 711 } else { 712 if (bus_phase == P_MESGOUT) { 713 ahc->msg_type = 714 MSG_TYPE_TARGET_MSGOUT; 715 ahc->msgin_index = 0; 716 } 717#if AHC_TARGET_MODE 718 else 719 ahc_setup_target_msgin(ahc, 720 &devinfo, 721 scb); 722#endif 723 } 724 } 725 726 ahc_handle_message_phase(ahc); 727 break; 728 } 729 case PERR_DETECTED: 730 { 731 /* 732 * If we've cleared the parity error interrupt 733 * but the sequencer still believes that SCSIPERR 734 * is true, it must be that the parity error is 735 * for the currently presented byte on the bus, 736 * and we are not in a phase (data-in) where we will 737 * eventually ack this byte. Ack the byte and 738 * throw it away in the hope that the target will 739 * take us to message out to deliver the appropriate 740 * error message. 741 */ 742 if ((intstat & SCSIINT) == 0 743 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 744 u_int curphase; 745 746 /* 747 * The hardware will only let you ack bytes 748 * if the expected phase in SCSISIGO matches 749 * the current phase. Make sure this is 750 * currently the case. 751 */ 752 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 753 ahc_outb(ahc, LASTPHASE, curphase); 754 ahc_outb(ahc, SCSISIGO, curphase); 755 ahc_inb(ahc, SCSIDATL); 756 } 757 break; 758 } 759 case DATA_OVERRUN: 760 { 761 /* 762 * When the sequencer detects an overrun, it 763 * places the controller in "BITBUCKET" mode 764 * and allows the target to complete its transfer. 765 * Unfortunately, none of the counters get updated 766 * when the controller is in this mode, so we have 767 * no way of knowing how large the overrun was. 768 */ 769 u_int scbindex = ahc_inb(ahc, SCB_TAG); 770 u_int lastphase = ahc_inb(ahc, LASTPHASE); 771 u_int i; 772 773 scb = ahc_lookup_scb(ahc, scbindex); 774 for (i = 0; i < num_phases; i++) { 775 if (lastphase == ahc_phase_table[i].phase) 776 break; 777 } 778 ahc_print_path(ahc, scb); 779 printf("data overrun detected %s." 780 " Tag == 0x%x.\n", 781 ahc_phase_table[i].phasemsg, 782 scb->hscb->tag); 783 ahc_print_path(ahc, scb); 784 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 785 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 786 ahc_get_transfer_length(scb), scb->sg_count); 787 if (scb->sg_count > 0) { 788 for (i = 0; i < scb->sg_count; i++) { 789 printf("sg[%d] - Addr 0x%x : Length %d\n", 790 i, 791 ahc_le32toh(scb->sg_list[i].addr), 792 ahc_le32toh(scb->sg_list[i].len) 793 & AHC_SG_LEN_MASK); 794 } 795 } 796 /* 797 * Set this and it will take effect when the 798 * target does a command complete. 799 */ 800 ahc_freeze_devq(ahc, scb); 801 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); 802 ahc_freeze_scb(scb); 803 break; 804 } 805 case MKMSG_FAILED: 806 { 807 u_int scbindex; 808 809 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 810 ahc_name(ahc), devinfo.channel, devinfo.target, 811 devinfo.lun); 812 scbindex = ahc_inb(ahc, SCB_TAG); 813 scb = ahc_lookup_scb(ahc, scbindex); 814 if (scb != NULL 815 && (scb->flags & SCB_RECOVERY_SCB) != 0) 816 /* 817 * Ensure that we didn't put a second instance of this 818 * SCB into the QINFIFO. 819 */ 820 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 821 SCB_GET_CHANNEL(ahc, scb), 822 SCB_GET_LUN(scb), scb->hscb->tag, 823 ROLE_INITIATOR, /*status*/0, 824 SEARCH_REMOVE); 825 break; 826 } 827 case NO_FREE_SCB: 828 { 829 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 830 ahc_dump_card_state(ahc); 831 panic("for safety"); 832 break; 833 } 834 case SCB_MISMATCH: 835 { 836 u_int scbptr; 837 838 scbptr = ahc_inb(ahc, SCBPTR); 839 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 840 scbptr, ahc_inb(ahc, ARG_1), 841 ahc->scb_data->hscbs[scbptr].tag); 842 ahc_dump_card_state(ahc); 843 panic("for saftey"); 844 break; 845 } 846 case OUT_OF_RANGE: 847 { 848 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 849 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 850 "ARG_1 == 0x%x ACCUM = 0x%x\n", 851 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 852 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 853 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 854 "SINDEX == 0x%x\n, A == 0x%x\n", 855 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 856 ahc_index_busy_tcl(ahc, 857 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 858 ahc_inb(ahc, SAVED_LUN))), 859 ahc_inb(ahc, SINDEX), 860 ahc_inb(ahc, ACCUM)); 861 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 862 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 863 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 864 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 865 ahc_inb(ahc, SCB_CONTROL)); 866 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 867 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 868 ahc_dump_card_state(ahc); 869 panic("for safety"); 870 break; 871 } 872 default: 873 printf("ahc_intr: seqint, " 874 "intstat == 0x%x, scsisigi = 0x%x\n", 875 intstat, ahc_inb(ahc, SCSISIGI)); 876 break; 877 } 878unpause: 879 /* 880 * The sequencer is paused immediately on 881 * a SEQINT, so we should restart it when 882 * we're done. 883 */ 884 ahc_unpause(ahc); 885} 886 887void 888ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 889{ 890 u_int scb_index; 891 u_int status0; 892 u_int status; 893 struct scb *scb; 894 char cur_channel; 895 char intr_channel; 896 897 /* Make sure the sequencer is in a safe location. */ 898 ahc_clear_critical_section(ahc); 899 900 if ((ahc->features & AHC_TWIN) != 0 901 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 902 cur_channel = 'B'; 903 else 904 cur_channel = 'A'; 905 intr_channel = cur_channel; 906 907 if ((ahc->features & AHC_ULTRA2) != 0) 908 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 909 else 910 status0 = 0; 911 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 912 if (status == 0 && status0 == 0) { 913 if ((ahc->features & AHC_TWIN) != 0) { 914 /* Try the other channel */ 915 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 916 status = ahc_inb(ahc, SSTAT1) 917 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 918 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 919 } 920 if (status == 0) { 921 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 922 ahc_outb(ahc, CLRINT, CLRSCSIINT); 923 ahc_unpause(ahc); 924 return; 925 } 926 } 927 928 scb_index = ahc_inb(ahc, SCB_TAG); 929 scb = ahc_lookup_scb(ahc, scb_index); 930 if (scb != NULL 931 && (ahc_inb(ahc, SEQ_FLAGS) & IDENTIFY_SEEN) == 0) 932 scb = NULL; 933 934 if ((ahc->features & AHC_ULTRA2) != 0 935 && (status0 & IOERR) != 0) { 936 int now_lvd; 937 938 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 939 printf("%s: Transceiver State Has Changed to %s mode\n", 940 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 941 ahc_outb(ahc, CLRSINT0, CLRIOERR); 942 /* 943 * When transitioning to SE mode, the reset line 944 * glitches, triggering an arbitration bug in some 945 * Ultra2 controllers. This bug is cleared when we 946 * assert the reset line. Since a reset glitch has 947 * already occurred with this transition and a 948 * transceiver state change is handled just like 949 * a bus reset anyway, asserting the reset line 950 * ourselves is safe. 951 */ 952 ahc_reset_channel(ahc, intr_channel, 953 /*Initiate Reset*/now_lvd == 0); 954 } else if ((status & SCSIRSTI) != 0) { 955 printf("%s: Someone reset channel %c\n", 956 ahc_name(ahc), intr_channel); 957 if (intr_channel != cur_channel) 958 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 959 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 960 } else if ((status & SCSIPERR) != 0) { 961 /* 962 * Determine the bus phase and queue an appropriate message. 963 * SCSIPERR is latched true as soon as a parity error 964 * occurs. If the sequencer acked the transfer that 965 * caused the parity error and the currently presented 966 * transfer on the bus has correct parity, SCSIPERR will 967 * be cleared by CLRSCSIPERR. Use this to determine if 968 * we should look at the last phase the sequencer recorded, 969 * or the current phase presented on the bus. 970 */ 971 u_int mesg_out; 972 u_int curphase; 973 u_int errorphase; 974 u_int lastphase; 975 u_int scsirate; 976 u_int i; 977 u_int sstat2; 978 979 lastphase = ahc_inb(ahc, LASTPHASE); 980 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 981 sstat2 = ahc_inb(ahc, SSTAT2); 982 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 983 /* 984 * For all phases save DATA, the sequencer won't 985 * automatically ack a byte that has a parity error 986 * in it. So the only way that the current phase 987 * could be 'data-in' is if the parity error is for 988 * an already acked byte in the data phase. During 989 * synchronous data-in transfers, we may actually 990 * ack bytes before latching the current phase in 991 * LASTPHASE, leading to the discrepancy between 992 * curphase and lastphase. 993 */ 994 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 995 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 996 errorphase = curphase; 997 else 998 errorphase = lastphase; 999 1000 for (i = 0; i < num_phases; i++) { 1001 if (errorphase == ahc_phase_table[i].phase) 1002 break; 1003 } 1004 mesg_out = ahc_phase_table[i].mesg_out; 1005 if (scb != NULL) 1006 ahc_print_path(ahc, scb); 1007 else 1008 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1009 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1010 scsirate = ahc_inb(ahc, SCSIRATE); 1011 printf("parity error detected %s. " 1012 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1013 ahc_phase_table[i].phasemsg, 1014 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8), 1015 scsirate); 1016 1017 if ((ahc->features & AHC_DT) != 0) { 1018 1019 if ((sstat2 & CRCVALERR) != 0) 1020 printf("\tCRC Value Mismatch\n"); 1021 if ((sstat2 & CRCENDERR) != 0) 1022 printf("\tNo terminal CRC packet recevied\n"); 1023 if ((sstat2 & CRCREQERR) != 0) 1024 printf("\tIllegal CRC packet request\n"); 1025 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1026 printf("\tUnexpected %sDT Data Phase\n", 1027 (scsirate & SINGLE_EDGE) ? "" : "non-"); 1028 } 1029 1030 /* 1031 * We've set the hardware to assert ATN if we 1032 * get a parity error on "in" phases, so all we 1033 * need to do is stuff the message buffer with 1034 * the appropriate message. "In" phases have set 1035 * mesg_out to something other than MSG_NOP. 1036 */ 1037 if (mesg_out != MSG_NOOP) { 1038 if (ahc->msg_type != MSG_TYPE_NONE) 1039 ahc->send_msg_perror = TRUE; 1040 else 1041 ahc_outb(ahc, MSG_OUT, mesg_out); 1042 } 1043 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1044 ahc_unpause(ahc); 1045 } else if ((status & BUSFREE) != 0 1046 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1047 u_int lastphase; 1048 u_int saved_scsiid; 1049 u_int saved_lun; 1050 u_int target; 1051 u_int initiator_role_id; 1052 char channel; 1053 int printerror; 1054 1055 /* 1056 * Clear our selection hardware as soon as possible. 1057 * We may have an entry in the waiting Q for this target, 1058 * that is affected by this busfree and we don't want to 1059 * go about selecting the target while we handle the event. 1060 */ 1061 ahc_outb(ahc, SCSISEQ, 1062 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1063 1064 /* 1065 * Disable busfree interrupts and clear the busfree 1066 * interrupt status. We do this here so that several 1067 * bus transactions occur prior to clearing the SCSIINT 1068 * latch. It can take a bit for the clearing to take effect. 1069 */ 1070 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1071 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1072 1073 /* 1074 * Look at what phase we were last in. 1075 * If its message out, chances are pretty good 1076 * that the busfree was in response to one of 1077 * our abort requests. 1078 */ 1079 lastphase = ahc_inb(ahc, LASTPHASE); 1080 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1081 saved_lun = ahc_inb(ahc, SAVED_LUN); 1082 target = SCSIID_TARGET(ahc, saved_scsiid); 1083 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1084 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1085 printerror = 1; 1086 1087 if (lastphase == P_MESGOUT) { 1088 struct ahc_devinfo devinfo; 1089 u_int tag; 1090 1091 ahc_fetch_devinfo(ahc, &devinfo); 1092 tag = SCB_LIST_NULL; 1093 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1094 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1095 if (ahc->msgout_buf[ahc->msgout_index - 1] 1096 == MSG_ABORT_TAG) 1097 tag = scb->hscb->tag; 1098 ahc_print_path(ahc, scb); 1099 printf("SCB %d - Abort%s Completed.\n", 1100 scb->hscb->tag, tag == SCB_LIST_NULL ? 1101 "" : " Tag"); 1102 ahc_abort_scbs(ahc, target, channel, 1103 saved_lun, tag, 1104 ROLE_INITIATOR, 1105 CAM_REQ_ABORTED); 1106 printerror = 0; 1107 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1108 MSG_BUS_DEV_RESET, TRUE)) { 1109 struct ahc_devinfo devinfo; 1110#ifdef __FreeBSD__ 1111 /* 1112 * Don't mark the user's request for this BDR 1113 * as completing with CAM_BDR_SENT. CAM3 1114 * specifies CAM_REQ_CMP. 1115 */ 1116 if (scb != NULL 1117 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1118 && ahc_match_scb(ahc, scb, target, channel, 1119 CAM_LUN_WILDCARD, 1120 SCB_LIST_NULL, 1121 ROLE_INITIATOR)) { 1122 ahc_set_transaction_status(scb, CAM_REQ_CMP); 1123 } 1124#endif 1125 ahc_compile_devinfo(&devinfo, 1126 initiator_role_id, 1127 target, 1128 CAM_LUN_WILDCARD, 1129 channel, 1130 ROLE_INITIATOR); 1131 ahc_handle_devreset(ahc, &devinfo, 1132 CAM_BDR_SENT, 1133 "Bus Device Reset", 1134 /*verbose_level*/0); 1135 printerror = 0; 1136 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1137 MSG_EXT_PPR, FALSE)) { 1138 struct ahc_initiator_tinfo *tinfo; 1139 struct ahc_tmode_tstate *tstate; 1140 1141 /* 1142 * PPR Rejected. Try non-ppr negotiation 1143 * and retry command. 1144 */ 1145 tinfo = ahc_fetch_transinfo(ahc, 1146 devinfo.channel, 1147 devinfo.our_scsiid, 1148 devinfo.target, 1149 &tstate); 1150 tinfo->current.transport_version = 2; 1151 tinfo->goal.transport_version = 2; 1152 tinfo->goal.ppr_options = 0; 1153 ahc_qinfifo_requeue_tail(ahc, scb); 1154 printerror = 0; 1155 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1156 MSG_EXT_WDTR, FALSE) 1157 || ahc_sent_msg(ahc, AHCMSG_EXT, 1158 MSG_EXT_SDTR, FALSE)) { 1159 /* 1160 * Negotiation Rejected. Go-async and 1161 * retry command. 1162 */ 1163 ahc_set_width(ahc, &devinfo, 1164 MSG_EXT_WDTR_BUS_8_BIT, 1165 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1166 /*paused*/TRUE); 1167 ahc_set_syncrate(ahc, &devinfo, 1168 /*syncrate*/NULL, 1169 /*period*/0, /*offset*/0, 1170 /*ppr_options*/0, 1171 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1172 /*paused*/TRUE); 1173 ahc_qinfifo_requeue_tail(ahc, scb); 1174 printerror = 0; 1175 } 1176 } 1177 if (printerror != 0) { 1178 u_int i; 1179 1180 if (scb != NULL) { 1181 u_int tag; 1182 1183 if ((scb->hscb->control & TAG_ENB) != 0) 1184 tag = scb->hscb->tag; 1185 else 1186 tag = SCB_LIST_NULL; 1187 ahc_print_path(ahc, scb); 1188 ahc_abort_scbs(ahc, target, channel, 1189 SCB_GET_LUN(scb), tag, 1190 ROLE_INITIATOR, 1191 CAM_UNEXP_BUSFREE); 1192 } else { 1193 /* 1194 * We had not fully identified this connection, 1195 * so we cannot abort anything. 1196 */ 1197 printf("%s: ", ahc_name(ahc)); 1198 } 1199 for (i = 0; i < num_phases; i++) { 1200 if (lastphase == ahc_phase_table[i].phase) 1201 break; 1202 } 1203 printf("Unexpected busfree %s\n" 1204 "SEQADDR == 0x%x\n", 1205 ahc_phase_table[i].phasemsg, 1206 ahc_inb(ahc, SEQADDR0) 1207 | (ahc_inb(ahc, SEQADDR1) << 8)); 1208 } 1209 ahc_clear_msg_state(ahc); 1210 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1211 ahc_restart(ahc); 1212 } else if ((status & SELTO) != 0) { 1213 u_int scbptr; 1214 1215 /* Stop the selection */ 1216 ahc_outb(ahc, SCSISEQ, 0); 1217 1218 /* No more pending messages */ 1219 ahc_clear_msg_state(ahc); 1220 1221 /* Clear interrupt state */ 1222 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1223 1224 /* 1225 * Although the driver does not care about the 1226 * 'Selection in Progress' status bit, the busy 1227 * LED does. SELINGO is only cleared by a sucessful 1228 * selection, so we must manually clear it to insure 1229 * the LED turns off just incase no future successful 1230 * selections occur (e.g. no devices on the bus). 1231 */ 1232 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1233 1234 scbptr = ahc_inb(ahc, WAITING_SCBH); 1235 ahc_outb(ahc, SCBPTR, scbptr); 1236 scb_index = ahc_inb(ahc, SCB_TAG); 1237 1238 scb = ahc_lookup_scb(ahc, scb_index); 1239 if (scb == NULL) { 1240 printf("%s: ahc_intr - referenced scb not " 1241 "valid during SELTO scb(%d, %d)\n", 1242 ahc_name(ahc), scbptr, scb_index); 1243 } else { 1244 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1245 ahc_freeze_devq(ahc, scb); 1246 } 1247 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1248 ahc_restart(ahc); 1249 } else { 1250 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1251 ahc_name(ahc), status); 1252 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1253 } 1254} 1255 1256#define AHC_MAX_STEPS 2000 1257void 1258ahc_clear_critical_section(struct ahc_softc *ahc) 1259{ 1260 int stepping; 1261 int steps; 1262 u_int simode0; 1263 u_int simode1; 1264 1265 if (ahc->num_critical_sections == 0) 1266 return; 1267 1268 stepping = FALSE; 1269 steps = 0; 1270 simode0 = 0; 1271 simode1 = 0; 1272 for (;;) { 1273 struct cs *cs; 1274 u_int seqaddr; 1275 u_int i; 1276 1277 seqaddr = ahc_inb(ahc, SEQADDR0) 1278 | (ahc_inb(ahc, SEQADDR1) << 8); 1279 1280 cs = ahc->critical_sections; 1281 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1282 1283 if (cs->begin < seqaddr && cs->end >= seqaddr) 1284 break; 1285 } 1286 1287 if (i == ahc->num_critical_sections) 1288 break; 1289 1290 if (steps > AHC_MAX_STEPS) { 1291 printf("%s: Infinite loop in critical section\n", 1292 ahc_name(ahc)); 1293 ahc_dump_card_state(ahc); 1294 panic("critical section loop"); 1295 } 1296 1297 steps++; 1298 if (stepping == FALSE) { 1299 1300 /* 1301 * Disable all interrupt sources so that the 1302 * sequencer will not be stuck by a pausing 1303 * interrupt condition while we attempt to 1304 * leave a critical section. 1305 */ 1306 simode0 = ahc_inb(ahc, SIMODE0); 1307 ahc_outb(ahc, SIMODE0, 0); 1308 simode1 = ahc_inb(ahc, SIMODE1); 1309 ahc_outb(ahc, SIMODE1, 0); 1310 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1311 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) | STEP); 1312 stepping = TRUE; 1313 } 1314 ahc_outb(ahc, HCNTRL, ahc->unpause); 1315 do { 1316 ahc_delay(200); 1317 } while (!ahc_is_paused(ahc)); 1318 } 1319 if (stepping) { 1320 ahc_outb(ahc, SIMODE0, simode0); 1321 ahc_outb(ahc, SIMODE1, simode1); 1322 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) & ~STEP); 1323 } 1324} 1325 1326/* 1327 * Clear any pending interrupt status. 1328 */ 1329void 1330ahc_clear_intstat(struct ahc_softc *ahc) 1331{ 1332 /* Clear any interrupt conditions this may have caused */ 1333 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1334 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1335 CLRREQINIT); 1336 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1337 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1338} 1339 1340/**************************** Debugging Routines ******************************/ 1341void 1342ahc_print_scb(struct scb *scb) 1343{ 1344 int i; 1345 1346 struct hardware_scb *hscb = scb->hscb; 1347 1348 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1349 scb, 1350 hscb->control, 1351 hscb->scsiid, 1352 hscb->lun, 1353 hscb->cdb_len); 1354 i = 0; 1355 printf("Shared Data: %#02x %#02x %#02x %#02x\n", 1356 hscb->shared_data.cdb[i++], 1357 hscb->shared_data.cdb[i++], 1358 hscb->shared_data.cdb[i++], 1359 hscb->shared_data.cdb[i++]); 1360 printf(" %#02x %#02x %#02x %#02x\n", 1361 hscb->shared_data.cdb[i++], 1362 hscb->shared_data.cdb[i++], 1363 hscb->shared_data.cdb[i++], 1364 hscb->shared_data.cdb[i++]); 1365 printf(" %#02x %#02x %#02x %#02x\n", 1366 hscb->shared_data.cdb[i++], 1367 hscb->shared_data.cdb[i++], 1368 hscb->shared_data.cdb[i++], 1369 hscb->shared_data.cdb[i++]); 1370 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1371 ahc_le32toh(hscb->dataptr), 1372 ahc_le32toh(hscb->datacnt), 1373 ahc_le32toh(hscb->sgptr), 1374 hscb->tag); 1375 if (scb->sg_count > 0) { 1376 for (i = 0; i < scb->sg_count; i++) { 1377 printf("sg[%d] - Addr 0x%x : Length %d\n", 1378 i, 1379 ahc_le32toh(scb->sg_list[i].addr), 1380 ahc_le32toh(scb->sg_list[i].len)); 1381 } 1382 } 1383} 1384 1385/************************* Transfer Negotiation *******************************/ 1386/* 1387 * Allocate per target mode instance (ID we respond to as a target) 1388 * transfer negotiation data structures. 1389 */ 1390static struct ahc_tmode_tstate * 1391ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1392{ 1393 struct ahc_tmode_tstate *master_tstate; 1394 struct ahc_tmode_tstate *tstate; 1395 int i; 1396 1397 master_tstate = ahc->enabled_targets[ahc->our_id]; 1398 if (channel == 'B') { 1399 scsi_id += 8; 1400 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1401 } 1402 if (ahc->enabled_targets[scsi_id] != NULL 1403 && ahc->enabled_targets[scsi_id] != master_tstate) 1404 panic("%s: ahc_alloc_tstate - Target already allocated", 1405 ahc_name(ahc)); 1406 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 1407 if (tstate == NULL) 1408 return (NULL); 1409 1410 /* 1411 * If we have allocated a master tstate, copy user settings from 1412 * the master tstate (taken from SRAM or the EEPROM) for this 1413 * channel, but reset our current and goal settings to async/narrow 1414 * until an initiator talks to us. 1415 */ 1416 if (master_tstate != NULL) { 1417 memcpy(tstate, master_tstate, sizeof(*tstate)); 1418 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1419 tstate->ultraenb = 0; 1420 for (i = 0; i < 16; i++) { 1421 memset(&tstate->transinfo[i].current, 0, 1422 sizeof(tstate->transinfo[i].current)); 1423 memset(&tstate->transinfo[i].goal, 0, 1424 sizeof(tstate->transinfo[i].goal)); 1425 } 1426 } else 1427 memset(tstate, 0, sizeof(*tstate)); 1428 ahc->enabled_targets[scsi_id] = tstate; 1429 return (tstate); 1430} 1431 1432#ifdef AHC_TARGET_MODE 1433/* 1434 * Free per target mode instance (ID we respond to as a target) 1435 * transfer negotiation data structures. 1436 */ 1437static void 1438ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1439{ 1440 struct ahc_tmode_tstate *tstate; 1441 1442 /* 1443 * Don't clean up our "master" tstate. 1444 * It has our default user settings. 1445 */ 1446 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1447 || (channel == 'A' && scsi_id == ahc->our_id)) 1448 && force == FALSE) 1449 return; 1450 1451 if (channel == 'B') 1452 scsi_id += 8; 1453 tstate = ahc->enabled_targets[scsi_id]; 1454 if (tstate != NULL) 1455 free(tstate, M_DEVBUF); 1456 ahc->enabled_targets[scsi_id] = NULL; 1457} 1458#endif 1459 1460/* 1461 * Called when we have an active connection to a target on the bus, 1462 * this function finds the nearest syncrate to the input period limited 1463 * by the capabilities of the bus connectivity of and sync settings for 1464 * the target. 1465 */ 1466struct ahc_syncrate * 1467ahc_devlimited_syncrate(struct ahc_softc *ahc, 1468 struct ahc_initiator_tinfo *tinfo, 1469 u_int *period, u_int *ppr_options, role_t role) { 1470 struct ahc_transinfo *transinfo; 1471 u_int maxsync; 1472 1473 if ((ahc->features & AHC_ULTRA2) != 0) { 1474 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1475 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1476 maxsync = AHC_SYNCRATE_DT; 1477 } else { 1478 maxsync = AHC_SYNCRATE_ULTRA; 1479 /* Can't do DT on an SE bus */ 1480 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1481 } 1482 } else if ((ahc->features & AHC_ULTRA) != 0 1483 && (ahc->flags & AHC_ULTRA_DISABLED) == 0) { 1484 maxsync = AHC_SYNCRATE_ULTRA; 1485 } else { 1486 maxsync = AHC_SYNCRATE_FAST; 1487 } 1488 /* 1489 * Never allow a value higher than our current goal 1490 * period otherwise we may allow a target initiated 1491 * negotiation to go above the limit as set by the 1492 * user. In the case of an initiator initiated 1493 * sync negotiation, we limit based on the user 1494 * setting. This allows the system to still accept 1495 * incoming negotiations even if target initiated 1496 * negotiation is not performed. 1497 */ 1498 if (role == ROLE_TARGET) 1499 transinfo = &tinfo->user; 1500 else 1501 transinfo = &tinfo->goal; 1502 *ppr_options &= transinfo->ppr_options; 1503 if (transinfo->period == 0) { 1504 *period = 0; 1505 *ppr_options = 0; 1506 return (NULL); 1507 } 1508 *period = MAX(*period, transinfo->period); 1509 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1510} 1511 1512/* 1513 * Look up the valid period to SCSIRATE conversion in our table. 1514 * Return the period and offset that should be sent to the target 1515 * if this was the beginning of an SDTR. 1516 */ 1517struct ahc_syncrate * 1518ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1519 u_int *ppr_options, u_int maxsync) 1520{ 1521 struct ahc_syncrate *syncrate; 1522 1523 if ((ahc->features & AHC_DT) == 0) 1524 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1525 1526 for (syncrate = &ahc_syncrates[maxsync]; 1527 syncrate->rate != NULL; 1528 syncrate++) { 1529 1530 /* 1531 * The Ultra2 table doesn't go as low 1532 * as for the Fast/Ultra cards. 1533 */ 1534 if ((ahc->features & AHC_ULTRA2) != 0 1535 && (syncrate->sxfr_u2 == 0)) 1536 break; 1537 1538 /* Skip any DT entries if DT is not available */ 1539 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1540 && (syncrate->sxfr_u2 & DT_SXFR) != 0) 1541 continue; 1542 1543 if (*period <= syncrate->period) { 1544 /* 1545 * When responding to a target that requests 1546 * sync, the requested rate may fall between 1547 * two rates that we can output, but still be 1548 * a rate that we can receive. Because of this, 1549 * we want to respond to the target with 1550 * the same rate that it sent to us even 1551 * if the period we use to send data to it 1552 * is lower. Only lower the response period 1553 * if we must. 1554 */ 1555 if (syncrate == &ahc_syncrates[maxsync]) 1556 *period = syncrate->period; 1557 1558 /* 1559 * At some speeds, we only support 1560 * ST transfers. 1561 */ 1562 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1563 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1564 break; 1565 } 1566 } 1567 1568 if ((*period == 0) 1569 || (syncrate->rate == NULL) 1570 || ((ahc->features & AHC_ULTRA2) != 0 1571 && (syncrate->sxfr_u2 == 0))) { 1572 /* Use asynchronous transfers. */ 1573 *period = 0; 1574 syncrate = NULL; 1575 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1576 } 1577 return (syncrate); 1578} 1579 1580/* 1581 * Convert from an entry in our syncrate table to the SCSI equivalent 1582 * sync "period" factor. 1583 */ 1584u_int 1585ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1586{ 1587 struct ahc_syncrate *syncrate; 1588 1589 if ((ahc->features & AHC_ULTRA2) != 0) 1590 scsirate &= SXFR_ULTRA2; 1591 else 1592 scsirate &= SXFR; 1593 1594 syncrate = &ahc_syncrates[maxsync]; 1595 while (syncrate->rate != NULL) { 1596 1597 if ((ahc->features & AHC_ULTRA2) != 0) { 1598 if (syncrate->sxfr_u2 == 0) 1599 break; 1600 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1601 return (syncrate->period); 1602 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1603 return (syncrate->period); 1604 } 1605 syncrate++; 1606 } 1607 return (0); /* async */ 1608} 1609 1610/* 1611 * Truncate the given synchronous offset to a value the 1612 * current adapter type and syncrate are capable of. 1613 */ 1614void 1615ahc_validate_offset(struct ahc_softc *ahc, 1616 struct ahc_initiator_tinfo *tinfo, 1617 struct ahc_syncrate *syncrate, 1618 u_int *offset, int wide, role_t role) 1619{ 1620 u_int maxoffset; 1621 1622 /* Limit offset to what we can do */ 1623 if (syncrate == NULL) { 1624 maxoffset = 0; 1625 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1626 maxoffset = MAX_OFFSET_ULTRA2; 1627 } else { 1628 if (wide) 1629 maxoffset = MAX_OFFSET_16BIT; 1630 else 1631 maxoffset = MAX_OFFSET_8BIT; 1632 } 1633 *offset = MIN(*offset, maxoffset); 1634 if (tinfo != NULL) { 1635 if (role == ROLE_TARGET) 1636 *offset = MIN(*offset, tinfo->user.offset); 1637 else 1638 *offset = MIN(*offset, tinfo->goal.offset); 1639 } 1640} 1641 1642/* 1643 * Truncate the given transfer width parameter to a value the 1644 * current adapter type is capable of. 1645 */ 1646void 1647ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1648 u_int *bus_width, role_t role) 1649{ 1650 switch (*bus_width) { 1651 default: 1652 if (ahc->features & AHC_WIDE) { 1653 /* Respond Wide */ 1654 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1655 break; 1656 } 1657 /* FALLTHROUGH */ 1658 case MSG_EXT_WDTR_BUS_8_BIT: 1659 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1660 break; 1661 } 1662 if (tinfo != NULL) { 1663 if (role == ROLE_TARGET) 1664 *bus_width = MIN(tinfo->user.width, *bus_width); 1665 else 1666 *bus_width = MIN(tinfo->goal.width, *bus_width); 1667 } 1668} 1669 1670/* 1671 * Update the bitmask of targets for which the controller should 1672 * negotiate with at the next convenient oportunity. This currently 1673 * means the next time we send the initial identify messages for 1674 * a new transaction. 1675 */ 1676int 1677ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1678 struct ahc_tmode_tstate *tstate, 1679 struct ahc_initiator_tinfo *tinfo, int force) 1680{ 1681 u_int auto_negotiate_orig; 1682 1683 auto_negotiate_orig = tstate->auto_negotiate; 1684 if (tinfo->current.period != tinfo->goal.period 1685 || tinfo->current.width != tinfo->goal.width 1686 || tinfo->current.offset != tinfo->goal.offset 1687 || tinfo->current.ppr_options != tinfo->goal.ppr_options 1688 || (force 1689 && (tinfo->goal.period != 0 1690 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1691 || tinfo->goal.ppr_options != 0))) 1692 tstate->auto_negotiate |= devinfo->target_mask; 1693 else 1694 tstate->auto_negotiate &= ~devinfo->target_mask; 1695 1696 return (auto_negotiate_orig != tstate->auto_negotiate); 1697} 1698 1699/* 1700 * Update the user/goal/current tables of synchronous negotiation 1701 * parameters as well as, in the case of a current or active update, 1702 * any data structures on the host controller. In the case of an 1703 * active update, the specified target is currently talking to us on 1704 * the bus, so the transfer parameter update must take effect 1705 * immediately. 1706 */ 1707void 1708ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1709 struct ahc_syncrate *syncrate, u_int period, 1710 u_int offset, u_int ppr_options, u_int type, int paused) 1711{ 1712 struct ahc_initiator_tinfo *tinfo; 1713 struct ahc_tmode_tstate *tstate; 1714 u_int old_period; 1715 u_int old_offset; 1716 u_int old_ppr; 1717 int active; 1718 int update_needed; 1719 1720 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1721 update_needed = 0; 1722 1723 if (syncrate == NULL) { 1724 period = 0; 1725 offset = 0; 1726 } 1727 1728 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1729 devinfo->target, &tstate); 1730 1731 if ((type & AHC_TRANS_USER) != 0) { 1732 tinfo->user.period = period; 1733 tinfo->user.offset = offset; 1734 tinfo->user.ppr_options = ppr_options; 1735 } 1736 1737 if ((type & AHC_TRANS_GOAL) != 0) { 1738 tinfo->goal.period = period; 1739 tinfo->goal.offset = offset; 1740 tinfo->goal.ppr_options = ppr_options; 1741 } 1742 1743 old_period = tinfo->current.period; 1744 old_offset = tinfo->current.offset; 1745 old_ppr = tinfo->current.ppr_options; 1746 1747 if ((type & AHC_TRANS_CUR) != 0 1748 && (old_period != period 1749 || old_offset != offset 1750 || old_ppr != ppr_options)) { 1751 u_int scsirate; 1752 1753 update_needed++; 1754 scsirate = tinfo->scsirate; 1755 if ((ahc->features & AHC_ULTRA2) != 0) { 1756 1757 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1758 if (syncrate != NULL) { 1759 scsirate |= syncrate->sxfr_u2; 1760 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 1761 scsirate |= ENABLE_CRC; 1762 else 1763 scsirate |= SINGLE_EDGE; 1764 } 1765 } else { 1766 1767 scsirate &= ~(SXFR|SOFS); 1768 /* 1769 * Ensure Ultra mode is set properly for 1770 * this target. 1771 */ 1772 tstate->ultraenb &= ~devinfo->target_mask; 1773 if (syncrate != NULL) { 1774 if (syncrate->sxfr & ULTRA_SXFR) { 1775 tstate->ultraenb |= 1776 devinfo->target_mask; 1777 } 1778 scsirate |= syncrate->sxfr & SXFR; 1779 scsirate |= offset & SOFS; 1780 } 1781 if (active) { 1782 u_int sxfrctl0; 1783 1784 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1785 sxfrctl0 &= ~FAST20; 1786 if (tstate->ultraenb & devinfo->target_mask) 1787 sxfrctl0 |= FAST20; 1788 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1789 } 1790 } 1791 if (active) { 1792 ahc_outb(ahc, SCSIRATE, scsirate); 1793 if ((ahc->features & AHC_ULTRA2) != 0) 1794 ahc_outb(ahc, SCSIOFFSET, offset); 1795 } 1796 1797 tinfo->scsirate = scsirate; 1798 tinfo->current.period = period; 1799 tinfo->current.offset = offset; 1800 tinfo->current.ppr_options = ppr_options; 1801 1802 ahc_send_async(ahc, devinfo->channel, devinfo->target, 1803 CAM_LUN_WILDCARD, AC_TRANSFER_NEG); 1804 if (bootverbose) { 1805 if (offset != 0) { 1806 printf("%s: target %d synchronous at %sMHz%s, " 1807 "offset = 0x%x\n", ahc_name(ahc), 1808 devinfo->target, syncrate->rate, 1809 (ppr_options & MSG_EXT_PPR_DT_REQ) 1810 ? " DT" : "", offset); 1811 } else { 1812 printf("%s: target %d using " 1813 "asynchronous transfers\n", 1814 ahc_name(ahc), devinfo->target); 1815 } 1816 } 1817 } 1818 1819 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 1820 tinfo, /*force*/FALSE); 1821 1822 if (update_needed) 1823 ahc_update_pending_scbs(ahc); 1824} 1825 1826/* 1827 * Update the user/goal/current tables of wide negotiation 1828 * parameters as well as, in the case of a current or active update, 1829 * any data structures on the host controller. In the case of an 1830 * active update, the specified target is currently talking to us on 1831 * the bus, so the transfer parameter update must take effect 1832 * immediately. 1833 */ 1834void 1835ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1836 u_int width, u_int type, int paused) 1837{ 1838 struct ahc_initiator_tinfo *tinfo; 1839 struct ahc_tmode_tstate *tstate; 1840 u_int oldwidth; 1841 int active; 1842 int update_needed; 1843 1844 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1845 update_needed = 0; 1846 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1847 devinfo->target, &tstate); 1848 1849 if ((type & AHC_TRANS_USER) != 0) 1850 tinfo->user.width = width; 1851 1852 if ((type & AHC_TRANS_GOAL) != 0) 1853 tinfo->goal.width = width; 1854 1855 oldwidth = tinfo->current.width; 1856 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 1857 u_int scsirate; 1858 1859 update_needed++; 1860 scsirate = tinfo->scsirate; 1861 scsirate &= ~WIDEXFER; 1862 if (width == MSG_EXT_WDTR_BUS_16_BIT) 1863 scsirate |= WIDEXFER; 1864 1865 tinfo->scsirate = scsirate; 1866 1867 if (active) 1868 ahc_outb(ahc, SCSIRATE, scsirate); 1869 1870 tinfo->current.width = width; 1871 1872 ahc_send_async(ahc, devinfo->channel, devinfo->target, 1873 CAM_LUN_WILDCARD, AC_TRANSFER_NEG); 1874 if (bootverbose) { 1875 printf("%s: target %d using %dbit transfers\n", 1876 ahc_name(ahc), devinfo->target, 1877 8 * (0x01 << width)); 1878 } 1879 } 1880 1881 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 1882 tinfo, /*force*/FALSE); 1883 if (update_needed) 1884 ahc_update_pending_scbs(ahc); 1885} 1886 1887/* 1888 * Update the current state of tagged queuing for a given target. 1889 */ 1890void 1891ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, int enable) 1892{ 1893 struct ahc_initiator_tinfo *tinfo; 1894 struct ahc_tmode_tstate *tstate; 1895 uint16_t orig_tagenable; 1896 1897 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1898 devinfo->target, &tstate); 1899 1900 orig_tagenable = tstate->tagenable; 1901 if (enable) 1902 tstate->tagenable |= devinfo->target_mask; 1903 else 1904 tstate->tagenable &= ~devinfo->target_mask; 1905 1906 if (orig_tagenable != tstate->tagenable) { 1907 ahc_platform_set_tags(ahc, devinfo, enable); 1908 ahc_send_async(ahc, devinfo->channel, devinfo->target, 1909 devinfo->lun, AC_TRANSFER_NEG); 1910 } 1911 1912} 1913 1914/* 1915 * When the transfer settings for a connection change, update any 1916 * in-transit SCBs to contain the new data so the hardware will 1917 * be set correctly during future (re)selections. 1918 */ 1919static void 1920ahc_update_pending_scbs(struct ahc_softc *ahc) 1921{ 1922 struct scb *pending_scb; 1923 int pending_scb_count; 1924 int i; 1925 int paused; 1926 u_int saved_scbptr; 1927 1928 /* 1929 * Traverse the pending SCB list and ensure that all of the 1930 * SCBs there have the proper settings. 1931 */ 1932 pending_scb_count = 0; 1933 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 1934 struct ahc_devinfo devinfo; 1935 struct hardware_scb *pending_hscb; 1936 struct ahc_initiator_tinfo *tinfo; 1937 struct ahc_tmode_tstate *tstate; 1938 1939 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 1940 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 1941 devinfo.our_scsiid, 1942 devinfo.target, &tstate); 1943 pending_hscb = pending_scb->hscb; 1944 pending_hscb->control &= ~ULTRAENB; 1945 if ((tstate->ultraenb & devinfo.target_mask) != 0) 1946 pending_hscb->control |= ULTRAENB; 1947 pending_hscb->scsirate = tinfo->scsirate; 1948 pending_hscb->scsioffset = tinfo->current.offset; 1949 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 1950 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 1951 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 1952 pending_hscb->control &= ~MK_MESSAGE; 1953 } 1954 pending_scb_count++; 1955 } 1956 1957 if (pending_scb_count == 0) 1958 return; 1959 1960 if (ahc_is_paused(ahc)) { 1961 paused = 1; 1962 } else { 1963 paused = 0; 1964 ahc_pause(ahc); 1965 } 1966 1967 saved_scbptr = ahc_inb(ahc, SCBPTR); 1968 /* Ensure that the hscbs down on the card match the new information */ 1969 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 1970 struct hardware_scb *pending_hscb; 1971 u_int control; 1972 u_int scb_tag; 1973 1974 ahc_outb(ahc, SCBPTR, i); 1975 scb_tag = ahc_inb(ahc, SCB_TAG); 1976 pending_scb = ahc_lookup_scb(ahc, scb_tag); 1977 if (pending_scb == NULL) 1978 continue; 1979 1980 pending_hscb = pending_scb->hscb; 1981 control = ahc_inb(ahc, SCB_CONTROL); 1982 control &= ~(ULTRAENB|MK_MESSAGE); 1983 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 1984 ahc_outb(ahc, SCB_CONTROL, control); 1985 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 1986 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 1987 } 1988 ahc_outb(ahc, SCBPTR, saved_scbptr); 1989 1990 if (paused == 0) 1991 ahc_unpause(ahc); 1992} 1993 1994/**************************** Pathing Information *****************************/ 1995static void 1996ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1997{ 1998 u_int saved_scsiid; 1999 role_t role; 2000 int our_id; 2001 2002 if (ahc_inb(ahc, SSTAT0) & TARGET) 2003 role = ROLE_TARGET; 2004 else 2005 role = ROLE_INITIATOR; 2006 2007 if (role == ROLE_TARGET 2008 && (ahc->features & AHC_MULTI_TID) != 0 2009 && (ahc_inb(ahc, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 2010 /* We were selected, so pull our id from TARGIDIN */ 2011 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2012 } else if ((ahc->features & AHC_ULTRA2) != 0) 2013 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2014 else 2015 our_id = ahc_inb(ahc, SCSIID) & OID; 2016 2017 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2018 ahc_compile_devinfo(devinfo, 2019 our_id, 2020 SCSIID_TARGET(ahc, saved_scsiid), 2021 ahc_inb(ahc, SAVED_LUN), 2022 SCSIID_CHANNEL(ahc, saved_scsiid), 2023 role); 2024} 2025 2026struct ahc_phase_table_entry* 2027ahc_lookup_phase_entry(int phase) 2028{ 2029 struct ahc_phase_table_entry *entry; 2030 struct ahc_phase_table_entry *last_entry; 2031 2032 /* 2033 * num_phases doesn't include the default entry which 2034 * will be returned if the phase doesn't match. 2035 */ 2036 last_entry = &ahc_phase_table[num_phases]; 2037 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2038 if (phase == entry->phase) 2039 break; 2040 } 2041 return (entry); 2042} 2043 2044void 2045ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2046 u_int lun, char channel, role_t role) 2047{ 2048 devinfo->our_scsiid = our_id; 2049 devinfo->target = target; 2050 devinfo->lun = lun; 2051 devinfo->target_offset = target; 2052 devinfo->channel = channel; 2053 devinfo->role = role; 2054 if (channel == 'B') 2055 devinfo->target_offset += 8; 2056 devinfo->target_mask = (0x01 << devinfo->target_offset); 2057} 2058 2059static void 2060ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2061 struct scb *scb) 2062{ 2063 role_t role; 2064 int our_id; 2065 2066 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2067 role = ROLE_INITIATOR; 2068 if ((scb->hscb->control & TARGET_SCB) != 0) 2069 role = ROLE_TARGET; 2070 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2071 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2072} 2073 2074 2075/************************ Message Phase Processing ****************************/ 2076/* 2077 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2078 * or enters the initial message out phase, we are interrupted. Fill our 2079 * outgoing message buffer with the appropriate message and beging handing 2080 * the message phase(s) manually. 2081 */ 2082static void 2083ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2084 struct scb *scb) 2085{ 2086 /* 2087 * To facilitate adding multiple messages together, 2088 * each routine should increment the index and len 2089 * variables instead of setting them explicitly. 2090 */ 2091 ahc->msgout_index = 0; 2092 ahc->msgout_len = 0; 2093 2094 if ((scb->flags & SCB_DEVICE_RESET) == 0 2095 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2096 u_int identify_msg; 2097 2098 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2099 if ((scb->hscb->control & DISCENB) != 0) 2100 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2101 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2102 ahc->msgout_len++; 2103 2104 if ((scb->hscb->control & TAG_ENB) != 0) { 2105 ahc->msgout_buf[ahc->msgout_index++] = 2106 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2107 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2108 ahc->msgout_len += 2; 2109 } 2110 } 2111 2112 if (scb->flags & SCB_DEVICE_RESET) { 2113 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2114 ahc->msgout_len++; 2115 ahc_print_path(ahc, scb); 2116 printf("Bus Device Reset Message Sent\n"); 2117 /* 2118 * Clear our selection hardware in advance of 2119 * the busfree. We may have an entry in the waiting 2120 * Q for this target, and we don't want to go about 2121 * selecting while we handle the busfree and blow it 2122 * away. 2123 */ 2124 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2125 } else if ((scb->flags & SCB_ABORT) != 0) { 2126 if ((scb->hscb->control & TAG_ENB) != 0) 2127 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2128 else 2129 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2130 ahc->msgout_len++; 2131 ahc_print_path(ahc, scb); 2132 printf("Abort%s Message Sent\n", 2133 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2134 /* 2135 * Clear our selection hardware in advance of 2136 * the busfree. We may have an entry in the waiting 2137 * Q for this target, and we don't want to go about 2138 * selecting while we handle the busfree and blow it 2139 * away. 2140 */ 2141 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2142 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2143 ahc_build_transfer_msg(ahc, devinfo); 2144 } else { 2145 printf("ahc_intr: AWAITING_MSG for an SCB that " 2146 "does not have a waiting message\n"); 2147 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2148 devinfo->target_mask); 2149 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2150 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2151 ahc_inb(ahc, MSG_OUT), scb->flags); 2152 } 2153 2154 /* 2155 * Clear the MK_MESSAGE flag from the SCB so we aren't 2156 * asked to send this message again. 2157 */ 2158 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2159 scb->hscb->control &= ~MK_MESSAGE; 2160 ahc->msgout_index = 0; 2161 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2162} 2163 2164/* 2165 * Build an appropriate transfer negotiation message for the 2166 * currently active target. 2167 */ 2168static void 2169ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2170{ 2171 /* 2172 * We need to initiate transfer negotiations. 2173 * If our current and goal settings are identical, 2174 * we want to renegotiate due to a check condition. 2175 */ 2176 struct ahc_initiator_tinfo *tinfo; 2177 struct ahc_tmode_tstate *tstate; 2178 struct ahc_syncrate *rate; 2179 int dowide; 2180 int dosync; 2181 int doppr; 2182 int use_ppr; 2183 u_int period; 2184 u_int ppr_options; 2185 u_int offset; 2186 2187 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2188 devinfo->target, &tstate); 2189 dowide = tinfo->current.width != tinfo->goal.width; 2190 dosync = tinfo->current.period != tinfo->goal.period; 2191 doppr = tinfo->current.ppr_options != tinfo->goal.ppr_options; 2192 2193 if (!dowide && !dosync && !doppr) { 2194 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2195 dosync = tinfo->goal.period != 0; 2196 doppr = tinfo->goal.ppr_options != 0; 2197 } 2198 2199 if (!dowide && !dosync && !doppr) { 2200 panic("ahc_intr: AWAITING_MSG for negotiation, " 2201 "but no negotiation needed\n"); 2202 } 2203 2204 use_ppr = (tinfo->current.transport_version >= 3) || doppr; 2205 /* Target initiated PPR is not allowed in the SCSI spec */ 2206 if (devinfo->role == ROLE_TARGET) 2207 use_ppr = 0; 2208 2209 /* 2210 * Both the PPR message and SDTR message require the 2211 * goal syncrate to be limited to what the target device 2212 * is capable of handling (based on whether an LVD->SE 2213 * expander is on the bus), so combine these two cases. 2214 * Regardless, guarantee that if we are using WDTR and SDTR 2215 * messages that WDTR comes first. 2216 */ 2217 if (use_ppr || (dosync && !dowide)) { 2218 2219 period = tinfo->goal.period; 2220 ppr_options = tinfo->goal.ppr_options; 2221 if (use_ppr == 0) 2222 ppr_options = 0; 2223 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2224 &ppr_options, devinfo->role); 2225 offset = tinfo->goal.offset; 2226 ahc_validate_offset(ahc, tinfo, rate, &offset, 2227 use_ppr ? tinfo->goal.width 2228 : tinfo->current.width, 2229 devinfo->role); 2230 if (use_ppr) { 2231 ahc_construct_ppr(ahc, devinfo, period, offset, 2232 tinfo->goal.width, ppr_options); 2233 } else { 2234 ahc_construct_sdtr(ahc, devinfo, period, offset); 2235 } 2236 } else { 2237 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2238 } 2239} 2240 2241/* 2242 * Build a synchronous negotiation message in our message 2243 * buffer based on the input parameters. 2244 */ 2245static void 2246ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2247 u_int period, u_int offset) 2248{ 2249 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2250 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 2251 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 2252 ahc->msgout_buf[ahc->msgout_index++] = period; 2253 ahc->msgout_buf[ahc->msgout_index++] = offset; 2254 ahc->msgout_len += 5; 2255 if (bootverbose) { 2256 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2257 ahc_name(ahc), devinfo->channel, devinfo->target, 2258 devinfo->lun, period, offset); 2259 } 2260} 2261 2262/* 2263 * Build a wide negotiateion message in our message 2264 * buffer based on the input parameters. 2265 */ 2266static void 2267ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2268 u_int bus_width) 2269{ 2270 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2271 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 2272 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 2273 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2274 ahc->msgout_len += 4; 2275 if (bootverbose) { 2276 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2277 ahc_name(ahc), devinfo->channel, devinfo->target, 2278 devinfo->lun, bus_width); 2279 } 2280} 2281 2282/* 2283 * Build a parallel protocol request message in our message 2284 * buffer based on the input parameters. 2285 */ 2286static void 2287ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2288 u_int period, u_int offset, u_int bus_width, 2289 u_int ppr_options) 2290{ 2291 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2292 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; 2293 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; 2294 ahc->msgout_buf[ahc->msgout_index++] = period; 2295 ahc->msgout_buf[ahc->msgout_index++] = 0; 2296 ahc->msgout_buf[ahc->msgout_index++] = offset; 2297 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2298 ahc->msgout_buf[ahc->msgout_index++] = ppr_options; 2299 ahc->msgout_len += 8; 2300 if (bootverbose) { 2301 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2302 "offset %x, ppr_options %x\n", ahc_name(ahc), 2303 devinfo->channel, devinfo->target, devinfo->lun, 2304 bus_width, period, offset, ppr_options); 2305 } 2306} 2307 2308/* 2309 * Clear any active message state. 2310 */ 2311static void 2312ahc_clear_msg_state(struct ahc_softc *ahc) 2313{ 2314 ahc->msgout_len = 0; 2315 ahc->msgin_index = 0; 2316 ahc->msg_type = MSG_TYPE_NONE; 2317 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2318 /* 2319 * The target didn't care to respond to our 2320 * message request, so clear ATN. 2321 */ 2322 ahc_outb(ahc, CLRSINT1, CLRATNO); 2323 } 2324 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2325} 2326 2327/* 2328 * Manual message loop handler. 2329 */ 2330static void 2331ahc_handle_message_phase(struct ahc_softc *ahc) 2332{ 2333 struct ahc_devinfo devinfo; 2334 u_int bus_phase; 2335 int end_session; 2336 2337 ahc_fetch_devinfo(ahc, &devinfo); 2338 end_session = FALSE; 2339 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2340 2341reswitch: 2342 switch (ahc->msg_type) { 2343 case MSG_TYPE_INITIATOR_MSGOUT: 2344 { 2345 int lastbyte; 2346 int phasemis; 2347 int msgdone; 2348 2349 if (ahc->msgout_len == 0) 2350 panic("HOST_MSG_LOOP interrupt with no active message"); 2351 2352 phasemis = bus_phase != P_MESGOUT; 2353 if (phasemis) { 2354 if (bus_phase == P_MESGIN) { 2355 /* 2356 * Change gears and see if 2357 * this messages is of interest to 2358 * us or should be passed back to 2359 * the sequencer. 2360 */ 2361 ahc_outb(ahc, CLRSINT1, CLRATNO); 2362 ahc->send_msg_perror = FALSE; 2363 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2364 ahc->msgin_index = 0; 2365 goto reswitch; 2366 } 2367 end_session = TRUE; 2368 break; 2369 } 2370 2371 if (ahc->send_msg_perror) { 2372 ahc_outb(ahc, CLRSINT1, CLRATNO); 2373 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2374 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2375 break; 2376 } 2377 2378 msgdone = ahc->msgout_index == ahc->msgout_len; 2379 if (msgdone) { 2380 /* 2381 * The target has requested a retry. 2382 * Re-assert ATN, reset our message index to 2383 * 0, and try again. 2384 */ 2385 ahc->msgout_index = 0; 2386 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2387 } 2388 2389 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2390 if (lastbyte) { 2391 /* Last byte is signified by dropping ATN */ 2392 ahc_outb(ahc, CLRSINT1, CLRATNO); 2393 } 2394 2395 /* 2396 * Clear our interrupt status and present 2397 * the next byte on the bus. 2398 */ 2399 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2400 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2401 break; 2402 } 2403 case MSG_TYPE_INITIATOR_MSGIN: 2404 { 2405 int phasemis; 2406 int message_done; 2407 2408 phasemis = bus_phase != P_MESGIN; 2409 2410 if (phasemis) { 2411 ahc->msgin_index = 0; 2412 if (bus_phase == P_MESGOUT 2413 && (ahc->send_msg_perror == TRUE 2414 || (ahc->msgout_len != 0 2415 && ahc->msgout_index == 0))) { 2416 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2417 goto reswitch; 2418 } 2419 end_session = TRUE; 2420 break; 2421 } 2422 2423 /* Pull the byte in without acking it */ 2424 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2425 2426 message_done = ahc_parse_msg(ahc, &devinfo); 2427 2428 if (message_done) { 2429 /* 2430 * Clear our incoming message buffer in case there 2431 * is another message following this one. 2432 */ 2433 ahc->msgin_index = 0; 2434 2435 /* 2436 * If this message illicited a response, 2437 * assert ATN so the target takes us to the 2438 * message out phase. 2439 */ 2440 if (ahc->msgout_len != 0) 2441 ahc_outb(ahc, SCSISIGO, 2442 ahc_inb(ahc, SCSISIGO) | ATNO); 2443 } else 2444 ahc->msgin_index++; 2445 2446 /* Ack the byte */ 2447 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2448 ahc_inb(ahc, SCSIDATL); 2449 break; 2450 } 2451 case MSG_TYPE_TARGET_MSGIN: 2452 { 2453 int msgdone; 2454 int msgout_request; 2455 2456 if (ahc->msgout_len == 0) 2457 panic("Target MSGIN with no active message"); 2458 2459 /* 2460 * If we interrupted a mesgout session, the initiator 2461 * will not know this until our first REQ. So, we 2462 * only honor mesgout requests after we've sent our 2463 * first byte. 2464 */ 2465 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2466 && ahc->msgout_index > 0) 2467 msgout_request = TRUE; 2468 else 2469 msgout_request = FALSE; 2470 2471 if (msgout_request) { 2472 2473 /* 2474 * Change gears and see if 2475 * this messages is of interest to 2476 * us or should be passed back to 2477 * the sequencer. 2478 */ 2479 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2480 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2481 ahc->msgin_index = 0; 2482 /* Dummy read to REQ for first byte */ 2483 ahc_inb(ahc, SCSIDATL); 2484 ahc_outb(ahc, SXFRCTL0, 2485 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2486 break; 2487 } 2488 2489 msgdone = ahc->msgout_index == ahc->msgout_len; 2490 if (msgdone) { 2491 ahc_outb(ahc, SXFRCTL0, 2492 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2493 end_session = TRUE; 2494 break; 2495 } 2496 2497 /* 2498 * Present the next byte on the bus. 2499 */ 2500 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2501 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2502 break; 2503 } 2504 case MSG_TYPE_TARGET_MSGOUT: 2505 { 2506 int lastbyte; 2507 int msgdone; 2508 2509 /* 2510 * The initiator signals that this is 2511 * the last byte by dropping ATN. 2512 */ 2513 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2514 2515 /* 2516 * Read the latched byte, but turn off SPIOEN first 2517 * so that we don't inadvertantly cause a REQ for the 2518 * next byte. 2519 */ 2520 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2521 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2522 msgdone = ahc_parse_msg(ahc, &devinfo); 2523 if (msgdone == MSGLOOP_TERMINATED) { 2524 /* 2525 * The message is *really* done in that it caused 2526 * us to go to bus free. The sequencer has already 2527 * been reset at this point, so pull the ejection 2528 * handle. 2529 */ 2530 return; 2531 } 2532 2533 ahc->msgin_index++; 2534 2535 /* 2536 * XXX Read spec about initiator dropping ATN too soon 2537 * and use msgdone to detect it. 2538 */ 2539 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2540 ahc->msgin_index = 0; 2541 2542 /* 2543 * If this message illicited a response, transition 2544 * to the Message in phase and send it. 2545 */ 2546 if (ahc->msgout_len != 0) { 2547 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2548 ahc_outb(ahc, SXFRCTL0, 2549 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2550 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2551 ahc->msgin_index = 0; 2552 break; 2553 } 2554 } 2555 2556 if (lastbyte) 2557 end_session = TRUE; 2558 else { 2559 /* Ask for the next byte. */ 2560 ahc_outb(ahc, SXFRCTL0, 2561 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2562 } 2563 2564 break; 2565 } 2566 default: 2567 panic("Unknown REQINIT message type"); 2568 } 2569 2570 if (end_session) { 2571 ahc_clear_msg_state(ahc); 2572 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2573 } else 2574 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2575} 2576 2577/* 2578 * See if we sent a particular extended message to the target. 2579 * If "full" is true, return true only if the target saw the full 2580 * message. If "full" is false, return true if the target saw at 2581 * least the first byte of the message. 2582 */ 2583static int 2584ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 2585{ 2586 int found; 2587 u_int index; 2588 2589 found = FALSE; 2590 index = 0; 2591 2592 while (index < ahc->msgout_len) { 2593 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2594 u_int end_index; 2595 2596 end_index = index + 1 + ahc->msgout_buf[index + 1]; 2597 if (ahc->msgout_buf[index+2] == msgval 2598 && type == AHCMSG_EXT) { 2599 2600 if (full) { 2601 if (ahc->msgout_index > end_index) 2602 found = TRUE; 2603 } else if (ahc->msgout_index > index) 2604 found = TRUE; 2605 } 2606 index = end_index; 2607 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2608 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2609 2610 /* Skip tag type and tag id or residue param*/ 2611 index += 2; 2612 } else { 2613 /* Single byte message */ 2614 if (type == AHCMSG_1B 2615 && ahc->msgout_buf[index] == msgval 2616 && ahc->msgout_index > index) 2617 found = TRUE; 2618 index++; 2619 } 2620 2621 if (found) 2622 break; 2623 } 2624 return (found); 2625} 2626 2627/* 2628 * Wait for a complete incomming message, parse it, and respond accordingly. 2629 */ 2630static int 2631ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2632{ 2633 struct ahc_initiator_tinfo *tinfo; 2634 struct ahc_tmode_tstate *tstate; 2635 int reject; 2636 int done; 2637 int response; 2638 u_int targ_scsirate; 2639 2640 done = MSGLOOP_IN_PROG; 2641 response = FALSE; 2642 reject = FALSE; 2643 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2644 devinfo->target, &tstate); 2645 targ_scsirate = tinfo->scsirate; 2646 2647 /* 2648 * Parse as much of the message as is availible, 2649 * rejecting it if we don't support it. When 2650 * the entire message is availible and has been 2651 * handled, return MSGLOOP_MSGCOMPLETE, indicating 2652 * that we have parsed an entire message. 2653 * 2654 * In the case of extended messages, we accept the length 2655 * byte outright and perform more checking once we know the 2656 * extended message type. 2657 */ 2658 switch (ahc->msgin_buf[0]) { 2659 case MSG_MESSAGE_REJECT: 2660 response = ahc_handle_msg_reject(ahc, devinfo); 2661 /* FALLTHROUGH */ 2662 case MSG_NOOP: 2663 done = MSGLOOP_MSGCOMPLETE; 2664 break; 2665 case MSG_EXTENDED: 2666 { 2667 /* Wait for enough of the message to begin validation */ 2668 if (ahc->msgin_index < 2) 2669 break; 2670 switch (ahc->msgin_buf[2]) { 2671 case MSG_EXT_SDTR: 2672 { 2673 struct ahc_syncrate *syncrate; 2674 u_int period; 2675 u_int ppr_options; 2676 u_int offset; 2677 u_int saved_offset; 2678 2679 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2680 reject = TRUE; 2681 break; 2682 } 2683 2684 /* 2685 * Wait until we have both args before validating 2686 * and acting on this message. 2687 * 2688 * Add one to MSG_EXT_SDTR_LEN to account for 2689 * the extended message preamble. 2690 */ 2691 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2692 break; 2693 2694 period = ahc->msgin_buf[3]; 2695 ppr_options = 0; 2696 saved_offset = offset = ahc->msgin_buf[4]; 2697 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2698 &ppr_options, 2699 devinfo->role); 2700 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 2701 targ_scsirate & WIDEXFER, 2702 devinfo->role); 2703 if (bootverbose) { 2704 printf("(%s:%c:%d:%d): Received " 2705 "SDTR period %x, offset %x\n\t" 2706 "Filtered to period %x, offset %x\n", 2707 ahc_name(ahc), devinfo->channel, 2708 devinfo->target, devinfo->lun, 2709 ahc->msgin_buf[3], saved_offset, 2710 period, offset); 2711 } 2712 ahc_set_syncrate(ahc, devinfo, 2713 syncrate, period, 2714 offset, ppr_options, 2715 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2716 /*paused*/TRUE); 2717 2718 /* 2719 * See if we initiated Sync Negotiation 2720 * and didn't have to fall down to async 2721 * transfers. 2722 */ 2723 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 2724 /* We started it */ 2725 if (saved_offset != offset) { 2726 /* Went too low - force async */ 2727 reject = TRUE; 2728 } 2729 } else { 2730 /* 2731 * Send our own SDTR in reply 2732 */ 2733 if (bootverbose 2734 && devinfo->role == ROLE_INITIATOR) { 2735 printf("(%s:%c:%d:%d): Target " 2736 "Initiated SDTR\n", 2737 ahc_name(ahc), devinfo->channel, 2738 devinfo->target, devinfo->lun); 2739 } 2740 ahc->msgout_index = 0; 2741 ahc->msgout_len = 0; 2742 ahc_construct_sdtr(ahc, devinfo, 2743 period, offset); 2744 ahc->msgout_index = 0; 2745 response = TRUE; 2746 } 2747 done = MSGLOOP_MSGCOMPLETE; 2748 break; 2749 } 2750 case MSG_EXT_WDTR: 2751 { 2752 u_int bus_width; 2753 u_int saved_width; 2754 u_int sending_reply; 2755 2756 sending_reply = FALSE; 2757 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 2758 reject = TRUE; 2759 break; 2760 } 2761 2762 /* 2763 * Wait until we have our arg before validating 2764 * and acting on this message. 2765 * 2766 * Add one to MSG_EXT_WDTR_LEN to account for 2767 * the extended message preamble. 2768 */ 2769 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 2770 break; 2771 2772 bus_width = ahc->msgin_buf[3]; 2773 saved_width = bus_width; 2774 ahc_validate_width(ahc, tinfo, &bus_width, 2775 devinfo->role); 2776 if (bootverbose) { 2777 printf("(%s:%c:%d:%d): Received WDTR " 2778 "%x filtered to %x\n", 2779 ahc_name(ahc), devinfo->channel, 2780 devinfo->target, devinfo->lun, 2781 saved_width, bus_width); 2782 } 2783 2784 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 2785 /* 2786 * Don't send a WDTR back to the 2787 * target, since we asked first. 2788 * If the width went higher than our 2789 * request, reject it. 2790 */ 2791 if (saved_width > bus_width) { 2792 reject = TRUE; 2793 printf("(%s:%c:%d:%d): requested %dBit " 2794 "transfers. Rejecting...\n", 2795 ahc_name(ahc), devinfo->channel, 2796 devinfo->target, devinfo->lun, 2797 8 * (0x01 << bus_width)); 2798 bus_width = 0; 2799 } 2800 } else { 2801 /* 2802 * Send our own WDTR in reply 2803 */ 2804 if (bootverbose 2805 && devinfo->role == ROLE_INITIATOR) { 2806 printf("(%s:%c:%d:%d): Target " 2807 "Initiated WDTR\n", 2808 ahc_name(ahc), devinfo->channel, 2809 devinfo->target, devinfo->lun); 2810 } 2811 ahc->msgout_index = 0; 2812 ahc->msgout_len = 0; 2813 ahc_construct_wdtr(ahc, devinfo, bus_width); 2814 ahc->msgout_index = 0; 2815 response = TRUE; 2816 sending_reply = TRUE; 2817 } 2818 ahc_set_width(ahc, devinfo, bus_width, 2819 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2820 /*paused*/TRUE); 2821 /* After a wide message, we are async */ 2822 ahc_set_syncrate(ahc, devinfo, 2823 /*syncrate*/NULL, /*period*/0, 2824 /*offset*/0, /*ppr_options*/0, 2825 AHC_TRANS_ACTIVE, /*paused*/TRUE); 2826 if (sending_reply == FALSE && reject == FALSE) { 2827 2828 if (tinfo->goal.period) { 2829 ahc->msgout_index = 0; 2830 ahc->msgout_len = 0; 2831 ahc_build_transfer_msg(ahc, devinfo); 2832 ahc->msgout_index = 0; 2833 response = TRUE; 2834 } 2835 } 2836 done = MSGLOOP_MSGCOMPLETE; 2837 break; 2838 } 2839 case MSG_EXT_PPR: 2840 { 2841 struct ahc_syncrate *syncrate; 2842 u_int period; 2843 u_int offset; 2844 u_int bus_width; 2845 u_int ppr_options; 2846 u_int saved_width; 2847 u_int saved_offset; 2848 u_int saved_ppr_options; 2849 2850 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 2851 reject = TRUE; 2852 break; 2853 } 2854 2855 /* 2856 * Wait until we have all args before validating 2857 * and acting on this message. 2858 * 2859 * Add one to MSG_EXT_PPR_LEN to account for 2860 * the extended message preamble. 2861 */ 2862 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 2863 break; 2864 2865 period = ahc->msgin_buf[3]; 2866 offset = ahc->msgin_buf[5]; 2867 bus_width = ahc->msgin_buf[6]; 2868 saved_width = bus_width; 2869 ppr_options = ahc->msgin_buf[7]; 2870 /* 2871 * According to the spec, a DT only 2872 * period factor with no DT option 2873 * set implies async. 2874 */ 2875 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 2876 && period == 9) 2877 offset = 0; 2878 saved_ppr_options = ppr_options; 2879 saved_offset = offset; 2880 2881 /* 2882 * Mask out any options we don't support 2883 * on any controller. Transfer options are 2884 * only available if we are negotiating wide. 2885 */ 2886 ppr_options &= MSG_EXT_PPR_DT_REQ; 2887 if (bus_width == 0) 2888 ppr_options = 0; 2889 2890 ahc_validate_width(ahc, tinfo, &bus_width, 2891 devinfo->role); 2892 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2893 &ppr_options, 2894 devinfo->role); 2895 ahc_validate_offset(ahc, tinfo, syncrate, 2896 &offset, bus_width, 2897 devinfo->role); 2898 2899 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 2900 /* 2901 * If we are unable to do any of the 2902 * requested options (we went too low), 2903 * then we'll have to reject the message. 2904 */ 2905 if (saved_width > bus_width 2906 || saved_offset != offset 2907 || saved_ppr_options != ppr_options) { 2908 reject = TRUE; 2909 period = 0; 2910 offset = 0; 2911 bus_width = 0; 2912 ppr_options = 0; 2913 syncrate = NULL; 2914 } 2915 } else { 2916 if (devinfo->role != ROLE_TARGET) 2917 printf("(%s:%c:%d:%d): Target " 2918 "Initiated PPR\n", 2919 ahc_name(ahc), devinfo->channel, 2920 devinfo->target, devinfo->lun); 2921 else 2922 printf("(%s:%c:%d:%d): Initiator " 2923 "Initiated PPR\n", 2924 ahc_name(ahc), devinfo->channel, 2925 devinfo->target, devinfo->lun); 2926 ahc->msgout_index = 0; 2927 ahc->msgout_len = 0; 2928 ahc_construct_ppr(ahc, devinfo, period, offset, 2929 bus_width, ppr_options); 2930 ahc->msgout_index = 0; 2931 response = TRUE; 2932 } 2933 if (bootverbose) { 2934 printf("(%s:%c:%d:%d): Received PPR width %x, " 2935 "period %x, offset %x,options %x\n" 2936 "\tFiltered to width %x, period %x, " 2937 "offset %x, options %x\n", 2938 ahc_name(ahc), devinfo->channel, 2939 devinfo->target, devinfo->lun, 2940 saved_width, ahc->msgin_buf[3], 2941 saved_offset, saved_ppr_options, 2942 bus_width, period, offset, ppr_options); 2943 } 2944 ahc_set_width(ahc, devinfo, bus_width, 2945 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2946 /*paused*/TRUE); 2947 ahc_set_syncrate(ahc, devinfo, 2948 syncrate, period, 2949 offset, ppr_options, 2950 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 2951 /*paused*/TRUE); 2952 done = MSGLOOP_MSGCOMPLETE; 2953 break; 2954 } 2955 default: 2956 /* Unknown extended message. Reject it. */ 2957 reject = TRUE; 2958 break; 2959 } 2960 break; 2961 } 2962 case MSG_BUS_DEV_RESET: 2963 ahc_handle_devreset(ahc, devinfo, 2964 CAM_BDR_SENT, 2965 "Bus Device Reset Received", 2966 /*verbose_level*/0); 2967 ahc_restart(ahc); 2968 done = MSGLOOP_TERMINATED; 2969 break; 2970 case MSG_ABORT_TAG: 2971 case MSG_ABORT: 2972 case MSG_CLEAR_QUEUE: 2973#ifdef AHC_TARGET_MODE 2974 /* Target mode messages */ 2975 if (devinfo->role != ROLE_TARGET) { 2976 reject = TRUE; 2977 break; 2978 } 2979 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 2980 devinfo->lun, 2981 ahc->msgin_buf[0] == MSG_ABORT_TAG 2982 ? SCB_LIST_NULL 2983 : ahc_inb(ahc, INITIATOR_TAG), 2984 ROLE_TARGET, CAM_REQ_ABORTED); 2985 2986 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 2987 if (tstate != NULL) { 2988 struct ahc_tmode_lstate* lstate; 2989 2990 lstate = tstate->enabled_luns[devinfo->lun]; 2991 if (lstate != NULL) { 2992 ahc_queue_lstate_event(ahc, lstate, 2993 devinfo->our_scsiid, 2994 ahc->msgin_buf[0], 2995 /*arg*/0); 2996 ahc_send_lstate_events(ahc, lstate); 2997 } 2998 } 2999 done = MSGLOOP_MSGCOMPLETE; 3000 break; 3001#endif 3002 case MSG_TERM_IO_PROC: 3003 default: 3004 reject = TRUE; 3005 break; 3006 } 3007 3008 if (reject) { 3009 /* 3010 * Setup to reject the message. 3011 */ 3012 ahc->msgout_index = 0; 3013 ahc->msgout_len = 1; 3014 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3015 done = MSGLOOP_MSGCOMPLETE; 3016 response = TRUE; 3017 } 3018 3019 if (done != MSGLOOP_IN_PROG && !response) 3020 /* Clear the outgoing message buffer */ 3021 ahc->msgout_len = 0; 3022 3023 return (done); 3024} 3025 3026/* 3027 * Process a message reject message. 3028 */ 3029static int 3030ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3031{ 3032 /* 3033 * What we care about here is if we had an 3034 * outstanding SDTR or WDTR message for this 3035 * target. If we did, this is a signal that 3036 * the target is refusing negotiation. 3037 */ 3038 struct scb *scb; 3039 struct ahc_initiator_tinfo *tinfo; 3040 struct ahc_tmode_tstate *tstate; 3041 u_int scb_index; 3042 u_int last_msg; 3043 int response = 0; 3044 3045 scb_index = ahc_inb(ahc, SCB_TAG); 3046 scb = ahc_lookup_scb(ahc, scb_index); 3047 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3048 devinfo->our_scsiid, 3049 devinfo->target, &tstate); 3050 /* Might be necessary */ 3051 last_msg = ahc_inb(ahc, LAST_MSG); 3052 3053 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3054 /* 3055 * Target does not support the PPR message. 3056 * Attempt to negotiate SPI-2 style. 3057 */ 3058 if (bootverbose) { 3059 printf("(%s:%c:%d:%d): PPR Rejected. " 3060 "Trying WDTR/SDTR\n", 3061 ahc_name(ahc), devinfo->channel, 3062 devinfo->target, devinfo->lun); 3063 } 3064 tinfo->goal.ppr_options = 0; 3065 tinfo->current.transport_version = 2; 3066 tinfo->goal.transport_version = 2; 3067 ahc->msgout_index = 0; 3068 ahc->msgout_len = 0; 3069 ahc_build_transfer_msg(ahc, devinfo); 3070 ahc->msgout_index = 0; 3071 response = 1; 3072 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3073 3074 /* note 8bit xfers */ 3075 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3076 "8bit transfers\n", ahc_name(ahc), 3077 devinfo->channel, devinfo->target, devinfo->lun); 3078 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3079 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3080 /*paused*/TRUE); 3081 /* 3082 * No need to clear the sync rate. If the target 3083 * did not accept the command, our syncrate is 3084 * unaffected. If the target started the negotiation, 3085 * but rejected our response, we already cleared the 3086 * sync rate before sending our WDTR. 3087 */ 3088 if (tinfo->goal.period) { 3089 3090 /* Start the sync negotiation */ 3091 ahc->msgout_index = 0; 3092 ahc->msgout_len = 0; 3093 ahc_build_transfer_msg(ahc, devinfo); 3094 ahc->msgout_index = 0; 3095 response = 1; 3096 } 3097 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3098 /* note asynch xfers and clear flag */ 3099 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3100 /*offset*/0, /*ppr_options*/0, 3101 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3102 /*paused*/TRUE); 3103 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 3104 "Using asynchronous transfers\n", 3105 ahc_name(ahc), devinfo->channel, 3106 devinfo->target, devinfo->lun); 3107 } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 3108 3109 printf("(%s:%c:%d:%d): refuses tagged commands. Performing " 3110 "non-tagged I/O\n", ahc_name(ahc), 3111 devinfo->channel, devinfo->target, devinfo->lun); 3112 ahc_set_tags(ahc, devinfo, FALSE); 3113 3114 /* 3115 * Resend the identify for this CCB as the target 3116 * may believe that the selection is invalid otherwise. 3117 */ 3118 ahc_outb(ahc, SCB_CONTROL, 3119 ahc_inb(ahc, SCB_CONTROL) & ~MSG_SIMPLE_Q_TAG); 3120 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 3121 ahc_set_transaction_tag(scb, /*enabled*/FALSE, 3122 /*type*/MSG_SIMPLE_Q_TAG); 3123 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3124 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 3125 3126 /* 3127 * This transaction is now at the head of 3128 * the untagged queue for this target. 3129 */ 3130 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3131 struct scb_tailq *untagged_q; 3132 3133 untagged_q = 3134 &(ahc->untagged_queues[devinfo->target_offset]); 3135 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3136 scb->flags |= SCB_UNTAGGEDQ; 3137 } 3138 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3139 scb->hscb->tag); 3140 3141 /* 3142 * Requeue all tagged commands for this target 3143 * currently in our posession so they can be 3144 * converted to untagged commands. 3145 */ 3146 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3147 SCB_GET_CHANNEL(ahc, scb), 3148 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3149 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3150 SEARCH_COMPLETE); 3151 } else { 3152 /* 3153 * Otherwise, we ignore it. 3154 */ 3155 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3156 ahc_name(ahc), devinfo->channel, devinfo->target, 3157 last_msg); 3158 } 3159 return (response); 3160} 3161 3162/* 3163 * Process an ingnore wide residue message. 3164 */ 3165static void 3166ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3167{ 3168 u_int scb_index; 3169 struct scb *scb; 3170 3171 scb_index = ahc_inb(ahc, SCB_TAG); 3172 scb = ahc_lookup_scb(ahc, scb_index); 3173 /* 3174 * XXX Actually check data direction in the sequencer? 3175 * Perhaps add datadir to some spare bits in the hscb? 3176 */ 3177 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3178 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { 3179 /* 3180 * Ignore the message if we haven't 3181 * seen an appropriate data phase yet. 3182 */ 3183 } else { 3184 /* 3185 * If the residual occurred on the last 3186 * transfer and the transfer request was 3187 * expected to end on an odd count, do 3188 * nothing. Otherwise, subtract a byte 3189 * and update the residual count accordingly. 3190 */ 3191 uint32_t sgptr; 3192 3193 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3194 if ((sgptr & SG_LIST_NULL) != 0 3195 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3196 /* 3197 * If the residual occurred on the last 3198 * transfer and the transfer request was 3199 * expected to end on an odd count, do 3200 * nothing. 3201 */ 3202 } else { 3203 struct ahc_dma_seg *sg; 3204 uint32_t data_cnt; 3205 uint32_t data_addr; 3206 3207 /* Pull in the rest of the sgptr */ 3208 sgptr |= (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3209 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3210 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8); 3211 sgptr &= SG_PTR_MASK; 3212 data_cnt = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+2) << 16) 3213 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+1) << 8) 3214 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT)); 3215 3216 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3217 | (ahc_inb(ahc, SHADDR + 2) << 16) 3218 | (ahc_inb(ahc, SHADDR + 1) << 8) 3219 | (ahc_inb(ahc, SHADDR)); 3220 3221 data_cnt += 1; 3222 data_addr -= 1; 3223 3224 sg = ahc_sg_bus_to_virt(scb, sgptr); 3225 /* 3226 * The residual sg ptr points to the next S/G 3227 * to load so we must go back one. 3228 */ 3229 sg--; 3230 if (sg != scb->sg_list 3231 && (sg->len & AHC_SG_LEN_MASK) < data_cnt) { 3232 3233 sg--; 3234 data_cnt = 1 | (sg->len & AHC_DMA_LAST_SEG); 3235 data_addr = sg->addr 3236 + (sg->len & AHC_SG_LEN_MASK) - 1; 3237 3238 /* 3239 * Increment sg so it points to the 3240 * "next" sg. 3241 */ 3242 sg++; 3243 sgptr = ahc_sg_virt_to_bus(scb, sg); 3244 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 3, 3245 sgptr >> 24); 3246 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 2, 3247 sgptr >> 16); 3248 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 1, 3249 sgptr >> 8); 3250 ahc_outb(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3251 } 3252 3253/* XXX What about high address byte??? */ 3254 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24); 3255 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16); 3256 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8); 3257 ahc_outb(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3258 3259/* XXX Perhaps better to just keep the saved address in sram */ 3260 if ((ahc->features & AHC_ULTRA2) != 0) { 3261 ahc_outb(ahc, HADDR + 3, data_addr >> 24); 3262 ahc_outb(ahc, HADDR + 2, data_addr >> 16); 3263 ahc_outb(ahc, HADDR + 1, data_addr >> 8); 3264 ahc_outb(ahc, HADDR, data_addr); 3265 ahc_outb(ahc, DFCNTRL, PRELOADEN); 3266 ahc_outb(ahc, SXFRCTL0, 3267 ahc_inb(ahc, SXFRCTL0) | CLRCHN); 3268 } else { 3269 ahc_outb(ahc, HADDR + 3, data_addr >> 24); 3270 ahc_outb(ahc, HADDR + 2, data_addr >> 16); 3271 ahc_outb(ahc, HADDR + 1, data_addr >> 8); 3272 ahc_outb(ahc, HADDR, data_addr); 3273 } 3274 } 3275 } 3276} 3277 3278/* 3279 * Handle the effects of issuing a bus device reset message. 3280 */ 3281static void 3282ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3283 cam_status status, char *message, int verbose_level) 3284{ 3285#ifdef AHC_TARGET_MODE 3286 struct ahc_tmode_tstate* tstate; 3287 u_int lun; 3288#endif 3289 int found; 3290 3291 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3292 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3293 status); 3294 3295#ifdef AHC_TARGET_MODE 3296 /* 3297 * Send an immediate notify ccb to all target mord peripheral 3298 * drivers affected by this action. 3299 */ 3300 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3301 if (tstate != NULL) { 3302 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3303 struct ahc_tmode_lstate* lstate; 3304 3305 lstate = tstate->enabled_luns[lun]; 3306 if (lstate == NULL) 3307 continue; 3308 3309 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3310 MSG_BUS_DEV_RESET, /*arg*/0); 3311 ahc_send_lstate_events(ahc, lstate); 3312 } 3313 } 3314#endif 3315 3316 /* 3317 * Go back to async/narrow transfers and renegotiate. 3318 */ 3319 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3320 AHC_TRANS_CUR, /*paused*/TRUE); 3321 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3322 /*period*/0, /*offset*/0, /*ppr_options*/0, 3323 AHC_TRANS_CUR, /*paused*/TRUE); 3324 3325 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3326 CAM_LUN_WILDCARD, AC_SENT_BDR); 3327 3328 if (message != NULL 3329 && (verbose_level <= bootverbose)) 3330 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3331 message, devinfo->channel, devinfo->target, found); 3332} 3333 3334#ifdef AHC_TARGET_MODE 3335static void 3336ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3337 struct scb *scb) 3338{ 3339 3340 /* 3341 * To facilitate adding multiple messages together, 3342 * each routine should increment the index and len 3343 * variables instead of setting them explicitly. 3344 */ 3345 ahc->msgout_index = 0; 3346 ahc->msgout_len = 0; 3347 3348 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3349 ahc_build_transfer_msg(ahc, devinfo); 3350 else 3351 panic("ahc_intr: AWAITING target message with no message"); 3352 3353 ahc->msgout_index = 0; 3354 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3355} 3356#endif 3357/**************************** Initialization **********************************/ 3358/* 3359 * Allocate a controller structure for a new device 3360 * and perform initial initializion. 3361 */ 3362struct ahc_softc * 3363ahc_alloc(void *platform_arg, char *name) 3364{ 3365 struct ahc_softc *ahc; 3366 int i; 3367 3368#ifndef __FreeBSD__ 3369 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT); 3370 if (!ahc) { 3371 printf("aic7xxx: cannot malloc softc!\n"); 3372 free(name, M_DEVBUF); 3373 return NULL; 3374 } 3375#else 3376 ahc = device_get_softc((device_t)platform_arg); 3377#endif 3378 memset(ahc, 0, sizeof(*ahc)); 3379 LIST_INIT(&ahc->pending_scbs); 3380 /* We don't know our unit number until the OSM sets it */ 3381 ahc->name = name; 3382 ahc->unit = -1; 3383 for (i = 0; i < 16; i++) 3384 TAILQ_INIT(&ahc->untagged_queues[i]); 3385 if (ahc_platform_alloc(ahc, platform_arg) != 0) { 3386 ahc_free(ahc); 3387 ahc = NULL; 3388 } 3389 return (ahc); 3390} 3391 3392int 3393ahc_softc_init(struct ahc_softc *ahc, struct ahc_probe_config *config) 3394{ 3395 3396 ahc->chip = config->chip; 3397 ahc->features = config->features; 3398 ahc->bugs = config->bugs; 3399 ahc->flags = config->flags; 3400 ahc->channel = config->channel; 3401 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS); 3402 ahc->description = config->description; 3403 /* The IRQMS bit is only valid on VL and EISA chips */ 3404 if ((ahc->chip & AHC_PCI) != 0) 3405 ahc->unpause &= ~IRQMS; 3406 ahc->pause = ahc->unpause | PAUSE; 3407 /* XXX The shared scb data stuff should be deprecated */ 3408 if (ahc->scb_data == NULL) { 3409 ahc->scb_data = malloc(sizeof(*ahc->scb_data), 3410 M_DEVBUF, M_NOWAIT); 3411 if (ahc->scb_data == NULL) 3412 return (ENOMEM); 3413 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); 3414 } 3415 3416 return (0); 3417} 3418 3419void 3420ahc_softc_insert(struct ahc_softc *ahc) 3421{ 3422 struct ahc_softc *list_ahc; 3423 3424#if AHC_PCI_CONFIG > 0 3425 /* 3426 * Second Function PCI devices need to inherit some 3427 * settings from function 0. 3428 */ 3429 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI 3430 && (ahc->features & AHC_MULTI_FUNC) != 0) { 3431 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3432 ahc_dev_softc_t list_pci; 3433 ahc_dev_softc_t pci; 3434 3435 list_pci = list_ahc->dev_softc; 3436 pci = ahc->dev_softc; 3437 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci) 3438 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) { 3439 struct ahc_softc *master; 3440 struct ahc_softc *slave; 3441 3442 if (ahc_get_pci_function(list_pci) == 0) { 3443 master = list_ahc; 3444 slave = ahc; 3445 } else { 3446 master = ahc; 3447 slave = list_ahc; 3448 } 3449 slave->flags &= ~AHC_BIOS_ENABLED; 3450 slave->flags |= 3451 master->flags & AHC_BIOS_ENABLED; 3452 slave->flags &= ~AHC_PRIMARY_CHANNEL; 3453 slave->flags |= 3454 master->flags & AHC_PRIMARY_CHANNEL; 3455 break; 3456 } 3457 } 3458 } 3459#endif 3460 3461 /* 3462 * Insertion sort into our list of softcs. 3463 */ 3464 list_ahc = TAILQ_FIRST(&ahc_tailq); 3465 while (list_ahc != NULL 3466 && ahc_softc_comp(list_ahc, ahc) <= 0) 3467 list_ahc = TAILQ_NEXT(list_ahc, links); 3468 if (list_ahc != NULL) 3469 TAILQ_INSERT_BEFORE(list_ahc, ahc, links); 3470 else 3471 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); 3472 ahc->init_level++; 3473} 3474 3475void 3476ahc_set_unit(struct ahc_softc *ahc, int unit) 3477{ 3478 ahc->unit = unit; 3479} 3480 3481void 3482ahc_set_name(struct ahc_softc *ahc, char *name) 3483{ 3484 if (ahc->name != NULL) 3485 free(ahc->name, M_DEVBUF); 3486 ahc->name = name; 3487} 3488 3489void 3490ahc_free(struct ahc_softc *ahc) 3491{ 3492 int i; 3493 3494 ahc_fini_scbdata(ahc); 3495 switch (ahc->init_level) { 3496 default: 3497 case 5: 3498 ahc_shutdown(ahc); 3499 TAILQ_REMOVE(&ahc_tailq, ahc, links); 3500 /* FALLTHROUGH */ 3501 case 4: 3502 ahc_dmamap_unload(ahc, ahc->shared_data_dmat, 3503 ahc->shared_data_dmamap); 3504 /* FALLTHROUGH */ 3505 case 3: 3506 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo, 3507 ahc->shared_data_dmamap); 3508 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat, 3509 ahc->shared_data_dmamap); 3510 /* FALLTHROUGH */ 3511 case 2: 3512 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat); 3513 case 1: 3514#ifndef __linux__ 3515 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat); 3516#endif 3517 break; 3518 case 0: 3519 break; 3520 } 3521 3522#ifndef __linux__ 3523 ahc_dma_tag_destroy(ahc, ahc->parent_dmat); 3524#endif 3525 ahc_platform_free(ahc); 3526 for (i = 0; i < AHC_NUM_TARGETS; i++) { 3527 struct ahc_tmode_tstate *tstate; 3528 3529 tstate = ahc->enabled_targets[i]; 3530 if (tstate != NULL) { 3531#if AHC_TARGET_MODE 3532 int j; 3533 3534 for (j = 0; j < AHC_NUM_LUNS; j++) { 3535 struct ahc_tmode_lstate *lstate; 3536 3537 lstate = tstate->enabled_luns[j]; 3538 if (lstate != NULL) { 3539 xpt_free_path(lstate->path); 3540 free(lstate, M_DEVBUF); 3541 } 3542 } 3543#endif 3544 free(tstate, M_DEVBUF); 3545 } 3546 } 3547#if AHC_TARGET_MODE 3548 if (ahc->black_hole != NULL) { 3549 xpt_free_path(ahc->black_hole->path); 3550 free(ahc->black_hole, M_DEVBUF); 3551 } 3552#endif 3553 if (ahc->name != NULL) 3554 free(ahc->name, M_DEVBUF); 3555#ifndef __FreeBSD__ 3556 free(ahc, M_DEVBUF); 3557#endif 3558 return; 3559} 3560 3561void 3562ahc_shutdown(void *arg) 3563{ 3564 struct ahc_softc *ahc; 3565 int i; 3566 3567 ahc = (struct ahc_softc *)arg; 3568 3569 /* This will reset most registers to 0, but not all */ 3570 ahc_reset(ahc); 3571 ahc_outb(ahc, SCSISEQ, 0); 3572 ahc_outb(ahc, SXFRCTL0, 0); 3573 ahc_outb(ahc, DSPCISTATUS, 0); 3574 3575 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 3576 ahc_outb(ahc, i, 0); 3577} 3578 3579/* 3580 * Reset the controller and record some information about it 3581 * that is only availabel just after a reset. 3582 */ 3583int 3584ahc_reset(struct ahc_softc *ahc) 3585{ 3586 u_int sblkctl; 3587 u_int sxfrctl1_a, sxfrctl1_b; 3588 int wait; 3589 3590 /* 3591 * Preserve the value of the SXFRCTL1 register for all channels. 3592 * It contains settings that affect termination and we don't want 3593 * to disturb the integrity of the bus. 3594 */ 3595 ahc_pause(ahc); 3596 sxfrctl1_b = 0; 3597 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 3598 u_int sblkctl; 3599 3600 /* 3601 * Save channel B's settings in case this chip 3602 * is setup for TWIN channel operation. 3603 */ 3604 sblkctl = ahc_inb(ahc, SBLKCTL); 3605 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 3606 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 3607 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 3608 } 3609 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 3610 3611 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 3612 3613 /* 3614 * Ensure that the reset has finished 3615 */ 3616 wait = 1000; 3617 do { 3618 ahc_delay(1000); 3619 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 3620 3621 if (wait == 0) { 3622 printf("%s: WARNING - Failed chip reset! " 3623 "Trying to initialize anyway.\n", ahc_name(ahc)); 3624 } 3625 ahc_outb(ahc, HCNTRL, ahc->pause); 3626 3627 /* Determine channel configuration */ 3628 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 3629 /* No Twin Channel PCI cards */ 3630 if ((ahc->chip & AHC_PCI) != 0) 3631 sblkctl &= ~SELBUSB; 3632 switch (sblkctl) { 3633 case 0: 3634 /* Single Narrow Channel */ 3635 break; 3636 case 2: 3637 /* Wide Channel */ 3638 ahc->features |= AHC_WIDE; 3639 break; 3640 case 8: 3641 /* Twin Channel */ 3642 ahc->features |= AHC_TWIN; 3643 break; 3644 default: 3645 printf(" Unsupported adapter type. Ignoring\n"); 3646 return(-1); 3647 } 3648 3649 /* 3650 * Reload sxfrctl1. 3651 * 3652 * We must always initialize STPWEN to 1 before we 3653 * restore the saved values. STPWEN is initialized 3654 * to a tri-state condition which can only be cleared 3655 * by turning it on. 3656 */ 3657 if ((ahc->features & AHC_TWIN) != 0) { 3658 u_int sblkctl; 3659 3660 sblkctl = ahc_inb(ahc, SBLKCTL); 3661 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 3662 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 3663 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 3664 } 3665 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 3666 3667#ifdef AHC_DUMP_SEQ 3668 if (ahc->init_level == 0) 3669 ahc_dumpseq(ahc); 3670#endif 3671 3672 return (0); 3673} 3674 3675/* 3676 * Determine the number of SCBs available on the controller 3677 */ 3678int 3679ahc_probe_scbs(struct ahc_softc *ahc) { 3680 int i; 3681 3682 for (i = 0; i < AHC_SCB_MAX; i++) { 3683 3684 ahc_outb(ahc, SCBPTR, i); 3685 ahc_outb(ahc, SCB_BASE, i); 3686 if (ahc_inb(ahc, SCB_BASE) != i) 3687 break; 3688 ahc_outb(ahc, SCBPTR, 0); 3689 if (ahc_inb(ahc, SCB_BASE) != 0) 3690 break; 3691 } 3692 return (i); 3693} 3694 3695void 3696ahc_init_probe_config(struct ahc_probe_config *probe_config) 3697{ 3698 probe_config->description = NULL; 3699 probe_config->channel = 'A'; 3700 probe_config->channel_b = 'B'; 3701 probe_config->chip = AHC_NONE; 3702 probe_config->features = AHC_FENONE; 3703 probe_config->bugs = AHC_BUGNONE; 3704 probe_config->flags = AHC_FNONE; 3705} 3706 3707static void 3708ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3709{ 3710 bus_addr_t *baddr; 3711 3712 baddr = (bus_addr_t *)arg; 3713 *baddr = segs->ds_addr; 3714} 3715 3716static void 3717ahc_build_free_scb_list(struct ahc_softc *ahc) 3718{ 3719 int i; 3720 3721 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 3722 ahc_outb(ahc, SCBPTR, i); 3723 3724 /* Clear the control byte. */ 3725 ahc_outb(ahc, SCB_CONTROL, 0); 3726 3727 /* Set the next pointer */ 3728 if ((ahc->flags & AHC_PAGESCBS) != 0) 3729 ahc_outb(ahc, SCB_NEXT, i+1); 3730 else 3731 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 3732 3733 /* Make the tag number invalid */ 3734 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 3735 } 3736 3737 /* Make sure that the last SCB terminates the free list */ 3738 ahc_outb(ahc, SCBPTR, i-1); 3739 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 3740 3741 /* Ensure we clear the 0 SCB's control byte. */ 3742 ahc_outb(ahc, SCBPTR, 0); 3743 ahc_outb(ahc, SCB_CONTROL, 0); 3744} 3745 3746static int 3747ahc_init_scbdata(struct ahc_softc *ahc) 3748{ 3749 struct scb_data *scb_data; 3750 3751 scb_data = ahc->scb_data; 3752 SLIST_INIT(&scb_data->free_scbs); 3753 SLIST_INIT(&scb_data->sg_maps); 3754 3755 /* Allocate SCB resources */ 3756 scb_data->scbarray = 3757 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX, 3758 M_DEVBUF, M_NOWAIT); 3759 if (scb_data->scbarray == NULL) 3760 return (ENOMEM); 3761 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX); 3762 3763 /* Determine the number of hardware SCBs and initialize them */ 3764 3765 scb_data->maxhscbs = ahc_probe_scbs(ahc); 3766 if ((ahc->flags & AHC_PAGESCBS) != 0) { 3767 /* SCB 0 heads the free list */ 3768 ahc_outb(ahc, FREE_SCBH, 0); 3769 } else { 3770 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 3771 } 3772 3773 if (ahc->scb_data->maxhscbs == 0) { 3774 printf("%s: No SCB space found\n", ahc_name(ahc)); 3775 return (ENXIO); 3776 } 3777 3778 ahc_build_free_scb_list(ahc); 3779 3780 /* 3781 * Create our DMA tags. These tags define the kinds of device 3782 * accessible memory allocations and memory mappings we will 3783 * need to perform during normal operation. 3784 * 3785 * Unless we need to further restrict the allocation, we rely 3786 * on the restrictions of the parent dmat, hence the common 3787 * use of MAXADDR and MAXSIZE. 3788 */ 3789 3790 /* DMA tag for our hardware scb structures */ 3791 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 3792 /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR, 3793 /*highaddr*/BUS_SPACE_MAXADDR, 3794 /*filter*/NULL, /*filterarg*/NULL, 3795 AHC_SCB_MAX * sizeof(struct hardware_scb), 3796 /*nsegments*/1, 3797 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 3798 /*flags*/0, &scb_data->hscb_dmat) != 0) { 3799 goto error_exit; 3800 } 3801 3802 scb_data->init_level++; 3803 3804 /* Allocation for our ccbs */ 3805 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat, 3806 (void **)&scb_data->hscbs, 3807 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) { 3808 goto error_exit; 3809 } 3810 3811 scb_data->init_level++; 3812 3813 /* And permanently map them */ 3814 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap, 3815 scb_data->hscbs, 3816 AHC_SCB_MAX * sizeof(struct hardware_scb), 3817 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0); 3818 3819 scb_data->init_level++; 3820 3821 /* DMA tag for our sense buffers */ 3822 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 3823 /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR, 3824 /*highaddr*/BUS_SPACE_MAXADDR, 3825 /*filter*/NULL, /*filterarg*/NULL, 3826 AHC_SCB_MAX * sizeof(struct scsi_sense_data), 3827 /*nsegments*/1, 3828 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 3829 /*flags*/0, &scb_data->sense_dmat) != 0) { 3830 goto error_exit; 3831 } 3832 3833 scb_data->init_level++; 3834 3835 /* Allocate them */ 3836 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat, 3837 (void **)&scb_data->sense, 3838 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) { 3839 goto error_exit; 3840 } 3841 3842 scb_data->init_level++; 3843 3844 /* And permanently map them */ 3845 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap, 3846 scb_data->sense, 3847 AHC_SCB_MAX * sizeof(struct scsi_sense_data), 3848 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0); 3849 3850 scb_data->init_level++; 3851 3852 /* DMA tag for our S/G structures. We allocate in page sized chunks */ 3853 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 3854 /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR, 3855 /*highaddr*/BUS_SPACE_MAXADDR, 3856 /*filter*/NULL, /*filterarg*/NULL, 3857 PAGE_SIZE, /*nsegments*/1, 3858 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 3859 /*flags*/0, &scb_data->sg_dmat) != 0) { 3860 goto error_exit; 3861 } 3862 3863 scb_data->init_level++; 3864 3865 /* Perform initial CCB allocation */ 3866 memset(scb_data->hscbs, 0, AHC_SCB_MAX * sizeof(struct hardware_scb)); 3867 ahc_alloc_scbs(ahc); 3868 3869 if (scb_data->numscbs == 0) { 3870 printf("%s: ahc_init_scbdata - " 3871 "Unable to allocate initial scbs\n", 3872 ahc_name(ahc)); 3873 goto error_exit; 3874 } 3875 3876 /* 3877 * Tell the sequencer which SCB will be the next one it receives. 3878 */ 3879 ahc->next_queued_scb = ahc_get_scb(ahc); 3880 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 3881 3882 /* 3883 * Note that we were successfull 3884 */ 3885 return (0); 3886 3887error_exit: 3888 3889 return (ENOMEM); 3890} 3891 3892static void 3893ahc_fini_scbdata(struct ahc_softc *ahc) 3894{ 3895 struct scb_data *scb_data; 3896 3897 scb_data = ahc->scb_data; 3898 if (scb_data == NULL) 3899 return; 3900 3901 switch (scb_data->init_level) { 3902 default: 3903 case 7: 3904 { 3905 struct sg_map_node *sg_map; 3906 3907 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 3908 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 3909 ahc_dmamap_unload(ahc, scb_data->sg_dmat, 3910 sg_map->sg_dmamap); 3911 ahc_dmamem_free(ahc, scb_data->sg_dmat, 3912 sg_map->sg_vaddr, 3913 sg_map->sg_dmamap); 3914 free(sg_map, M_DEVBUF); 3915 } 3916 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat); 3917 } 3918 case 6: 3919 ahc_dmamap_unload(ahc, scb_data->sense_dmat, 3920 scb_data->sense_dmamap); 3921 case 5: 3922 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense, 3923 scb_data->sense_dmamap); 3924 ahc_dmamap_destroy(ahc, scb_data->sense_dmat, 3925 scb_data->sense_dmamap); 3926 case 4: 3927 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat); 3928 case 3: 3929 ahc_dmamap_unload(ahc, scb_data->hscb_dmat, 3930 scb_data->hscb_dmamap); 3931 case 2: 3932 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs, 3933 scb_data->hscb_dmamap); 3934 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat, 3935 scb_data->hscb_dmamap); 3936 case 1: 3937 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat); 3938 break; 3939 case 0: 3940 break; 3941 } 3942 if (scb_data->scbarray != NULL) 3943 free(scb_data->scbarray, M_DEVBUF); 3944} 3945 3946void 3947ahc_alloc_scbs(struct ahc_softc *ahc) 3948{ 3949 struct scb_data *scb_data; 3950 struct scb *next_scb; 3951 struct sg_map_node *sg_map; 3952 bus_addr_t physaddr; 3953 struct ahc_dma_seg *segs; 3954 int newcount; 3955 int i; 3956 3957 scb_data = ahc->scb_data; 3958 if (scb_data->numscbs >= AHC_SCB_MAX) 3959 /* Can't allocate any more */ 3960 return; 3961 3962 next_scb = &scb_data->scbarray[scb_data->numscbs]; 3963 3964 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 3965 3966 if (sg_map == NULL) 3967 return; 3968 3969 /* Allocate S/G space for the next batch of SCBS */ 3970 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat, 3971 (void **)&sg_map->sg_vaddr, 3972 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { 3973 free(sg_map, M_DEVBUF); 3974 return; 3975 } 3976 3977 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 3978 3979 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap, 3980 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb, 3981 &sg_map->sg_physaddr, /*flags*/0); 3982 3983 segs = sg_map->sg_vaddr; 3984 physaddr = sg_map->sg_physaddr; 3985 3986 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 3987 for (i = 0; scb_data->numscbs < AHC_SCB_MAX && i < newcount; i++) { 3988 struct scb_platform_data *pdata; 3989#ifndef __linux__ 3990 int error; 3991#endif 3992 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 3993 M_DEVBUF, M_NOWAIT); 3994 if (pdata == NULL) 3995 break; 3996 next_scb->platform_data = pdata; 3997 next_scb->sg_list = segs; 3998 /* 3999 * The sequencer always starts with the second entry. 4000 * The first entry is embedded in the scb. 4001 */ 4002 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4003 next_scb->ahc_softc = ahc; 4004 next_scb->flags = SCB_FREE; 4005#ifndef __linux__ 4006 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0, 4007 &next_scb->dmamap); 4008 if (error != 0) 4009 break; 4010#endif 4011 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4012 next_scb->hscb->tag = ahc->scb_data->numscbs; 4013 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4014 next_scb, links.sle); 4015 segs += AHC_NSEG; 4016 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4017 next_scb++; 4018 ahc->scb_data->numscbs++; 4019 } 4020} 4021 4022void 4023ahc_controller_info(struct ahc_softc *ahc, char *buf) 4024{ 4025 int len; 4026 4027 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4028 buf += len; 4029 if ((ahc->features & AHC_TWIN) != 0) 4030 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " 4031 "B SCSI Id=%d, primary %c, ", 4032 ahc->our_id, ahc->our_id_b, 4033 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4034 else { 4035 const char *type; 4036 4037 if ((ahc->features & AHC_WIDE) != 0) { 4038 type = "Wide"; 4039 } else { 4040 type = "Single"; 4041 } 4042 len = sprintf(buf, "%s Channel %c, SCSI Id=%d, ", 4043 type, ahc->channel, ahc->our_id); 4044 } 4045 buf += len; 4046 4047 if ((ahc->flags & AHC_PAGESCBS) != 0) 4048 sprintf(buf, "%d/%d SCBs", 4049 ahc->scb_data->maxhscbs, AHC_SCB_MAX); 4050 else 4051 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); 4052} 4053 4054/* 4055 * Start the board, ready for normal operation 4056 */ 4057int 4058ahc_init(struct ahc_softc *ahc) 4059{ 4060 int max_targ; 4061 int i; 4062 int term; 4063 u_int scsi_conf; 4064 u_int scsiseq_template; 4065 u_int ultraenb; 4066 u_int discenable; 4067 u_int tagenable; 4068 size_t driver_data_size; 4069 uint32_t physaddr; 4070 4071#ifdef AHC_DEBUG_SEQUENCER 4072 ahc->flags |= AHC_SEQUENCER_DEBUG; 4073#endif 4074 4075#ifdef AHC_PRINT_SRAM 4076 printf("Scratch Ram:"); 4077 for (i = 0x20; i < 0x5f; i++) { 4078 if (((i % 8) == 0) && (i != 0)) { 4079 printf ("\n "); 4080 } 4081 printf (" 0x%x", ahc_inb(ahc, i)); 4082 } 4083 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4084 for (i = 0x70; i < 0x7f; i++) { 4085 if (((i % 8) == 0) && (i != 0)) { 4086 printf ("\n "); 4087 } 4088 printf (" 0x%x", ahc_inb(ahc, i)); 4089 } 4090 } 4091 printf ("\n"); 4092#endif 4093 max_targ = 15; 4094 4095 /* 4096 * Assume we have a board at this stage and it has been reset. 4097 */ 4098 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4099 ahc->our_id = ahc->our_id_b = 7; 4100 4101 /* 4102 * Default to allowing initiator operations. 4103 */ 4104 ahc->flags |= AHC_INITIATORROLE; 4105 4106 /* 4107 * Only allow target mode features if this unit has them enabled. 4108 */ 4109 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4110 ahc->features &= ~AHC_TARGETMODE; 4111 4112#ifndef __linux__ 4113 /* DMA tag for mapping buffers into device visible space. */ 4114 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4115 /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR, 4116 /*highaddr*/BUS_SPACE_MAXADDR, 4117 /*filter*/NULL, /*filterarg*/NULL, 4118 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, 4119 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 4120 /*flags*/BUS_DMA_ALLOCNOW, 4121 &ahc->buffer_dmat) != 0) { 4122 return (ENOMEM); 4123 } 4124#endif 4125 4126 ahc->init_level++; 4127 4128 /* 4129 * DMA tag for our command fifos and other data in system memory 4130 * the card's sequencer must be able to access. For initiator 4131 * roles, we need to allocate space for the the qinfifo and qoutfifo. 4132 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4133 * When providing for the target mode role, we must additionally 4134 * provide space for the incoming target command fifo and an extra 4135 * byte to deal with a dma bug in some chip versions. 4136 */ 4137 driver_data_size = 2 * 256 * sizeof(uint8_t); 4138 if ((ahc->features & AHC_TARGETMODE) != 0) 4139 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4140 + /*DMA WideOdd Bug Buffer*/1; 4141 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4142 /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR, 4143 /*highaddr*/BUS_SPACE_MAXADDR, 4144 /*filter*/NULL, /*filterarg*/NULL, 4145 driver_data_size, 4146 /*nsegments*/1, 4147 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4148 /*flags*/0, &ahc->shared_data_dmat) != 0) { 4149 return (ENOMEM); 4150 } 4151 4152 ahc->init_level++; 4153 4154 /* Allocation of driver data */ 4155 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat, 4156 (void **)&ahc->qoutfifo, 4157 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) { 4158 return (ENOMEM); 4159 } 4160 4161 ahc->init_level++; 4162 4163 /* And permanently map it in */ 4164 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, 4165 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb, 4166 &ahc->shared_data_busaddr, /*flags*/0); 4167 4168 if ((ahc->features & AHC_TARGETMODE) != 0) { 4169 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4170 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4171 ahc->dma_bug_buf = ahc->shared_data_busaddr 4172 + driver_data_size - 1; 4173 /* All target command blocks start out invalid. */ 4174 for (i = 0; i < AHC_TMODE_CMDS; i++) 4175 ahc->targetcmds[i].cmd_valid = 0; 4176 ahc->tqinfifonext = 1; 4177 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4178 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4179 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4180 } 4181 ahc->qinfifo = &ahc->qoutfifo[256]; 4182 4183 ahc->init_level++; 4184 4185 /* Allocate SCB data now that buffer_dmat is initialized */ 4186 if (ahc->scb_data->maxhscbs == 0) 4187 if (ahc_init_scbdata(ahc) != 0) 4188 return (ENOMEM); 4189 4190 /* 4191 * Allocate a tstate to house information for our 4192 * initiator presence on the bus as well as the user 4193 * data for any target mode initiator. 4194 */ 4195 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4196 printf("%s: unable to allocate ahc_tmode_tstate. " 4197 "Failing attach\n", ahc_name(ahc)); 4198 return (ENOMEM); 4199 } 4200 4201 if ((ahc->features & AHC_TWIN) != 0) { 4202 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4203 printf("%s: unable to allocate ahc_tmode_tstate. " 4204 "Failing attach\n", ahc_name(ahc)); 4205 return (ENOMEM); 4206 } 4207 } 4208 4209 ahc_outb(ahc, SEQ_FLAGS, 0); 4210 ahc_outb(ahc, SEQ_FLAGS2, 0); 4211 4212 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 4213 ahc->flags |= AHC_PAGESCBS; 4214 } else { 4215 ahc->flags &= ~AHC_PAGESCBS; 4216 } 4217 4218#ifdef AHC_DEBUG 4219 if (ahc_debug & AHC_SHOWMISC) { 4220 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 4221 "ahc_dma %d bytes\n", 4222 ahc_name(ahc), 4223 sizeof(struct hardware_scb), 4224 sizeof(struct scb), 4225 sizeof(struct ahc_dma_seg)); 4226 } 4227#endif /* AHC_DEBUG */ 4228 4229 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4230 if (ahc->features & AHC_TWIN) { 4231 4232 /* 4233 * The device is gated to channel B after a chip reset, 4234 * so set those values first 4235 */ 4236 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4237 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4238 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4239 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4240 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4241 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4242 if ((ahc->features & AHC_ULTRA2) != 0) 4243 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4244 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4245 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4246 4247 if ((scsi_conf & RESET_SCSI) != 0 4248 && (ahc->flags & AHC_INITIATORROLE) != 0) 4249 ahc->flags |= AHC_RESET_BUS_B; 4250 4251 /* Select Channel A */ 4252 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4253 } 4254 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4255 if ((ahc->features & AHC_ULTRA2) != 0) 4256 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4257 else 4258 ahc_outb(ahc, SCSIID, ahc->our_id); 4259 scsi_conf = ahc_inb(ahc, SCSICONF); 4260 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4261 |term|ahc->seltime 4262 |ENSTIMER|ACTNEGEN); 4263 if ((ahc->features & AHC_ULTRA2) != 0) 4264 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4265 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4266 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4267 4268 if ((scsi_conf & RESET_SCSI) != 0 4269 && (ahc->flags & AHC_INITIATORROLE) != 0) 4270 ahc->flags |= AHC_RESET_BUS_A; 4271 4272 /* 4273 * Look at the information that board initialization or 4274 * the board bios has left us. 4275 */ 4276 ultraenb = 0; 4277 tagenable = ALL_TARGETS_MASK; 4278 4279 /* Grab the disconnection disable table and invert it for our needs */ 4280 if (ahc->flags & AHC_USEDEFAULTS) { 4281 printf("%s: Host Adapter Bios disabled. Using default SCSI " 4282 "device parameters\n", ahc_name(ahc)); 4283 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 4284 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 4285 discenable = ALL_TARGETS_MASK; 4286 if ((ahc->features & AHC_ULTRA) != 0) 4287 ultraenb = ALL_TARGETS_MASK; 4288 } else { 4289 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 4290 | ahc_inb(ahc, DISC_DSB)); 4291 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 4292 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 4293 | ahc_inb(ahc, ULTRA_ENB); 4294 } 4295 if ((ahc->flags & AHC_ULTRA_DISABLED) != 0) 4296 ultraenb = 0; 4297 4298 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 4299 max_targ = 7; 4300 4301 for (i = 0; i <= max_targ; i++) { 4302 struct ahc_initiator_tinfo *tinfo; 4303 struct ahc_tmode_tstate *tstate; 4304 u_int our_id; 4305 u_int target_id; 4306 char channel; 4307 4308 channel = 'A'; 4309 our_id = ahc->our_id; 4310 target_id = i; 4311 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 4312 channel = 'B'; 4313 our_id = ahc->our_id_b; 4314 target_id = i % 8; 4315 } 4316 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 4317 target_id, &tstate); 4318 /* Default to async narrow across the board */ 4319 memset(tinfo, 0, sizeof(*tinfo)); 4320 if (ahc->flags & AHC_USEDEFAULTS) { 4321 if ((ahc->features & AHC_WIDE) != 0) 4322 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4323 4324 /* 4325 * These will be truncated when we determine the 4326 * connection type we have with the target. 4327 */ 4328 tinfo->user.period = ahc_syncrates->period; 4329 tinfo->user.offset = ~0; 4330 } else { 4331 u_int scsirate; 4332 uint16_t mask; 4333 4334 /* Take the settings leftover in scratch RAM. */ 4335 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 4336 mask = (0x01 << i); 4337 if ((ahc->features & AHC_ULTRA2) != 0) { 4338 u_int offset; 4339 u_int maxsync; 4340 4341 if ((scsirate & SOFS) == 0x0F) { 4342 /* 4343 * Haven't negotiated yet, 4344 * so the format is different. 4345 */ 4346 scsirate = (scsirate & SXFR) >> 4 4347 | (ultraenb & mask) 4348 ? 0x08 : 0x0 4349 | (scsirate & WIDEXFER); 4350 offset = MAX_OFFSET_ULTRA2; 4351 } else 4352 offset = ahc_inb(ahc, TARG_OFFSET + i); 4353 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 4354 /* Set to the lowest sync rate, 5MHz */ 4355 scsirate |= 0x1c; 4356 maxsync = AHC_SYNCRATE_ULTRA2; 4357 if ((ahc->features & AHC_DT) != 0) 4358 maxsync = AHC_SYNCRATE_DT; 4359 tinfo->user.period = 4360 ahc_find_period(ahc, scsirate, maxsync); 4361 if (offset == 0) 4362 tinfo->user.period = 0; 4363 else 4364 tinfo->user.offset = ~0; 4365 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 4366 && (ahc->features & AHC_DT) != 0) 4367 tinfo->user.ppr_options = 4368 MSG_EXT_PPR_DT_REQ; 4369 } else if ((scsirate & SOFS) != 0) { 4370 if ((scsirate & SXFR) == 0x40 4371 && (ultraenb & mask) != 0) { 4372 /* Treat 10MHz as a non-ultra speed */ 4373 scsirate &= ~SXFR; 4374 ultraenb &= ~mask; 4375 } 4376 tinfo->user.period = 4377 ahc_find_period(ahc, scsirate, 4378 (ultraenb & mask) 4379 ? AHC_SYNCRATE_ULTRA 4380 : AHC_SYNCRATE_FAST); 4381 if (tinfo->user.period != 0) 4382 tinfo->user.offset = ~0; 4383 } 4384 if (tinfo->user.period == 0) 4385 tinfo->user.offset = 0; 4386 if ((scsirate & WIDEXFER) != 0 4387 && (ahc->features & AHC_WIDE) != 0) 4388 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4389 tinfo->user.protocol_version = 4; 4390 if ((ahc->features & AHC_DT) != 0) 4391 tinfo->user.transport_version = 3; 4392 else 4393 tinfo->user.transport_version = 2; 4394 tinfo->goal.protocol_version = 2; 4395 tinfo->goal.transport_version = 2; 4396 tinfo->current.protocol_version = 2; 4397 tinfo->current.transport_version = 2; 4398 } 4399 tstate->ultraenb = ultraenb; 4400 tstate->discenable = discenable; 4401 tstate->tagenable = 0; /* Wait until the XPT says its okay */ 4402 } 4403 ahc->user_discenable = discenable; 4404 ahc->user_tagenable = tagenable; 4405 4406 /* There are no untagged SCBs active yet. */ 4407 for (i = 0; i < 16; i++) { 4408 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4409 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4410 int lun; 4411 4412 /* 4413 * The SCB based BTT allows an entry per 4414 * target and lun pair. 4415 */ 4416 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4417 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4418 } 4419 } 4420 4421 /* All of our queues are empty */ 4422 for (i = 0; i < 256; i++) 4423 ahc->qoutfifo[i] = SCB_LIST_NULL; 4424 4425 for (i = 0; i < 256; i++) 4426 ahc->qinfifo[i] = SCB_LIST_NULL; 4427 4428 if ((ahc->features & AHC_MULTI_TID) != 0) { 4429 ahc_outb(ahc, TARGID, 0); 4430 ahc_outb(ahc, TARGID + 1, 0); 4431 } 4432 4433 /* 4434 * Tell the sequencer where it can find our arrays in memory. 4435 */ 4436 physaddr = ahc->scb_data->hscb_busaddr; 4437 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4438 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4439 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4440 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4441 4442 physaddr = ahc->shared_data_busaddr; 4443 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4444 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4445 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4446 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4447 4448 /* 4449 * Initialize the group code to command length table. 4450 * This overrides the values in TARG_SCSIRATE, so only 4451 * setup the table after we have processed that information. 4452 */ 4453 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4454 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4455 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4456 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4457 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4458 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4459 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4460 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4461 4462 /* Tell the sequencer of our initial queue positions */ 4463 ahc_outb(ahc, KERNEL_QINPOS, 0); 4464 ahc_outb(ahc, QINPOS, 0); 4465 ahc_outb(ahc, QOUTPOS, 0); 4466 4467 /* 4468 * Use the built in queue management registers 4469 * if they are available. 4470 */ 4471 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4472 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4473 ahc_outb(ahc, SDSCB_QOFF, 0); 4474 ahc_outb(ahc, SNSCB_QOFF, 0); 4475 ahc_outb(ahc, HNSCB_QOFF, 0); 4476 } 4477 4478 4479 /* We don't have any waiting selections */ 4480 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4481 4482 /* Our disconnection list is empty too */ 4483 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4484 4485 /* Message out buffer starts empty */ 4486 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4487 4488 /* 4489 * Setup the allowed SCSI Sequences based on operational mode. 4490 * If we are a target, we'll enalbe select in operations once 4491 * we've had a lun enabled. 4492 */ 4493 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4494 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4495 scsiseq_template |= ENRSELI; 4496 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4497 4498 /* 4499 * Load the Sequencer program and Enable the adapter 4500 * in "fast" mode. 4501 */ 4502 if (bootverbose) 4503 printf("%s: Downloading Sequencer Program...", 4504 ahc_name(ahc)); 4505 4506 ahc_loadseq(ahc); 4507 4508 if ((ahc->features & AHC_ULTRA2) != 0) { 4509 int wait; 4510 4511 /* 4512 * Wait for up to 500ms for our transceivers 4513 * to settle. If the adapter does not have 4514 * a cable attached, the tranceivers may 4515 * never settle, so don't complain if we 4516 * fail here. 4517 */ 4518 ahc_pause(ahc); 4519 for (wait = 5000; 4520 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4521 wait--) 4522 ahc_delay(100); 4523 ahc_unpause(ahc); 4524 } 4525 return (0); 4526} 4527 4528void 4529ahc_intr_enable(struct ahc_softc *ahc, int enable) 4530{ 4531 u_int hcntrl; 4532 4533 hcntrl = ahc_inb(ahc, HCNTRL); 4534 hcntrl &= ~INTEN; 4535 ahc->pause &= ~INTEN; 4536 ahc->unpause &= ~INTEN; 4537 if (enable) { 4538 hcntrl |= INTEN; 4539 ahc->pause |= INTEN; 4540 ahc->unpause |= INTEN; 4541 } 4542 ahc_outb(ahc, HCNTRL, hcntrl); 4543} 4544 4545/* 4546 * Ensure that the card is paused in a location 4547 * outside of all critical sections and that all 4548 * pending work is completed prior to returning. 4549 * This routine should only be called from outside 4550 * an interrupt context. 4551 */ 4552void 4553ahc_pause_and_flushwork(struct ahc_softc *ahc) 4554{ 4555 int intstat; 4556 int maxloops; 4557 4558 maxloops = 1000; 4559 ahc->flags |= AHC_ALL_INTERRUPTS; 4560 intstat = 0; 4561 do { 4562 ahc_intr(ahc); 4563 ahc_pause(ahc); 4564 ahc_clear_critical_section(ahc); 4565 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) 4566 break; 4567 maxloops--; 4568 } while (((intstat = ahc_inb(ahc, INTSTAT)) & INT_PEND) && --maxloops); 4569 if (maxloops == 0) { 4570 printf("Infinite interrupt loop, INTSTAT = %x", 4571 ahc_inb(ahc, INTSTAT)); 4572 } 4573 ahc_platform_flushwork(ahc); 4574 ahc->flags &= ~AHC_ALL_INTERRUPTS; 4575} 4576 4577int 4578ahc_suspend(struct ahc_softc *ahc) 4579{ 4580 uint8_t *ptr; 4581 int i; 4582 4583 ahc_pause_and_flushwork(ahc); 4584 4585 if (LIST_FIRST(&ahc->pending_scbs) != NULL) 4586 return (EBUSY); 4587 4588#if AHC_TARGET_MODE 4589 /* 4590 * XXX What about ATIOs that have not yet been serviced? 4591 * Perhaps we should just refuse to be suspended if we 4592 * are acting in a target role. 4593 */ 4594 if (ahc->pending_device != NULL) 4595 return (EBUSY); 4596#endif 4597 4598 /* Save volatile registers */ 4599 if ((ahc->features & AHC_TWIN) != 0) { 4600 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4601 ahc->suspend_state.channel[1].scsiseq = ahc_inb(ahc, SCSISEQ); 4602 ahc->suspend_state.channel[1].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 4603 ahc->suspend_state.channel[1].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 4604 ahc->suspend_state.channel[1].simode0 = ahc_inb(ahc, SIMODE0); 4605 ahc->suspend_state.channel[1].simode1 = ahc_inb(ahc, SIMODE1); 4606 ahc->suspend_state.channel[1].seltimer = ahc_inb(ahc, SELTIMER); 4607 ahc->suspend_state.channel[1].seqctl = ahc_inb(ahc, SEQCTL); 4608 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4609 } 4610 ahc->suspend_state.channel[0].scsiseq = ahc_inb(ahc, SCSISEQ); 4611 ahc->suspend_state.channel[0].sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 4612 ahc->suspend_state.channel[0].sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 4613 ahc->suspend_state.channel[0].simode0 = ahc_inb(ahc, SIMODE0); 4614 ahc->suspend_state.channel[0].simode1 = ahc_inb(ahc, SIMODE1); 4615 ahc->suspend_state.channel[0].seltimer = ahc_inb(ahc, SELTIMER); 4616 ahc->suspend_state.channel[0].seqctl = ahc_inb(ahc, SEQCTL); 4617 4618 if ((ahc->chip & AHC_PCI) != 0) { 4619 ahc->suspend_state.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 4620 ahc->suspend_state.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 4621 } 4622 4623 if ((ahc->features & AHC_DT) != 0) { 4624 u_int sfunct; 4625 4626 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 4627 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 4628 ahc->suspend_state.optionmode = ahc_inb(ahc, OPTIONMODE); 4629 ahc_outb(ahc, SFUNCT, sfunct); 4630 ahc->suspend_state.crccontrol1 = ahc_inb(ahc, CRCCONTROL1); 4631 } 4632 4633 if ((ahc->features & AHC_MULTI_FUNC) != 0) 4634 ahc->suspend_state.scbbaddr = ahc_inb(ahc, SCBBADDR); 4635 4636 if ((ahc->features & AHC_ULTRA2) != 0) 4637 ahc->suspend_state.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 4638 4639 ptr = ahc->suspend_state.scratch_ram; 4640 for (i = 0; i < 64; i++) 4641 *ptr++ = ahc_inb(ahc, SRAM_BASE + i); 4642 4643 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4644 for (i = 0; i < 16; i++) 4645 *ptr++ = ahc_inb(ahc, TARG_OFFSET + i); 4646 } 4647 4648 ptr = ahc->suspend_state.btt; 4649 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4650 for (i = 0;i < AHC_NUM_TARGETS; i++) { 4651 int j; 4652 4653 for (j = 0;j < AHC_NUM_LUNS; j++) { 4654 u_int tcl; 4655 4656 tcl = BUILD_TCL(i << 4, j); 4657 *ptr = ahc_index_busy_tcl(ahc, tcl); 4658 } 4659 } 4660 } 4661 ahc_shutdown(ahc); 4662 return (0); 4663} 4664 4665int 4666ahc_resume(struct ahc_softc *ahc) 4667{ 4668 uint8_t *ptr; 4669 int i; 4670 4671 ahc_reset(ahc); 4672 4673 ahc_build_free_scb_list(ahc); 4674 4675 /* Restore volatile registers */ 4676 if ((ahc->features & AHC_TWIN) != 0) { 4677 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4678 ahc_outb(ahc, SCSIID, ahc->our_id); 4679 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[1].scsiseq); 4680 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[1].sxfrctl0); 4681 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[1].sxfrctl1); 4682 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[1].simode0); 4683 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[1].simode1); 4684 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[1].seltimer); 4685 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[1].seqctl); 4686 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4687 } 4688 ahc_outb(ahc, SCSISEQ, ahc->suspend_state.channel[0].scsiseq); 4689 ahc_outb(ahc, SXFRCTL0, ahc->suspend_state.channel[0].sxfrctl0); 4690 ahc_outb(ahc, SXFRCTL1, ahc->suspend_state.channel[0].sxfrctl1); 4691 ahc_outb(ahc, SIMODE0, ahc->suspend_state.channel[0].simode0); 4692 ahc_outb(ahc, SIMODE1, ahc->suspend_state.channel[0].simode1); 4693 ahc_outb(ahc, SELTIMER, ahc->suspend_state.channel[0].seltimer); 4694 ahc_outb(ahc, SEQCTL, ahc->suspend_state.channel[0].seqctl); 4695 if ((ahc->features & AHC_ULTRA2) != 0) 4696 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4697 else 4698 ahc_outb(ahc, SCSIID, ahc->our_id); 4699 4700 if ((ahc->chip & AHC_PCI) != 0) { 4701 ahc_outb(ahc, DSCOMMAND0, ahc->suspend_state.dscommand0); 4702 ahc_outb(ahc, DSPCISTATUS, ahc->suspend_state.dspcistatus); 4703 } 4704 4705 if ((ahc->features & AHC_DT) != 0) { 4706 u_int sfunct; 4707 4708 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 4709 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 4710 ahc_outb(ahc, OPTIONMODE, ahc->suspend_state.optionmode); 4711 ahc_outb(ahc, SFUNCT, sfunct); 4712 ahc_outb(ahc, CRCCONTROL1, ahc->suspend_state.crccontrol1); 4713 } 4714 4715 if ((ahc->features & AHC_MULTI_FUNC) != 0) 4716 ahc_outb(ahc, SCBBADDR, ahc->suspend_state.scbbaddr); 4717 4718 if ((ahc->features & AHC_ULTRA2) != 0) 4719 ahc_outb(ahc, DFF_THRSH, ahc->suspend_state.dff_thrsh); 4720 4721 ptr = ahc->suspend_state.scratch_ram; 4722 for (i = 0; i < 64; i++) 4723 ahc_outb(ahc, SRAM_BASE + i, *ptr++); 4724 4725 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4726 for (i = 0; i < 16; i++) 4727 ahc_outb(ahc, TARG_OFFSET + i, *ptr++); 4728 } 4729 4730 ptr = ahc->suspend_state.btt; 4731 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4732 for (i = 0;i < AHC_NUM_TARGETS; i++) { 4733 int j; 4734 4735 for (j = 0;j < AHC_NUM_LUNS; j++) { 4736 u_int tcl; 4737 4738 tcl = BUILD_TCL(i << 4, j); 4739 ahc_busy_tcl(ahc, tcl, *ptr); 4740 } 4741 } 4742 } 4743 return (0); 4744} 4745 4746/************************** Busy Target Table *********************************/ 4747/* 4748 * Return the untagged transaction id for a given target/channel lun. 4749 * Optionally, clear the entry. 4750 */ 4751u_int 4752ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 4753{ 4754 u_int scbid; 4755 u_int target_offset; 4756 4757 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4758 u_int saved_scbptr; 4759 4760 saved_scbptr = ahc_inb(ahc, SCBPTR); 4761 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 4762 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 4763 ahc_outb(ahc, SCBPTR, saved_scbptr); 4764 } else { 4765 target_offset = TCL_TARGET_OFFSET(tcl); 4766 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 4767 } 4768 4769 return (scbid); 4770} 4771 4772void 4773ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 4774{ 4775 u_int target_offset; 4776 4777 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4778 u_int saved_scbptr; 4779 4780 saved_scbptr = ahc_inb(ahc, SCBPTR); 4781 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 4782 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 4783 ahc_outb(ahc, SCBPTR, saved_scbptr); 4784 } else { 4785 target_offset = TCL_TARGET_OFFSET(tcl); 4786 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 4787 } 4788} 4789 4790void 4791ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 4792{ 4793 u_int target_offset; 4794 4795 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4796 u_int saved_scbptr; 4797 4798 saved_scbptr = ahc_inb(ahc, SCBPTR); 4799 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 4800 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 4801 ahc_outb(ahc, SCBPTR, saved_scbptr); 4802 } else { 4803 target_offset = TCL_TARGET_OFFSET(tcl); 4804 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 4805 } 4806} 4807 4808/************************** SCB and SCB queue management **********************/ 4809int 4810ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 4811 char channel, int lun, u_int tag, role_t role) 4812{ 4813 int targ = SCB_GET_TARGET(ahc, scb); 4814 char chan = SCB_GET_CHANNEL(ahc, scb); 4815 int slun = SCB_GET_LUN(scb); 4816 int match; 4817 4818 match = ((chan == channel) || (channel == ALL_CHANNELS)); 4819 if (match != 0) 4820 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 4821 if (match != 0) 4822 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 4823 if (match != 0) { 4824#if AHC_TARGET_MODE 4825 int group; 4826 4827 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 4828 if (role == ROLE_INITIATOR) { 4829 match = (group != XPT_FC_GROUP_TMODE) 4830 && ((tag == scb->hscb->tag) 4831 || (tag == SCB_LIST_NULL)); 4832 } else if (role == ROLE_TARGET) { 4833 match = (group == XPT_FC_GROUP_TMODE) 4834 && ((tag == scb->io_ctx->csio.tag_id) 4835 || (tag == SCB_LIST_NULL)); 4836 } 4837#else /* !AHC_TARGET_MODE */ 4838 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 4839#endif /* AHC_TARGET_MODE */ 4840 } 4841 4842 return match; 4843} 4844 4845void 4846ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 4847{ 4848 int target; 4849 char channel; 4850 int lun; 4851 4852 target = SCB_GET_TARGET(ahc, scb); 4853 lun = SCB_GET_LUN(scb); 4854 channel = SCB_GET_CHANNEL(ahc, scb); 4855 4856 ahc_search_qinfifo(ahc, target, channel, lun, 4857 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 4858 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 4859 4860 ahc_platform_freeze_devq(ahc, scb); 4861} 4862 4863void 4864ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 4865{ 4866 struct scb *prev_scb; 4867 4868 prev_scb = NULL; 4869 if (ahc_qinfifo_count(ahc) != 0) { 4870 u_int prev_tag; 4871 uint8_t prev_pos; 4872 4873 prev_pos = ahc->qinfifonext - 1; 4874 prev_tag = ahc->qinfifo[prev_pos]; 4875 prev_scb = ahc_lookup_scb(ahc, prev_tag); 4876 } 4877 ahc_qinfifo_requeue(ahc, prev_scb, scb); 4878 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4879 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4880 } else { 4881 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4882 } 4883} 4884 4885static void 4886ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 4887 struct scb *scb) 4888{ 4889 if (prev_scb == NULL) 4890 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 4891 else 4892 prev_scb->hscb->next = scb->hscb->tag; 4893 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 4894 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 4895} 4896 4897static int 4898ahc_qinfifo_count(struct ahc_softc *ahc) 4899{ 4900 u_int8_t qinpos; 4901 u_int8_t diff; 4902 4903 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4904 qinpos = ahc_inb(ahc, SNSCB_QOFF); 4905 ahc_outb(ahc, SNSCB_QOFF, qinpos); 4906 } else 4907 qinpos = ahc_inb(ahc, QINPOS); 4908 diff = ahc->qinfifonext - qinpos; 4909 return (diff); 4910} 4911 4912int 4913ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4914 int lun, u_int tag, role_t role, uint32_t status, 4915 ahc_search_action action) 4916{ 4917 struct scb *scb; 4918 struct scb *prev_scb; 4919 uint8_t qinstart; 4920 uint8_t qinpos; 4921 uint8_t qintail; 4922 uint8_t next, prev; 4923 uint8_t curscbptr; 4924 int found; 4925 int maxtarget; 4926 int i; 4927 int have_qregs; 4928 4929 qintail = ahc->qinfifonext; 4930 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 4931 if (have_qregs) { 4932 qinstart = ahc_inb(ahc, SNSCB_QOFF); 4933 ahc_outb(ahc, SNSCB_QOFF, qinstart); 4934 } else 4935 qinstart = ahc_inb(ahc, QINPOS); 4936 qinpos = qinstart; 4937 next = ahc_inb(ahc, NEXT_QUEUED_SCB); 4938 found = 0; 4939 prev_scb = NULL; 4940 4941 if (action == SEARCH_COMPLETE) { 4942 /* 4943 * Don't attempt to run any queued untagged transactions 4944 * until we are done with the abort process. 4945 */ 4946 ahc_freeze_untagged_queues(ahc); 4947 } 4948 4949 /* 4950 * Start with an empty queue. Entries that are not chosen 4951 * for removal will be re-added to the queue as we go. 4952 */ 4953 ahc->qinfifonext = qinpos; 4954 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4955 4956 while (qinpos != qintail) { 4957 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 4958 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 4959 /* 4960 * We found an scb that needs to be acted on. 4961 */ 4962 found++; 4963 switch (action) { 4964 case SEARCH_COMPLETE: 4965 { 4966 cam_status ostat; 4967 cam_status cstat; 4968 4969 ostat = ahc_get_transaction_status(scb); 4970 if (ostat == CAM_REQ_INPROG) 4971 ahc_set_transaction_status(scb, 4972 status); 4973 cstat = ahc_get_transaction_status(scb); 4974 if (cstat != CAM_REQ_CMP) 4975 ahc_freeze_scb(scb); 4976 if ((scb->flags & SCB_ACTIVE) == 0) 4977 printf("Inactive SCB in qinfifo\n"); 4978 ahc_done(ahc, scb); 4979 4980 /* FALLTHROUGH */ 4981 case SEARCH_REMOVE: 4982 break; 4983 } 4984 case SEARCH_COUNT: 4985 ahc_qinfifo_requeue(ahc, prev_scb, scb); 4986 prev_scb = scb; 4987 break; 4988 } 4989 } else { 4990 ahc_qinfifo_requeue(ahc, prev_scb, scb); 4991 prev_scb = scb; 4992 } 4993 qinpos++; 4994 } 4995 4996 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4997 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4998 } else { 4999 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5000 } 5001 5002 if (action != SEARCH_COUNT 5003 && (found != 0) 5004 && (qinstart != ahc->qinfifonext)) { 5005 /* 5006 * The sequencer may be in the process of dmaing 5007 * down the SCB at the beginning of the queue. 5008 * This could be problematic if either the first, 5009 * or the second SCB is removed from the queue 5010 * (the first SCB includes a pointer to the "next" 5011 * SCB to dma). If we have removed any entries, swap 5012 * the first element in the queue with the next HSCB 5013 * so the sequencer will notice that NEXT_QUEUED_SCB 5014 * has changed during its dma attempt and will retry 5015 * the DMA. 5016 */ 5017 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5018 5019 /* 5020 * ahc_swap_with_next_hscb forces our next pointer to 5021 * point to the reserved SCB for future commands. Save 5022 * and restore our original next pointer to maintain 5023 * queue integrity. 5024 */ 5025 next = scb->hscb->next; 5026 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5027 ahc_swap_with_next_hscb(ahc, scb); 5028 scb->hscb->next = next; 5029 ahc->qinfifo[qinstart] = scb->hscb->tag; 5030 5031 /* Tell the card about the new head of the qinfifo. */ 5032 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5033 5034 /* Fixup the tail "next" pointer. */ 5035 qintail = ahc->qinfifonext - 1; 5036 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5037 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5038 } 5039 5040 /* 5041 * Search waiting for selection list. 5042 */ 5043 curscbptr = ahc_inb(ahc, SCBPTR); 5044 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5045 prev = SCB_LIST_NULL; 5046 5047 while (next != SCB_LIST_NULL) { 5048 uint8_t scb_index; 5049 5050 ahc_outb(ahc, SCBPTR, next); 5051 scb_index = ahc_inb(ahc, SCB_TAG); 5052 if (scb_index >= ahc->scb_data->numscbs) { 5053 printf("Waiting List inconsistency. " 5054 "SCB index == %d, yet numscbs == %d.", 5055 scb_index, ahc->scb_data->numscbs); 5056 ahc_dump_card_state(ahc); 5057 panic("for safety"); 5058 } 5059 scb = ahc_lookup_scb(ahc, scb_index); 5060 if (ahc_match_scb(ahc, scb, target, channel, 5061 lun, SCB_LIST_NULL, role)) { 5062 /* 5063 * We found an scb that needs to be acted on. 5064 */ 5065 found++; 5066 switch (action) { 5067 case SEARCH_COMPLETE: 5068 { 5069 cam_status ostat; 5070 cam_status cstat; 5071 5072 ostat = ahc_get_transaction_status(scb); 5073 if (ostat == CAM_REQ_INPROG) 5074 ahc_set_transaction_status(scb, 5075 status); 5076 cstat = ahc_get_transaction_status(scb); 5077 if (cstat != CAM_REQ_CMP) 5078 ahc_freeze_scb(scb); 5079 if ((scb->flags & SCB_ACTIVE) == 0) 5080 printf("Inactive SCB in Waiting List\n"); 5081 ahc_done(ahc, scb); 5082 /* FALLTHROUGH */ 5083 } 5084 case SEARCH_REMOVE: 5085 next = ahc_rem_wscb(ahc, next, prev); 5086 break; 5087 case SEARCH_COUNT: 5088 prev = next; 5089 next = ahc_inb(ahc, SCB_NEXT); 5090 break; 5091 } 5092 } else { 5093 5094 prev = next; 5095 next = ahc_inb(ahc, SCB_NEXT); 5096 } 5097 } 5098 ahc_outb(ahc, SCBPTR, curscbptr); 5099 5100 /* 5101 * And lastly, the untagged holding queues. 5102 */ 5103 i = 0; 5104 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5105 5106 maxtarget = 16; 5107 if (target != CAM_TARGET_WILDCARD) { 5108 5109 i = target; 5110 if (channel == 'B') 5111 i += 8; 5112 maxtarget = i + 1; 5113 } 5114 } else { 5115 maxtarget = 0; 5116 } 5117 5118 for (; i < maxtarget; i++) { 5119 struct scb_tailq *untagged_q; 5120 struct scb *next_scb; 5121 5122 untagged_q = &(ahc->untagged_queues[i]); 5123 next_scb = TAILQ_FIRST(untagged_q); 5124 while (next_scb != NULL) { 5125 5126 scb = next_scb; 5127 next_scb = TAILQ_NEXT(scb, links.tqe); 5128 5129 /* 5130 * The head of the list may be the currently 5131 * active untagged command for a device. 5132 * We're only searching for commands that 5133 * have not been started. A transaction 5134 * marked active but still in the qinfifo 5135 * is removed by the qinfifo scanning code 5136 * above. 5137 */ 5138 if ((scb->flags & SCB_ACTIVE) != 0) 5139 continue; 5140 5141 if (ahc_match_scb(ahc, scb, target, channel, 5142 lun, SCB_LIST_NULL, role)) { 5143 /* 5144 * We found an scb that needs to be acted on. 5145 */ 5146 found++; 5147 switch (action) { 5148 case SEARCH_COMPLETE: 5149 { 5150 cam_status ostat; 5151 cam_status cstat; 5152 5153 ostat = ahc_get_transaction_status(scb); 5154 if (ostat == CAM_REQ_INPROG) 5155 ahc_set_transaction_status(scb, 5156 status); 5157 cstat = ahc_get_transaction_status(scb); 5158 if (cstat != CAM_REQ_CMP) 5159 ahc_freeze_scb(scb); 5160 if ((scb->flags & SCB_ACTIVE) == 0) 5161 printf("Inactive SCB in untaggedQ\n"); 5162 ahc_done(ahc, scb); 5163 break; 5164 } 5165 case SEARCH_REMOVE: 5166 TAILQ_REMOVE(untagged_q, scb, 5167 links.tqe); 5168 break; 5169 case SEARCH_COUNT: 5170 break; 5171 } 5172 } 5173 } 5174 } 5175 5176 if (action == SEARCH_COMPLETE) 5177 ahc_release_untagged_queues(ahc); 5178 return (found); 5179} 5180 5181int 5182ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5183 int lun, u_int tag, int stop_on_first, int remove, 5184 int save_state) 5185{ 5186 struct scb *scbp; 5187 u_int next; 5188 u_int prev; 5189 u_int count; 5190 u_int active_scb; 5191 5192 count = 0; 5193 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5194 prev = SCB_LIST_NULL; 5195 5196 if (save_state) { 5197 /* restore this when we're done */ 5198 active_scb = ahc_inb(ahc, SCBPTR); 5199 } else 5200 /* Silence compiler */ 5201 active_scb = SCB_LIST_NULL; 5202 5203 while (next != SCB_LIST_NULL) { 5204 u_int scb_index; 5205 5206 ahc_outb(ahc, SCBPTR, next); 5207 scb_index = ahc_inb(ahc, SCB_TAG); 5208 if (scb_index >= ahc->scb_data->numscbs) { 5209 printf("Disconnected List inconsistency. " 5210 "SCB index == %d, yet numscbs == %d.", 5211 scb_index, ahc->scb_data->numscbs); 5212 ahc_dump_card_state(ahc); 5213 panic("for safety"); 5214 } 5215 5216 if (next == prev) { 5217 panic("Disconnected List Loop. " 5218 "cur SCBPTR == %x, prev SCBPTR == %x.", 5219 next, prev); 5220 } 5221 scbp = ahc_lookup_scb(ahc, scb_index); 5222 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5223 tag, ROLE_INITIATOR)) { 5224 count++; 5225 if (remove) { 5226 next = 5227 ahc_rem_scb_from_disc_list(ahc, prev, next); 5228 } else { 5229 prev = next; 5230 next = ahc_inb(ahc, SCB_NEXT); 5231 } 5232 if (stop_on_first) 5233 break; 5234 } else { 5235 prev = next; 5236 next = ahc_inb(ahc, SCB_NEXT); 5237 } 5238 } 5239 if (save_state) 5240 ahc_outb(ahc, SCBPTR, active_scb); 5241 return (count); 5242} 5243 5244/* 5245 * Remove an SCB from the on chip list of disconnected transactions. 5246 * This is empty/unused if we are not performing SCB paging. 5247 */ 5248static u_int 5249ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5250{ 5251 u_int next; 5252 5253 ahc_outb(ahc, SCBPTR, scbptr); 5254 next = ahc_inb(ahc, SCB_NEXT); 5255 5256 ahc_outb(ahc, SCB_CONTROL, 0); 5257 5258 ahc_add_curscb_to_free_list(ahc); 5259 5260 if (prev != SCB_LIST_NULL) { 5261 ahc_outb(ahc, SCBPTR, prev); 5262 ahc_outb(ahc, SCB_NEXT, next); 5263 } else 5264 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5265 5266 return (next); 5267} 5268 5269/* 5270 * Add the SCB as selected by SCBPTR onto the on chip list of 5271 * free hardware SCBs. This list is empty/unused if we are not 5272 * performing SCB paging. 5273 */ 5274static void 5275ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5276{ 5277 /* 5278 * Invalidate the tag so that our abort 5279 * routines don't think it's active. 5280 */ 5281 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5282 5283 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5284 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5285 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5286 } 5287} 5288 5289/* 5290 * Manipulate the waiting for selection list and return the 5291 * scb that follows the one that we remove. 5292 */ 5293static u_int 5294ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5295{ 5296 u_int curscb, next; 5297 5298 /* 5299 * Select the SCB we want to abort and 5300 * pull the next pointer out of it. 5301 */ 5302 curscb = ahc_inb(ahc, SCBPTR); 5303 ahc_outb(ahc, SCBPTR, scbpos); 5304 next = ahc_inb(ahc, SCB_NEXT); 5305 5306 /* Clear the necessary fields */ 5307 ahc_outb(ahc, SCB_CONTROL, 0); 5308 5309 ahc_add_curscb_to_free_list(ahc); 5310 5311 /* update the waiting list */ 5312 if (prev == SCB_LIST_NULL) { 5313 /* First in the list */ 5314 ahc_outb(ahc, WAITING_SCBH, next); 5315 5316 /* 5317 * Ensure we aren't attempting to perform 5318 * selection for this entry. 5319 */ 5320 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5321 } else { 5322 /* 5323 * Select the scb that pointed to us 5324 * and update its next pointer. 5325 */ 5326 ahc_outb(ahc, SCBPTR, prev); 5327 ahc_outb(ahc, SCB_NEXT, next); 5328 } 5329 5330 /* 5331 * Point us back at the original scb position. 5332 */ 5333 ahc_outb(ahc, SCBPTR, curscb); 5334 return next; 5335} 5336 5337/******************************** Error Handling ******************************/ 5338/* 5339 * Abort all SCBs that match the given description (target/channel/lun/tag), 5340 * setting their status to the passed in status if the status has not already 5341 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5342 * is paused before it is called. 5343 */ 5344int 5345ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5346 int lun, u_int tag, role_t role, uint32_t status) 5347{ 5348 struct scb *scbp; 5349 struct scb *scbp_next; 5350 u_int active_scb; 5351 int i, j; 5352 int maxtarget; 5353 int minlun; 5354 int maxlun; 5355 5356 int found; 5357 5358 /* 5359 * Don't attempt to run any queued untagged transactions 5360 * until we are done with the abort process. 5361 */ 5362 ahc_freeze_untagged_queues(ahc); 5363 5364 /* restore this when we're done */ 5365 active_scb = ahc_inb(ahc, SCBPTR); 5366 5367 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5368 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5369 5370 /* 5371 * Clean out the busy target table for any untagged commands. 5372 */ 5373 i = 0; 5374 maxtarget = 16; 5375 if (target != CAM_TARGET_WILDCARD) { 5376 i = target; 5377 if (channel == 'B') 5378 i += 8; 5379 maxtarget = i + 1; 5380 } 5381 5382 if (lun == CAM_LUN_WILDCARD) { 5383 5384 /* 5385 * Unless we are using an SCB based 5386 * busy targets table, there is only 5387 * one table entry for all luns of 5388 * a target. 5389 */ 5390 minlun = 0; 5391 maxlun = 1; 5392 if ((ahc->flags & AHC_SCB_BTT) != 0) 5393 maxlun = AHC_NUM_LUNS; 5394 } else { 5395 minlun = lun; 5396 maxlun = lun + 1; 5397 } 5398 5399 for (;i < maxtarget; i++) { 5400 for (j = minlun;j < maxlun; j++) 5401 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5402 } 5403 5404 /* 5405 * Go through the disconnected list and remove any entries we 5406 * have queued for completion, 0'ing their control byte too. 5407 * We save the active SCB and restore it ourselves, so there 5408 * is no reason for this search to restore it too. 5409 */ 5410 ahc_search_disc_list(ahc, target, channel, lun, tag, 5411 /*stop_on_first*/FALSE, /*remove*/TRUE, 5412 /*save_state*/FALSE); 5413 5414 /* 5415 * Go through the hardware SCB array looking for commands that 5416 * were active but not on any list. 5417 */ 5418 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5419 u_int scbid; 5420 5421 ahc_outb(ahc, SCBPTR, i); 5422 scbid = ahc_inb(ahc, SCB_TAG); 5423 scbp = ahc_lookup_scb(ahc, scbid); 5424 if (scbp != NULL 5425 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) 5426 ahc_add_curscb_to_free_list(ahc); 5427 } 5428 5429 /* 5430 * Go through the pending CCB list and look for 5431 * commands for this target that are still active. 5432 * These are other tagged commands that were 5433 * disconnected when the reset occured. 5434 */ 5435 scbp_next = LIST_FIRST(&ahc->pending_scbs); 5436 while (scbp_next != NULL) { 5437 scbp = scbp_next; 5438 scbp_next = LIST_NEXT(scbp, pending_links); 5439 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 5440 cam_status ostat; 5441 5442 ostat = ahc_get_transaction_status(scbp); 5443 if (ostat == CAM_REQ_INPROG) 5444 ahc_set_transaction_status(scbp, status); 5445 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) 5446 ahc_freeze_scb(scbp); 5447 if ((scbp->flags & SCB_ACTIVE) == 0) 5448 printf("Inactive SCB on pending list\n"); 5449 ahc_done(ahc, scbp); 5450 found++; 5451 } 5452 } 5453 ahc_outb(ahc, SCBPTR, active_scb); 5454 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 5455 ahc_release_untagged_queues(ahc); 5456 return found; 5457} 5458 5459static void 5460ahc_reset_current_bus(struct ahc_softc *ahc) 5461{ 5462 uint8_t scsiseq; 5463 5464 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5465 scsiseq = ahc_inb(ahc, SCSISEQ); 5466 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5467 ahc_delay(AHC_BUSRESET_DELAY); 5468 /* Turn off the bus reset */ 5469 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5470 5471 ahc_clear_intstat(ahc); 5472 5473 /* Re-enable reset interrupts */ 5474 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5475} 5476 5477int 5478ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5479{ 5480 struct ahc_devinfo devinfo; 5481 u_int initiator, target, max_scsiid; 5482 u_int sblkctl; 5483 int found; 5484 int restart_needed; 5485 char cur_channel; 5486 5487 ahc->pending_device = NULL; 5488 5489 ahc_compile_devinfo(&devinfo, 5490 CAM_TARGET_WILDCARD, 5491 CAM_TARGET_WILDCARD, 5492 CAM_LUN_WILDCARD, 5493 channel, ROLE_UNKNOWN); 5494 ahc_pause(ahc); 5495 5496 /* Make sure the sequencer is in a safe location. */ 5497 ahc_clear_critical_section(ahc); 5498 5499 /* 5500 * Run our command complete fifos to ensure that we perform 5501 * completion processing on any commands that 'completed' 5502 * before the reset occurred. 5503 */ 5504 ahc_run_qoutfifo(ahc); 5505#if AHC_TARGET_MODE 5506 if ((ahc->flags & AHC_TARGETROLE) != 0) { 5507 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 5508 } 5509#endif 5510 5511 /* 5512 * Reset the bus if we are initiating this reset 5513 */ 5514 sblkctl = ahc_inb(ahc, SBLKCTL); 5515 cur_channel = 'A'; 5516 if ((ahc->features & AHC_TWIN) != 0 5517 && ((sblkctl & SELBUSB) != 0)) 5518 cur_channel = 'B'; 5519 if (cur_channel != channel) { 5520 /* Case 1: Command for another bus is active 5521 * Stealthily reset the other bus without 5522 * upsetting the current bus. 5523 */ 5524 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5525 ahc_outb(ahc, SIMODE1, 5526 ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST)); 5527 ahc_outb(ahc, SCSISEQ, 5528 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5529 if (initiate_reset) 5530 ahc_reset_current_bus(ahc); 5531 ahc_clear_intstat(ahc); 5532 ahc_outb(ahc, SBLKCTL, sblkctl); 5533 restart_needed = FALSE; 5534 } else { 5535 /* Case 2: A command from this bus is active or we're idle */ 5536 ahc_clear_msg_state(ahc); 5537 ahc_outb(ahc, SIMODE1, 5538 ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST)); 5539 ahc_outb(ahc, SCSISEQ, 5540 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5541 if (initiate_reset) 5542 ahc_reset_current_bus(ahc); 5543 ahc_clear_intstat(ahc); 5544 restart_needed = TRUE; 5545 } 5546 5547 /* 5548 * Clean up all the state information for the 5549 * pending transactions on this bus. 5550 */ 5551 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 5552 CAM_LUN_WILDCARD, SCB_LIST_NULL, 5553 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 5554 5555 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 5556 5557#ifdef AHC_TARGET_MODE 5558 /* 5559 * Send an immediate notify ccb to all target more peripheral 5560 * drivers affected by this action. 5561 */ 5562 for (target = 0; target <= max_scsiid; target++) { 5563 struct ahc_tmode_tstate* tstate; 5564 u_int lun; 5565 5566 tstate = ahc->enabled_targets[target]; 5567 if (tstate == NULL) 5568 continue; 5569 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 5570 struct ahc_tmode_lstate* lstate; 5571 5572 lstate = tstate->enabled_luns[lun]; 5573 if (lstate == NULL) 5574 continue; 5575 5576 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 5577 EVENT_TYPE_BUS_RESET, /*arg*/0); 5578 ahc_send_lstate_events(ahc, lstate); 5579 } 5580 } 5581#endif 5582 /* Notify the XPT that a bus reset occurred */ 5583 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD, 5584 CAM_LUN_WILDCARD, AC_BUS_RESET); 5585 5586 /* 5587 * Revert to async/narrow transfers until we renegotiate. 5588 */ 5589 for (target = 0; target <= max_scsiid; target++) { 5590 5591 if (ahc->enabled_targets[target] == NULL) 5592 continue; 5593 for (initiator = 0; initiator <= max_scsiid; initiator++) { 5594 struct ahc_devinfo devinfo; 5595 5596 ahc_compile_devinfo(&devinfo, target, initiator, 5597 CAM_LUN_WILDCARD, 5598 channel, ROLE_UNKNOWN); 5599 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 5600 AHC_TRANS_CUR, /*paused*/TRUE); 5601 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 5602 /*period*/0, /*offset*/0, 5603 /*ppr_options*/0, AHC_TRANS_CUR, 5604 /*paused*/TRUE); 5605 } 5606 } 5607 5608 if (restart_needed) 5609 ahc_restart(ahc); 5610 else 5611 ahc_unpause(ahc); 5612 return found; 5613} 5614 5615 5616/***************************** Residual Processing ****************************/ 5617/* 5618 * Calculate the residual for a just completed SCB. 5619 */ 5620static void 5621ahc_calc_residual(struct scb *scb) 5622{ 5623 struct hardware_scb *hscb; 5624 struct status_pkt *spkt; 5625 uint32_t sgptr; 5626 uint32_t resid_sgptr; 5627 uint32_t resid; 5628 5629 /* 5630 * 5 cases. 5631 * 1) No residual. 5632 * SG_RESID_VALID clear in sgptr. 5633 * 2) Transferless command 5634 * 3) Never performed any transfers. 5635 * sgptr has SG_FULL_RESID set. 5636 * 4) No residual but target did not 5637 * save data pointers after the 5638 * last transfer, so sgptr was 5639 * never updated. 5640 * 5) We have a partial residual. 5641 * Use residual_sgptr to determine 5642 * where we are. 5643 */ 5644 5645 hscb = scb->hscb; 5646 sgptr = ahc_le32toh(hscb->sgptr); 5647 if ((sgptr & SG_RESID_VALID) == 0) 5648 /* Case 1 */ 5649 return; 5650 sgptr &= ~SG_RESID_VALID; 5651 5652 if ((sgptr & SG_LIST_NULL) != 0) 5653 /* Case 2 */ 5654 return; 5655 5656 spkt = &hscb->shared_data.status; 5657 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr); 5658 if ((sgptr & SG_FULL_RESID) != 0) { 5659 /* Case 3 */ 5660 resid = ahc_get_transfer_length(scb); 5661 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 5662 /* Case 4 */ 5663 return; 5664 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 5665 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 5666 } else { 5667 struct ahc_dma_seg *sg; 5668 5669 /* 5670 * Remainder of the SG where the transfer 5671 * stopped. 5672 */ 5673 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 5674 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 5675 5676 /* The residual sg_ptr always points to the next sg */ 5677 sg--; 5678 5679 /* 5680 * Add up the contents of all residual 5681 * SG segments that are after the SG where 5682 * the transfer stopped. 5683 */ 5684 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 5685 sg++; 5686 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 5687 } 5688 } 5689 if ((scb->flags & SCB_SENSE) == 0) 5690 ahc_set_residual(scb, resid); 5691 else 5692 ahc_set_sense_residual(scb, resid); 5693 5694#ifdef AHC_DEBUG 5695 if (ahc_debug & AHC_SHOWMISC) { 5696 ahc_print_path(ahc, scb); 5697 printf("Handled Residual of %d bytes\n", resid); 5698 } 5699#endif 5700} 5701 5702/******************************* Target Mode **********************************/ 5703#ifdef AHC_TARGET_MODE 5704/* 5705 * Add a target mode event to this lun's queue 5706 */ 5707static void 5708ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 5709 u_int initiator_id, u_int event_type, u_int event_arg) 5710{ 5711 struct ahc_tmode_event *event; 5712 int pending; 5713 5714 xpt_freeze_devq(lstate->path, /*count*/1); 5715 if (lstate->event_w_idx >= lstate->event_r_idx) 5716 pending = lstate->event_w_idx - lstate->event_r_idx; 5717 else 5718 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 5719 - (lstate->event_r_idx - lstate->event_w_idx); 5720 5721 if (event_type == EVENT_TYPE_BUS_RESET 5722 || event_type == MSG_BUS_DEV_RESET) { 5723 /* 5724 * Any earlier events are irrelevant, so reset our buffer. 5725 * This has the effect of allowing us to deal with reset 5726 * floods (an external device holding down the reset line) 5727 * without losing the event that is really interesting. 5728 */ 5729 lstate->event_r_idx = 0; 5730 lstate->event_w_idx = 0; 5731 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 5732 } 5733 5734 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 5735 xpt_print_path(lstate->path); 5736 printf("immediate event %x:%x lost\n", 5737 lstate->event_buffer[lstate->event_r_idx].event_type, 5738 lstate->event_buffer[lstate->event_r_idx].event_arg); 5739 lstate->event_r_idx++; 5740 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 5741 lstate->event_r_idx = 0; 5742 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 5743 } 5744 5745 event = &lstate->event_buffer[lstate->event_w_idx]; 5746 event->initiator_id = initiator_id; 5747 event->event_type = event_type; 5748 event->event_arg = event_arg; 5749 lstate->event_w_idx++; 5750 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 5751 lstate->event_w_idx = 0; 5752} 5753 5754/* 5755 * Send any target mode events queued up waiting 5756 * for immediate notify resources. 5757 */ 5758void 5759ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 5760{ 5761 struct ccb_hdr *ccbh; 5762 struct ccb_immed_notify *inot; 5763 5764 while (lstate->event_r_idx != lstate->event_w_idx 5765 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 5766 struct ahc_tmode_event *event; 5767 5768 event = &lstate->event_buffer[lstate->event_r_idx]; 5769 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 5770 inot = (struct ccb_immed_notify *)ccbh; 5771 switch (event->event_type) { 5772 case EVENT_TYPE_BUS_RESET: 5773 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 5774 break; 5775 default: 5776 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 5777 inot->message_args[0] = event->event_type; 5778 inot->message_args[1] = event->event_arg; 5779 break; 5780 } 5781 inot->initiator_id = event->initiator_id; 5782 inot->sense_len = 0; 5783 xpt_done((union ccb *)inot); 5784 lstate->event_r_idx++; 5785 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 5786 lstate->event_r_idx = 0; 5787 } 5788} 5789#endif 5790 5791/******************** Sequencer Program Patching/Download *********************/ 5792 5793#ifdef AHC_DUMP_SEQ 5794void 5795ahc_dumpseq(struct ahc_softc* ahc) 5796{ 5797 int i; 5798 int max_prog; 5799 5800 if ((ahc->chip & AHC_BUS_MASK) < AHC_PCI) 5801 max_prog = 448; 5802 else if ((ahc->features & AHC_ULTRA2) != 0) 5803 max_prog = 768; 5804 else 5805 max_prog = 512; 5806 5807 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 5808 ahc_outb(ahc, SEQADDR0, 0); 5809 ahc_outb(ahc, SEQADDR1, 0); 5810 for (i = 0; i < max_prog; i++) { 5811 uint8_t ins_bytes[4]; 5812 5813 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 5814 printf("0x%08x\n", ins_bytes[0] << 24 5815 | ins_bytes[1] << 16 5816 | ins_bytes[2] << 8 5817 | ins_bytes[3]); 5818 } 5819} 5820#endif 5821 5822static void 5823ahc_loadseq(struct ahc_softc *ahc) 5824{ 5825 struct cs cs_table[num_critical_sections]; 5826 u_int begin_set[num_critical_sections]; 5827 u_int end_set[num_critical_sections]; 5828 struct patch *cur_patch; 5829 u_int cs_count; 5830 u_int cur_cs; 5831 u_int i; 5832 int downloaded; 5833 u_int skip_addr; 5834 u_int sg_prefetch_cnt; 5835 uint8_t download_consts[7]; 5836 5837 /* 5838 * Start out with 0 critical sections 5839 * that apply to this firmware load. 5840 */ 5841 cs_count = 0; 5842 cur_cs = 0; 5843 memset(begin_set, 0, sizeof(begin_set)); 5844 memset(end_set, 0, sizeof(end_set)); 5845 5846 /* Setup downloadable constant table */ 5847 download_consts[QOUTFIFO_OFFSET] = 0; 5848 if (ahc->targetcmds != NULL) 5849 download_consts[QOUTFIFO_OFFSET] += 32; 5850 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 5851 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 5852 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 5853 sg_prefetch_cnt = ahc->pci_cachesize; 5854 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 5855 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 5856 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 5857 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 5858 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 5859 5860 cur_patch = patches; 5861 downloaded = 0; 5862 skip_addr = 0; 5863 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 5864 ahc_outb(ahc, SEQADDR0, 0); 5865 ahc_outb(ahc, SEQADDR1, 0); 5866 5867 for (i = 0; i < sizeof(seqprog)/4; i++) { 5868 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 5869 /* 5870 * Don't download this instruction as it 5871 * is in a patch that was removed. 5872 */ 5873 continue; 5874 } 5875 /* 5876 * Move through the CS table until we find a CS 5877 * that might apply to this instruction. 5878 */ 5879 for (; cur_cs < num_critical_sections; cur_cs++) { 5880 if (critical_sections[cur_cs].end <= i) { 5881 if (begin_set[cs_count] == TRUE 5882 && end_set[cs_count] == FALSE) { 5883 cs_table[cs_count].end = downloaded; 5884 end_set[cs_count] = TRUE; 5885 cs_count++; 5886 } 5887 continue; 5888 } 5889 if (critical_sections[cur_cs].begin <= i 5890 && begin_set[cs_count] == FALSE) { 5891 cs_table[cs_count].begin = downloaded; 5892 begin_set[cs_count] = TRUE; 5893 } 5894 break; 5895 } 5896 ahc_download_instr(ahc, i, download_consts); 5897 downloaded++; 5898 } 5899 5900 ahc->num_critical_sections = cs_count; 5901 if (cs_count != 0) { 5902 5903 cs_count *= sizeof(struct cs); 5904 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 5905 if (ahc->critical_sections == NULL) 5906 panic("ahc_loadseq: Could not malloc"); 5907 memcpy(ahc->critical_sections, cs_table, cs_count); 5908 } 5909 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 5910 ahc_restart(ahc); 5911 5912 if (bootverbose) 5913 printf(" %d instructions downloaded\n", downloaded); 5914} 5915 5916static int 5917ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 5918 u_int start_instr, u_int *skip_addr) 5919{ 5920 struct patch *cur_patch; 5921 struct patch *last_patch; 5922 u_int num_patches; 5923 5924 num_patches = sizeof(patches)/sizeof(struct patch); 5925 last_patch = &patches[num_patches]; 5926 cur_patch = *start_patch; 5927 5928 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 5929 5930 if (cur_patch->patch_func(ahc) == 0) { 5931 5932 /* Start rejecting code */ 5933 *skip_addr = start_instr + cur_patch->skip_instr; 5934 cur_patch += cur_patch->skip_patch; 5935 } else { 5936 /* Accepted this patch. Advance to the next 5937 * one and wait for our intruction pointer to 5938 * hit this point. 5939 */ 5940 cur_patch++; 5941 } 5942 } 5943 5944 *start_patch = cur_patch; 5945 if (start_instr < *skip_addr) 5946 /* Still skipping */ 5947 return (0); 5948 5949 return (1); 5950} 5951 5952static void 5953ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 5954{ 5955 union ins_formats instr; 5956 struct ins_format1 *fmt1_ins; 5957 struct ins_format3 *fmt3_ins; 5958 u_int opcode; 5959 5960 /* 5961 * The firmware is always compiled into a little endian format. 5962 */ 5963 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 5964 5965 fmt1_ins = &instr.format1; 5966 fmt3_ins = NULL; 5967 5968 /* Pull the opcode */ 5969 opcode = instr.format1.opcode; 5970 switch (opcode) { 5971 case AIC_OP_JMP: 5972 case AIC_OP_JC: 5973 case AIC_OP_JNC: 5974 case AIC_OP_CALL: 5975 case AIC_OP_JNE: 5976 case AIC_OP_JNZ: 5977 case AIC_OP_JE: 5978 case AIC_OP_JZ: 5979 { 5980 struct patch *cur_patch; 5981 int address_offset; 5982 u_int address; 5983 u_int skip_addr; 5984 u_int i; 5985 5986 fmt3_ins = &instr.format3; 5987 address_offset = 0; 5988 address = fmt3_ins->address; 5989 cur_patch = patches; 5990 skip_addr = 0; 5991 5992 for (i = 0; i < address;) { 5993 5994 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 5995 5996 if (skip_addr > i) { 5997 int end_addr; 5998 5999 end_addr = MIN(address, skip_addr); 6000 address_offset += end_addr - i; 6001 i = skip_addr; 6002 } else { 6003 i++; 6004 } 6005 } 6006 address -= address_offset; 6007 fmt3_ins->address = address; 6008 /* FALLTHROUGH */ 6009 } 6010 case AIC_OP_OR: 6011 case AIC_OP_AND: 6012 case AIC_OP_XOR: 6013 case AIC_OP_ADD: 6014 case AIC_OP_ADC: 6015 case AIC_OP_BMOV: 6016 if (fmt1_ins->parity != 0) { 6017 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6018 } 6019 fmt1_ins->parity = 0; 6020 if ((ahc->features & AHC_CMD_CHAN) == 0 6021 && opcode == AIC_OP_BMOV) { 6022 /* 6023 * Block move was added at the same time 6024 * as the command channel. Verify that 6025 * this is only a move of a single element 6026 * and convert the BMOV to a MOV 6027 * (AND with an immediate of FF). 6028 */ 6029 if (fmt1_ins->immediate != 1) 6030 panic("%s: BMOV not supported\n", 6031 ahc_name(ahc)); 6032 fmt1_ins->opcode = AIC_OP_AND; 6033 fmt1_ins->immediate = 0xff; 6034 } 6035 /* FALLTHROUGH */ 6036 case AIC_OP_ROL: 6037 if ((ahc->features & AHC_ULTRA2) != 0) { 6038 int i, count; 6039 6040 /* Calculate odd parity for the instruction */ 6041 for (i = 0, count = 0; i < 31; i++) { 6042 uint32_t mask; 6043 6044 mask = 0x01 << i; 6045 if ((instr.integer & mask) != 0) 6046 count++; 6047 } 6048 if ((count & 0x01) == 0) 6049 instr.format1.parity = 1; 6050 } else { 6051 /* Compress the instruction for older sequencers */ 6052 if (fmt3_ins != NULL) { 6053 instr.integer = 6054 fmt3_ins->immediate 6055 | (fmt3_ins->source << 8) 6056 | (fmt3_ins->address << 16) 6057 | (fmt3_ins->opcode << 25); 6058 } else { 6059 instr.integer = 6060 fmt1_ins->immediate 6061 | (fmt1_ins->source << 8) 6062 | (fmt1_ins->destination << 16) 6063 | (fmt1_ins->ret << 24) 6064 | (fmt1_ins->opcode << 25); 6065 } 6066 } 6067 /* The sequencer is a little endian cpu */ 6068 instr.integer = ahc_htole32(instr.integer); 6069 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6070 break; 6071 default: 6072 panic("Unknown opcode encountered in seq program"); 6073 break; 6074 } 6075} 6076 6077void 6078ahc_dump_card_state(struct ahc_softc *ahc) 6079{ 6080 struct scb *scb; 6081 struct scb_tailq *untagged_q; 6082 int target; 6083 int maxtarget; 6084 int i; 6085 uint8_t last_phase; 6086 uint8_t qinpos; 6087 uint8_t qintail; 6088 uint8_t qoutpos; 6089 uint8_t scb_index; 6090 uint8_t saved_scbptr; 6091 6092 saved_scbptr = ahc_inb(ahc, SCBPTR); 6093 6094 last_phase = ahc_inb(ahc, LASTPHASE); 6095 printf("%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6096 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6097 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6098 printf("SCSISEQ = 0x%x, SBLKCTL = 0x%x\n", 6099 ahc_inb(ahc, SCSISEQ), ahc_inb(ahc, SBLKCTL)); 6100 printf(" DFCNTRL = 0x%x, DFSTATUS = 0x%x\n", 6101 ahc_inb(ahc, DFCNTRL), ahc_inb(ahc, DFSTATUS)); 6102 printf("LASTPHASE = 0x%x, SCSISIGI = 0x%x, SXFRCTL0 = 0x%x\n", 6103 last_phase, ahc_inb(ahc, SCSISIGI), ahc_inb(ahc, SXFRCTL0)); 6104 printf("SSTAT0 = 0x%x, SSTAT1 = 0x%x\n", 6105 ahc_inb(ahc, SSTAT0), ahc_inb(ahc, SSTAT1)); 6106 if ((ahc->features & AHC_DT) != 0) 6107 printf("SCSIPHASE = 0x%x\n", ahc_inb(ahc, SCSIPHASE)); 6108 printf("STACK == 0x%x, 0x%x, 0x%x, 0x%x\n", 6109 ahc_inb(ahc, STACK) | (ahc_inb(ahc, STACK) << 8), 6110 ahc_inb(ahc, STACK) | (ahc_inb(ahc, STACK) << 8), 6111 ahc_inb(ahc, STACK) | (ahc_inb(ahc, STACK) << 8), 6112 ahc_inb(ahc, STACK) | (ahc_inb(ahc, STACK) << 8)); 6113 printf("SCB count = %d\n", ahc->scb_data->numscbs); 6114 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6115 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6116 /* QINFIFO */ 6117 printf("QINFIFO entries: "); 6118 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6119 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6120 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6121 } else 6122 qinpos = ahc_inb(ahc, QINPOS); 6123 qintail = ahc->qinfifonext; 6124 while (qinpos != qintail) { 6125 printf("%d ", ahc->qinfifo[qinpos]); 6126 qinpos++; 6127 } 6128 printf("\n"); 6129 6130 printf("Waiting Queue entries: "); 6131 scb_index = ahc_inb(ahc, WAITING_SCBH); 6132 i = 0; 6133 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6134 ahc_outb(ahc, SCBPTR, scb_index); 6135 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6136 scb_index = ahc_inb(ahc, SCB_NEXT); 6137 } 6138 printf("\n"); 6139 6140 printf("Disconnected Queue entries: "); 6141 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6142 i = 0; 6143 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6144 ahc_outb(ahc, SCBPTR, scb_index); 6145 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6146 scb_index = ahc_inb(ahc, SCB_NEXT); 6147 } 6148 printf("\n"); 6149 6150 printf("QOUTFIFO entries: "); 6151 qoutpos = ahc->qoutfifonext; 6152 i = 0; 6153 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6154 printf("%d ", ahc->qoutfifo[qoutpos]); 6155 qoutpos++; 6156 } 6157 printf("\n"); 6158 6159 printf("Sequencer Free SCB List: "); 6160 scb_index = ahc_inb(ahc, FREE_SCBH); 6161 i = 0; 6162 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6163 ahc_outb(ahc, SCBPTR, scb_index); 6164 printf("%d ", scb_index); 6165 scb_index = ahc_inb(ahc, SCB_NEXT); 6166 } 6167 printf("\n"); 6168 6169 printf("Pending list: "); 6170 i = 0; 6171 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6172 if (i++ > 256) 6173 break; 6174 printf("%d ", scb->hscb->tag); 6175 } 6176 printf("\n"); 6177 6178 printf("Kernel Free SCB list: "); 6179 i = 0; 6180 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6181 if (i++ > 256) 6182 break; 6183 printf("%d ", scb->hscb->tag); 6184 } 6185 printf("\n"); 6186 6187 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6188 for (target = 0; target <= maxtarget; target++) { 6189 untagged_q = &ahc->untagged_queues[target]; 6190 if (TAILQ_FIRST(untagged_q) == NULL) 6191 continue; 6192 printf("Untagged Q(%d): ", target); 6193 i = 0; 6194 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6195 if (i++ > 256) 6196 break; 6197 printf("%d ", scb->hscb->tag); 6198 } 6199 printf("\n"); 6200 } 6201 6202 ahc_platform_dump_card_state(ahc); 6203 ahc_outb(ahc, SCBPTR, saved_scbptr); 6204} 6205 6206/************************* Target Mode ****************************************/ 6207#ifdef AHC_TARGET_MODE 6208cam_status 6209ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 6210 struct ahc_tmode_tstate **tstate, 6211 struct ahc_tmode_lstate **lstate, 6212 int notfound_failure) 6213{ 6214 6215 if ((ahc->features & AHC_TARGETMODE) == 0) 6216 return (CAM_REQ_INVALID); 6217 6218 /* 6219 * Handle the 'black hole' device that sucks up 6220 * requests to unattached luns on enabled targets. 6221 */ 6222 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 6223 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 6224 *tstate = NULL; 6225 *lstate = ahc->black_hole; 6226 } else { 6227 u_int max_id; 6228 6229 max_id = (ahc->features & AHC_WIDE) ? 15 : 7; 6230 if (ccb->ccb_h.target_id > max_id) 6231 return (CAM_TID_INVALID); 6232 6233 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 6234 return (CAM_LUN_INVALID); 6235 6236 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 6237 *lstate = NULL; 6238 if (*tstate != NULL) 6239 *lstate = 6240 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 6241 } 6242 6243 if (notfound_failure != 0 && *lstate == NULL) 6244 return (CAM_PATH_INVALID); 6245 6246 return (CAM_REQ_CMP); 6247} 6248 6249void 6250ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 6251{ 6252 struct ahc_tmode_tstate *tstate; 6253 struct ahc_tmode_lstate *lstate; 6254 struct ccb_en_lun *cel; 6255 cam_status status; 6256 u_int target; 6257 u_int lun; 6258 u_int target_mask; 6259 u_long s; 6260 char channel; 6261 6262 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 6263 /*notfound_failure*/FALSE); 6264 6265 if (status != CAM_REQ_CMP) { 6266 ccb->ccb_h.status = status; 6267 return; 6268 } 6269 6270 if ((ahc->features & AHC_MULTIROLE) != 0) { 6271 u_int our_id; 6272 6273 if (cam_sim_bus(sim) == 0) 6274 our_id = ahc->our_id; 6275 else 6276 our_id = ahc->our_id_b; 6277 6278 if (ccb->ccb_h.target_id != our_id) { 6279 if ((ahc->features & AHC_MULTI_TID) != 0 6280 && (ahc->flags & AHC_INITIATORROLE) != 0) { 6281 /* 6282 * Only allow additional targets if 6283 * the initiator role is disabled. 6284 * The hardware cannot handle a re-select-in 6285 * on the initiator id during a re-select-out 6286 * on a different target id. 6287 */ 6288 status = CAM_TID_INVALID; 6289 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 6290 || ahc->enabled_luns > 0) { 6291 /* 6292 * Only allow our target id to change 6293 * if the initiator role is not configured 6294 * and there are no enabled luns which 6295 * are attached to the currently registered 6296 * scsi id. 6297 */ 6298 status = CAM_TID_INVALID; 6299 } 6300 } 6301 } 6302 6303 if (status != CAM_REQ_CMP) { 6304 ccb->ccb_h.status = status; 6305 return; 6306 } 6307 6308 /* 6309 * We now have an id that is valid. 6310 * If we aren't in target mode, switch modes. 6311 */ 6312 if ((ahc->flags & AHC_TARGETROLE) == 0 6313 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 6314 u_long s; 6315 6316 printf("Configuring Target Mode\n"); 6317 ahc_lock(ahc, &s); 6318 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 6319 ccb->ccb_h.status = CAM_BUSY; 6320 ahc_unlock(ahc, &s); 6321 return; 6322 } 6323 ahc->flags |= AHC_TARGETROLE; 6324 if ((ahc->features & AHC_MULTIROLE) == 0) 6325 ahc->flags &= ~AHC_INITIATORROLE; 6326 ahc_pause(ahc); 6327 ahc_loadseq(ahc); 6328 ahc_unlock(ahc, &s); 6329 } 6330 cel = &ccb->cel; 6331 target = ccb->ccb_h.target_id; 6332 lun = ccb->ccb_h.target_lun; 6333 channel = SIM_CHANNEL(ahc, sim); 6334 target_mask = 0x01 << target; 6335 if (channel == 'B') 6336 target_mask <<= 8; 6337 6338 if (cel->enable != 0) { 6339 u_int scsiseq; 6340 6341 /* Are we already enabled?? */ 6342 if (lstate != NULL) { 6343 xpt_print_path(ccb->ccb_h.path); 6344 printf("Lun already enabled\n"); 6345 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 6346 return; 6347 } 6348 6349 if (cel->grp6_len != 0 6350 || cel->grp7_len != 0) { 6351 /* 6352 * Don't (yet?) support vendor 6353 * specific commands. 6354 */ 6355 ccb->ccb_h.status = CAM_REQ_INVALID; 6356 printf("Non-zero Group Codes\n"); 6357 return; 6358 } 6359 6360 /* 6361 * Seems to be okay. 6362 * Setup our data structures. 6363 */ 6364 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 6365 tstate = ahc_alloc_tstate(ahc, target, channel); 6366 if (tstate == NULL) { 6367 xpt_print_path(ccb->ccb_h.path); 6368 printf("Couldn't allocate tstate\n"); 6369 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6370 return; 6371 } 6372 } 6373 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 6374 if (lstate == NULL) { 6375 xpt_print_path(ccb->ccb_h.path); 6376 printf("Couldn't allocate lstate\n"); 6377 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6378 return; 6379 } 6380 memset(lstate, 0, sizeof(*lstate)); 6381 status = xpt_create_path(&lstate->path, /*periph*/NULL, 6382 xpt_path_path_id(ccb->ccb_h.path), 6383 xpt_path_target_id(ccb->ccb_h.path), 6384 xpt_path_lun_id(ccb->ccb_h.path)); 6385 if (status != CAM_REQ_CMP) { 6386 free(lstate, M_DEVBUF); 6387 xpt_print_path(ccb->ccb_h.path); 6388 printf("Couldn't allocate path\n"); 6389 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6390 return; 6391 } 6392 SLIST_INIT(&lstate->accept_tios); 6393 SLIST_INIT(&lstate->immed_notifies); 6394 ahc_lock(ahc, &s); 6395 ahc_pause(ahc); 6396 if (target != CAM_TARGET_WILDCARD) { 6397 tstate->enabled_luns[lun] = lstate; 6398 ahc->enabled_luns++; 6399 6400 if ((ahc->features & AHC_MULTI_TID) != 0) { 6401 u_int targid_mask; 6402 6403 targid_mask = ahc_inb(ahc, TARGID) 6404 | (ahc_inb(ahc, TARGID + 1) << 8); 6405 6406 targid_mask |= target_mask; 6407 ahc_outb(ahc, TARGID, targid_mask); 6408 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 6409 6410 ahc_update_scsiid(ahc, targid_mask); 6411 } else { 6412 u_int our_id; 6413 char channel; 6414 6415 channel = SIM_CHANNEL(ahc, sim); 6416 our_id = SIM_SCSI_ID(ahc, sim); 6417 6418 /* 6419 * This can only happen if selections 6420 * are not enabled 6421 */ 6422 if (target != our_id) { 6423 u_int sblkctl; 6424 char cur_channel; 6425 int swap; 6426 6427 sblkctl = ahc_inb(ahc, SBLKCTL); 6428 cur_channel = (sblkctl & SELBUSB) 6429 ? 'B' : 'A'; 6430 if ((ahc->features & AHC_TWIN) == 0) 6431 cur_channel = 'A'; 6432 swap = cur_channel != channel; 6433 if (channel == 'A') 6434 ahc->our_id = target; 6435 else 6436 ahc->our_id_b = target; 6437 6438 if (swap) 6439 ahc_outb(ahc, SBLKCTL, 6440 sblkctl ^ SELBUSB); 6441 6442 ahc_outb(ahc, SCSIID, target); 6443 6444 if (swap) 6445 ahc_outb(ahc, SBLKCTL, sblkctl); 6446 } 6447 } 6448 } else 6449 ahc->black_hole = lstate; 6450 /* Allow select-in operations */ 6451 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 6452 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 6453 scsiseq |= ENSELI; 6454 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 6455 scsiseq = ahc_inb(ahc, SCSISEQ); 6456 scsiseq |= ENSELI; 6457 ahc_outb(ahc, SCSISEQ, scsiseq); 6458 } 6459 ahc_unpause(ahc); 6460 ahc_unlock(ahc, &s); 6461 ccb->ccb_h.status = CAM_REQ_CMP; 6462 xpt_print_path(ccb->ccb_h.path); 6463 printf("Lun now enabled for target mode\n"); 6464 } else { 6465 struct scb *scb; 6466 int i, empty; 6467 6468 if (lstate == NULL) { 6469 ccb->ccb_h.status = CAM_LUN_INVALID; 6470 return; 6471 } 6472 6473 ahc_lock(ahc, &s); 6474 6475 ccb->ccb_h.status = CAM_REQ_CMP; 6476 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6477 struct ccb_hdr *ccbh; 6478 6479 ccbh = &scb->io_ctx->ccb_h; 6480 if (ccbh->func_code == XPT_CONT_TARGET_IO 6481 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 6482 printf("CTIO pending\n"); 6483 ccb->ccb_h.status = CAM_REQ_INVALID; 6484 ahc_unlock(ahc, &s); 6485 return; 6486 } 6487 } 6488 6489 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 6490 printf("ATIOs pending\n"); 6491 ccb->ccb_h.status = CAM_REQ_INVALID; 6492 } 6493 6494 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 6495 printf("INOTs pending\n"); 6496 ccb->ccb_h.status = CAM_REQ_INVALID; 6497 } 6498 6499 if (ccb->ccb_h.status != CAM_REQ_CMP) { 6500 ahc_unlock(ahc, &s); 6501 return; 6502 } 6503 6504 xpt_print_path(ccb->ccb_h.path); 6505 printf("Target mode disabled\n"); 6506 xpt_free_path(lstate->path); 6507 free(lstate, M_DEVBUF); 6508 6509 ahc_pause(ahc); 6510 /* Can we clean up the target too? */ 6511 if (target != CAM_TARGET_WILDCARD) { 6512 tstate->enabled_luns[lun] = NULL; 6513 ahc->enabled_luns--; 6514 for (empty = 1, i = 0; i < 8; i++) 6515 if (tstate->enabled_luns[i] != NULL) { 6516 empty = 0; 6517 break; 6518 } 6519 6520 if (empty) { 6521 ahc_free_tstate(ahc, target, channel, 6522 /*force*/FALSE); 6523 if (ahc->features & AHC_MULTI_TID) { 6524 u_int targid_mask; 6525 6526 targid_mask = ahc_inb(ahc, TARGID) 6527 | (ahc_inb(ahc, TARGID + 1) 6528 << 8); 6529 6530 targid_mask &= ~target_mask; 6531 ahc_outb(ahc, TARGID, targid_mask); 6532 ahc_outb(ahc, TARGID+1, 6533 (targid_mask >> 8)); 6534 ahc_update_scsiid(ahc, targid_mask); 6535 } 6536 } 6537 } else { 6538 6539 ahc->black_hole = NULL; 6540 6541 /* 6542 * We can't allow selections without 6543 * our black hole device. 6544 */ 6545 empty = TRUE; 6546 } 6547 if (ahc->enabled_luns == 0) { 6548 /* Disallow select-in */ 6549 u_int scsiseq; 6550 6551 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 6552 scsiseq &= ~ENSELI; 6553 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 6554 scsiseq = ahc_inb(ahc, SCSISEQ); 6555 scsiseq &= ~ENSELI; 6556 ahc_outb(ahc, SCSISEQ, scsiseq); 6557 6558 if ((ahc->features & AHC_MULTIROLE) == 0) { 6559 printf("Configuring Initiator Mode\n"); 6560 ahc->flags &= ~AHC_TARGETROLE; 6561 ahc->flags |= AHC_INITIATORROLE; 6562 ahc_pause(ahc); 6563 ahc_loadseq(ahc); 6564 } 6565 } 6566 ahc_unpause(ahc); 6567 ahc_unlock(ahc, &s); 6568 } 6569} 6570 6571static void 6572ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 6573{ 6574 u_int scsiid_mask; 6575 u_int scsiid; 6576 6577 if ((ahc->features & AHC_MULTI_TID) == 0) 6578 panic("ahc_update_scsiid called on non-multitid unit\n"); 6579 6580 /* 6581 * Since we will rely on the the TARGID mask 6582 * for selection enables, ensure that OID 6583 * in SCSIID is not set to some other ID 6584 * that we don't want to allow selections on. 6585 */ 6586 if ((ahc->features & AHC_ULTRA2) != 0) 6587 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 6588 else 6589 scsiid = ahc_inb(ahc, SCSIID); 6590 scsiid_mask = 0x1 << (scsiid & OID); 6591 if ((targid_mask & scsiid_mask) == 0) { 6592 u_int our_id; 6593 6594 /* ffs counts from 1 */ 6595 our_id = ffs(targid_mask); 6596 if (our_id == 0) 6597 our_id = ahc->our_id; 6598 else 6599 our_id--; 6600 scsiid &= TID; 6601 scsiid |= our_id; 6602 } 6603 if ((ahc->features & AHC_ULTRA2) != 0) 6604 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 6605 else 6606 ahc_outb(ahc, SCSIID, scsiid); 6607} 6608 6609void 6610ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 6611{ 6612 struct target_cmd *cmd; 6613 6614 /* 6615 * If the card supports auto-access pause, 6616 * we can access the card directly regardless 6617 * of whether it is paused or not. 6618 */ 6619 if ((ahc->features & AHC_AUTOPAUSE) != 0) 6620 paused = TRUE; 6621 6622 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 6623 6624 /* 6625 * Only advance through the queue if we 6626 * have the resources to process the command. 6627 */ 6628 if (ahc_handle_target_cmd(ahc, cmd) != 0) 6629 break; 6630 6631 ahc->tqinfifonext++; 6632 cmd->cmd_valid = 0; 6633 6634 /* 6635 * Lazily update our position in the target mode incomming 6636 * command queue as seen by the sequencer. 6637 */ 6638 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 6639 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 6640 u_int hs_mailbox; 6641 6642 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 6643 hs_mailbox &= ~HOST_TQINPOS; 6644 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 6645 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 6646 } else { 6647 if (!paused) 6648 ahc_pause(ahc); 6649 ahc_outb(ahc, KERNEL_TQINPOS, 6650 ahc->tqinfifonext & HOST_TQINPOS); 6651 if (!paused) 6652 ahc_unpause(ahc); 6653 } 6654 } 6655 } 6656} 6657 6658static int 6659ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 6660{ 6661 struct ahc_tmode_tstate *tstate; 6662 struct ahc_tmode_lstate *lstate; 6663 struct ccb_accept_tio *atio; 6664 uint8_t *byte; 6665 int initiator; 6666 int target; 6667 int lun; 6668 6669 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 6670 target = SCSIID_OUR_ID(cmd->scsiid); 6671 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 6672 6673 byte = cmd->bytes; 6674 tstate = ahc->enabled_targets[target]; 6675 lstate = NULL; 6676 if (tstate != NULL) 6677 lstate = tstate->enabled_luns[lun]; 6678 6679 /* 6680 * Commands for disabled luns go to the black hole driver. 6681 */ 6682 if (lstate == NULL) 6683 lstate = ahc->black_hole; 6684 6685 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 6686 if (atio == NULL) { 6687 ahc->flags |= AHC_TQINFIFO_BLOCKED; 6688 /* 6689 * Wait for more ATIOs from the peripheral driver for this lun. 6690 */ 6691 return (1); 6692 } else 6693 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 6694#if 0 6695 printf("Incoming command from %d for %d:%d%s\n", 6696 initiator, target, lun, 6697 lstate == ahc->black_hole ? "(Black Holed)" : ""); 6698#endif 6699 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 6700 6701 if (lstate == ahc->black_hole) { 6702 /* Fill in the wildcards */ 6703 atio->ccb_h.target_id = target; 6704 atio->ccb_h.target_lun = lun; 6705 } 6706 6707 /* 6708 * Package it up and send it off to 6709 * whomever has this lun enabled. 6710 */ 6711 atio->sense_len = 0; 6712 atio->init_id = initiator; 6713 if (byte[0] != 0xFF) { 6714 /* Tag was included */ 6715 atio->tag_action = *byte++; 6716 atio->tag_id = *byte++; 6717 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 6718 } else { 6719 atio->ccb_h.flags = 0; 6720 } 6721 byte++; 6722 6723 /* Okay. Now determine the cdb size based on the command code */ 6724 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 6725 case 0: 6726 atio->cdb_len = 6; 6727 break; 6728 case 1: 6729 case 2: 6730 atio->cdb_len = 10; 6731 break; 6732 case 4: 6733 atio->cdb_len = 16; 6734 break; 6735 case 5: 6736 atio->cdb_len = 12; 6737 break; 6738 case 3: 6739 default: 6740 /* Only copy the opcode. */ 6741 atio->cdb_len = 1; 6742 printf("Reserved or VU command code type encountered\n"); 6743 break; 6744 } 6745 6746 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 6747 6748 atio->ccb_h.status |= CAM_CDB_RECVD; 6749 6750 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 6751 /* 6752 * We weren't allowed to disconnect. 6753 * We're hanging on the bus until a 6754 * continue target I/O comes in response 6755 * to this accept tio. 6756 */ 6757#if 0 6758 printf("Received Immediate Command %d:%d:%d - %p\n", 6759 initiator, target, lun, ahc->pending_device); 6760#endif 6761 ahc->pending_device = lstate; 6762 ahc_freeze_ccb((union ccb *)atio); 6763 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 6764 } 6765 xpt_done((union ccb*)atio); 6766 return (0); 6767} 6768 6769#endif 6770