aic7xxx.c revision 41816
1/* 2 * Generic driver for the aic7xxx based adaptec SCSI controllers 3 * Product specific probe and attach routines can be found in: 4 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 5 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 6 * aic7880, aic7870, aic7860, and aic7850 controllers 7 * 8 * Copyright (c) 1994, 1995, 1996, 1997, 1998 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification, immediately at the beginning of the file. 17 * 2. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * Where this Software is combined with software released under the terms of 21 * the GNU Public License ("GPL") and the terms of the GPL would require the 22 * combined work to also be released under the terms of the GPL, the terms 23 * and conditions of this License will apply in addition to those of the 24 * GPL with the exception of any terms or conditions of this License that 25 * conflict with, or are expressly prohibited by, the GPL. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 31 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * $Id: aic7xxx.c,v 1.12 1998/12/10 04:14:49 gibbs Exp $ 40 */ 41/* 42 * A few notes on features of the driver. 43 * 44 * SCB paging takes advantage of the fact that devices stay disconnected 45 * from the bus a relatively long time and that while they're disconnected, 46 * having the SCBs for these transactions down on the host adapter is of 47 * little use. Instead of leaving this idle SCB down on the card we copy 48 * it back up into kernel memory and reuse the SCB slot on the card to 49 * schedule another transaction. This can be a real payoff when doing random 50 * I/O to tagged queueing devices since there are more transactions active at 51 * once for the device to sort for optimal seek reduction. The algorithm goes 52 * like this... 53 * 54 * The sequencer maintains two lists of its hardware SCBs. The first is the 55 * singly linked free list which tracks all SCBs that are not currently in 56 * use. The second is the doubly linked disconnected list which holds the 57 * SCBs of transactions that are in the disconnected state sorted most 58 * recently disconnected first. When the kernel queues a transaction to 59 * the card, a hardware SCB to "house" this transaction is retrieved from 60 * either of these two lists. If the SCB came from the disconnected list, 61 * a check is made to see if any data transfer or SCB linking (more on linking 62 * in a bit) information has been changed since it was copied from the host 63 * and if so, DMAs the SCB back up before it can be used. Once a hardware 64 * SCB has been obtained, the SCB is DMAed from the host. Before any work 65 * can begin on this SCB, the sequencer must ensure that either the SCB is 66 * for a tagged transaction or the target is not already working on another 67 * non-tagged transaction. If a conflict arises in the non-tagged case, the 68 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 69 * field in that SCB to this next SCB to execute. To facilitate finding 70 * active non-tagged SCBs, the last four bytes of up to the first four hardware 71 * SCBs serve as a storage area for the currently active SCB ID for each 72 * target. 73 * 74 * When a device reconnects, a search is made of the hardware SCBs to find 75 * the SCB for this transaction. If the search fails, a hardware SCB is 76 * pulled from either the free or disconnected SCB list and the proper 77 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 78 * in the control byte of the SCB while it was disconnected, the sequencer 79 * will assert ATN and attempt to issue a message to the host. 80 * 81 * When a command completes, a check for non-zero status and residuals is 82 * made. If either of these conditions exists, the SCB is DMAed back up to 83 * the host so that it can interpret this information. Additionally, in the 84 * case of bad status, the sequencer generates a special interrupt and pauses 85 * itself. This allows the host to setup a request sense command if it 86 * chooses for this target synchronously with the error so that sense 87 * information isn't lost. 88 * 89 */ 90 91#include <opt_aic7xxx.h> 92 93#include <pci.h> 94#include <stddef.h> /* For offsetof */ 95 96#include <sys/param.h> 97#include <sys/systm.h> 98#include <sys/malloc.h> 99#include <sys/buf.h> 100#include <sys/proc.h> 101 102#include <cam/cam.h> 103#include <cam/cam_ccb.h> 104#include <cam/cam_sim.h> 105#include <cam/cam_xpt_sim.h> 106#include <cam/cam_debug.h> 107 108#include <cam/scsi/scsi_all.h> 109#include <cam/scsi/scsi_message.h> 110 111#if NPCI > 0 112#include <machine/bus_memio.h> 113#endif 114#include <machine/bus_pio.h> 115#include <machine/bus.h> 116#include <machine/clock.h> 117 118#include <vm/vm.h> 119#include <vm/vm_param.h> 120#include <vm/pmap.h> 121 122#include <dev/aic7xxx/aic7xxx.h> 123#include <dev/aic7xxx/sequencer.h> 124 125#include <aic7xxx_reg.h> 126#include <aic7xxx_seq.h> 127 128#include <sys/kernel.h> 129 130#ifndef AHC_TMODE_ENABLE 131#define AHC_TMODE_ENABLE 0 132#endif 133 134#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 135#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 136#define ALL_CHANNELS '\0' 137#define ALL_TARGETS_MASK 0xFFFF 138 139#define SIM_IS_SCSIBUS_B(ahc, sim) \ 140 (sim == ahc->sim_b) 141#define SCB_IS_SCSIBUS_B(scb) \ 142 (((scb)->hscb->tcl & SELBUSB) != 0) 143#define SCB_TARGET(scb) \ 144 (((scb)->hscb->tcl & TID) >> 4) 145#define SCB_CHANNEL(scb) \ 146 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 147#define SCB_LUN(scb) \ 148 ((scb)->hscb->tcl & LID) 149#define SCB_TARGET_OFFSET(scb) \ 150 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 151#define SCB_TARGET_MASK(scb) \ 152 (0x01 << (SCB_TARGET_OFFSET(scb))) 153 154#define ccb_scb_ptr spriv_ptr0 155#define ccb_ahc_ptr spriv_ptr1 156 157typedef enum { 158 ROLE_UNKNOWN, 159 ROLE_INITIATOR, 160 ROLE_TARGET, 161} role_t; 162 163struct ahc_devinfo { 164 int target_offset; 165 u_int16_t target_mask; 166 u_int8_t target; 167 u_int8_t lun; 168 char channel; 169 role_t role; /* 170 * Only guaranteed to be correct if not 171 * in the busfree state. 172 */ 173}; 174 175typedef enum { 176 SEARCH_COMPLETE, 177 SEARCH_COUNT, 178 SEARCH_REMOVE 179} ahc_search_action; 180 181u_long ahc_unit = 0; 182 183#ifdef AHC_DEBUG 184static int ahc_debug = AHC_DEBUG; 185#endif 186 187#if NPCI > 0 188void ahc_pci_intr(struct ahc_softc *ahc); 189#endif 190 191static void ahc_dump_targcmd(struct target_cmd *cmd); 192static void ahc_shutdown(int howto, void *arg); 193static void ahcminphys(struct buf *bp); 194static cam_status 195 ahc_find_tmode_devs(struct ahc_softc *ahc, 196 struct cam_sim *sim, union ccb *ccb, 197 struct tmode_tstate **tstate, 198 struct tmode_lstate **lstate, 199 int notfound_failure); 200static void ahc_action(struct cam_sim *sim, union ccb *ccb); 201static void ahc_async(void *callback_arg, u_int32_t code, 202 struct cam_path *path, void *arg); 203static void ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, 204 int nsegments, int error); 205static void ahc_poll(struct cam_sim *sim); 206static void ahc_setup_data(struct ahc_softc *ahc, 207 struct ccb_scsiio *csio, struct scb *scb); 208static void ahc_freeze_devq(struct ahc_softc *ahc, struct cam_path *path); 209static struct scb * 210 ahc_get_scb(struct ahc_softc *ahc); 211static void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb); 212static struct scb * 213 ahc_alloc_scb(struct ahc_softc *ahc); 214static void ahc_fetch_devinfo(struct ahc_softc *ahc, 215 struct ahc_devinfo *devinfo); 216static void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 217 u_int target, u_int lun, char channel, 218 role_t role); 219static u_int ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev); 220static void ahc_done(struct ahc_softc *ahc, struct scb *scbp); 221static void ahc_handle_target_cmd(struct ahc_softc *ahc, 222 struct target_cmd *cmd); 223static void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 224static void ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat); 225static void ahc_build_transfer_msg(struct ahc_softc *ahc, 226 struct ahc_devinfo *devinfo); 227static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 228 struct ahc_devinfo *devinfo, 229 struct scb *scb); 230static void ahc_setup_target_msgin(struct ahc_softc *ahc, 231 struct ahc_devinfo *devinfo); 232static void ahc_handle_msg_reject(struct ahc_softc *ahc, 233 struct ahc_devinfo *devinfo); 234static void ahc_clear_msg_state(struct ahc_softc *ahc); 235static void ahc_handle_message_phase(struct ahc_softc *ahc, 236 struct cam_path *path); 237static int ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full); 238static int ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path, 239 struct ahc_devinfo *devinfo); 240static void ahc_handle_devreset(struct ahc_softc *ahc, int target, 241 char channel, cam_status status, 242 ac_code acode, char *message, 243 int verbose_only); 244static void ahc_loadseq(struct ahc_softc *ahc); 245static int ahc_check_patch(struct ahc_softc *ahc, 246 struct patch **start_patch, 247 int start_instr, int *skip_addr); 248static void ahc_download_instr(struct ahc_softc *ahc, 249 int instrptr, u_int8_t *dconsts); 250static int ahc_match_scb(struct scb *scb, int target, char channel, 251 int lun, u_int tag); 252#ifdef AHC_DEBUG 253static void ahc_print_scb(struct scb *scb); 254#endif 255static int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 256 char channel, int lun, u_int tag, 257 u_int32_t status, ahc_search_action action); 258static void ahc_abort_ccb(struct ahc_softc *ahc, struct cam_sim *sim, 259 union ccb *ccb); 260static int ahc_reset_channel(struct ahc_softc *ahc, char channel, 261 int initiate_reset); 262static int ahc_abort_scbs(struct ahc_softc *ahc, int target, 263 char channel, int lun, u_int tag, 264 u_int32_t status); 265static int ahc_search_disc_list(struct ahc_softc *ahc, int target, 266 char channel, int lun, u_int tag); 267static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 268 u_int prev, u_int scbptr); 269static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 270static void ahc_clear_intstat(struct ahc_softc *ahc); 271static void ahc_reset_current_bus(struct ahc_softc *ahc); 272static struct ahc_syncrate * 273 ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period); 274static struct ahc_syncrate * 275 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 276 u_int maxsync); 277static u_int ahc_find_period(struct ahc_softc *ahc, u_int scsirate, 278 u_int maxsync); 279static void ahc_validate_offset(struct ahc_softc *ahc, 280 struct ahc_syncrate *syncrate, 281 u_int *offset, int wide); 282static void ahc_update_target_msg_request(struct ahc_softc *ahc, 283 struct ahc_devinfo *devinfo, 284 struct ahc_target_tinfo *tinfo, 285 int force); 286static int ahc_create_path(struct ahc_softc *ahc, 287 struct ahc_devinfo *devinfo, 288 struct cam_path **path); 289static void ahc_set_syncrate(struct ahc_softc *ahc, 290 struct ahc_devinfo *devinfo, 291 struct cam_path *path, 292 struct ahc_syncrate *syncrate, 293 u_int period, u_int offset, u_int type); 294static void ahc_set_width(struct ahc_softc *ahc, 295 struct ahc_devinfo *devinfo, 296 struct cam_path *path, u_int width, u_int type); 297static void ahc_construct_sdtr(struct ahc_softc *ahc, 298 u_int period, u_int offset); 299 300static void ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width); 301 302static void ahc_calc_residual(struct scb *scb); 303 304static void ahc_update_pending_syncrates(struct ahc_softc *ahc); 305 306static void ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb); 307 308static timeout_t 309 ahc_timeout; 310static __inline int sequencer_paused(struct ahc_softc *ahc); 311static __inline void pause_sequencer(struct ahc_softc *ahc); 312static __inline void unpause_sequencer(struct ahc_softc *ahc, 313 int unpause_always); 314static __inline void restart_sequencer(struct ahc_softc *ahc); 315static __inline u_int ahc_index_busy_tcl(struct ahc_softc *ahc, 316 u_int tcl, int unbusy); 317 318static __inline void ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb); 319 320static __inline void ahc_freeze_ccb(union ccb* ccb); 321static __inline cam_status ahc_ccb_status(union ccb* ccb); 322static __inline void ahc_set_ccb_status(union ccb* ccb, 323 cam_status status); 324 325static __inline u_int32_t 326ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 327{ 328 return (ahc->hscb_busaddr + (sizeof(struct hardware_scb) * index)); 329} 330 331#define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 332 333static __inline int 334sequencer_paused(struct ahc_softc *ahc) 335{ 336 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 337} 338 339static __inline void 340pause_sequencer(struct ahc_softc *ahc) 341{ 342 ahc_outb(ahc, HCNTRL, ahc->pause); 343 344 /* 345 * Since the sequencer can disable pausing in a critical section, we 346 * must loop until it actually stops. 347 */ 348 while (sequencer_paused(ahc) == 0) 349 ; 350} 351 352static __inline void 353unpause_sequencer(struct ahc_softc *ahc, int unpause_always) 354{ 355 if (unpause_always 356 || (ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 357 ahc_outb(ahc, HCNTRL, ahc->unpause); 358} 359 360/* 361 * Restart the sequencer program from address zero 362 */ 363static __inline void 364restart_sequencer(struct ahc_softc *ahc) 365{ 366 pause_sequencer(ahc); 367 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 368 unpause_sequencer(ahc, /*unpause_always*/TRUE); 369} 370 371static __inline u_int 372ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl, int unbusy) 373{ 374 u_int scbid; 375 376 scbid = ahc->untagged_scbs[tcl]; 377 if (unbusy) 378 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 379 380 return (scbid); 381} 382 383static __inline void 384ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 385{ 386 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 387} 388 389static __inline void 390ahc_freeze_ccb(union ccb* ccb) 391{ 392 if ((ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) { 393 ccb->ccb_h.status |= CAM_DEV_QFRZN; 394 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 395 } 396} 397 398static __inline cam_status 399ahc_ccb_status(union ccb* ccb) 400{ 401 return (ccb->ccb_h.status & CAM_STATUS_MASK); 402} 403 404static __inline void 405ahc_set_ccb_status(union ccb* ccb, cam_status status) 406{ 407 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 408 ccb->ccb_h.status |= status; 409} 410 411char * 412ahc_name(struct ahc_softc *ahc) 413{ 414 static char name[10]; 415 416 snprintf(name, sizeof(name), "ahc%d", ahc->unit); 417 return (name); 418} 419 420#ifdef AHC_DEBUG 421static void 422ahc_print_scb(struct scb *scb) 423{ 424 struct hardware_scb *hscb = scb->hscb; 425 426 printf("scb:%p control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 427 scb, 428 hscb->control, 429 hscb->tcl, 430 hscb->cmdlen, 431 hscb->cmdpointer ); 432 printf(" datlen:%d data:0x%lx segs:0x%x segp:0x%lx\n", 433 hscb->datalen, 434 hscb->data, 435 hscb->SG_count, 436 hscb->SG_pointer); 437 printf(" sg_addr:%lx sg_len:%ld\n", 438 scb->ahc_dma[0].addr, 439 scb->ahc_dma[0].len); 440 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 441 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 442 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 443 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 444 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 445} 446#endif 447 448static struct { 449 u_int8_t errno; 450 char *errmesg; 451} hard_error[] = { 452 { ILLHADDR, "Illegal Host Access" }, 453 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 454 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 455 { SQPARERR, "Sequencer Parity Error" }, 456 { DPARERR, "Data-path Parity Error" }, 457 { MPARERR, "Scratch or SCB Memory Parity Error" }, 458 { PCIERRSTAT, "PCI Error detected" }, 459 { CIOPARERR, "CIOBUS Parity Error" }, 460}; 461 462 463/* 464 * Valid SCSIRATE values. (p. 3-17) 465 * Provides a mapping of tranfer periods in ns to the proper value to 466 * stick in the scsiscfr reg to use that transfer rate. 467 */ 468#define AHC_SYNCRATE_ULTRA2 0 469#define AHC_SYNCRATE_ULTRA 2 470#define AHC_SYNCRATE_FAST 5 471static struct ahc_syncrate ahc_syncrates[] = { 472 /* ultra2 fast/ultra period rate */ 473 { 0x13, 0x000, 10, "40.0" }, 474 { 0x14, 0x000, 11, "33.0" }, 475 { 0x15, 0x100, 12, "20.0" }, 476 { 0x16, 0x110, 15, "16.0" }, 477 { 0x17, 0x120, 18, "13.4" }, 478 { 0x18, 0x000, 25, "10.0" }, 479 { 0x19, 0x010, 31, "8.0" }, 480 { 0x1a, 0x020, 37, "6.67" }, 481 { 0x1b, 0x030, 43, "5.7" }, 482 { 0x10, 0x040, 50, "5.0" }, 483 { 0x00, 0x050, 56, "4.4" }, 484 { 0x00, 0x060, 62, "4.0" }, 485 { 0x00, 0x070, 68, "3.6" }, 486 { 0x00, 0x000, 0, NULL } 487}; 488 489/* 490 * Allocate a controller structure for a new device and initialize it. 491 */ 492struct ahc_softc * 493ahc_alloc(int unit, u_int32_t iobase, vm_offset_t maddr, ahc_chip chip, 494 ahc_feature features, ahc_flag flags, struct scb_data *scb_data) 495{ 496 /* 497 * find unit and check we have that many defined 498 */ 499 struct ahc_softc *ahc; 500 size_t alloc_size; 501 502 /* 503 * Allocate a storage area for us 504 */ 505 if (scb_data == NULL) 506 /* 507 * We are not sharing SCB space with another controller 508 * so allocate our own SCB data space. 509 */ 510 alloc_size = sizeof(struct full_ahc_softc); 511 else 512 alloc_size = sizeof(struct ahc_softc); 513 ahc = malloc(alloc_size, M_DEVBUF, M_NOWAIT); 514 if (!ahc) { 515 printf("ahc%d: cannot malloc!\n", unit); 516 return NULL; 517 } 518 bzero(ahc, alloc_size); 519 if (scb_data == NULL) { 520 struct full_ahc_softc* full_softc = (struct full_ahc_softc*)ahc; 521 ahc->scb_data = &full_softc->scb_data_storage; 522 STAILQ_INIT(&ahc->scb_data->free_scbs); 523 } else 524 ahc->scb_data = scb_data; 525 LIST_INIT(&ahc->pending_ccbs); 526 ahc->unit = unit; 527 528 /* 529 * XXX This should be done by the bus specific probe stubs with 530 * the bus layer providing the bsh and tag. Unfortunately, 531 * we need to clean up how we configure things before this 532 * can happen. 533 */ 534 if (maddr != NULL) { 535 ahc->tag = I386_BUS_SPACE_MEM; 536 ahc->bsh = (bus_space_handle_t)maddr; 537 } else { 538 ahc->tag = I386_BUS_SPACE_IO; 539 ahc->bsh = (bus_space_handle_t)iobase; 540 } 541 ahc->chip = chip; 542 ahc->features = features; 543 ahc->flags = flags; 544 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 545 ahc->pause = ahc->unpause | PAUSE; 546 547 return (ahc); 548} 549 550void 551ahc_free(ahc) 552 struct ahc_softc *ahc; 553{ 554 free(ahc, M_DEVBUF); 555 return; 556} 557 558int 559ahc_reset(struct ahc_softc *ahc) 560{ 561 u_int sblkctl; 562 int wait; 563 564 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 565 /* 566 * Ensure that the reset has finished 567 */ 568 wait = 1000; 569 while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)) 570 DELAY(1000); 571 if (wait == 0) { 572 printf("%s: WARNING - Failed chip reset! " 573 "Trying to initialize anyway.\n", ahc_name(ahc)); 574 } 575 ahc_outb(ahc, HCNTRL, ahc->pause); 576 577 /* Determine channel configuration */ 578 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 579 /* No Twin Channel PCI cards */ 580 if ((ahc->chip & AHC_PCI) != 0) 581 sblkctl &= ~SELBUSB; 582 switch (sblkctl) { 583 case 0: 584 /* Single Narrow Channel */ 585 break; 586 case 2: 587 /* Wide Channel */ 588 ahc->features |= AHC_WIDE; 589 break; 590 case 8: 591 /* Twin Channel */ 592 ahc->features |= AHC_TWIN; 593 break; 594 default: 595 printf(" Unsupported adapter type. Ignoring\n"); 596 return(-1); 597 } 598 return (0); 599} 600 601/* 602 * Called when we have an active connection to a target on the bus, 603 * this function finds the nearest syncrate to the input period limited 604 * by the capabilities of the bus connectivity of the target. 605 */ 606static struct ahc_syncrate * 607ahc_devlimited_syncrate(struct ahc_softc *ahc, u_int *period) { 608 u_int maxsync; 609 610 if ((ahc->features & AHC_ULTRA2) != 0) { 611 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 612 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 613 maxsync = AHC_SYNCRATE_ULTRA2; 614 } else { 615 maxsync = AHC_SYNCRATE_ULTRA; 616 } 617 } else if ((ahc->features & AHC_ULTRA) != 0) { 618 maxsync = AHC_SYNCRATE_ULTRA; 619 } else { 620 maxsync = AHC_SYNCRATE_FAST; 621 } 622 return (ahc_find_syncrate(ahc, period, maxsync)); 623} 624 625/* 626 * Look up the valid period to SCSIRATE conversion in our table. 627 * Return the period and offset that should be sent to the target 628 * if this was the beginning of an SDTR. 629 */ 630static struct ahc_syncrate * 631ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 632{ 633 struct ahc_syncrate *syncrate; 634 635 syncrate = &ahc_syncrates[maxsync]; 636 while ((syncrate->rate != NULL) 637 && ((ahc->features & AHC_ULTRA2) == 0 638 || (syncrate->sxfr_ultra2 != 0))) { 639 640 if (*period <= syncrate->period) { 641 /* 642 * When responding to a target that requests 643 * sync, the requested rate may fall between 644 * two rates that we can output, but still be 645 * a rate that we can receive. Because of this, 646 * we want to respond to the target with 647 * the same rate that it sent to us even 648 * if the period we use to send data to it 649 * is lower. Only lower the response period 650 * if we must. 651 */ 652 if (syncrate == &ahc_syncrates[maxsync]) { 653 *period = syncrate->period; 654 } 655 break; 656 } 657 syncrate++; 658 } 659 660 if ((*period == 0) 661 || (syncrate->rate == NULL) 662 || ((ahc->features & AHC_ULTRA2) != 0 663 && (syncrate->sxfr_ultra2 == 0))) { 664 /* Use asynchronous transfers. */ 665 *period = 0; 666 syncrate = NULL; 667 } 668 return (syncrate); 669} 670 671static u_int 672ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 673{ 674 struct ahc_syncrate *syncrate; 675 676 if ((ahc->features & AHC_ULTRA2) != 0) { 677 scsirate &= SXFR_ULTRA2; 678 } else { 679 scsirate &= SXFR; 680 } 681 682 syncrate = &ahc_syncrates[maxsync]; 683 while (syncrate->rate != NULL) { 684 685 if ((ahc->features & AHC_ULTRA2) != 0) { 686 if (syncrate->sxfr_ultra2 == 0) 687 break; 688 else if (scsirate == syncrate->sxfr_ultra2) 689 return (syncrate->period); 690 } else if (scsirate == (syncrate->sxfr & ~ULTRA_SXFR)) { 691 return (syncrate->period); 692 } 693 syncrate++; 694 } 695 return (0); /* async */ 696} 697 698static void 699ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate, 700 u_int *offset, int wide) 701{ 702 u_int maxoffset; 703 704 /* Limit offset to what we can do */ 705 if (syncrate == NULL) { 706 maxoffset = 0; 707 } else if ((ahc->features & AHC_ULTRA2) != 0) { 708 maxoffset = MAX_OFFSET_ULTRA2; 709 } else { 710 if (wide) 711 maxoffset = MAX_OFFSET_16BIT; 712 else 713 maxoffset = MAX_OFFSET_8BIT; 714 } 715 *offset = MIN(*offset, maxoffset); 716} 717 718static void 719ahc_update_target_msg_request(struct ahc_softc *ahc, 720 struct ahc_devinfo *devinfo, 721 struct ahc_target_tinfo *tinfo, 722 int force) 723{ 724 int paused; 725 u_int targ_msg_req_orig; 726 727 targ_msg_req_orig = ahc->targ_msg_req; 728 if (tinfo->current.period != tinfo->goal.period 729 || tinfo->current.width != tinfo->goal.width 730 || (force 731 && (tinfo->goal.period != 0 732 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT))) 733 ahc->targ_msg_req |= devinfo->target_mask; 734 else 735 ahc->targ_msg_req &= ~devinfo->target_mask; 736 737 if (ahc->targ_msg_req != targ_msg_req_orig) { 738 /* Update the message request bit for this target */ 739 paused = sequencer_paused(ahc); 740 741 if (!paused) 742 pause_sequencer(ahc); 743 744 ahc_outb(ahc, TARGET_MSG_REQUEST, ahc->targ_msg_req & 0xFF); 745 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 746 (ahc->targ_msg_req >> 8) & 0xFF); 747 748 if (!paused) 749 unpause_sequencer(ahc, /*unpause always*/FALSE); 750 } 751} 752 753static int 754ahc_create_path(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 755 struct cam_path **path) 756{ 757 path_id_t path_id; 758 int error; 759 760 if (devinfo->channel == 'B') 761 path_id = cam_sim_path(ahc->sim_b); 762 else 763 path_id = cam_sim_path(ahc->sim); 764 765 return (xpt_create_path(path, /*periph*/NULL, 766 path_id, devinfo->target, 767 devinfo->lun)); 768} 769 770static void 771ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 772 struct cam_path *path, struct ahc_syncrate *syncrate, 773 u_int period, u_int offset, u_int type) 774{ 775 struct ahc_target_tinfo *tinfo; 776 u_int old_period; 777 u_int old_offset; 778 779 if (syncrate == NULL) { 780 period = 0; 781 offset = 0; 782 } 783 784 tinfo = &ahc->transinfo[devinfo->target_offset]; 785 old_period = tinfo->current.period; 786 old_offset = tinfo->current.offset; 787 788 if ((type & AHC_TRANS_CUR) != 0 789 && (old_period != period || old_offset != offset)) { 790 struct cam_path *path2; 791 u_int scsirate; 792 793 scsirate = tinfo->scsirate; 794 if ((ahc->features & AHC_ULTRA2) != 0) { 795 796 scsirate &= ~SXFR_ULTRA2; 797 798 if (syncrate != NULL) { 799 scsirate |= syncrate->sxfr_ultra2; 800 } 801 802 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) 803 ahc_outb(ahc, SCSIOFFSET, offset); 804 } else { 805 806 scsirate &= ~(SXFR|SOFS); 807 /* 808 * Ensure Ultra mode is set properly for 809 * this target. 810 */ 811 ahc->ultraenb &= ~devinfo->target_mask; 812 if (syncrate != NULL) { 813 if (syncrate->sxfr & ULTRA_SXFR) { 814 ahc->ultraenb |= devinfo->target_mask; 815 } 816 scsirate |= syncrate->sxfr & SXFR; 817 scsirate |= offset & SOFS; 818 } 819 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) { 820 u_int sxfrctl0; 821 822 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 823 sxfrctl0 &= ~FAST20; 824 if (ahc->ultraenb & devinfo->target_mask) 825 sxfrctl0 |= FAST20; 826 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 827 } 828 } 829 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) 830 ahc_outb(ahc, SCSIRATE, scsirate); 831 832 tinfo->scsirate = scsirate; 833 tinfo->current.period = period; 834 tinfo->current.offset = offset; 835 836 /* Update the syncrates in any pending scbs */ 837 ahc_update_pending_syncrates(ahc); 838 839 /* 840 * If possible, tell the SCSI layer about the 841 * new transfer parameters. 842 */ 843 /* If possible, update the XPT's notion of our transfer rate */ 844 path2 = NULL; 845 if (path == NULL) { 846 int error; 847 848 error = ahc_create_path(ahc, devinfo, &path2); 849 if (error == CAM_REQ_CMP) 850 path = path2; 851 else 852 path2 = NULL; 853 } 854 855 if (path != NULL) { 856 struct ccb_trans_settings neg; 857 858 neg.sync_period = period; 859 neg.sync_offset = offset; 860 neg.valid = CCB_TRANS_SYNC_RATE_VALID 861 | CCB_TRANS_SYNC_OFFSET_VALID; 862 xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1); 863 xpt_async(AC_TRANSFER_NEG, path, &neg); 864 } 865 866 if (path2 != NULL) 867 xpt_free_path(path2); 868 869 if (bootverbose) { 870 if (offset != 0) { 871 printf("%s: target %d synchronous at %sMHz, " 872 "offset = 0x%x\n", ahc_name(ahc), 873 devinfo->target, syncrate->rate, offset); 874 } else { 875 printf("%s: target %d using " 876 "asynchronous transfers\n", 877 ahc_name(ahc), devinfo->target); 878 } 879 } 880 } 881 882 if ((type & AHC_TRANS_GOAL) != 0) { 883 tinfo->goal.period = period; 884 tinfo->goal.offset = offset; 885 } 886 887 if ((type & AHC_TRANS_USER) != 0) { 888 tinfo->user.period = period; 889 tinfo->user.offset = offset; 890 } 891 892 ahc_update_target_msg_request(ahc, devinfo, tinfo, /*force*/FALSE); 893} 894 895static void 896ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 897 struct cam_path *path, u_int width, u_int type) 898{ 899 struct ahc_target_tinfo *tinfo; 900 u_int oldwidth; 901 902 tinfo = &ahc->transinfo[devinfo->target_offset]; 903 oldwidth = tinfo->current.width; 904 905 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 906 struct cam_path *path2; 907 u_int scsirate; 908 909 scsirate = tinfo->scsirate; 910 scsirate &= ~WIDEXFER; 911 if (width == MSG_EXT_WDTR_BUS_16_BIT) 912 scsirate |= WIDEXFER; 913 914 tinfo->scsirate = scsirate; 915 916 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) 917 ahc_outb(ahc, SCSIRATE, scsirate); 918 919 tinfo->current.width = width; 920 921 /* If possible, update the XPT's notion of our transfer rate */ 922 path2 = NULL; 923 if (path == NULL) { 924 int error; 925 926 error = ahc_create_path(ahc, devinfo, &path2); 927 if (error == CAM_REQ_CMP) 928 path = path2; 929 else 930 path2 = NULL; 931 } 932 933 if (path != NULL) { 934 struct ccb_trans_settings neg; 935 936 neg.bus_width = width; 937 neg.valid = CCB_TRANS_BUS_WIDTH_VALID; 938 xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1); 939 xpt_async(AC_TRANSFER_NEG, path, &neg); 940 } 941 942 if (path2 != NULL) 943 xpt_free_path(path2); 944 945 if (bootverbose) { 946 printf("%s: target %d using %dbit transfers\n", 947 ahc_name(ahc), devinfo->target, 948 8 * (0x01 << width)); 949 } 950 } 951 if ((type & AHC_TRANS_GOAL) != 0) 952 tinfo->goal.width = width; 953 if ((type & AHC_TRANS_USER) != 0) 954 tinfo->user.width = width; 955 956 ahc_update_target_msg_request(ahc, devinfo, tinfo, /*force*/FALSE); 957} 958 959/* 960 * Attach all the sub-devices we can find 961 */ 962int 963ahc_attach(struct ahc_softc *ahc) 964{ 965 struct ccb_setasync csa; 966 struct cam_devq *devq; 967 int bus_id; 968 int bus_id2; 969 struct cam_sim *sim; 970 struct cam_sim *sim2; 971 struct cam_path *path; 972 struct cam_path *path2; 973 int count; 974 975 count = 0; 976 sim = NULL; 977 sim2 = NULL; 978 979 /* 980 * Attach secondary channel first if the user has 981 * declared it the primary channel. 982 */ 983 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) != 0) { 984 bus_id = 1; 985 bus_id2 = 0; 986 } else { 987 bus_id = 0; 988 bus_id2 = 1; 989 } 990 991 /* 992 * Create the device queue for our SIM(s). 993 */ 994 devq = cam_simq_alloc(ahc->scb_data->maxscbs); 995 if (devq == NULL) 996 goto fail; 997 998 /* 999 * Construct our first channel SIM entry 1000 */ 1001 sim = cam_sim_alloc(ahc_action, ahc_poll, "ahc", ahc, ahc->unit, 1002 1, ahc->scb_data->maxscbs, devq); 1003 if (sim == NULL) { 1004 cam_simq_free(devq); 1005 goto fail; 1006 } 1007 1008 if (xpt_bus_register(sim, bus_id) != CAM_SUCCESS) { 1009 cam_sim_free(sim, /*free_devq*/TRUE); 1010 sim = NULL; 1011 goto fail; 1012 } 1013 1014 if (xpt_create_path(&path, /*periph*/NULL, 1015 cam_sim_path(sim), CAM_TARGET_WILDCARD, 1016 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1017 xpt_bus_deregister(cam_sim_path(sim)); 1018 cam_sim_free(sim, /*free_devq*/TRUE); 1019 sim = NULL; 1020 goto fail; 1021 } 1022 1023 xpt_setup_ccb(&csa.ccb_h, path, /*priority*/5); 1024 csa.ccb_h.func_code = XPT_SASYNC_CB; 1025 csa.event_enable = AC_LOST_DEVICE; 1026 csa.callback = ahc_async; 1027 csa.callback_arg = sim; 1028 xpt_action((union ccb *)&csa); 1029 count++; 1030 1031 if (ahc->features & AHC_TWIN) { 1032 sim2 = cam_sim_alloc(ahc_action, ahc_poll, "ahc", 1033 ahc, ahc->unit, 1, 1034 ahc->scb_data->maxscbs, devq); 1035 1036 if (sim2 == NULL) { 1037 printf("ahc_attach: Unable to attach second " 1038 "bus due to resource shortage"); 1039 goto fail; 1040 } 1041 1042 if (xpt_bus_register(sim2, bus_id2) != CAM_SUCCESS) { 1043 printf("ahc_attach: Unable to attach second " 1044 "bus due to resource shortage"); 1045 /* 1046 * We do not want to destroy the device queue 1047 * because the first bus is using it. 1048 */ 1049 cam_sim_free(sim2, /*free_devq*/FALSE); 1050 goto fail; 1051 } 1052 1053 if (xpt_create_path(&path2, /*periph*/NULL, 1054 cam_sim_path(sim2), 1055 CAM_TARGET_WILDCARD, 1056 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1057 xpt_bus_deregister(cam_sim_path(sim2)); 1058 cam_sim_free(sim2, /*free_devq*/FALSE); 1059 sim2 = NULL; 1060 goto fail; 1061 } 1062 xpt_setup_ccb(&csa.ccb_h, path2, /*priority*/5); 1063 csa.ccb_h.func_code = XPT_SASYNC_CB; 1064 csa.event_enable = AC_LOST_DEVICE; 1065 csa.callback = ahc_async; 1066 csa.callback_arg = sim2; 1067 xpt_action((union ccb *)&csa); 1068 count++; 1069 } 1070fail: 1071 if ((ahc->flags & AHC_CHANNEL_B_PRIMARY) != 0) { 1072 ahc->sim_b = sim; 1073 ahc->path_b = path; 1074 ahc->sim = sim2; 1075 ahc->path = path2; 1076 } else { 1077 ahc->sim = sim; 1078 ahc->path = path; 1079 ahc->sim_b = sim2; 1080 ahc->path_b = path2; 1081 } 1082 return (count); 1083} 1084 1085static void 1086ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1087{ 1088 u_int saved_tcl; 1089 role_t role; 1090 1091 if (ahc_inb(ahc, SSTAT0) & TARGET) 1092 role = ROLE_TARGET; 1093 else 1094 role = ROLE_INITIATOR; 1095 1096 saved_tcl = ahc_inb(ahc, SAVED_TCL); 1097 ahc_compile_devinfo(devinfo, (saved_tcl >> 4) & 0x0f, 1098 saved_tcl & 0x3, (saved_tcl & SELBUSB) ? 'B': 'A', 1099 role); 1100} 1101 1102static void 1103ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int target, u_int lun, 1104 char channel, role_t role) 1105{ 1106 devinfo->target = target; 1107 devinfo->lun = lun; 1108 devinfo->target_offset = target; 1109 devinfo->channel = channel; 1110 devinfo->role = role; 1111 if (channel == 'B') 1112 devinfo->target_offset += 8; 1113 devinfo->target_mask = (0x01 << devinfo->target_offset); 1114} 1115 1116/* 1117 * Catch an interrupt from the adapter 1118 */ 1119void 1120ahc_intr(void *arg) 1121{ 1122 struct ahc_softc *ahc; 1123 u_int intstat; 1124 1125 ahc = (struct ahc_softc *)arg; 1126 1127 intstat = ahc_inb(ahc, INTSTAT); 1128 1129 /* 1130 * Any interrupts to process? 1131 */ 1132#if NPCI > 0 1133 if ((intstat & INT_PEND) == 0) { 1134 if ((ahc->chip & AHC_PCI) != 0 1135 && (ahc->unsolicited_ints > 500)) { 1136 if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0) 1137 ahc_pci_intr(ahc); 1138 ahc->unsolicited_ints = 0; 1139 } else { 1140 ahc->unsolicited_ints++; 1141 } 1142 return; 1143 } else { 1144 ahc->unsolicited_ints = 0; 1145 } 1146#else 1147 if ((intstat & INT_PEND) == 0) 1148 return; 1149#endif 1150 1151 if (intstat & CMDCMPLT) { 1152 struct scb *scb; 1153 u_int scb_index; 1154 1155 ahc_outb(ahc, CLRINT, CLRCMDINT); 1156 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 1157 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 1158 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 1159 1160 scb = ahc->scb_data->scbarray[scb_index]; 1161 if (!scb || !(scb->flags & SCB_ACTIVE)) { 1162 printf("%s: WARNING no command for scb %d " 1163 "(cmdcmplt)\nQOUTPOS = %d\n", 1164 ahc_name(ahc), scb_index, 1165 ahc->qoutfifonext - 1); 1166 continue; 1167 } 1168 1169 /* 1170 * Save off the residual 1171 * if there is one. 1172 */ 1173 if (scb->hscb->residual_SG_count != 0) 1174 ahc_calc_residual(scb); 1175 ahc_done(ahc, scb); 1176 } 1177 1178 if ((ahc->flags & AHC_TARGETMODE) != 0) { 1179 while (ahc->targetcmds[ahc->tqinfifonext].cmd_valid) { 1180 struct target_cmd *cmd; 1181 1182 cmd = &ahc->targetcmds[ahc->tqinfifonext++]; 1183 ahc_handle_target_cmd(ahc, cmd); 1184 cmd->cmd_valid = 0; 1185 } 1186 } 1187 } 1188 if (intstat & BRKADRINT) { 1189 /* 1190 * We upset the sequencer :-( 1191 * Lookup the error message 1192 */ 1193 int i, error, num_errors; 1194 1195 error = ahc_inb(ahc, ERROR); 1196 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 1197 for (i = 0; error != 1 && i < num_errors; i++) 1198 error >>= 1; 1199 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 1200 ahc_name(ahc), hard_error[i].errmesg, 1201 ahc_inb(ahc, SEQADDR0) | 1202 (ahc_inb(ahc, SEQADDR1) << 8)); 1203 1204 /* Tell everyone that this HBA is no longer availible */ 1205 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 1206 CAM_LUN_WILDCARD, SCB_LIST_NULL, CAM_NO_HBA); 1207 } 1208 if (intstat & SEQINT) 1209 ahc_handle_seqint(ahc, intstat); 1210 1211 if (intstat & SCSIINT) 1212 ahc_handle_scsiint(ahc, intstat); 1213} 1214 1215static void 1216ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 1217{ 1218 struct tmode_tstate *tstate; 1219 struct tmode_lstate *lstate; 1220 struct ccb_accept_tio *atio; 1221 u_int8_t *byte; 1222 int initiator; 1223 int target; 1224 int lun; 1225 1226 initiator = cmd->initiator_channel >> 4; 1227 target = cmd->targ_id; 1228 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 1229 1230 byte = cmd->bytes; 1231 tstate = ahc->enabled_targets[target]; 1232 lstate = NULL; 1233 if (tstate != NULL && lun < 8) 1234 lstate = tstate->enabled_luns[lun]; 1235 1236 /* 1237 * XXX Need to have a default TMODE devce that attaches to luns 1238 * that wouldn't otherwise be enabled and returns the proper 1239 * inquiry information. After all, we don't want to duplicate 1240 * this code in each driver. For now, simply drop it on the 1241 * floor. 1242 */ 1243 if (lstate == NULL) { 1244 printf("Incoming Command on disabled lun\n"); 1245 return; 1246 } 1247 1248 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 1249 /* XXX Should reconnect and return BUSY status */ 1250 if (atio == NULL) { 1251 printf("No ATIOs for incoming command\n"); 1252 return; 1253 } 1254 1255 /* 1256 * Package it up and send it off to 1257 * whomever has this lun enabled. 1258 */ 1259 atio->init_id = initiator; 1260 if (byte[0] != 0xFF) { 1261 /* Tag was included */ 1262 atio->tag_action = *byte++; 1263 atio->tag_id = *byte++; 1264 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 1265 } else { 1266 byte++; 1267 atio->ccb_h.flags = 0; 1268 } 1269 1270 /* Okay. Now determine the cdb size based on the command code */ 1271 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 1272 case 0: 1273 atio->cdb_len = 6; 1274 break; 1275 case 1: 1276 case 2: 1277 atio->cdb_len = 10; 1278 break; 1279 case 4: 1280 atio->cdb_len = 16; 1281 break; 1282 case 5: 1283 atio->cdb_len = 12; 1284 break; 1285 case 3: 1286 default: 1287 /* Only copy the opcode. */ 1288 atio->cdb_len = 1; 1289 printf("Reserved or VU command code type encountered\n"); 1290 break; 1291 } 1292 bcopy(byte, atio->cdb_io.cdb_bytes, atio->cdb_len); 1293 1294 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 1295 atio->ccb_h.status |= CAM_CDB_RECVD; 1296 1297 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 1298 /* 1299 * We weren't allowed to disconnect. 1300 * We're hanging on the bus until a 1301 * continue target I/O comes in response 1302 * to this accept tio. 1303 */ 1304 ahc->pending_device = lstate; 1305 } 1306 xpt_done((union ccb*)atio); 1307} 1308 1309static void 1310ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 1311{ 1312 struct scb *scb; 1313 struct ahc_devinfo devinfo; 1314 1315 ahc_fetch_devinfo(ahc, &devinfo); 1316 1317 /* 1318 * Clear the upper byte that holds SEQINT status 1319 * codes and clear the SEQINT bit. We will unpause 1320 * the sequencer, if appropriate, after servicing 1321 * the request. 1322 */ 1323 ahc_outb(ahc, CLRINT, CLRSEQINT); 1324 switch (intstat & SEQINT_MASK) { 1325 case NO_MATCH: 1326 { 1327 /* Ensure we don't leave the selection hardware on */ 1328 ahc_outb(ahc, SCSISEQ, 1329 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1330 1331 printf("%s:%c:%d: no active SCB for reconnecting " 1332 "target - issuing BUS DEVICE RESET\n", 1333 ahc_name(ahc), devinfo.channel, devinfo.target); 1334 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1335 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1336 ahc_inb(ahc, SEQ_FLAGS)); 1337 break; 1338 } 1339 case SEND_REJECT: 1340 { 1341 u_int rejbyte = ahc_inb(ahc, ACCUM); 1342 printf("%s:%c:%d: Warning - unknown message received from " 1343 "target (0x%x). Rejecting\n", 1344 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1345 break; 1346 } 1347 case NO_IDENT: 1348 { 1349 /* 1350 * The reconnecting target either did not send an identify 1351 * message, or did, but we didn't find and SCB to match and 1352 * before it could respond to our ATN/abort, it hit a dataphase. 1353 * The only safe thing to do is to blow it away with a bus 1354 * reset. 1355 */ 1356 int found; 1357 1358 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1359 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1360 ahc_name(ahc), devinfo.channel, devinfo.target, 1361 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1362 found = ahc_reset_channel(ahc, devinfo.channel, 1363 /*initiate reset*/TRUE); 1364 printf("%s: Issued Channel %c Bus Reset. " 1365 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1366 found); 1367 break; 1368 } 1369 case BAD_PHASE: 1370 if (ahc_inb(ahc, LASTPHASE) == P_BUSFREE) { 1371 printf("%s:%c:%d: Missed busfree.\n", ahc_name(ahc), 1372 devinfo.channel, devinfo.target); 1373 restart_sequencer(ahc); 1374 return; 1375 } else { 1376 printf("%s:%c:%d: unknown scsi bus phase. Attempting " 1377 "to continue\n", ahc_name(ahc), devinfo.channel, 1378 devinfo.target); 1379 } 1380 break; 1381 case REJECT_MSG: 1382 { 1383 ahc_handle_msg_reject(ahc, &devinfo); 1384 break; 1385 } 1386 case BAD_STATUS: 1387 { 1388 u_int scb_index; 1389 struct hardware_scb *hscb; 1390 struct ccb_scsiio *csio; 1391 /* 1392 * The sequencer will notify us when a command 1393 * has an error that would be of interest to 1394 * the kernel. This allows us to leave the sequencer 1395 * running in the common case of command completes 1396 * without error. The sequencer will already have 1397 * dma'd the SCB back up to us, so we can reference 1398 * the in kernel copy directly. 1399 */ 1400 scb_index = ahc_inb(ahc, SCB_TAG); 1401 scb = ahc->scb_data->scbarray[scb_index]; 1402 hscb = scb->hscb; 1403 1404 /* 1405 * Set the default return value to 0 (don't 1406 * send sense). The sense code will change 1407 * this if needed. 1408 */ 1409 ahc_outb(ahc, RETURN_1, 0); 1410 if (!(scb && (scb->flags & SCB_ACTIVE))) { 1411 printf("%s:%c:%d: ahc_intr - referenced scb " 1412 "not valid during seqint 0x%x scb(%d)\n", 1413 ahc_name(ahc), devinfo.channel, 1414 devinfo.target, intstat, scb_index); 1415 goto unpause; 1416 } 1417 1418 /* Don't want to clobber the original sense code */ 1419 if ((scb->flags & SCB_SENSE) != 0) { 1420 /* 1421 * Clear the SCB_SENSE Flag and have 1422 * the sequencer do a normal command 1423 * complete. 1424 */ 1425 scb->flags &= ~SCB_SENSE; 1426 ahc_set_ccb_status(scb->ccb, CAM_AUTOSENSE_FAIL); 1427 break; 1428 } 1429 ahc_set_ccb_status(scb->ccb, CAM_SCSI_STATUS_ERROR); 1430 csio = &scb->ccb->csio; 1431 csio->scsi_status = hscb->status; 1432 switch (hscb->status) { 1433 case SCSI_STATUS_OK: 1434 printf("%s: Interrupted for staus of 0???\n", 1435 ahc_name(ahc)); 1436 break; 1437 case SCSI_STATUS_CMD_TERMINATED: 1438 case SCSI_STATUS_CHECK_COND: 1439#ifdef AHC_DEBUG 1440 if (ahc_debug & AHC_SHOWSENSE) { 1441 xpt_print_path(csio->ccb_h.path); 1442 printf("SCB %d: requests Check Status\n", 1443 scb->hscb->tag); 1444 } 1445#endif 1446 1447 if ((csio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 1448 struct ahc_dma_seg *sg = scb->ahc_dma; 1449 struct scsi_sense *sc = 1450 (struct scsi_sense *)(&hscb->cmdstore); 1451 struct ahc_target_tinfo *tinfo; 1452 1453 /* 1454 * Save off the residual if there is one. 1455 */ 1456 if (hscb->residual_SG_count != 0) 1457 ahc_calc_residual(scb); 1458 1459#ifdef AHC_DEBUG 1460 if (ahc_debug & AHC_SHOWSENSE) { 1461 xpt_print_path(csio->ccb_h.path); 1462 printf("Sending Sense\n"); 1463 } 1464#endif 1465 /* 1466 * bzero from the sense data before having 1467 * the drive fill it. The SCSI spec mandates 1468 * that any untransfered data should be 1469 * assumed to be zero. 1470 */ 1471 bzero(&csio->sense_data, 1472 sizeof(csio->sense_data)); 1473 sc->opcode = REQUEST_SENSE; 1474 sc->byte2 = SCB_LUN(scb) << 5; 1475 sc->unused[0] = 0; 1476 sc->unused[1] = 0; 1477 sc->length = csio->sense_len; 1478 sc->control = 0; 1479 1480 sg->addr = vtophys(&csio->sense_data); 1481 sg->len = csio->sense_len; 1482 1483 /* 1484 * Would be nice to preserve DISCENB here, 1485 * but due to the way we page SCBs, we can't. 1486 */ 1487 hscb->control = 0; 1488 1489 /* 1490 * This request sense could be because the 1491 * the device lost power or in some other 1492 * way has lost our transfer negotiations. 1493 * Renegotiate if appropriate. 1494 */ 1495 tinfo = &ahc->transinfo[devinfo.target_offset]; 1496 ahc_update_target_msg_request(ahc, &devinfo, 1497 tinfo, 1498 /*force*/TRUE); 1499 hscb->status = 0; 1500 hscb->SG_count = 1; 1501 hscb->SG_pointer = scb->ahc_dmaphys; 1502 hscb->data = sg->addr; 1503 hscb->datalen = sg->len; 1504 hscb->cmdpointer = hscb->cmdstore_busaddr; 1505 hscb->cmdlen = sizeof(*sc); 1506 scb->sg_count = hscb->SG_count; 1507 scb->flags |= SCB_SENSE; 1508 /* 1509 * Ensure the target is busy since this 1510 * will be an untagged request. 1511 */ 1512 ahc_busy_tcl(ahc, scb); 1513 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1514 1515 /* 1516 * Ensure we have enough time to actually 1517 * retrieve the sense. 1518 */ 1519 untimeout(ahc_timeout, (caddr_t)scb, 1520 scb->ccb->ccb_h.timeout_ch); 1521 scb->ccb->ccb_h.timeout_ch = 1522 timeout(ahc_timeout, (caddr_t)scb, 5 * hz); 1523 /* Freeze the queue while the sense occurs. */ 1524 ahc_freeze_devq(ahc, scb->ccb->ccb_h.path); 1525 ahc_freeze_ccb(scb->ccb); 1526 break; 1527 } 1528 break; 1529 case SCSI_STATUS_BUSY: 1530 case SCSI_STATUS_QUEUE_FULL: 1531 /* 1532 * Requeue any transactions that haven't been 1533 * sent yet. 1534 */ 1535 ahc_freeze_devq(ahc, scb->ccb->ccb_h.path); 1536 ahc_freeze_ccb(scb->ccb); 1537 break; 1538 } 1539 break; 1540 } 1541 case TARGET_MSG_HELP: 1542 { 1543 /* 1544 * XXX Handle BDR, Abort, Abort Tag, and transfer negotiations. 1545 */ 1546 restart_sequencer(ahc); 1547 return; 1548 } 1549 case HOST_MSG_LOOP: 1550 { 1551 /* 1552 * The sequencer has encountered a message phase 1553 * that requires host assistance for completion. 1554 * While handling the message phase(s), we will be 1555 * notified by the sequencer after each byte is 1556 * transfered so we can track bus phases. 1557 * 1558 * If this is the first time we've seen a HOST_MSG_LOOP, 1559 * initialize the state of the host message loop. 1560 */ 1561 if (ahc->msg_type == MSG_TYPE_NONE) { 1562 u_int bus_phase; 1563 1564 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1565 if (bus_phase != P_MESGIN && bus_phase != P_MESGOUT) 1566 panic("ahc_intr: HOST_MSG_LOOP bad phase 0x%x", 1567 bus_phase); 1568 1569 if (devinfo.role == ROLE_INITIATOR) { 1570 struct scb *scb; 1571 u_int scb_index; 1572 1573 scb_index = ahc_inb(ahc, SCB_TAG); 1574 scb = ahc->scb_data->scbarray[scb_index]; 1575 1576 if (bus_phase == P_MESGOUT) 1577 ahc_setup_initiator_msgout(ahc, 1578 &devinfo, 1579 scb); 1580 else { 1581 ahc->msg_type = 1582 MSG_TYPE_INITIATOR_MSGIN; 1583 ahc->msgin_index = 0; 1584 } 1585 } else { 1586 if (bus_phase == P_MESGOUT) { 1587 ahc->msg_type = 1588 MSG_TYPE_TARGET_MSGOUT; 1589 ahc->msgin_index = 0; 1590 } else 1591 /* XXX Ever executed??? */ 1592 ahc_setup_target_msgin(ahc, &devinfo); 1593 } 1594 } 1595 1596 /* Pass a NULL path so that handlers generate their own */ 1597 ahc_handle_message_phase(ahc, /*path*/NULL); 1598 break; 1599 } 1600 case DATA_OVERRUN: 1601 { 1602 /* 1603 * When the sequencer detects an overrun, it 1604 * places the controller in "BITBUCKET" mode 1605 * and allows the target to complete its transfer. 1606 * Unfortunately, none of the counters get updated 1607 * when the controller is in this mode, so we have 1608 * no way of knowing how large the overrun was. 1609 */ 1610 u_int scbindex = ahc_inb(ahc, SCB_TAG); 1611 u_int lastphase = ahc_inb(ahc, LASTPHASE); 1612 int i; 1613 1614 scb = ahc->scb_data->scbarray[scbindex]; 1615 xpt_print_path(scb->ccb->ccb_h.path); 1616 printf("data overrun detected in %s phase." 1617 " Tag == 0x%x.\n", 1618 lastphase == P_DATAIN ? "Data-In" : "Data-Out", 1619 scb->hscb->tag); 1620 xpt_print_path(scb->ccb->ccb_h.path); 1621 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 1622 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 1623 scb->ccb->csio.dxfer_len, scb->sg_count); 1624 for (i = 0; i < scb->sg_count - 1; i++) { 1625 printf("sg[%d] - Addr 0x%x : Length %d\n", 1626 i, 1627 scb->ahc_dma[i].addr, 1628 scb->ahc_dma[i].len); 1629 } 1630 /* 1631 * Set this and it will take affect when the 1632 * target does a command complete. 1633 */ 1634 ahc_freeze_devq(ahc, scb->ccb->ccb_h.path); 1635 ahc_set_ccb_status(scb->ccb, CAM_DATA_RUN_ERR); 1636 ahc_freeze_ccb(scb->ccb); 1637 break; 1638 } 1639 case TRACEPOINT: 1640 { 1641 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 1642#if 0 1643 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 1644 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 1645 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 1646 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 1647 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 1648 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 1649 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 1650 ahc_inb(ahc, CCHADDR) 1651 | (ahc_inb(ahc, CCHADDR+1) << 8) 1652 | (ahc_inb(ahc, CCHADDR+2) << 16) 1653 | (ahc_inb(ahc, CCHADDR+3) << 24), 1654 ahc_inb(ahc, CCHCNT) 1655 | (ahc_inb(ahc, CCHCNT+1) << 8) 1656 | (ahc_inb(ahc, CCHCNT+2) << 16), 1657 ahc_inb(ahc, SCBPTR)); 1658 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 1659 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 1660#endif 1661 break; 1662 } 1663#if NOT_YET 1664 /* XXX Fill these in later */ 1665 case MESG_BUFFER_BUSY: 1666 break; 1667 case MSGIN_PHASEMIS: 1668 break; 1669#endif 1670 default: 1671 printf("ahc_intr: seqint, " 1672 "intstat == 0x%x, scsisigi = 0x%x\n", 1673 intstat, ahc_inb(ahc, SCSISIGI)); 1674 break; 1675 } 1676 1677unpause: 1678 /* 1679 * The sequencer is paused immediately on 1680 * a SEQINT, so we should restart it when 1681 * we're done. 1682 */ 1683 unpause_sequencer(ahc, /*unpause_always*/TRUE); 1684} 1685 1686static void 1687ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 1688{ 1689 u_int scb_index; 1690 u_int status; 1691 struct scb *scb; 1692 char cur_channel; 1693 char intr_channel; 1694 1695 if ((ahc->features & AHC_TWIN) != 0 1696 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 1697 cur_channel = 'B'; 1698 else 1699 cur_channel = 'A'; 1700 intr_channel = cur_channel; 1701 1702 status = ahc_inb(ahc, SSTAT1); 1703 if (status == 0) { 1704 if ((ahc->features & AHC_TWIN) != 0) { 1705 /* Try the other channel */ 1706 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1707 status = ahc_inb(ahc, SSTAT1); 1708 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1709 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 1710 } 1711 if (status == 0) { 1712 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 1713 return; 1714 } 1715 } 1716 1717 scb_index = ahc_inb(ahc, SCB_TAG); 1718 if (scb_index < ahc->scb_data->numscbs) { 1719 scb = ahc->scb_data->scbarray[scb_index]; 1720 if ((scb->flags & SCB_ACTIVE) == 0) 1721 scb = NULL; 1722 } else 1723 scb = NULL; 1724 1725 if ((status & SCSIRSTI) != 0) { 1726 printf("%s: Someone reset channel %c\n", 1727 ahc_name(ahc), intr_channel); 1728 ahc_reset_channel(ahc, intr_channel, /* Initiate Reset */FALSE); 1729 } else if ((status & BUSFREE) != 0 && (status & SELTO) == 0) { 1730 /* 1731 * First look at what phase we were last in. 1732 * If its message out, chances are pretty good 1733 * that the busfree was in response to one of 1734 * our abort requests. 1735 */ 1736 u_int lastphase = ahc_inb(ahc, LASTPHASE); 1737 u_int saved_tcl = ahc_inb(ahc, SAVED_TCL); 1738 u_int target = (saved_tcl >> 4) & 0x0f; 1739 char channel = saved_tcl & SELBUSB ? 'B': 'A'; 1740 int printerror = 1; 1741 1742 ahc_outb(ahc, SCSISEQ, 1743 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1744 if (lastphase == P_MESGOUT) { 1745 u_int message; 1746 u_int tag; 1747 1748 message = ahc_inb(ahc, SINDEX); 1749 1750 tag = SCB_LIST_NULL; 1751 switch (message) { 1752 case MSG_ABORT_TAG: 1753 tag = scb->hscb->tag; 1754 /* FALLTRHOUGH */ 1755 case MSG_ABORT: 1756 xpt_print_path(scb->ccb->ccb_h.path); 1757 printf("SCB %d - Abort %s Completed.\n", 1758 scb->hscb->tag, tag == SCB_LIST_NULL ? 1759 "" : "Tag"); 1760 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 1761 ahc_set_ccb_status(scb->ccb, 1762 CAM_REQ_ABORTED); 1763 ahc_done(ahc, scb); 1764 } 1765 printerror = 0; 1766 break; 1767 case MSG_BUS_DEV_RESET: 1768 ahc_handle_devreset(ahc, target, channel, 1769 CAM_BDR_SENT, AC_SENT_BDR, 1770 "Bus Device Reset", 1771 /*verbose_only*/FALSE); 1772 printerror = 0; 1773 break; 1774 default: 1775 break; 1776 } 1777 } 1778 if (printerror != 0) { 1779 if (scb != NULL) { 1780 u_int tag; 1781 1782 if ((scb->hscb->control & TAG_ENB) != 0) 1783 tag = scb->hscb->tag; 1784 else 1785 tag = SCB_LIST_NULL; 1786 ahc_abort_scbs(ahc, target, channel, 1787 SCB_LUN(scb), tag, 1788 CAM_UNEXP_BUSFREE); 1789 } else { 1790 ahc_abort_scbs(ahc, target, channel, 1791 CAM_LUN_WILDCARD, SCB_LIST_NULL, 1792 CAM_UNEXP_BUSFREE); 1793 printf("%s: ", ahc_name(ahc)); 1794 } 1795 printf("Unexpected busfree. LASTPHASE == 0x%x\n" 1796 "SEQADDR == 0x%x\n", 1797 lastphase, ahc_inb(ahc, SEQADDR0) 1798 | (ahc_inb(ahc, SEQADDR1) << 8)); 1799 } 1800 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 1801 ahc_clear_msg_state(ahc); 1802 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1803 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1804 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1805 restart_sequencer(ahc); 1806 } else if ((status & SELTO) != 0) { 1807 u_int scbptr; 1808 1809 scbptr = ahc_inb(ahc, WAITING_SCBH); 1810 ahc_outb(ahc, SCBPTR, scbptr); 1811 scb_index = ahc_inb(ahc, SCB_TAG); 1812 1813 if (scb_index < ahc->scb_data->numscbs) { 1814 scb = ahc->scb_data->scbarray[scb_index]; 1815 if ((scb->flags & SCB_ACTIVE) == 0) 1816 scb = NULL; 1817 } else 1818 scb = NULL; 1819 1820 if (scb == NULL) { 1821 printf("%s: ahc_intr - referenced scb not " 1822 "valid during SELTO scb(%d, %d)\n", 1823 ahc_name(ahc), scbptr, scb_index); 1824 } else { 1825 /* 1826 * Clear any pending messages for the timed out 1827 * target. 1828 */ 1829 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 1830 ahc_handle_devreset(ahc, SCB_TARGET(scb), 1831 SCB_CHANNEL(scb), CAM_SEL_TIMEOUT, 1832 /*ac_code*/0, "Selection Timeout", 1833 /*verbose_only*/TRUE); 1834 } 1835 /* Stop the selection */ 1836 ahc_outb(ahc, SCSISEQ, 0); 1837 1838 ahc_clear_msg_state(ahc); 1839 1840 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE); 1841 1842 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1843 1844 restart_sequencer(ahc); 1845 } else if (scb == NULL) { 1846 printf("%s: ahc_intr - referenced scb not " 1847 "valid during scsiint 0x%x scb(%d)\n" 1848 "SIMODE0 = 0x%x, SIMODE1 = 0x%x, SSTAT0 = 0x%x\n" 1849 "SEQADDR = 0x%x\n", ahc_name(ahc), 1850 status, scb_index, ahc_inb(ahc, SIMODE0), 1851 ahc_inb(ahc, SIMODE1), ahc_inb(ahc, SSTAT0), 1852 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1853 ahc_outb(ahc, CLRSINT1, status); 1854 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1855 unpause_sequencer(ahc, /*unpause_always*/TRUE); 1856 scb = NULL; 1857 } else if ((status & SCSIPERR) != 0) { 1858 /* 1859 * Determine the bus phase and 1860 * queue an appropriate message 1861 */ 1862 char *phase; 1863 u_int mesg_out = MSG_NOOP; 1864 u_int lastphase = ahc_inb(ahc, LASTPHASE); 1865 1866 xpt_print_path(scb->ccb->ccb_h.path); 1867 1868 switch (lastphase) { 1869 case P_DATAOUT: 1870 phase = "Data-Out"; 1871 break; 1872 case P_DATAIN: 1873 phase = "Data-In"; 1874 mesg_out = MSG_INITIATOR_DET_ERR; 1875 break; 1876 case P_COMMAND: 1877 phase = "Command"; 1878 break; 1879 case P_MESGOUT: 1880 phase = "Message-Out"; 1881 break; 1882 case P_STATUS: 1883 phase = "Status"; 1884 mesg_out = MSG_INITIATOR_DET_ERR; 1885 break; 1886 case P_MESGIN: 1887 phase = "Message-In"; 1888 mesg_out = MSG_PARITY_ERROR; 1889 break; 1890 default: 1891 phase = "unknown"; 1892 break; 1893 } 1894 printf("parity error during %s phase.\n", phase); 1895 1896 printf("SEQADDR == 0x%x\n", ahc_inb(ahc, SEQADDR0) 1897 | (ahc_inb(ahc, SEQADDR1) << 8)); 1898 1899 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 1900 1901 /* 1902 * We've set the hardware to assert ATN if we 1903 * get a parity error on "in" phases, so all we 1904 * need to do is stuff the message buffer with 1905 * the appropriate message. "In" phases have set 1906 * mesg_out to something other than MSG_NOP. 1907 */ 1908 if (mesg_out != MSG_NOOP) { 1909 if (ahc->msg_type != MSG_TYPE_NONE) 1910 ahc->send_msg_perror = TRUE; 1911 else 1912 ahc_outb(ahc, MSG_OUT, mesg_out); 1913 } 1914 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1915 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1916 unpause_sequencer(ahc, /*unpause_always*/TRUE); 1917 } else { 1918 xpt_print_path(scb->ccb->ccb_h.path); 1919 printf("Unknown SCSIINT. Status = 0x%x\n", status); 1920 ahc_outb(ahc, CLRSINT1, status); 1921 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1922 unpause_sequencer(ahc, /*unpause_always*/TRUE); 1923 } 1924} 1925 1926static void 1927ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1928{ 1929 /* 1930 * We need to initiate transfer negotiations. 1931 * If our current and goal settings are identical, 1932 * we want to renegotiate due to a check condition. 1933 */ 1934 struct ahc_target_tinfo *tinfo; 1935 int dowide; 1936 int dosync; 1937 1938 tinfo = &ahc->transinfo[devinfo->target_offset]; 1939 dowide = tinfo->current.width != tinfo->goal.width; 1940 dosync = tinfo->current.period != tinfo->goal.period; 1941 1942 if (!dowide && !dosync) { 1943 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 1944 dosync = tinfo->goal.period != 0; 1945 } 1946 1947 if (dowide) 1948 ahc_construct_wdtr(ahc, tinfo->goal.width); 1949 else if (dosync) { 1950 u_int period; 1951 1952 period = tinfo->goal.period; 1953 ahc_devlimited_syncrate(ahc, &period); 1954 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 1955 } else { 1956 panic("ahc_intr: AWAITING_MSG for negotiation, " 1957 "but no negotiation needed\n"); 1958 } 1959} 1960 1961static void 1962ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1963 struct scb *scb) 1964{ 1965 /* 1966 * To facilitate adding multiple messages together, 1967 * each routine should increment the index and len 1968 * variables instead of setting them explicitly. 1969 */ 1970 ahc->msgout_index = 0; 1971 ahc->msgout_len = 0; 1972 1973 if ((scb->flags & SCB_DEVICE_RESET) == 0 1974 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 1975 u_int identify_msg; 1976 1977 identify_msg = MSG_IDENTIFYFLAG | SCB_LUN(scb); 1978 if ((scb->hscb->control & DISCENB) != 0) 1979 identify_msg |= MSG_IDENTIFY_DISCFLAG; 1980 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 1981 ahc->msgout_len++; 1982 1983 if ((scb->hscb->control & TAG_ENB) != 0) { 1984 ahc->msgout_buf[ahc->msgout_index++] = 1985 scb->ccb->csio.tag_action; 1986 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 1987 ahc->msgout_len += 2; 1988 } 1989 } 1990 1991 if (scb->flags & SCB_DEVICE_RESET) { 1992 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 1993 ahc->msgout_len++; 1994 xpt_print_path(scb->ccb->ccb_h.path); 1995 printf("Bus Device Reset Message Sent\n"); 1996 } else if (scb->flags & SCB_ABORT) { 1997 if ((scb->hscb->control & TAG_ENB) != 0) 1998 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 1999 else 2000 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2001 ahc->msgout_len++; 2002 xpt_print_path(scb->ccb->ccb_h.path); 2003 printf("Abort Message Sent\n"); 2004 } else if ((ahc->targ_msg_req & devinfo->target_mask) != 0) { 2005 ahc_build_transfer_msg(ahc, devinfo); 2006 } else { 2007 printf("ahc_intr: AWAITING_MSG for an SCB that " 2008 "does not have a waiting message"); 2009 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2010 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2011 ahc_inb(ahc, MSG_OUT), scb->flags); 2012 } 2013 2014 /* 2015 * Clear the MK_MESSAGE flag from the SCB so we aren't 2016 * asked to send this message again. 2017 */ 2018 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2019 ahc->msgout_index = 0; 2020 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2021} 2022 2023static void 2024ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2025{ 2026 /* 2027 * To facilitate adding multiple messages together, 2028 * each routine should increment the index and len 2029 * variables instead of setting them explicitly. 2030 */ 2031 ahc->msgout_index = 0; 2032 ahc->msgout_len = 0; 2033 2034 if ((ahc->targ_msg_req & devinfo->target_mask) != 0) 2035 ahc_build_transfer_msg(ahc, devinfo); 2036 else 2037 panic("ahc_intr: AWAITING target message with no message"); 2038 2039 ahc->msgout_index = 0; 2040 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2041} 2042 2043static void 2044ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2045{ 2046 /* 2047 * What we care about here is if we had an 2048 * outstanding SDTR or WDTR message for this 2049 * target. If we did, this is a signal that 2050 * the target is refusing negotiation. 2051 */ 2052 struct scb *scb; 2053 u_int scb_index; 2054 u_int last_msg; 2055 2056 scb_index = ahc_inb(ahc, SCB_TAG); 2057 scb = ahc->scb_data->scbarray[scb_index]; 2058 2059 /* Might be necessary */ 2060 last_msg = ahc_inb(ahc, LAST_MSG); 2061 2062 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/FALSE)) { 2063 struct ahc_target_tinfo *tinfo; 2064 2065 /* note 8bit xfers and clear flag */ 2066 printf("%s:%c:%d: refuses WIDE negotiation. Using " 2067 "8bit transfers\n", ahc_name(ahc), 2068 devinfo->channel, devinfo->target); 2069 ahc_set_width(ahc, devinfo, scb->ccb->ccb_h.path, 2070 MSG_EXT_WDTR_BUS_8_BIT, 2071 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 2072 ahc_set_syncrate(ahc, devinfo, scb->ccb->ccb_h.path, 2073 /*syncrate*/NULL, /*period*/0, 2074 /*offset*/0, AHC_TRANS_ACTIVE); 2075 tinfo = &ahc->transinfo[devinfo->target_offset]; 2076 if (tinfo->goal.period) { 2077 u_int period; 2078 2079 /* Start the sync negotiation */ 2080 period = tinfo->goal.period; 2081 ahc_devlimited_syncrate(ahc, &period); 2082 ahc->msgout_index = 0; 2083 ahc->msgout_len = 0; 2084 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 2085 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2086 } 2087 } else if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/FALSE)) { 2088 /* note asynch xfers and clear flag */ 2089 ahc_set_syncrate(ahc, devinfo, scb->ccb->ccb_h.path, 2090 /*syncrate*/NULL, /*period*/0, 2091 /*offset*/0, 2092 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 2093 printf("%s:%c:%d: refuses synchronous negotiation. " 2094 "Using asynchronous transfers\n", 2095 ahc_name(ahc), 2096 devinfo->channel, devinfo->target); 2097 } else if ((scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 2098 struct ccb_trans_settings neg; 2099 2100 printf("%s:%c:%d: refuses tagged commands. Performing " 2101 "non-tagged I/O\n", ahc_name(ahc), 2102 devinfo->channel, devinfo->target); 2103 2104 ahc->tagenable &= ~devinfo->target_mask; 2105 neg.flags = 0; 2106 neg.valid = CCB_TRANS_TQ_VALID; 2107 xpt_setup_ccb(&neg.ccb_h, scb->ccb->ccb_h.path, /*priority*/1); 2108 xpt_async(AC_TRANSFER_NEG, scb->ccb->ccb_h.path, &neg); 2109 2110 /* 2111 * Resend the identify for this CCB as the target 2112 * may believe that the selection is invalid otherwise. 2113 */ 2114 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 2115 & ~MSG_SIMPLE_Q_TAG); 2116 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 2117 scb->ccb->ccb_h.flags &= ~CAM_TAG_ACTION_VALID; 2118 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 2119 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2120 2121 /* 2122 * Requeue all tagged commands for this target 2123 * currently in our posession so they can be 2124 * converted to untagged commands. 2125 */ 2126 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2127 SCB_LUN(scb), /*tag*/SCB_LIST_NULL, 2128 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 2129 } else { 2130 /* 2131 * Otherwise, we ignore it. 2132 */ 2133 printf("%s:%c:%d: Message reject for %x -- ignored\n", 2134 ahc_name(ahc), devinfo->channel, devinfo->target, 2135 last_msg); 2136 } 2137} 2138 2139static void 2140ahc_clear_msg_state(struct ahc_softc *ahc) 2141{ 2142 ahc->msgout_len = 0; 2143 ahc->msgin_index = 0; 2144 ahc->msg_type = MSG_TYPE_NONE; 2145} 2146 2147static void 2148ahc_handle_message_phase(struct ahc_softc *ahc, struct cam_path *path) 2149{ 2150 struct ahc_devinfo devinfo; 2151 u_int bus_phase; 2152 int end_session; 2153 2154 ahc_fetch_devinfo(ahc, &devinfo); 2155 2156 2157 end_session = FALSE; 2158 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2159 2160reswitch: 2161 switch (ahc->msg_type) { 2162 case MSG_TYPE_INITIATOR_MSGOUT: 2163 { 2164 int lastbyte; 2165 int phasemis; 2166 int msgdone; 2167 2168 if (ahc->msgout_len == 0) 2169 panic("REQINIT interrupt with no active message"); 2170 2171 phasemis = bus_phase != P_MESGOUT; 2172 if (phasemis) { 2173 if (bus_phase == P_MESGIN) { 2174 u_int scsisigo; 2175 2176 /* 2177 * Change gears and see if 2178 * this messages is of interest to 2179 * us or should be passed back to 2180 * the sequencer. 2181 */ 2182 ahc->send_msg_perror = FALSE; 2183 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2184 ahc->msgin_index = 0; 2185 goto reswitch; 2186 } 2187 end_session = TRUE; 2188 break; 2189 } 2190 2191 if (ahc->send_msg_perror) { 2192 ahc_outb(ahc, CLRSINT1, CLRATNO); 2193 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2194 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2195 break; 2196 } 2197 2198 msgdone = ahc->msgout_index == ahc->msgout_len; 2199 if (msgdone) { 2200 /* 2201 * The target has requested a retry. 2202 * Re-assert ATN, reset our message index to 2203 * 0, and try again. 2204 */ 2205 ahc->msgout_index = 0; 2206 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2207 } 2208 2209 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2210 if (lastbyte) { 2211 /* Last byte is signified by dropping ATN */ 2212 ahc_outb(ahc, CLRSINT1, CLRATNO); 2213 } 2214 2215 /* 2216 * Clear our interrupt status and present 2217 * the next byte on the bus. 2218 */ 2219 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2220 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2221 break; 2222 } 2223 case MSG_TYPE_INITIATOR_MSGIN: 2224 { 2225 int phasemis; 2226 int message_done; 2227 2228 phasemis = bus_phase != P_MESGIN; 2229 2230 if (phasemis) { 2231 ahc->msgin_index = 0; 2232 if (bus_phase == P_MESGOUT 2233 && (ahc->send_msg_perror == TRUE 2234 || (ahc->msgout_len != 0 2235 && ahc->msgout_index == 0))) { 2236 u_int scsisigo; 2237 2238 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2239 goto reswitch; 2240 } 2241 end_session = TRUE; 2242 break; 2243 } 2244 2245 /* Pull the byte in without acking it */ 2246 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2247 2248 message_done = ahc_parse_msg(ahc, path, &devinfo); 2249 2250 if (message_done) { 2251 /* 2252 * Clear our incoming message buffer in case there 2253 * is another message following this one. 2254 */ 2255 ahc->msgin_index = 0; 2256 2257 /* 2258 * If this message illicited a response, 2259 * assert ATN so the target takes us to the 2260 * message out phase. 2261 */ 2262 if (ahc->msgout_len != 0) 2263 ahc_outb(ahc, SCSISIGO, 2264 ahc_inb(ahc, SCSISIGO) | ATNO); 2265 } 2266 2267 /* Ack the byte */ 2268 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2269 ahc_inb(ahc, SCSIDATL); 2270 ahc->msgin_index++; 2271 break; 2272 } 2273 case MSG_TYPE_TARGET_MSGIN: 2274 { 2275 int msgdone; 2276 int msgout_request; 2277 2278 if (ahc->msgout_len == 0) 2279 panic("Target REQINIT with no active message"); 2280 2281 /* 2282 * If we interrupted a mesgout session, the initiator 2283 * will not know this until our first REQ. So, we 2284 * only honor mesgout requests after we've sent our 2285 * first byte. 2286 */ 2287 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2288 && ahc->msgout_index > 0) 2289 msgout_request = TRUE; 2290 else 2291 msgout_request = FALSE; 2292 2293 if (msgout_request) { 2294 2295 /* 2296 * Change gears and see if 2297 * this messages is of interest to 2298 * us or should be passed back to 2299 * the sequencer. 2300 */ 2301 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2302 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2303 ahc->msgin_index = 0; 2304 /* Dummy read to REQ for first byte */ 2305 ahc_inb(ahc, SCSIDATL); 2306 ahc_outb(ahc, SXFRCTL0, 2307 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2308 break; 2309 } 2310 2311 msgdone = ahc->msgout_index == ahc->msgout_len; 2312 if (msgdone) { 2313 ahc_outb(ahc, SXFRCTL0, 2314 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2315 end_session = TRUE; 2316 break; 2317 } 2318 2319 /* 2320 * Present the next byte on the bus. 2321 */ 2322 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2323 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2324 break; 2325 } 2326 case MSG_TYPE_TARGET_MSGOUT: 2327 { 2328 int lastbyte; 2329 int msgdone; 2330 2331 /* 2332 * The initiator signals that this is 2333 * the last byte by dropping ATN. 2334 */ 2335 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2336 2337 /* 2338 * Read the latched byte, but turn off SPIOEN first 2339 * so that we don't inadvertantly cause a REQ for the 2340 * next byte. 2341 */ 2342 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2343 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2344 msgdone = ahc_parse_msg(ahc, path, &devinfo); 2345 ahc->msgin_index++; 2346 2347 /* 2348 * XXX Read spec about initiator dropping ATN too soon 2349 * and use msgdone to detect it. 2350 */ 2351 if (msgdone) { 2352 ahc->msgin_index = 0; 2353 2354 /* 2355 * If this message illicited a response, transition 2356 * to the Message in phase and send it. 2357 */ 2358 if (ahc->msgout_len != 0) { 2359 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2360 ahc_outb(ahc, SXFRCTL0, 2361 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2362 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2363 ahc->msgin_index = 0; 2364 break; 2365 } 2366 } 2367 2368 if (lastbyte) 2369 end_session = TRUE; 2370 else { 2371 /* Ask for the next byte. */ 2372 ahc_outb(ahc, SXFRCTL0, 2373 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2374 } 2375 2376 break; 2377 } 2378 default: 2379 panic("Unknown REQINIT message type"); 2380 } 2381 2382 if (end_session) { 2383 ahc_clear_msg_state(ahc); 2384 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2385 } else 2386 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2387} 2388 2389/* 2390 * See if we sent a particular extended message to the target. 2391 * If "full" is true, the target saw the full message. 2392 * If "full" is false, the target saw at least the first 2393 * byte of the message. 2394 */ 2395static int 2396ahc_sent_msg(struct ahc_softc *ahc, u_int msgtype, int full) 2397{ 2398 int found; 2399 int index; 2400 2401 found = FALSE; 2402 index = 0; 2403 2404 while (index < ahc->msgout_len) { 2405 if ((ahc->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 2406 || ahc->msgout_buf[index] == MSG_MESSAGE_REJECT) 2407 index++; 2408 else if (ahc->msgout_buf[index] >= MSG_SIMPLE_Q_TAG 2409 && ahc->msgout_buf[index] < MSG_IGN_WIDE_RESIDUE) { 2410 /* Skip tag type and tag id */ 2411 index += 2; 2412 } else if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2413 /* Found a candidate */ 2414 if (ahc->msgout_buf[index+2] == msgtype) { 2415 u_int end_index; 2416 2417 end_index = index + 1 2418 + ahc->msgout_buf[index + 1]; 2419 if (full) { 2420 if (ahc->msgout_index > end_index) 2421 found = TRUE; 2422 } else if (ahc->msgout_index > index) 2423 found = TRUE; 2424 } 2425 break; 2426 } else { 2427 panic("ahc_sent_msg: Inconsistent msg buffer"); 2428 } 2429 } 2430 return (found); 2431} 2432 2433static int 2434ahc_parse_msg(struct ahc_softc *ahc, struct cam_path *path, 2435 struct ahc_devinfo *devinfo) 2436{ 2437 int reject; 2438 int done; 2439 int response; 2440 u_int targ_scsirate; 2441 2442 done = FALSE; 2443 response = FALSE; 2444 reject = FALSE; 2445 targ_scsirate = ahc->transinfo[devinfo->target_offset].scsirate; 2446 /* 2447 * Parse as much of the message as is availible, 2448 * rejecting it if we don't support it. When 2449 * the entire message is availible and has been 2450 * handled, return TRUE indicating that we have 2451 * parsed an entire message. 2452 * 2453 * In the case of extended messages, we accept the length 2454 * byte outright and perform more checking once we know the 2455 * extended message type. 2456 */ 2457 if (ahc->msgin_buf[0] == MSG_MESSAGE_REJECT) { 2458 ahc_handle_msg_reject(ahc, devinfo); 2459 done = TRUE; 2460 } else if (ahc->msgin_buf[0] == MSG_NOOP) { 2461 done = TRUE; 2462 } else if (ahc->msgin_buf[0] != MSG_EXTENDED) { 2463 reject = TRUE; 2464 } else if (ahc->msgin_index >= 2) { 2465 switch (ahc->msgin_buf[2]) { 2466 case MSG_EXT_SDTR: 2467 { 2468 struct ahc_syncrate *syncrate; 2469 u_int period; 2470 u_int offset; 2471 u_int saved_offset; 2472 u_int maxsync; 2473 2474 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 2475 reject = TRUE; 2476 break; 2477 } 2478 2479 /* 2480 * Wait until we have both args before validating 2481 * and acting on this message. 2482 * 2483 * Add one to MSG_EXT_SDTR_LEN to account for 2484 * the extended message preamble. 2485 */ 2486 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 2487 break; 2488 2489 period = ahc->msgin_buf[3]; 2490 saved_offset = offset = ahc->msgin_buf[4]; 2491 syncrate = ahc_devlimited_syncrate(ahc, &period); 2492 ahc_validate_offset(ahc, syncrate, &offset, 2493 targ_scsirate & WIDEXFER); 2494 ahc_set_syncrate(ahc, devinfo, path, 2495 syncrate, period, offset, 2496 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 2497 2498 /* 2499 * See if we initiated Sync Negotiation 2500 * and didn't have to fall down to async 2501 * transfers. 2502 */ 2503 if (ahc_sent_msg(ahc, MSG_EXT_SDTR, /*full*/TRUE)) { 2504 /* We started it */ 2505 if (saved_offset != offset) { 2506 /* Went too low - force async */ 2507 reject = TRUE; 2508 } 2509 } else { 2510 /* 2511 * Send our own SDTR in reply 2512 */ 2513 if (bootverbose) 2514 printf("Sending SDTR!\n"); 2515 ahc->msgout_index = 0; 2516 ahc->msgout_len = 0; 2517 ahc_construct_sdtr(ahc, period, offset); 2518 ahc->msgout_index = 0; 2519 response = TRUE; 2520 } 2521 done = TRUE; 2522 break; 2523 } 2524 case MSG_EXT_WDTR: 2525 { 2526 u_int bus_width; 2527 u_int sending_reply; 2528 2529 sending_reply = FALSE; 2530 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 2531 reject = TRUE; 2532 break; 2533 } 2534 2535 /* 2536 * Wait until we have our arg before validating 2537 * and acting on this message. 2538 * 2539 * Add one to MSG_EXT_WDTR_LEN to account for 2540 * the extended message preamble. 2541 */ 2542 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 2543 break; 2544 2545 bus_width = ahc->msgin_buf[3]; 2546 if (ahc_sent_msg(ahc, MSG_EXT_WDTR, /*full*/TRUE)) { 2547 /* 2548 * Don't send a WDTR back to the 2549 * target, since we asked first. 2550 */ 2551 switch (bus_width){ 2552 default: 2553 /* 2554 * How can we do anything greater 2555 * than 16bit transfers on a 16bit 2556 * bus? 2557 */ 2558 reject = TRUE; 2559 printf("%s: target %d requested %dBit " 2560 "transfers. Rejecting...\n", 2561 ahc_name(ahc), devinfo->target, 2562 8 * (0x01 << bus_width)); 2563 /* FALLTHROUGH */ 2564 case MSG_EXT_WDTR_BUS_8_BIT: 2565 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2566 break; 2567 case MSG_EXT_WDTR_BUS_16_BIT: 2568 break; 2569 } 2570 } else { 2571 /* 2572 * Send our own WDTR in reply 2573 */ 2574 if (bootverbose) 2575 printf("Sending WDTR!\n"); 2576 switch (bus_width) { 2577 default: 2578 if (ahc->features & AHC_WIDE) { 2579 /* Respond Wide */ 2580 bus_width = 2581 MSG_EXT_WDTR_BUS_16_BIT; 2582 break; 2583 } 2584 /* FALLTHROUGH */ 2585 case MSG_EXT_WDTR_BUS_8_BIT: 2586 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2587 break; 2588 } 2589 ahc->msgout_index = 0; 2590 ahc->msgout_len = 0; 2591 ahc_construct_wdtr(ahc, bus_width); 2592 ahc->msgout_index = 0; 2593 response = TRUE; 2594 sending_reply = TRUE; 2595 } 2596 ahc_set_width(ahc, devinfo, path, bus_width, 2597 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 2598 2599 /* After a wide message, we are async */ 2600 ahc_set_syncrate(ahc, devinfo, path, 2601 /*syncrate*/NULL, /*period*/0, 2602 /*offset*/0, AHC_TRANS_ACTIVE); 2603 if (sending_reply == FALSE && reject == FALSE) { 2604 struct ahc_target_tinfo *tinfo; 2605 2606 tinfo = &ahc->transinfo[devinfo->target_offset]; 2607 if (tinfo->goal.period) { 2608 u_int period; 2609 2610 /* Start the sync negotiation */ 2611 period = tinfo->goal.period; 2612 ahc_devlimited_syncrate(ahc, &period); 2613 ahc->msgout_index = 0; 2614 ahc->msgout_len = 0; 2615 ahc_construct_sdtr(ahc, period, 2616 tinfo->goal.offset); 2617 ahc->msgout_index = 0; 2618 response = TRUE; 2619 } 2620 } 2621 done = TRUE; 2622 break; 2623 } 2624 default: 2625 /* Unknown extended message. Reject it. */ 2626 reject = TRUE; 2627 break; 2628 } 2629 } 2630 2631 if (reject) { 2632 /* 2633 * Assert attention and setup to 2634 * reject the message. 2635 */ 2636 ahc->msgout_index = 0; 2637 ahc->msgout_len = 1; 2638 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 2639 done = TRUE; 2640 response = TRUE; 2641 } 2642 2643 if (done && !response) 2644 /* Clear the outgoing message buffer */ 2645 ahc->msgout_len = 0; 2646 2647 return (done); 2648} 2649 2650static void 2651ahc_handle_devreset(struct ahc_softc *ahc, int target, char channel, 2652 cam_status status, ac_code acode, char *message, 2653 int verbose_only) 2654{ 2655 struct ahc_devinfo devinfo; 2656 struct cam_path *path; 2657 int found; 2658 int error; 2659 2660 ahc_compile_devinfo(&devinfo, target, CAM_LUN_WILDCARD, channel, 2661 ROLE_UNKNOWN); 2662 2663 error = ahc_create_path(ahc, &devinfo, &path); 2664 2665 /* 2666 * Go back to async/narrow transfers and renegotiate. 2667 * ahc_set_width and ahc_set_syncrate can cope with NULL 2668 * paths. 2669 */ 2670 ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, 2671 AHC_TRANS_CUR); 2672 ahc_set_syncrate(ahc, &devinfo, path, /*syncrate*/NULL, 2673 /*period*/0, /*offset*/0, AHC_TRANS_CUR); 2674 found = ahc_abort_scbs(ahc, target, channel, CAM_LUN_WILDCARD, 2675 SCB_LIST_NULL, status); 2676 2677 if (error == CAM_REQ_CMP && acode != 0) 2678 xpt_async(AC_SENT_BDR, path, NULL); 2679 2680 if (error == CAM_REQ_CMP) 2681 xpt_free_path(path); 2682 2683 if (message != NULL 2684 && (verbose_only == 0 || bootverbose != 0)) 2685 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 2686 message, channel, target, found); 2687} 2688 2689/* 2690 * We have an scb which has been processed by the 2691 * adaptor, now we look to see how the operation 2692 * went. 2693 */ 2694static void 2695ahc_done(struct ahc_softc *ahc, struct scb *scb) 2696{ 2697 union ccb *ccb; 2698 2699 CAM_DEBUG(scb->ccb->ccb_h.path, CAM_DEBUG_TRACE, 2700 ("ahc_done - scb %d\n", scb->hscb->tag)); 2701 2702 ccb = scb->ccb; 2703 LIST_REMOVE(&ccb->ccb_h, sim_links.le); 2704 2705 untimeout(ahc_timeout, (caddr_t)scb, ccb->ccb_h.timeout_ch); 2706 2707 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2708 bus_dmasync_op_t op; 2709 2710 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2711 op = BUS_DMASYNC_POSTREAD; 2712 else 2713 op = BUS_DMASYNC_POSTWRITE; 2714 bus_dmamap_sync(ahc->dmat, scb->dmamap, op); 2715 bus_dmamap_unload(ahc->dmat, scb->dmamap); 2716 } 2717 2718 /* 2719 * Unbusy this target/channel/lun. 2720 * XXX if we are holding two commands per lun, 2721 * send the next command. 2722 */ 2723 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 2724 2725 if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { 2726 ccb->ccb_h.status = CAM_REQ_CMP; 2727 ahc_free_scb(ahc, scb); 2728 xpt_done(ccb); 2729 return; 2730 } 2731 2732 /* 2733 * If the recovery SCB completes, we have to be 2734 * out of our timeout. 2735 */ 2736 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 2737 2738 struct ccb_hdr *ccbh; 2739 2740 /* 2741 * We were able to complete the command successfully, 2742 * so reinstate the timeouts for all other pending 2743 * commands. 2744 */ 2745 ccbh = ahc->pending_ccbs.lh_first; 2746 while (ccbh != NULL) { 2747 struct scb *pending_scb; 2748 2749 pending_scb = (struct scb *)ccbh->ccb_scb_ptr; 2750 ccbh->timeout_ch = 2751 timeout(ahc_timeout, pending_scb, 2752 (ccbh->timeout * hz)/1000); 2753 ccbh = LIST_NEXT(ccbh, sim_links.le); 2754 } 2755 2756 /* 2757 * Ensure that we didn't put a second instance of this 2758 * SCB into the QINFIFO. 2759 */ 2760 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2761 SCB_LUN(scb), scb->hscb->tag, /*status*/0, 2762 SEARCH_REMOVE); 2763 if (ahc_ccb_status(ccb) == CAM_BDR_SENT) 2764 ahc_set_ccb_status(ccb, CAM_CMD_TIMEOUT); 2765 xpt_print_path(ccb->ccb_h.path); 2766 printf("no longer in timeout, status = %x\n", 2767 ccb->ccb_h.status); 2768 } 2769 2770 /* Don't clobber any existing error state */ 2771 if (ahc_ccb_status(ccb) == CAM_REQ_INPROG) { 2772 ccb->ccb_h.status |= CAM_REQ_CMP; 2773 } else if ((scb->flags & SCB_SENSE) != 0) { 2774 /* We performed autosense retrieval */ 2775 scb->ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 2776 } 2777 ccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2778 ahc_free_scb(ahc, scb); 2779 xpt_done(ccb); 2780} 2781 2782/* 2783 * Determine the number of SCBs available on the controller 2784 */ 2785int 2786ahc_probe_scbs(struct ahc_softc *ahc) { 2787 int i; 2788 2789 for (i = 0; i < AHC_SCB_MAX; i++) { 2790 ahc_outb(ahc, SCBPTR, i); 2791 ahc_outb(ahc, SCB_CONTROL, i); 2792 if (ahc_inb(ahc, SCB_CONTROL) != i) 2793 break; 2794 ahc_outb(ahc, SCBPTR, 0); 2795 if (ahc_inb(ahc, SCB_CONTROL) != 0) 2796 break; 2797 } 2798 2799 return (i); 2800} 2801 2802/* 2803 * Start the board, ready for normal operation 2804 */ 2805int 2806ahc_init(struct ahc_softc *ahc) 2807{ 2808 int max_targ = 15; 2809 int i; 2810 int term; 2811 u_int scsi_conf; 2812 u_int scsiseq_template; 2813 2814#ifdef AHC_PRINT_SRAM 2815 printf("Scratch Ram:"); 2816 for (i = 0x20; i < 0x5f; i++) { 2817 if (((i % 8) == 0) && (i != 0)) { 2818 printf ("\n "); 2819 } 2820 printf (" 0x%x", ahc_inb(ahc, i)); 2821 } 2822 if ((ahc->features & AHC_MORE_SRAM) != 0) { 2823 for (i = 0x70; i < 0x7f; i++) { 2824 if (((i % 8) == 0) && (i != 0)) { 2825 printf ("\n "); 2826 } 2827 printf (" 0x%x", ahc_inb(ahc, i)); 2828 } 2829 } 2830 printf ("\n"); 2831#endif 2832 2833 /* 2834 * Assume we have a board at this stage and it has been reset. 2835 */ 2836 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 2837 ahc->our_id = ahc->our_id_b = 7; 2838 } 2839 2840 /* 2841 * Default to allowing initiator operations. 2842 */ 2843 ahc->flags |= AHC_INITIATORMODE; 2844 2845 /* 2846 * XXX Would be better to use a per device flag, but PCI and EISA 2847 * devices don't have them yet. 2848 */ 2849 if ((AHC_TMODE_ENABLE & (0x01 << ahc->unit)) != 0) { 2850 ahc->flags |= AHC_TARGETMODE; 2851 if ((ahc->features & AHC_ULTRA2) == 0) 2852 /* Only have space for both on the Ultra2 chips */ 2853 ahc->flags &= ~AHC_INITIATORMODE; 2854 } 2855 2856 2857 if ((ahc->features & AHC_TWIN) != 0) { 2858 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, primary %c, ", 2859 ahc->our_id, ahc->our_id_b, 2860 ahc->flags & AHC_CHANNEL_B_PRIMARY? 'B': 'A'); 2861 } else { 2862 if ((ahc->features & AHC_WIDE) != 0) { 2863 printf("Wide "); 2864 } else { 2865 printf("Single "); 2866 } 2867 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 2868 } 2869 2870 ahc_outb(ahc, SEQ_FLAGS, 0); 2871 2872 /* Determine the number of SCBs and initialize them */ 2873 2874 if (ahc->scb_data->maxhscbs == 0) { 2875 ahc->scb_data->maxhscbs = ahc_probe_scbs(ahc); 2876 /* SCB 0 heads the free list */ 2877 ahc_outb(ahc, FREE_SCBH, 0); 2878 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2879 ahc_outb(ahc, SCBPTR, i); 2880 2881 /* Clear the control byte. */ 2882 ahc_outb(ahc, SCB_CONTROL, 0); 2883 2884 /* Set the next pointer */ 2885 ahc_outb(ahc, SCB_NEXT, i+1); 2886 2887 /* Make the tag number invalid */ 2888 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 2889 } 2890 2891 /* Make that the last SCB terminates the free list */ 2892 ahc_outb(ahc, SCBPTR, i-1); 2893 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 2894 2895 /* Ensure we clear the 0 SCB's control byte. */ 2896 ahc_outb(ahc, SCBPTR, 0); 2897 ahc_outb(ahc, SCB_CONTROL, 0); 2898 2899 ahc->scb_data->maxhscbs = i; 2900 } 2901 2902 if (ahc->scb_data->maxhscbs == 0) 2903 panic("%s: No SCB space found", ahc_name(ahc)); 2904 2905 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 2906 ahc->flags |= AHC_PAGESCBS; 2907 ahc->scb_data->maxscbs = AHC_SCB_MAX; 2908 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, 2909 ahc->scb_data->maxscbs); 2910 } else { 2911 ahc->scb_data->maxscbs = ahc->scb_data->maxhscbs; 2912 ahc->flags &= ~AHC_PAGESCBS; 2913 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 2914 } 2915 2916#ifdef AHC_DEBUG 2917 if (ahc_debug & AHC_SHOWMISC) { 2918 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 2919 "ahc_dma %d bytes\n", 2920 ahc_name(ahc), 2921 sizeof(struct hardware_scb), 2922 sizeof(struct scb), 2923 sizeof(struct ahc_dma_seg)); 2924 } 2925#endif /* AHC_DEBUG */ 2926 2927 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 2928 if (ahc->features & AHC_TWIN) { 2929 2930 /* 2931 * The device is gated to channel B after a chip reset, 2932 * so set those values first 2933 */ 2934 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 2935 if ((ahc->features & AHC_ULTRA2) != 0) 2936 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 2937 else 2938 ahc_outb(ahc, SCSIID, ahc->our_id_b); 2939 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 2940 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 2941 |term|ENSTIMER|ACTNEGEN); 2942 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 2943 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 2944 2945 if ((scsi_conf & RESET_SCSI) != 0 2946 && (ahc->flags & AHC_INITIATORMODE) != 0) 2947 ahc->flags |= AHC_RESET_BUS_B; 2948 2949 /* Select Channel A */ 2950 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 2951 } 2952 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 2953 if ((ahc->features & AHC_ULTRA2) != 0) 2954 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 2955 else 2956 ahc_outb(ahc, SCSIID, ahc->our_id); 2957 scsi_conf = ahc_inb(ahc, SCSICONF); 2958 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 2959 |term 2960 |ENSTIMER|ACTNEGEN); 2961 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 2962 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 2963 2964 if ((ahc->features & AHC_ULTRA2) != 0) { 2965 /* Wait for our transceiver status to settle */ 2966 i = 1000000; 2967 while (--i && ((ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0)) 2968 DELAY(100); 2969 2970 if (i == 0) 2971 panic("%s: Transceiver state never settled\n", 2972 ahc_name(ahc)); 2973 } 2974 2975 if ((scsi_conf & RESET_SCSI) != 0 2976 && (ahc->flags & AHC_INITIATORMODE) != 0) 2977 ahc->flags |= AHC_RESET_BUS_A; 2978 2979 /* 2980 * Look at the information that board initialization or 2981 * the board bios has left us. In the lower four bits of each 2982 * target's scratch space any value other than 0 indicates 2983 * that we should initiate synchronous transfers. If it's zero, 2984 * the user or the BIOS has decided to disable synchronous 2985 * negotiation to that target so we don't activate the needsdtr 2986 * flag. 2987 */ 2988 ahc->ultraenb = 0; 2989 ahc->tagenable = ALL_TARGETS_MASK; 2990 2991 /* Grab the disconnection disable table and invert it for our needs */ 2992 if (ahc->flags & AHC_USEDEFAULTS) { 2993 printf("%s: Host Adapter Bios disabled. Using default SCSI " 2994 "device parameters\n", ahc_name(ahc)); 2995 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 2996 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 2997 ahc->discenable = ALL_TARGETS_MASK; 2998 if ((ahc->features & AHC_ULTRA) != 0) 2999 ahc->ultraenb = 0xffff; 3000 } else { 3001 ahc->discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 3002 | ahc_inb(ahc, DISC_DSB)); 3003 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 3004 ahc->ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 3005 | ahc_inb(ahc, ULTRA_ENB); 3006 } 3007 3008 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 3009 max_targ = 7; 3010 3011 for (i = 0; i <= max_targ; i++) { 3012 struct ahc_target_tinfo *transinfo; 3013 3014 transinfo = &ahc->transinfo[i]; 3015 /* Default to async narrow across the board */ 3016 bzero(transinfo, sizeof(*transinfo)); 3017 if (ahc->flags & AHC_USEDEFAULTS) { 3018 if ((ahc->features & AHC_WIDE) != 0) 3019 transinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3020 3021 /* 3022 * These will be truncated when we determine the 3023 * connection type we have with the target. 3024 */ 3025 transinfo->user.period = ahc_syncrates->period; 3026 transinfo->user.offset = ~0; 3027 } else { 3028 u_int scsirate; 3029 u_int16_t mask; 3030 3031 /* Take the settings leftover in scratch RAM. */ 3032 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 3033 mask = (0x01 << i); 3034 if ((ahc->features & AHC_ULTRA2) != 0) { 3035 u_int offset; 3036 3037 if ((scsirate & SOFS) == 0x0F) { 3038 /* 3039 * Haven't negotiated yet, 3040 * so the format is different. 3041 */ 3042 scsirate = (scsirate & SXFR) >> 4 3043 | (ahc->ultraenb & mask) 3044 ? 0x18 : 0x10 3045 | (scsirate & WIDEXFER); 3046 offset = MAX_OFFSET_ULTRA2; 3047 } else 3048 offset = ahc_inb(ahc, TARG_OFFSET + i); 3049 ahc_find_period(ahc, scsirate, 3050 AHC_SYNCRATE_ULTRA2); 3051 if (offset == 0) 3052 transinfo->user.period = 0; 3053 else 3054 transinfo->user.offset = ~0; 3055 } else if ((scsirate & SOFS) != 0) { 3056 transinfo->user.period = 3057 ahc_find_period(ahc, scsirate, 3058 (ahc->ultraenb & mask) 3059 ? AHC_SYNCRATE_ULTRA 3060 : AHC_SYNCRATE_FAST); 3061 if ((scsirate & SOFS) != 0 3062 && transinfo->user.period != 0) { 3063 transinfo->user.offset = ~0; 3064 } 3065 } 3066 if ((scsirate & WIDEXFER) != 0 3067 && (ahc->features & AHC_WIDE) != 0) { 3068 transinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 3069 } 3070 3071 } 3072 } 3073 3074#ifdef AHC_DEBUG 3075 if (ahc_debug & AHC_SHOWMISC) 3076 printf("NEEDSDTR == 0x%x\nNEEDWDTR == 0x%x\n" 3077 "DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 3078 ahc->needsdtr_orig, ahc->needwdtr_orig, 3079 ahc->discenable, ahc->ultraenb); 3080#endif 3081 /* 3082 * Allocate enough "hardware scbs" to handle 3083 * the maximum number of concurrent transactions 3084 * we can have active. We have to use contigmalloc 3085 * if this array crosses a page boundary since the 3086 * sequencer depends on this array being physically 3087 * contiguous. 3088 */ 3089 if (ahc->scb_data->hscbs == NULL) { 3090 size_t array_size; 3091 3092 array_size = ahc->scb_data->maxscbs*sizeof(struct hardware_scb); 3093 if (array_size > PAGE_SIZE) { 3094 ahc->scb_data->hscbs = (struct hardware_scb *) 3095 contigmalloc(array_size, M_DEVBUF, 3096 M_NOWAIT, 0ul, 0xffffffff, 3097 PAGE_SIZE, 0x10000); 3098 } else { 3099 ahc->scb_data->hscbs = (struct hardware_scb *) 3100 malloc(array_size, M_DEVBUF, M_NOWAIT); 3101 } 3102 3103 if (ahc->scb_data->hscbs == NULL) { 3104 printf("%s: unable to allocate hardware SCB array. " 3105 "Failing attach\n", ahc_name(ahc)); 3106 return (-1); 3107 } 3108 /* At least the control byte of each hscb needs to be zeroed */ 3109 bzero(ahc->scb_data->hscbs, array_size); 3110 } 3111 3112 if ((ahc->flags & AHC_TARGETMODE) != 0) { 3113 size_t array_size; 3114 3115 array_size = AHC_TMODE_CMDS * sizeof(struct target_cmd); 3116 ahc->targetcmds = contigmalloc(array_size, M_DEVBUF, 3117 M_NOWAIT, 0ul, 0xffffffff, 3118 PAGE_SIZE, 0x10000); 3119 3120 if (ahc->targetcmds == NULL) { 3121 printf("%s: unable to allocate targetcmd array. " 3122 "Failing attach\n", ahc_name(ahc)); 3123 return (-1); 3124 } 3125 3126 /* All target command blocks start out invalid. */ 3127 for (i = 0; i < AHC_TMODE_CMDS; i++) 3128 ahc->targetcmds[i].cmd_valid = 0; 3129 ahc_outb(ahc, KERNEL_TQINPOS, 0); 3130 ahc_outb(ahc, TQINPOS, 0); 3131 } 3132 3133 /* 3134 * Tell the sequencer where it can find the our arrays in memory. 3135 */ 3136 { 3137 u_int32_t physaddr; 3138 3139 /* Tell the sequencer where it can find the hscb array. */ 3140 physaddr = vtophys(ahc->scb_data->hscbs); 3141 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 3142 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 3143 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 3144 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 3145 ahc->hscb_busaddr = physaddr; 3146 3147 physaddr = vtophys(ahc->qoutfifo); 3148 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 3149 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 3150 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 3151 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 3152 3153 if ((ahc->flags & AHC_TARGETMODE) != 0) { 3154 physaddr = vtophys(ahc->targetcmds); 3155 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 3156 ahc_outb(ahc, TMODE_CMDADDR + 1, 3157 (physaddr >> 8) & 0xFF); 3158 ahc_outb(ahc, TMODE_CMDADDR + 2, 3159 (physaddr >> 16) & 0xFF); 3160 ahc_outb(ahc, TMODE_CMDADDR + 3, 3161 (physaddr >> 24) & 0xFF); 3162 3163 ahc_outb(ahc, CMDSIZE_TABLE, 5); 3164 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 3165 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 3166 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 3167 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 3168 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 3169 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 3170 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 3171 } 3172 3173 /* There are no untagged SCBs active yet. */ 3174 for (i = 0; i < sizeof(ahc->untagged_scbs); i++) { 3175 ahc->untagged_scbs[i] = SCB_LIST_NULL; 3176 } 3177 for (i = 0; i < sizeof(ahc->qoutfifo); i++) { 3178 ahc->qoutfifo[i] = SCB_LIST_NULL; 3179 } 3180 } 3181 3182 /* Our Q FIFOs are empty. */ 3183 ahc_outb(ahc, KERNEL_QINPOS, 0); 3184 ahc_outb(ahc, QINPOS, 0); 3185 ahc_outb(ahc, QOUTPOS, 0); 3186 3187 /* Don't have any special messages to send to targets */ 3188 ahc_outb(ahc, TARGET_MSG_REQUEST, 0); 3189 ahc_outb(ahc, TARGET_MSG_REQUEST + 1, 0); 3190 3191 /* 3192 * Use the built in queue management registers 3193 * if they are available. 3194 */ 3195 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3196 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 3197 ahc_outb(ahc, SDSCB_QOFF, 0); 3198 ahc_outb(ahc, SNSCB_QOFF, 0); 3199 ahc_outb(ahc, HNSCB_QOFF, 0); 3200 } 3201 3202 3203 /* We don't have any waiting selections */ 3204 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 3205 3206 /* Our disconnection list is empty too */ 3207 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 3208 3209 /* Message out buffer starts empty */ 3210 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3211 3212 /* 3213 * Setup the allowed SCSI Sequences based on operational mode. 3214 * If we are a target, we'll enalbe select in operations once 3215 * we've had a lun enabled. 3216 */ 3217 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 3218 if ((ahc->flags & AHC_INITIATORMODE) != 0) 3219 scsiseq_template |= ENRSELI; 3220 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 3221 3222 /* 3223 * Load the Sequencer program and Enable the adapter 3224 * in "fast" mode. 3225 */ 3226 if (bootverbose) 3227 printf("%s: Downloading Sequencer Program...", 3228 ahc_name(ahc)); 3229 3230 ahc_loadseq(ahc); 3231 3232 /* We have to wait until after any system dumps... */ 3233 at_shutdown(ahc_shutdown, ahc, SHUTDOWN_FINAL); 3234 3235 return (0); 3236} 3237 3238static void 3239ahcminphys(struct buf *bp) 3240{ 3241/* 3242 * Even though the card can transfer up to 16megs per command 3243 * we are limited by the number of segments in the dma segment 3244 * list that we can hold. The worst case is that all pages are 3245 * discontinuous physically, hense the "page per segment" limit 3246 * enforced here. 3247 */ 3248 if (bp->b_bcount > ((AHC_NSEG - 1) * PAGE_SIZE)) { 3249 bp->b_bcount = ((AHC_NSEG - 1) * PAGE_SIZE); 3250 } 3251} 3252 3253static cam_status 3254ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 3255 struct tmode_tstate **tstate, struct tmode_lstate **lstate, 3256 int notfound_failure) 3257{ 3258 int our_id; 3259 3260 /* 3261 * If we are not configured for target mode, someone 3262 * is really confused to be sending this to us. 3263 */ 3264 if ((ahc->flags & AHC_TARGETMODE) == 0) 3265 return (CAM_REQ_INVALID); 3266 3267 /* Range check target and lun */ 3268 if (cam_sim_bus(sim) == 0) 3269 our_id = ahc->our_id; 3270 else 3271 our_id = ahc->our_id_b; 3272 if (ccb->ccb_h.target_id > ((ahc->features & AHC_WIDE) ? 15 : 7) 3273 || ((ahc->features & AHC_MULTI_TID) == 0 3274 && (ccb->ccb_h.target_id != our_id))) 3275 return (CAM_TID_INVALID); 3276 3277 if (ccb->ccb_h.target_lun > 8) 3278 return (CAM_LUN_INVALID); 3279 3280 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 3281 *lstate = NULL; 3282 if (*tstate != NULL) 3283 *lstate = (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 3284 3285 if (notfound_failure != 0 && *lstate == NULL) 3286 return (CAM_PATH_INVALID); 3287 3288 return (CAM_REQ_CMP); 3289} 3290 3291static void 3292ahc_action(struct cam_sim *sim, union ccb *ccb) 3293{ 3294 struct ahc_softc *ahc; 3295 struct tmode_lstate *lstate; 3296 int target_id; 3297 int s; 3298 3299 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahc_action\n")); 3300 3301 ahc = (struct ahc_softc *)cam_sim_softc(sim); 3302 3303 target_id = ccb->ccb_h.target_id; 3304 3305 switch (ccb->ccb_h.func_code) { 3306 /* Common cases first */ 3307 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 3308 case XPT_CONT_TARGET_IO:/* Continue Host Target I/O Connection*/ 3309 { 3310 struct tmode_tstate *tstate; 3311 cam_status status; 3312 3313 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, 3314 &lstate, TRUE); 3315 3316 if (status != CAM_REQ_CMP) { 3317 ccb->ccb_h.status = status; 3318 xpt_done(ccb); 3319 break; 3320 } 3321 if (ccb->ccb_h.func_code == XPT_ACCEPT_TARGET_IO) { 3322 SLIST_INSERT_HEAD(&lstate->accept_tios, &ccb->ccb_h, 3323 sim_links.sle); 3324 ccb->ccb_h.status = CAM_REQ_INPROG; 3325 break; 3326 } 3327 3328 /* 3329 * The target_id represents the target we attempt to 3330 * select. In target mode, this is the initiator of 3331 * the original command. 3332 */ 3333 target_id = ccb->csio.init_id; 3334 /* FALLTHROUGH */ 3335 } 3336 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 3337 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 3338 { 3339 struct scb *scb; 3340 struct hardware_scb *hscb; 3341 struct ahc_target_tinfo *tinfo; 3342 u_int16_t mask; 3343 3344 /* 3345 * get an scb to use. 3346 */ 3347 if ((scb = ahc_get_scb(ahc)) == NULL) { 3348 int s; 3349 3350 s = splcam(); 3351 ahc->flags |= AHC_RESOURCE_SHORTAGE; 3352 splx(s); 3353 xpt_freeze_simq(ahc->sim, /*count*/1); 3354 ahc_set_ccb_status(ccb, CAM_REQUEUE_REQ); 3355 xpt_done(ccb); 3356 return; 3357 } 3358 3359 hscb = scb->hscb; 3360 3361 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_SUBTRACE, 3362 ("start scb(%p)\n", scb)); 3363 scb->ccb = ccb; 3364 /* 3365 * So we can find the SCB when an abort is requested 3366 */ 3367 ccb->ccb_h.ccb_scb_ptr = scb; 3368 ccb->ccb_h.ccb_ahc_ptr = ahc; 3369 3370 /* 3371 * Put all the arguments for the xfer in the scb 3372 */ 3373 hscb->tcl = ((target_id << 4) & 0xF0) 3374 | (SIM_IS_SCSIBUS_B(ahc, sim) ? SELBUSB : 0) 3375 | (ccb->ccb_h.target_lun & 0x07); 3376 3377 mask = SCB_TARGET_MASK(scb); 3378 tinfo = &ahc->transinfo[SCB_TARGET_OFFSET(scb)]; 3379 3380 hscb->scsirate = tinfo->scsirate; 3381 hscb->scsioffset = tinfo->current.offset; 3382 if ((ahc->ultraenb & mask) != 0) 3383 hscb->control |= ULTRAENB; 3384 3385 if ((ahc->discenable & mask) != 0 3386 && (ccb->ccb_h.flags & CAM_DIS_DISCONNECT) == 0) 3387 hscb->control |= DISCENB; 3388 3389 if (ccb->ccb_h.func_code == XPT_RESET_DEV) { 3390 hscb->cmdpointer = NULL; 3391 scb->flags |= SCB_DEVICE_RESET; 3392 hscb->control |= MK_MESSAGE; 3393 ahc_execute_scb(scb, NULL, 0, 0); 3394 } else { 3395 if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { 3396 if (ahc->pending_device == lstate) { 3397 scb->flags |= SCB_TARGET_IMMEDIATE; 3398 ahc->pending_device = NULL; 3399 } 3400 hscb->control |= TARGET_SCB; 3401 hscb->cmdpointer = IDENTIFY_SEEN; 3402 if ((ccb->ccb_h.flags & CAM_SEND_STATUS) != 0) { 3403 hscb->cmdpointer |= SPHASE_PENDING; 3404 hscb->status = ccb->csio.scsi_status; 3405 } 3406 3407 /* Overloaded with tag ID */ 3408 hscb->cmdlen = ccb->csio.tag_id; 3409 /* 3410 * Overloaded with our target ID to 3411 * use for reselection. 3412 */ 3413 hscb->next = ccb->ccb_h.target_id; 3414 } 3415 if (ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) 3416 hscb->control |= ccb->csio.tag_action; 3417 3418 ahc_setup_data(ahc, &ccb->csio, scb); 3419 } 3420 break; 3421 } 3422 case XPT_NOTIFY_ACK: 3423 case XPT_IMMED_NOTIFY: 3424 { 3425 struct tmode_tstate *tstate; 3426 struct tmode_lstate *lstate; 3427 cam_status status; 3428 3429 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, 3430 &lstate, TRUE); 3431 3432 if (status != CAM_REQ_CMP) { 3433 ccb->ccb_h.status = status; 3434 xpt_done(ccb); 3435 break; 3436 } 3437 if (ccb->ccb_h.func_code == XPT_NOTIFY_ACK) { 3438 /* Clear notification state */ 3439 } 3440 SLIST_INSERT_HEAD(&lstate->immed_notifies, &ccb->ccb_h, 3441 sim_links.sle); 3442 ccb->ccb_h.status = CAM_REQ_INPROG; 3443 break; 3444 } 3445 case XPT_EN_LUN: /* Enable LUN as a target */ 3446 { 3447 struct tmode_tstate *tstate; 3448 struct tmode_lstate *lstate; 3449 struct ccb_en_lun *cel; 3450 cam_status status; 3451 int target; 3452 int lun; 3453 3454 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 3455 /* notfound_failure*/FALSE); 3456 3457 if (status != CAM_REQ_CMP) { 3458 ccb->ccb_h.status = status; 3459 xpt_done(ccb); 3460 break; 3461 } 3462 3463 cel = &ccb->cel; 3464 target = ccb->ccb_h.target_id; 3465 lun = ccb->ccb_h.target_lun; 3466 if (cel->enable != 0) { 3467 u_int scsiseq; 3468 3469 /* Are we already enabled?? */ 3470 if (lstate != NULL) { 3471 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 3472 xpt_done(ccb); 3473 break; 3474 } 3475 3476 if (cel->grp6_len != 0 3477 || cel->grp7_len != 0) { 3478 /* 3479 * Don't (yet?) support vendor 3480 * specific commands. 3481 */ 3482 ccb->ccb_h.status = CAM_REQ_INVALID; 3483 xpt_done(ccb); 3484 break; 3485 } 3486 3487 /* 3488 * Seems to be okay. 3489 * Setup our data structures. 3490 */ 3491 if (tstate == NULL) { 3492 tstate = malloc(sizeof(*tstate), 3493 M_DEVBUF, M_NOWAIT); 3494 if (tstate == NULL) { 3495 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 3496 xpt_done(ccb); 3497 break; 3498 } 3499 bzero(tstate, sizeof(*tstate)); 3500 ahc->enabled_targets[target] = tstate; 3501 } 3502 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 3503 if (lstate == NULL) { 3504 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 3505 xpt_done(ccb); 3506 break; 3507 } 3508 bzero(lstate, sizeof(*lstate)); 3509 SLIST_INIT(&lstate->accept_tios); 3510 SLIST_INIT(&lstate->immed_notifies); 3511 tstate->enabled_luns[lun] = lstate; 3512 pause_sequencer(ahc); 3513 if ((ahc->features & AHC_MULTI_TID) != 0) { 3514 u_int16_t targid_mask; 3515 3516 targid_mask = ahc_inb(ahc, TARGID) 3517 | (ahc_inb(ahc, TARGID + 1) << 8); 3518 3519 targid_mask |= (0x01 << target); 3520 ahc_outb(ahc, TARGID, targid_mask); 3521 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 3522 } 3523 /* Allow select-in operations */ 3524 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 3525 scsiseq |= ENSELI; 3526 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 3527 scsiseq = ahc_inb(ahc, SCSISEQ); 3528 scsiseq |= ENSELI; 3529 ahc_outb(ahc, SCSISEQ, scsiseq); 3530 unpause_sequencer(ahc, /*always?*/FALSE); 3531 ccb->ccb_h.status = CAM_REQ_CMP; 3532 xpt_print_path(ccb->ccb_h.path); 3533 printf("Lun now enabled for target mode\n"); 3534 xpt_done(ccb); 3535 break; 3536 } else { 3537 struct ccb_hdr *elm; 3538 3539 /* XXX Fully Implement Disable */ 3540 if (lstate == NULL) { 3541 ccb->ccb_h.status = CAM_LUN_INVALID; 3542 xpt_done(ccb); 3543 break; 3544 } 3545 3546 ccb->ccb_h.status = CAM_REQ_CMP; 3547 LIST_FOREACH(elm, &ahc->pending_ccbs, sim_links.le) { 3548 if (elm->func_code == XPT_CONT_TARGET_IO 3549 && !xpt_path_comp(elm->path, ccb->ccb_h.path)){ 3550 ccb->ccb_h.status = CAM_REQ_INVALID; 3551 break; 3552 } 3553 } 3554 3555 if (SLIST_FIRST(&lstate->accept_tios) != NULL) 3556 ccb->ccb_h.status = CAM_REQ_INVALID; 3557 3558 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) 3559 ccb->ccb_h.status = CAM_REQ_INVALID; 3560 3561 if (ccb->ccb_h.status == CAM_REQ_CMP) { 3562 int i, empty; 3563 3564 free(lstate, M_DEVBUF); 3565 tstate->enabled_luns[lun] = NULL; 3566 3567 /* Can we clean up the target too? */ 3568 for (empty = 1, i = 0; i < 8; i++) 3569 if (tstate->enabled_luns[i] != NULL) { 3570 empty = 0; 3571 break; 3572 } 3573 if (empty) { 3574 printf("Target Empty\n"); 3575 free(tstate, M_DEVBUF); 3576 ahc->enabled_targets[target] = NULL; 3577 pause_sequencer(ahc); 3578 if (ahc->features & AHC_MULTI_TID) { 3579 u_int16_t targid_mask; 3580 3581 targid_mask = 3582 ahc_inb(ahc, TARGID) 3583 | (ahc_inb(ahc, TARGID + 1) 3584 << 8); 3585 3586 targid_mask &= (0x01 << target); 3587 ahc_outb(ahc, TARGID, 3588 targid_mask); 3589 ahc_outb(ahc, TARGID+1, 3590 (targid_mask >> 8)); 3591 } 3592 3593 for (empty = 1, i = 0; i < 16; i++) 3594 if (ahc->enabled_targets[i] 3595 != NULL) { 3596 empty = 0; 3597 break; 3598 } 3599 if (empty) { 3600 /* Disallow select-in */ 3601 u_int scsiseq; 3602 3603 printf("No targets\n"); 3604 scsiseq = 3605 ahc_inb(ahc, 3606 SCSISEQ_TEMPLATE); 3607 scsiseq &= ~ENSELI; 3608 ahc_outb(ahc, SCSISEQ_TEMPLATE, 3609 scsiseq); 3610 scsiseq = ahc_inb(ahc, SCSISEQ); 3611 scsiseq &= ~ENSELI; 3612 ahc_outb(ahc, SCSISEQ, scsiseq); 3613 } 3614 unpause_sequencer(ahc, 3615 /*always?*/FALSE); 3616 } 3617 } 3618 xpt_done(ccb); 3619 break; 3620 } 3621 break; 3622 } 3623 case XPT_ABORT: /* Abort the specified CCB */ 3624 { 3625 ahc_abort_ccb(ahc, sim, ccb); 3626 break; 3627 } 3628 case XPT_SET_TRAN_SETTINGS: 3629 { 3630 struct ahc_devinfo devinfo; 3631 struct ccb_trans_settings *cts; 3632 struct ahc_target_tinfo *tinfo; 3633 u_int update_type; 3634 int s; 3635 3636 cts = &ccb->cts; 3637 ahc_compile_devinfo(&devinfo, cts->ccb_h.target_id, 3638 cts->ccb_h.target_lun, 3639 SIM_IS_SCSIBUS_B(ahc, sim) ? 'B' : 'A', 3640 ROLE_UNKNOWN); 3641 tinfo = &ahc->transinfo[devinfo.target_offset]; 3642 update_type = 0; 3643 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 3644 update_type |= AHC_TRANS_GOAL; 3645 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 3646 update_type |= AHC_TRANS_USER; 3647 3648 s = splcam(); 3649 3650 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 3651 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0) 3652 ahc->discenable |= devinfo.target_mask; 3653 else 3654 ahc->discenable &= ~devinfo.target_mask; 3655 } 3656 3657 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 3658 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0) 3659 ahc->tagenable |= devinfo.target_mask; 3660 else 3661 ahc->tagenable &= ~devinfo.target_mask; 3662 } 3663 3664 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) { 3665 switch (cts->bus_width) { 3666 case MSG_EXT_WDTR_BUS_16_BIT: 3667 if ((ahc->features & AHC_WIDE) != 0) 3668 break; 3669 /* FALLTHROUGH to 8bit */ 3670 case MSG_EXT_WDTR_BUS_32_BIT: 3671 case MSG_EXT_WDTR_BUS_8_BIT: 3672 default: 3673 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3674 break; 3675 } 3676 ahc_set_width(ahc, &devinfo, cts->ccb_h.path, 3677 cts->bus_width, update_type); 3678 } 3679 3680 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 3681 struct ahc_syncrate *syncrate; 3682 u_int maxsync; 3683 3684 if ((ahc->features & AHC_ULTRA2) != 0) 3685 maxsync = AHC_SYNCRATE_ULTRA2; 3686 else if ((ahc->features & AHC_ULTRA) != 0) 3687 maxsync = AHC_SYNCRATE_ULTRA; 3688 else 3689 maxsync = AHC_SYNCRATE_FAST; 3690 3691 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0) { 3692 if (cts->sync_offset != 0) 3693 cts->sync_offset = ~0; 3694 } else { 3695 cts->sync_offset = 0; 3696 } 3697 3698 syncrate = ahc_find_syncrate(ahc, &cts->sync_period, 3699 maxsync); 3700 ahc_validate_offset(ahc, syncrate, &cts->sync_offset, 3701 tinfo->goal.width); 3702 3703 /* We use a period of 0 to represent async */ 3704 if (cts->sync_offset == 0) 3705 cts->sync_period = 0; 3706 3707 ahc_set_syncrate(ahc, &devinfo, cts->ccb_h.path, 3708 syncrate, cts->sync_period, 3709 cts->sync_offset, update_type); 3710 } 3711 splx(s); 3712 ccb->ccb_h.status = CAM_REQ_CMP; 3713 xpt_done(ccb); 3714 break; 3715 } 3716 case XPT_GET_TRAN_SETTINGS: 3717 /* Get default/user set transfer settings for the target */ 3718 { 3719 struct ahc_devinfo devinfo; 3720 struct ccb_trans_settings *cts; 3721 struct ahc_target_tinfo *targ_info; 3722 struct ahc_transinfo *tinfo; 3723 int s; 3724 3725 cts = &ccb->cts; 3726 ahc_compile_devinfo(&devinfo, cts->ccb_h.target_id, 3727 cts->ccb_h.target_lun, 3728 SIM_IS_SCSIBUS_B(ahc, sim) ? 'B' : 'A', 3729 ROLE_UNKNOWN); 3730 targ_info = &ahc->transinfo[devinfo.target_offset]; 3731 3732 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 3733 tinfo = &targ_info->current; 3734 else 3735 tinfo = &targ_info->user; 3736 3737 s = splcam(); 3738 3739 cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB); 3740 if ((ahc->discenable & devinfo.target_mask) != 0) 3741 cts->flags |= CCB_TRANS_DISC_ENB; 3742 3743 if ((ahc->tagenable & devinfo.target_mask) != 0) 3744 cts->flags |= CCB_TRANS_TAG_ENB; 3745 3746 cts->sync_period = tinfo->period; 3747 cts->sync_offset = tinfo->offset; 3748 cts->bus_width = tinfo->width; 3749 3750 splx(s); 3751 3752 cts->valid = CCB_TRANS_SYNC_RATE_VALID 3753 | CCB_TRANS_SYNC_OFFSET_VALID 3754 | CCB_TRANS_BUS_WIDTH_VALID 3755 | CCB_TRANS_DISC_VALID 3756 | CCB_TRANS_TQ_VALID; 3757 3758 ccb->ccb_h.status = CAM_REQ_CMP; 3759 xpt_done(ccb); 3760 break; 3761 } 3762 case XPT_CALC_GEOMETRY: 3763 { 3764 struct ccb_calc_geometry *ccg; 3765 u_int32_t size_mb; 3766 u_int32_t secs_per_cylinder; 3767 int extended; 3768 3769 ccg = &ccb->ccg; 3770 size_mb = ccg->volume_size 3771 / ((1024L * 1024L) / ccg->block_size); 3772 extended = SIM_IS_SCSIBUS_B(ahc, sim) 3773 ? ahc->flags & AHC_EXTENDED_TRANS_B 3774 : ahc->flags & AHC_EXTENDED_TRANS_A; 3775 3776 if (size_mb > 1024 && extended) { 3777 ccg->heads = 255; 3778 ccg->secs_per_track = 63; 3779 } else { 3780 ccg->heads = 64; 3781 ccg->secs_per_track = 32; 3782 } 3783 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 3784 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 3785 ccb->ccb_h.status = CAM_REQ_CMP; 3786 xpt_done(ccb); 3787 break; 3788 } 3789 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 3790 { 3791 struct cam_path *path; 3792 char channel; 3793 int found; 3794 3795 s = splcam(); 3796 if (SIM_IS_SCSIBUS_B(ahc, sim)) { 3797 channel = 'B'; 3798 path = ahc->path_b; 3799 } else { 3800 channel = 'A'; 3801 path = ahc->path; 3802 } 3803 found = ahc_reset_channel(ahc, channel, /*initiate reset*/TRUE); 3804 splx(s); 3805 if (bootverbose) { 3806 xpt_print_path(path); 3807 printf("SCSI bus reset delivered. " 3808 "%d SCBs aborted.\n", found); 3809 } 3810 ccb->ccb_h.status = CAM_REQ_CMP; 3811 xpt_done(ccb); 3812 break; 3813 } 3814 case XPT_TERM_IO: /* Terminate the I/O process */ 3815 /* XXX Implement */ 3816 ccb->ccb_h.status = CAM_REQ_INVALID; 3817 xpt_done(ccb); 3818 break; 3819 case XPT_PATH_INQ: /* Path routing inquiry */ 3820 { 3821 struct ccb_pathinq *cpi = &ccb->cpi; 3822 3823 cpi->version_num = 1; /* XXX??? */ 3824 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE; 3825 if ((ahc->features & AHC_WIDE) != 0) 3826 cpi->hba_inquiry |= PI_WIDE_16; 3827 if ((ahc->flags & AHC_TARGETMODE) != 0) { 3828 cpi->target_sprt = PIT_PROCESSOR 3829 | PIT_DISCONNECT 3830 | PIT_TERM_IO; 3831 } else { 3832 cpi->target_sprt = 0; 3833 } 3834 cpi->hba_misc = (ahc->flags & AHC_INITIATORMODE) 3835 ? 0 : PIM_NOINITIATOR; 3836 cpi->hba_eng_cnt = 0; 3837 cpi->max_target = (ahc->features & AHC_WIDE) ? 15 : 7; 3838 cpi->max_lun = 7; 3839 if (SIM_IS_SCSIBUS_B(ahc, sim)) { 3840 cpi->initiator_id = ahc->our_id_b; 3841 if ((ahc->flags & AHC_RESET_BUS_B) == 0) 3842 cpi->hba_misc |= PIM_NOBUSRESET; 3843 } else { 3844 cpi->initiator_id = ahc->our_id; 3845 if ((ahc->flags & AHC_RESET_BUS_A) == 0) 3846 cpi->hba_misc |= PIM_NOBUSRESET; 3847 } 3848 cpi->bus_id = cam_sim_bus(sim); 3849 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3850 strncpy(cpi->hba_vid, "Adaptec", HBA_IDLEN); 3851 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 3852 cpi->unit_number = cam_sim_unit(sim); 3853 cpi->ccb_h.status = CAM_REQ_CMP; 3854 xpt_done(ccb); 3855 break; 3856 } 3857 default: 3858 ccb->ccb_h.status = CAM_REQ_INVALID; 3859 xpt_done(ccb); 3860 break; 3861 } 3862} 3863 3864static void 3865ahc_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg) 3866{ 3867 struct ahc_softc *ahc; 3868 struct cam_sim *sim; 3869 3870 sim = (struct cam_sim *)callback_arg; 3871 ahc = (struct ahc_softc *)cam_sim_softc(sim); 3872 switch (code) { 3873 case AC_LOST_DEVICE: 3874 { 3875 struct ahc_devinfo devinfo; 3876 3877 ahc_compile_devinfo(&devinfo, xpt_path_target_id(path), 3878 xpt_path_lun_id(path), 3879 SIM_IS_SCSIBUS_B(ahc, sim) ? 'B' : 'A', 3880 ROLE_UNKNOWN); 3881 3882 /* 3883 * Revert to async/narrow transfers 3884 * for the next device. 3885 */ 3886 pause_sequencer(ahc); 3887 ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, 3888 AHC_TRANS_GOAL|AHC_TRANS_CUR); 3889 ahc_set_syncrate(ahc, &devinfo, path, /*syncrate*/NULL, 3890 /*period*/0, /*offset*/0, 3891 AHC_TRANS_GOAL|AHC_TRANS_CUR); 3892 unpause_sequencer(ahc, /*unpause always*/FALSE); 3893 break; 3894 } 3895 default: 3896 break; 3897 } 3898} 3899 3900static void 3901ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments, 3902 int error) 3903{ 3904 struct scb *scb; 3905 union ccb *ccb; 3906 struct ahc_softc *ahc; 3907 int s; 3908 3909 scb = (struct scb *)arg; 3910 ccb = scb->ccb; 3911 ahc = (struct ahc_softc *)ccb->ccb_h.ccb_ahc_ptr; 3912 3913 if (nsegments != 0) { 3914 struct ahc_dma_seg *sg; 3915 bus_dma_segment_t *end_seg; 3916 bus_dmasync_op_t op; 3917 3918 end_seg = dm_segs + nsegments; 3919 3920 /* Copy the first SG into the data pointer area */ 3921 scb->hscb->SG_pointer = scb->ahc_dmaphys; 3922 scb->hscb->data = dm_segs->ds_addr; 3923 scb->hscb->datalen = dm_segs->ds_len; 3924 dm_segs++; 3925 3926 /* Copy the remaining segments into our SG list */ 3927 sg = scb->ahc_dma; 3928 while (dm_segs < end_seg) { 3929 sg->addr = dm_segs->ds_addr; 3930 sg->len = dm_segs->ds_len; 3931 sg++; 3932 dm_segs++; 3933 } 3934 3935 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 3936 op = BUS_DMASYNC_PREREAD; 3937 else 3938 op = BUS_DMASYNC_PREWRITE; 3939 3940 bus_dmamap_sync(ahc->dmat, scb->dmamap, op); 3941 } else { 3942 scb->hscb->SG_pointer = 0; 3943 scb->hscb->data = 0; 3944 scb->hscb->datalen = 0; 3945 } 3946 3947 scb->sg_count = scb->hscb->SG_count = nsegments; 3948 3949 s = splcam(); 3950 3951 /* 3952 * Last time we need to check if this SCB needs to 3953 * be aborted. 3954 */ 3955 if (ahc_ccb_status(ccb) != CAM_REQ_INPROG) { 3956 if (nsegments != 0) 3957 bus_dmamap_unload(ahc->dmat, scb->dmamap); 3958 ahc_free_scb(ahc, scb); 3959 xpt_done(ccb); 3960 splx(s); 3961 return; 3962 } 3963 3964 /* Busy this tcl if we are untagged */ 3965 if ((scb->hscb->control & TAG_ENB) == 0) 3966 ahc_busy_tcl(ahc, scb); 3967 3968 LIST_INSERT_HEAD(&ahc->pending_ccbs, &ccb->ccb_h, 3969 sim_links.le); 3970 3971 scb->flags |= SCB_ACTIVE; 3972 ccb->ccb_h.status |= CAM_SIM_QUEUED; 3973 3974 ccb->ccb_h.timeout_ch = 3975 timeout(ahc_timeout, (caddr_t)scb, 3976 (ccb->ccb_h.timeout * hz) / 1000); 3977 3978 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 3979 if ((ahc->flags & AHC_PAGESCBS) == 0) 3980 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 3981 pause_sequencer(ahc); 3982 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 3983 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 3984 unpause_sequencer(ahc, /*unpause_always*/FALSE); 3985 } else { 3986 3987 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 3988 3989 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3990 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 3991 } else { 3992 pause_sequencer(ahc); 3993 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 3994 unpause_sequencer(ahc, /*unpause_always*/FALSE); 3995 } 3996 } 3997 3998 splx(s); 3999} 4000 4001static void 4002ahc_poll(struct cam_sim *sim) 4003{ 4004 ahc_intr(cam_sim_softc(sim)); 4005} 4006 4007static void 4008ahc_setup_data(struct ahc_softc *ahc, struct ccb_scsiio *csio, 4009 struct scb *scb) 4010{ 4011 struct hardware_scb *hscb; 4012 struct ccb_hdr *ccb_h; 4013 4014 hscb = scb->hscb; 4015 ccb_h = &csio->ccb_h; 4016 4017 if (ccb_h->func_code == XPT_SCSI_IO) { 4018 hscb->cmdlen = csio->cdb_len; 4019 if ((ccb_h->flags & CAM_CDB_POINTER) != 0) { 4020 if ((ccb_h->flags & CAM_CDB_PHYS) == 0) 4021 if (hscb->cmdlen <= 16) { 4022 memcpy(hscb->cmdstore, 4023 csio->cdb_io.cdb_ptr, 4024 hscb->cmdlen); 4025 hscb->cmdpointer = 4026 hscb->cmdstore_busaddr; 4027 } else 4028 hscb->cmdpointer = 4029 vtophys(csio->cdb_io.cdb_ptr); 4030 else 4031 hscb->cmdpointer = 4032 (u_int32_t)csio->cdb_io.cdb_ptr; 4033 } else { 4034 /* 4035 * CCB CDB Data Storage area is only 16 bytes 4036 * so no additional testing is required 4037 */ 4038 memcpy(hscb->cmdstore, csio->cdb_io.cdb_bytes, 4039 hscb->cmdlen); 4040 hscb->cmdpointer = hscb->cmdstore_busaddr; 4041 } 4042 } 4043 4044 /* Only use S/G if there is a transfer */ 4045 if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 4046 if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) { 4047 /* We've been given a pointer to a single buffer */ 4048 if ((ccb_h->flags & CAM_DATA_PHYS) == 0) { 4049 int s; 4050 int error; 4051 4052 s = splsoftvm(); 4053 error = bus_dmamap_load(ahc->dmat, 4054 scb->dmamap, 4055 csio->data_ptr, 4056 csio->dxfer_len, 4057 ahc_execute_scb, 4058 scb, /*flags*/0); 4059 if (error == EINPROGRESS) { 4060 /* 4061 * So as to maintain ordering, 4062 * freeze the controller queue 4063 * until our mapping is 4064 * returned. 4065 */ 4066 xpt_freeze_simq(ahc->sim, 4067 /*count*/1); 4068 scb->ccb->ccb_h.status |= 4069 CAM_RELEASE_SIMQ; 4070 } 4071 splx(s); 4072 } else { 4073 struct bus_dma_segment seg; 4074 4075 /* Pointer to physical buffer */ 4076 if (csio->dxfer_len > AHC_MAXTRANSFER_SIZE) 4077 panic("ahc_setup_data - Transfer size " 4078 "larger than can device max"); 4079 4080 seg.ds_addr = (bus_addr_t)csio->data_ptr; 4081 seg.ds_len = csio->dxfer_len; 4082 ahc_execute_scb(scb, &seg, 1, 0); 4083 } 4084 } else { 4085 struct bus_dma_segment *segs; 4086 4087 if ((ccb_h->flags & CAM_DATA_PHYS) != 0) 4088 panic("ahc_setup_data - Physical segment " 4089 "pointers unsupported"); 4090 4091 if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0) 4092 panic("ahc_setup_data - Virtual segment " 4093 "addresses unsupported"); 4094 4095 /* Just use the segments provided */ 4096 segs = (struct bus_dma_segment *)csio->data_ptr; 4097 ahc_execute_scb(scb, segs, csio->sglist_cnt, 0); 4098 } 4099 if (ccb_h->func_code == XPT_CONT_TARGET_IO) { 4100 hscb->cmdpointer |= DPHASE_PENDING; 4101 if ((ccb_h->flags & CAM_DIR_MASK) == CAM_DIR_IN) 4102 hscb->cmdpointer |= (TARGET_DATA_IN << 8); 4103 } 4104 } else { 4105 ahc_execute_scb(scb, NULL, 0, 0); 4106 } 4107} 4108 4109static void 4110ahc_freeze_devq(struct ahc_softc *ahc, struct cam_path *path) 4111{ 4112 int target; 4113 char channel; 4114 int lun; 4115 4116 target = xpt_path_target_id(path); 4117 lun = xpt_path_lun_id(path); 4118 channel = xpt_path_sim(path)->bus_id == 0 ? 'A' : 'B'; 4119 4120 ahc_search_qinfifo(ahc, target, channel, lun, 4121 /*tag*/SCB_LIST_NULL, CAM_REQUEUE_REQ, 4122 SEARCH_COMPLETE); 4123} 4124 4125/* 4126 * An scb (and hence an scb entry on the board) is put onto the 4127 * free list. 4128 */ 4129static void 4130ahc_free_scb(struct ahc_softc *ahc, struct scb *scb) 4131{ 4132 struct hardware_scb *hscb; 4133 int opri; 4134 4135 hscb = scb->hscb; 4136 4137 opri = splcam(); 4138 4139 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 4140 && (scb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) { 4141 scb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 4142 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 4143 } 4144 4145 /* Clean up for the next user */ 4146 scb->flags = SCB_FREE; 4147 hscb->control = 0; 4148 hscb->status = 0; 4149 4150 STAILQ_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 4151 splx(opri); 4152} 4153 4154/* 4155 * Get a free scb, either one already assigned to a hardware slot 4156 * on the adapter or one that will require an SCB to be paged out before 4157 * use. If there are none, see if we can allocate a new SCB. Otherwise 4158 * either return an error or sleep. 4159 */ 4160static struct scb * 4161ahc_get_scb(struct ahc_softc *ahc) 4162{ 4163 struct scb *scbp; 4164 int opri; 4165 4166 opri = splcam(); 4167 if ((scbp = STAILQ_FIRST(&ahc->scb_data->free_scbs))) { 4168 STAILQ_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 4169 } else if (ahc->scb_data->numscbs < ahc->scb_data->maxscbs) { 4170 scbp = ahc_alloc_scb(ahc); 4171 if (scbp == NULL) 4172 printf("%s: Can't malloc SCB\n", ahc_name(ahc)); 4173 } 4174 4175 splx(opri); 4176 4177 return (scbp); 4178} 4179 4180 4181static struct scb * 4182ahc_alloc_scb(struct ahc_softc *ahc) 4183{ 4184 static struct ahc_dma_seg *next_sg_array = NULL; 4185 static int sg_arrays_free = 0; 4186 struct scb *newscb; 4187 int error; 4188 4189 newscb = (struct scb *) malloc(sizeof(struct scb), M_DEVBUF, M_NOWAIT); 4190 if (newscb != NULL) { 4191 bzero(newscb, sizeof(struct scb)); 4192 error = bus_dmamap_create(ahc->dmat, /*flags*/0, 4193 &newscb->dmamap); 4194 if (error != 0) 4195 printf("%s: Unable to allocate SCB dmamap - error %d\n", 4196 ahc_name(ahc), error); 4197 4198 if (error == 0 && next_sg_array == NULL) { 4199 size_t alloc_size = sizeof(struct ahc_dma_seg) 4200 * AHC_NSEG; 4201 sg_arrays_free = PAGE_SIZE / alloc_size; 4202 alloc_size *= sg_arrays_free; 4203 if (alloc_size == 0) 4204 panic("%s: SG list doesn't fit in a page", 4205 ahc_name(ahc)); 4206 next_sg_array = (struct ahc_dma_seg *) 4207 malloc(alloc_size, M_DEVBUF, M_NOWAIT); 4208 } 4209 if (error == 0 && next_sg_array != NULL) { 4210 struct hardware_scb *hscb; 4211 4212 newscb->ahc_dma = next_sg_array; 4213 newscb->ahc_dmaphys = vtophys(next_sg_array); 4214 sg_arrays_free--; 4215 if (sg_arrays_free == 0) 4216 next_sg_array = NULL; 4217 else 4218 next_sg_array = &next_sg_array[AHC_NSEG]; 4219 hscb = &ahc->scb_data->hscbs[ahc->scb_data->numscbs]; 4220 newscb->hscb = hscb; 4221 hscb->control = 0; 4222 hscb->status = 0; 4223 hscb->tag = ahc->scb_data->numscbs; 4224 hscb->residual_data_count[2] = 0; 4225 hscb->residual_data_count[1] = 0; 4226 hscb->residual_data_count[0] = 0; 4227 hscb->residual_SG_count = 0; 4228 hscb->cmdstore_busaddr = 4229 ahc_hscb_busaddr(ahc, hscb->tag) 4230 + offsetof(struct hardware_scb, cmdstore); 4231 /* 4232 * Place in the scbarray 4233 * Never is removed. 4234 */ 4235 ahc->scb_data->scbarray[hscb->tag] = newscb; 4236 ahc->scb_data->numscbs++; 4237 } else { 4238 free(newscb, M_DEVBUF); 4239 newscb = NULL; 4240 } 4241 } 4242 return newscb; 4243} 4244 4245static void 4246ahc_loadseq(struct ahc_softc *ahc) 4247{ 4248 struct patch *cur_patch; 4249 int i; 4250 int downloaded; 4251 int skip_addr; 4252 u_int8_t download_consts[4]; 4253 4254 /* Setup downloadable constant table */ 4255#if 0 4256 /* No downloaded constants are currently defined. */ 4257 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 4258#endif 4259 4260 cur_patch = patches; 4261 downloaded = 0; 4262 skip_addr = 0; 4263 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 4264 ahc_outb(ahc, SEQADDR0, 0); 4265 ahc_outb(ahc, SEQADDR1, 0); 4266 4267 for (i = 0; i < sizeof(seqprog)/4; i++) { 4268 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 4269 /* 4270 * Don't download this instruction as it 4271 * is in a patch that was removed. 4272 */ 4273 continue; 4274 } 4275 ahc_download_instr(ahc, i, download_consts); 4276 downloaded++; 4277 } 4278 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 4279 restart_sequencer(ahc); 4280 4281 if (bootverbose) 4282 printf(" %d instructions downloaded\n", downloaded); 4283} 4284 4285static int 4286ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 4287 int start_instr, int *skip_addr) 4288{ 4289 struct patch *cur_patch; 4290 struct patch *last_patch; 4291 int num_patches; 4292 4293 num_patches = sizeof(patches)/sizeof(struct patch); 4294 last_patch = &patches[num_patches]; 4295 cur_patch = *start_patch; 4296 4297 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 4298 4299 if (cur_patch->patch_func(ahc) == 0) { 4300 4301 /* Start rejecting code */ 4302 *skip_addr = start_instr + cur_patch->skip_instr; 4303 cur_patch += cur_patch->skip_patch; 4304 } else { 4305 /* Accepted this patch. Advance to the next 4306 * one and wait for our intruction pointer to 4307 * hit this point. 4308 */ 4309 cur_patch++; 4310 } 4311 } 4312 4313 *start_patch = cur_patch; 4314 if (start_instr < *skip_addr) 4315 /* Still skipping */ 4316 return (0); 4317 4318 return (1); 4319} 4320 4321static void 4322ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 4323{ 4324 union ins_formats instr; 4325 struct ins_format1 *fmt1_ins; 4326 struct ins_format3 *fmt3_ins; 4327 u_int opcode; 4328 4329 /* Structure copy */ 4330 instr = *(union ins_formats*)&seqprog[instrptr * 4]; 4331 4332 fmt1_ins = &instr.format1; 4333 fmt3_ins = NULL; 4334 4335 /* Pull the opcode */ 4336 opcode = instr.format1.opcode; 4337 switch (opcode) { 4338 case AIC_OP_JMP: 4339 case AIC_OP_JC: 4340 case AIC_OP_JNC: 4341 case AIC_OP_CALL: 4342 case AIC_OP_JNE: 4343 case AIC_OP_JNZ: 4344 case AIC_OP_JE: 4345 case AIC_OP_JZ: 4346 { 4347 struct patch *cur_patch; 4348 int address_offset; 4349 u_int address; 4350 int skip_addr; 4351 int i; 4352 4353 fmt3_ins = &instr.format3; 4354 address_offset = 0; 4355 address = fmt3_ins->address; 4356 cur_patch = patches; 4357 skip_addr = 0; 4358 4359 for (i = 0; i < address;) { 4360 4361 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 4362 4363 if (skip_addr > i) { 4364 int end_addr; 4365 4366 end_addr = MIN(address, skip_addr); 4367 address_offset += end_addr - i; 4368 i = skip_addr; 4369 } else { 4370 i++; 4371 } 4372 } 4373 address -= address_offset; 4374 fmt3_ins->address = address; 4375 /* FALLTHROUGH */ 4376 } 4377 case AIC_OP_OR: 4378 case AIC_OP_AND: 4379 case AIC_OP_XOR: 4380 case AIC_OP_ADD: 4381 case AIC_OP_ADC: 4382 case AIC_OP_BMOV: 4383 if (fmt1_ins->parity != 0) { 4384 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 4385 } 4386 fmt1_ins->parity = 0; 4387 /* FALLTHROUGH */ 4388 case AIC_OP_ROL: 4389 if ((ahc->features & AHC_ULTRA2) != 0) { 4390 int i, count; 4391 4392 /* Calculate odd parity for the instruction */ 4393 for (i = 0, count = 0; i < 31; i++) { 4394 u_int32_t mask; 4395 4396 mask = 0x01 << i; 4397 if ((instr.integer & mask) != 0) 4398 count++; 4399 } 4400 if ((count & 0x01) == 0) 4401 instr.format1.parity = 1; 4402 } else { 4403 /* Compress the instruction for older sequencers */ 4404 if (fmt3_ins != NULL) { 4405 instr.integer = 4406 fmt3_ins->immediate 4407 | (fmt3_ins->source << 8) 4408 | (fmt3_ins->address << 16) 4409 | (fmt3_ins->opcode << 25); 4410 } else { 4411 instr.integer = 4412 fmt1_ins->immediate 4413 | (fmt1_ins->source << 8) 4414 | (fmt1_ins->destination << 16) 4415 | (fmt1_ins->ret << 24) 4416 | (fmt1_ins->opcode << 25); 4417 } 4418 } 4419 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 4420 break; 4421 default: 4422 panic("Unknown opcode encountered in seq program"); 4423 break; 4424 } 4425} 4426 4427static void 4428ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) { 4429 4430 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 4431 struct ccb_hdr *ccbh; 4432 4433 scb->flags |= SCB_RECOVERY_SCB; 4434 4435 /* 4436 * Take all queued, but not sent SCBs out of the equation. 4437 * Also ensure that no new CCBs are queued to us while we 4438 * try to fix this problem. 4439 */ 4440 if ((scb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) { 4441 xpt_freeze_simq(ahc->sim, /*count*/1); 4442 scb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 4443 } 4444 4445 /* 4446 * Go through all of our pending SCBs and remove 4447 * any scheduled timeouts for them. We will reschedule 4448 * them after we've successfully fixed this problem. 4449 */ 4450 ccbh = ahc->pending_ccbs.lh_first; 4451 while (ccbh != NULL) { 4452 struct scb *pending_scb; 4453 4454 pending_scb = (struct scb *)ccbh->ccb_scb_ptr; 4455 untimeout(ahc_timeout, pending_scb, ccbh->timeout_ch); 4456 ccbh = ccbh->sim_links.le.le_next; 4457 } 4458 } 4459} 4460 4461static void 4462ahc_timeout(void *arg) 4463{ 4464 struct scb *scb; 4465 struct ahc_softc *ahc; 4466 int s, found; 4467 u_int bus_state; 4468 int target; 4469 int lun; 4470 char channel; 4471 4472 scb = (struct scb *)arg; 4473 ahc = (struct ahc_softc *)scb->ccb->ccb_h.ccb_ahc_ptr; 4474 4475 s = splcam(); 4476 4477 /* 4478 * Ensure that the card doesn't do anything 4479 * behind our back. Also make sure that we 4480 * didn't "just" miss an interrupt that would 4481 * affect this timeout. 4482 */ 4483 do { 4484 ahc_intr(ahc); 4485 pause_sequencer(ahc); 4486 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4487 4488 if ((scb->flags & SCB_ACTIVE) == 0) { 4489 /* Previous timeout took care of me already */ 4490 printf("Timedout SCB handled by another timeout\n"); 4491 unpause_sequencer(ahc, /*unpause_always*/TRUE); 4492 splx(s); 4493 return; 4494 } 4495 4496 target = SCB_TARGET(scb); 4497 channel = SCB_CHANNEL(scb); 4498 lun = SCB_LUN(scb); 4499 4500 xpt_print_path(scb->ccb->ccb_h.path); 4501 printf("SCB 0x%x - timed out ", scb->hscb->tag); 4502 /* 4503 * Take a snapshot of the bus state and print out 4504 * some information so we can track down driver bugs. 4505 */ 4506 bus_state = ahc_inb(ahc, LASTPHASE); 4507 4508 switch(bus_state) 4509 { 4510 case P_DATAOUT: 4511 printf("in dataout phase"); 4512 break; 4513 case P_DATAIN: 4514 printf("in datain phase"); 4515 break; 4516 case P_COMMAND: 4517 printf("in command phase"); 4518 break; 4519 case P_MESGOUT: 4520 printf("in message out phase"); 4521 break; 4522 case P_STATUS: 4523 printf("in status phase"); 4524 break; 4525 case P_MESGIN: 4526 printf("in message in phase"); 4527 break; 4528 case P_BUSFREE: 4529 printf("while idle, LASTPHASE == 0x%x", 4530 bus_state); 4531 break; 4532 default: 4533 /* 4534 * We aren't in a valid phase, so assume we're 4535 * idle. 4536 */ 4537 printf("invalid phase, LASTPHASE == 0x%x", 4538 bus_state); 4539 bus_state = P_BUSFREE; 4540 break; 4541 } 4542 4543 printf(", SEQADDR == 0x%x\n", 4544 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 4545 4546#if 0 4547 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 4548 printf("SIMODE1 = 0x%x\n", ahc_inb(ahc, SIMODE1)); 4549 printf("INTSTAT = 0x%x\n", ahc_inb(ahc, INTSTAT)); 4550 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4551 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4552 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4553 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4554 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4555 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4556 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4557#endif 4558 if (scb->flags & SCB_DEVICE_RESET) { 4559 /* 4560 * Been down this road before. 4561 * Do a full bus reset. 4562 */ 4563bus_reset: 4564 ahc_set_ccb_status(scb->ccb, CAM_CMD_TIMEOUT); 4565 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4566 printf("%s: Issued Channel %c Bus Reset. " 4567 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4568 } else { 4569 /* 4570 * If we are a target, transition to bus free and report 4571 * the timeout. 4572 * 4573 * The target/initiator that is holding up the bus may not 4574 * be the same as the one that triggered this timeout 4575 * (different commands have different timeout lengths). 4576 * If the bus is idle and we are actiing as the initiator 4577 * for this request, queue a BDR message to the timed out 4578 * target. Otherwise, if the timed out transaction is 4579 * active: 4580 * Initiator transaction: 4581 * Stuff the message buffer with a BDR message and assert 4582 * ATN in the hopes that the target will let go of the bus 4583 * and go to the mesgout phase. If this fails, we'll 4584 * get another timeout 2 seconds later which will attempt 4585 * a bus reset. 4586 * 4587 * Target transaction: 4588 * Transition to BUS FREE and report the error. 4589 * It's good to be the target! 4590 */ 4591 u_int active_scb_index; 4592 4593 active_scb_index = ahc_inb(ahc, SCB_TAG); 4594 4595 if (bus_state != P_BUSFREE 4596 && (active_scb_index < ahc->scb_data->numscbs)) { 4597 struct scb *active_scb; 4598 4599 /* 4600 * If the active SCB is not from our device, 4601 * assume that another device is hogging the bus 4602 * and wait for it's timeout to expire before 4603 * taking additional action. 4604 */ 4605 active_scb = ahc->scb_data->scbarray[active_scb_index]; 4606 if (active_scb->hscb->tcl != scb->hscb->tcl 4607 && (scb->flags & SCB_OTHERTCL_TIMEOUT) == 0) { 4608 struct ccb_hdr *ccbh; 4609 u_int newtimeout; 4610 4611 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4612 newtimeout = MAX(active_scb->ccb->ccb_h.timeout, 4613 scb->ccb->ccb_h.timeout); 4614 ccbh = &scb->ccb->ccb_h; 4615 scb->ccb->ccb_h.timeout_ch = 4616 timeout(ahc_timeout, scb, 4617 (newtimeout * hz) / 1000); 4618 splx(s); 4619 return; 4620 } 4621 4622 /* It's us */ 4623 if ((scb->hscb->control & TARGET_SCB) != 0) { 4624 4625 /* 4626 * Send back any queued up transactions 4627 * and properly record the error condition. 4628 */ 4629 ahc_freeze_devq(ahc, scb->ccb->ccb_h.path); 4630 ahc_set_ccb_status(scb->ccb, CAM_CMD_TIMEOUT); 4631 ahc_freeze_ccb(scb->ccb); 4632 ahc_done(ahc, scb); 4633 4634 /* Will clear us from the bus */ 4635 restart_sequencer(ahc); 4636 return; 4637 } 4638 4639 ahc_set_recoveryscb(ahc, active_scb); 4640 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4641 ahc_outb(ahc, SCSISIGO, bus_state|ATNO); 4642 xpt_print_path(active_scb->ccb->ccb_h.path); 4643 printf("BDR message in message buffer\n"); 4644 active_scb->flags |= SCB_DEVICE_RESET; 4645 active_scb->ccb->ccb_h.timeout_ch = 4646 timeout(ahc_timeout, (caddr_t)active_scb, 2 * hz); 4647 unpause_sequencer(ahc, /*unpause_always*/TRUE); 4648 } else { 4649 int disconnected; 4650 4651 if (bus_state != P_BUSFREE 4652 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 4653 /* Hung target selection. Goto busfree */ 4654 printf("%s: Hung target selection\n", 4655 ahc_name(ahc)); 4656 restart_sequencer(ahc); 4657 return; 4658 } 4659 4660 if (ahc_search_qinfifo(ahc, target, channel, lun, 4661 scb->hscb->tag, /*status*/0, 4662 SEARCH_COUNT) > 0) { 4663 disconnected = FALSE; 4664 } else { 4665 disconnected = TRUE; 4666 } 4667 4668 if (disconnected) { 4669 4670 ahc_set_recoveryscb(ahc, scb); 4671 /* 4672 * Simply set the MK_MESSAGE control bit. 4673 */ 4674 scb->hscb->control |= MK_MESSAGE; 4675 scb->flags |= SCB_QUEUED_MSG 4676 | SCB_DEVICE_RESET; 4677 4678 /* 4679 * Remove this SCB from the disconnected 4680 * list so that a reconnect at this point 4681 * causes a BDR. 4682 */ 4683 ahc_search_disc_list(ahc, target, channel, lun, 4684 scb->hscb->tag); 4685 ahc_index_busy_tcl(ahc, scb->hscb->tcl, 4686 /*unbusy*/TRUE); 4687 4688 /* 4689 * Actually re-queue this SCB in case we can 4690 * select the device before it reconnects. 4691 * Clear out any entries in the QINFIFO first 4692 * so we are the next SCB for this target 4693 * to run. 4694 */ 4695 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4696 channel, SCB_LUN(scb), 4697 SCB_LIST_NULL, 4698 CAM_REQUEUE_REQ, 4699 SEARCH_COMPLETE); 4700 xpt_print_path(scb->ccb->ccb_h.path); 4701 printf("Queuing a BDR SCB\n"); 4702 ahc->qinfifo[ahc->qinfifonext++] = 4703 scb->hscb->tag; 4704 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4705 ahc_outb(ahc, HNSCB_QOFF, 4706 ahc->qinfifonext); 4707 } else { 4708 ahc_outb(ahc, KERNEL_QINPOS, 4709 ahc->qinfifonext); 4710 } 4711 scb->ccb->ccb_h.timeout_ch = 4712 timeout(ahc_timeout, (caddr_t)scb, 2 * hz); 4713 unpause_sequencer(ahc, /*unpause_always*/FALSE); 4714 } else { 4715 /* Go "immediatly" to the bus reset */ 4716 /* This shouldn't happen */ 4717 ahc_set_recoveryscb(ahc, scb); 4718 xpt_print_path(scb->ccb->ccb_h.path); 4719 printf("SCB %d: Immediate reset. " 4720 "Flags = 0x%x\n", scb->hscb->tag, 4721 scb->flags); 4722 goto bus_reset; 4723 } 4724 } 4725 } 4726 splx(s); 4727} 4728 4729static int 4730ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4731 int lun, u_int tag, u_int32_t status, 4732 ahc_search_action action) 4733{ 4734 struct scb *scbp; 4735 u_int8_t qinpos; 4736 u_int8_t qintail; 4737 int found; 4738 4739 qinpos = ahc_inb(ahc, QINPOS); 4740 qintail = ahc->qinfifonext; 4741 found = 0; 4742 4743 /* 4744 * Start with an empty queue. Entries that are not chosen 4745 * for removal will be re-added to the queue as we go. 4746 */ 4747 ahc->qinfifonext = qinpos; 4748 4749 while (qinpos != qintail) { 4750 scbp = ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4751 if (ahc_match_scb(scbp, target, channel, lun, tag)) { 4752 /* 4753 * We found an scb that needs to be removed. 4754 */ 4755 switch (action) { 4756 case SEARCH_COMPLETE: 4757 if (ahc_ccb_status(scbp->ccb) == CAM_REQ_INPROG) 4758 ahc_set_ccb_status(scbp->ccb, status); 4759 ahc_freeze_ccb(scbp->ccb); 4760 ahc_done(ahc, scbp); 4761 break; 4762 case SEARCH_COUNT: 4763 ahc->qinfifo[ahc->qinfifonext++] = 4764 scbp->hscb->tag; 4765 break; 4766 case SEARCH_REMOVE: 4767 break; 4768 } 4769 found++; 4770 } else { 4771 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4772 } 4773 qinpos++; 4774 } 4775 4776 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4777 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4778 } else { 4779 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4780 } 4781 4782 return (found); 4783} 4784 4785 4786static void 4787ahc_abort_ccb(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 4788{ 4789 union ccb *abort_ccb; 4790 4791 abort_ccb = ccb->cab.abort_ccb; 4792 switch (abort_ccb->ccb_h.func_code) { 4793 case XPT_ACCEPT_TARGET_IO: 4794 case XPT_IMMED_NOTIFY: 4795 case XPT_CONT_TARGET_IO: 4796 { 4797 struct tmode_tstate *tstate; 4798 struct tmode_lstate *lstate; 4799 struct ccb_hdr_slist *list; 4800 cam_status status; 4801 4802 status = ahc_find_tmode_devs(ahc, sim, abort_ccb, &tstate, 4803 &lstate, TRUE); 4804 4805 if (status != CAM_REQ_CMP) { 4806 ccb->ccb_h.status = status; 4807 break; 4808 } 4809 4810 if (abort_ccb->ccb_h.func_code == XPT_ACCEPT_TARGET_IO) 4811 list = &lstate->accept_tios; 4812 else if (abort_ccb->ccb_h.func_code == XPT_IMMED_NOTIFY) 4813 list = &lstate->immed_notifies; 4814 else 4815 list = NULL; 4816 4817 if (list != NULL) { 4818 struct ccb_hdr *curelm; 4819 int found; 4820 4821 curelm = SLIST_FIRST(list); 4822 found = 0; 4823 if (curelm == &abort_ccb->ccb_h) { 4824 found = 1; 4825 SLIST_REMOVE_HEAD(list, sim_links.sle); 4826 } else { 4827 while(curelm != NULL) { 4828 struct ccb_hdr *nextelm; 4829 4830 nextelm = 4831 SLIST_NEXT(curelm, sim_links.sle); 4832 4833 if (nextelm == &abort_ccb->ccb_h) { 4834 found = 1; 4835 SLIST_NEXT(curelm, 4836 sim_links.sle) = 4837 SLIST_NEXT(nextelm, 4838 sim_links.sle); 4839 break; 4840 } 4841 curelm = nextelm; 4842 } 4843 } 4844 4845 if (found) 4846 abort_ccb->ccb_h.status = CAM_REQ_ABORTED; 4847 else 4848 ccb->ccb_h.status = CAM_PATH_INVALID; 4849 break; 4850 } 4851 /* FALLTHROUGH */ 4852 } 4853 case XPT_SCSI_IO: 4854 /* XXX Fully implement the hard ones */ 4855 ccb->ccb_h.status = CAM_UA_ABORT; 4856 break; 4857 default: 4858 ccb->ccb_h.status = CAM_REQ_INVALID; 4859 break; 4860 } 4861 xpt_done(ccb); 4862} 4863 4864/* 4865 * Abort all SCBs that match the given description (target/channel/lun/tag), 4866 * setting their status to the passed in status if the status has not already 4867 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4868 * is paused before it is called. 4869 */ 4870static int 4871ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4872 int lun, u_int tag, u_int32_t status) 4873{ 4874 struct scb *scbp; 4875 u_int active_scb; 4876 int i; 4877 int found; 4878 4879 /* restore this when we're done */ 4880 active_scb = ahc_inb(ahc, SCBPTR); 4881 4882 found = ahc_search_qinfifo(ahc, target, channel, lun, tag, 4883 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 4884 4885 /* 4886 * Search waiting for selection list. 4887 */ 4888 { 4889 u_int8_t next, prev; 4890 4891 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4892 prev = SCB_LIST_NULL; 4893 4894 while (next != SCB_LIST_NULL) { 4895 u_int8_t scb_index; 4896 4897 ahc_outb(ahc, SCBPTR, next); 4898 scb_index = ahc_inb(ahc, SCB_TAG); 4899 if (scb_index >= ahc->scb_data->numscbs) { 4900 panic("Waiting List inconsistency. " 4901 "SCB index == %d, yet numscbs == %d.", 4902 scb_index, ahc->scb_data->numscbs); 4903 } 4904 scbp = ahc->scb_data->scbarray[scb_index]; 4905 if (ahc_match_scb(scbp, target, channel, lun, tag)) { 4906 4907 next = ahc_abort_wscb(ahc, next, prev); 4908 } else { 4909 4910 prev = next; 4911 next = ahc_inb(ahc, SCB_NEXT); 4912 } 4913 } 4914 } 4915 /* 4916 * Go through the disconnected list and remove any entries we 4917 * have queued for completion, 0'ing their control byte too. 4918 */ 4919 ahc_search_disc_list(ahc, target, channel, lun, tag); 4920 4921 /* 4922 * Go through the hardware SCB array looking for commands that 4923 * were active but not on any list. 4924 */ 4925 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 4926 u_int scbid; 4927 4928 ahc_outb(ahc, SCBPTR, i); 4929 scbid = ahc_inb(ahc, SCB_TAG); 4930 if (scbid < ahc->scb_data->numscbs) { 4931 scbp = ahc->scb_data->scbarray[scbid]; 4932 if (ahc_match_scb(scbp, target, channel, lun, tag)) { 4933 ahc_add_curscb_to_free_list(ahc); 4934 } 4935 } 4936 } 4937 /* 4938 * Go through the pending CCB list and look for 4939 * commands for this target that are still active. 4940 * These are other tagged commands that were 4941 * disconnected when the reset occured. 4942 */ 4943 { 4944 struct ccb_hdr *ccb_h; 4945 4946 4947 ccb_h = ahc->pending_ccbs.lh_first; 4948 4949 while (ccb_h != NULL) { 4950 scbp = (struct scb *)ccb_h->ccb_scb_ptr; 4951 ccb_h = ccb_h->sim_links.le.le_next; 4952 if (ahc_match_scb(scbp, target, channel, lun, tag)) { 4953 if (ahc_ccb_status(scbp->ccb) == CAM_REQ_INPROG) 4954 ahc_set_ccb_status(scbp->ccb, status); 4955 ahc_freeze_ccb(scbp->ccb); 4956 ahc_done(ahc, scbp); 4957 found++; 4958 } 4959 } 4960 } 4961 ahc_outb(ahc, SCBPTR, active_scb); 4962 return found; 4963} 4964 4965static int 4966ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 4967 int lun, u_int tag) 4968{ 4969 struct scb *scbp; 4970 u_int next; 4971 u_int prev; 4972 u_int count; 4973 u_int active_scb; 4974 4975 count = 0; 4976 next = ahc_inb(ahc, DISCONNECTED_SCBH); 4977 prev = SCB_LIST_NULL; 4978 4979 /* restore this when we're done */ 4980 active_scb = ahc_inb(ahc, SCBPTR); 4981 4982 while (next != SCB_LIST_NULL) { 4983 u_int scb_index; 4984 4985 ahc_outb(ahc, SCBPTR, next); 4986 scb_index = ahc_inb(ahc, SCB_TAG); 4987 if (scb_index >= ahc->scb_data->numscbs) { 4988 panic("Disconnected List inconsistency. " 4989 "SCB index == %d, yet numscbs == %d.", 4990 scb_index, ahc->scb_data->numscbs); 4991 } 4992 scbp = ahc->scb_data->scbarray[scb_index]; 4993 if (ahc_match_scb(scbp, target, channel, lun, tag)) { 4994 next = ahc_rem_scb_from_disc_list(ahc, prev, 4995 next); 4996 count++; 4997 } else { 4998 prev = next; 4999 next = ahc_inb(ahc, SCB_NEXT); 5000 } 5001 } 5002 ahc_outb(ahc, SCBPTR, active_scb); 5003 return (count); 5004} 5005 5006static u_int 5007ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5008{ 5009 u_int next; 5010 5011 ahc_outb(ahc, SCBPTR, scbptr); 5012 next = ahc_inb(ahc, SCB_NEXT); 5013 5014 ahc_outb(ahc, SCB_CONTROL, 0); 5015 5016 ahc_add_curscb_to_free_list(ahc); 5017 5018 if (prev != SCB_LIST_NULL) { 5019 ahc_outb(ahc, SCBPTR, prev); 5020 ahc_outb(ahc, SCB_NEXT, next); 5021 } else 5022 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5023 5024 return next; 5025} 5026 5027static void 5028ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5029{ 5030 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 5031 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5032 5033 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5034 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5035} 5036 5037/* 5038 * Manipulate the waiting for selection list and return the 5039 * scb that follows the one that we remove. 5040 */ 5041static u_int 5042ahc_abort_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5043{ 5044 u_int curscb, next; 5045 5046 /* 5047 * Select the SCB we want to abort and 5048 * pull the next pointer out of it. 5049 */ 5050 curscb = ahc_inb(ahc, SCBPTR); 5051 ahc_outb(ahc, SCBPTR, scbpos); 5052 next = ahc_inb(ahc, SCB_NEXT); 5053 5054 /* Clear the necessary fields */ 5055 ahc_outb(ahc, SCB_CONTROL, 0); 5056 5057 ahc_add_curscb_to_free_list(ahc); 5058 5059 /* update the waiting list */ 5060 if (prev == SCB_LIST_NULL) { 5061 /* First in the list */ 5062 ahc_outb(ahc, WAITING_SCBH, next); 5063 5064 /* 5065 * Ensure we aren't attempting to perform 5066 * selection for this entry. 5067 */ 5068 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5069 } else { 5070 /* 5071 * Select the scb that pointed to us 5072 * and update its next pointer. 5073 */ 5074 ahc_outb(ahc, SCBPTR, prev); 5075 ahc_outb(ahc, SCB_NEXT, next); 5076 } 5077 5078 /* 5079 * Point us back at the original scb position. 5080 */ 5081 ahc_outb(ahc, SCBPTR, curscb); 5082 return next; 5083} 5084 5085static void 5086ahc_clear_intstat(struct ahc_softc *ahc) 5087{ 5088 /* Clear any interrupt conditions this may have caused */ 5089 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 5090 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 5091 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 5092 CLRREQINIT); 5093 ahc_outb(ahc, CLRINT, CLRSCSIINT); 5094} 5095 5096static void 5097ahc_reset_current_bus(struct ahc_softc *ahc) 5098{ 5099 u_int8_t scsiseq; 5100 5101 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5102 scsiseq = ahc_inb(ahc, SCSISEQ); 5103 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5104 DELAY(AHC_BUSRESET_DELAY); 5105 /* Turn off the bus reset */ 5106 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5107 5108 ahc_clear_intstat(ahc); 5109 5110 /* Re-enable reset interrupts */ 5111 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5112} 5113 5114static int 5115ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5116{ 5117 u_int target, max_target; 5118 int found; 5119 u_int8_t sblkctl; 5120 char cur_channel; 5121 struct cam_path *path; 5122 5123 pause_sequencer(ahc); 5124 /* 5125 * Clean up all the state information for the 5126 * pending transactions on this bus. 5127 */ 5128 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 5129 CAM_LUN_WILDCARD, SCB_LIST_NULL, 5130 CAM_SCSI_BUS_RESET); 5131 path = channel == 'B' ? ahc->path_b : ahc->path; 5132 5133 /* Notify the XPT that a bus reset occurred */ 5134 xpt_async(AC_BUS_RESET, path, NULL); 5135 5136 /* 5137 * Revert to async/narrow transfers until we renegotiate. 5138 */ 5139 max_target = (ahc->features & AHC_WIDE) ? 15 : 7; 5140 for (target = 0; target <= max_target; target++) { 5141 struct ahc_devinfo devinfo; 5142 5143 ahc_compile_devinfo(&devinfo, target, CAM_LUN_WILDCARD, 5144 channel, ROLE_UNKNOWN); 5145 ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, 5146 AHC_TRANS_CUR); 5147 ahc_set_syncrate(ahc, &devinfo, path, /*syncrate*/NULL, 5148 /*period*/0, /*offset*/0, AHC_TRANS_CUR); 5149 } 5150 5151 /* 5152 * Reset the bus if we are initiating this reset and 5153 * restart/unpause the sequencer 5154 */ 5155 sblkctl = ahc_inb(ahc, SBLKCTL); 5156 cur_channel = 'A'; 5157 if ((ahc->features & AHC_TWIN) != 0 5158 && ((sblkctl & SELBUSB) != 0)) 5159 cur_channel = 'B'; 5160 if (cur_channel != channel) { 5161 /* Case 1: Command for another bus is active 5162 * Stealthily reset the other bus without 5163 * upsetting the current bus. 5164 */ 5165 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5166 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5167 ahc_outb(ahc, SCSISEQ, 5168 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5169 if (initiate_reset) 5170 ahc_reset_current_bus(ahc); 5171 ahc_clear_intstat(ahc); 5172 ahc_outb(ahc, SBLKCTL, sblkctl); 5173 unpause_sequencer(ahc, /*unpause_always*/FALSE); 5174 } else { 5175 /* Case 2: A command from this bus is active or we're idle */ 5176 ahc_clear_msg_state(ahc); 5177 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 5178 ahc_outb(ahc, SCSISEQ, 5179 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 5180 if (initiate_reset) 5181 ahc_reset_current_bus(ahc); 5182 ahc_clear_intstat(ahc); 5183 restart_sequencer(ahc); 5184 } 5185 return found; 5186} 5187 5188static int 5189ahc_match_scb (struct scb *scb, int target, char channel, int lun, u_int tag) 5190{ 5191 int targ = SCB_TARGET(scb); 5192 char chan = SCB_CHANNEL(scb); 5193 int slun = SCB_LUN(scb); 5194 int match; 5195 5196 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5197 if (match != 0) 5198 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5199 if (match != 0) 5200 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5201 if (match != 0) 5202 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5203 5204 return match; 5205} 5206 5207static void 5208ahc_construct_sdtr(struct ahc_softc *ahc, u_int period, u_int offset) 5209{ 5210 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5211 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 5212 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 5213 ahc->msgout_buf[ahc->msgout_index++] = period; 5214 ahc->msgout_buf[ahc->msgout_index++] = offset; 5215 ahc->msgout_len += 5; 5216} 5217 5218static void 5219ahc_construct_wdtr(struct ahc_softc *ahc, u_int bus_width) 5220{ 5221 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 5222 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 5223 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 5224 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 5225 ahc->msgout_len += 4; 5226} 5227 5228static void 5229ahc_calc_residual(struct scb *scb) 5230{ 5231 struct hardware_scb *hscb; 5232 5233 hscb = scb->hscb; 5234 5235 /* 5236 * If the disconnected flag is still set, this is bogus 5237 * residual information left over from a sequencer 5238 * pagin/pageout, so ignore this case. 5239 */ 5240 if ((scb->hscb->control & DISCONNECTED) == 0) { 5241 u_int32_t resid; 5242 int resid_sgs; 5243 int sg; 5244 5245 /* 5246 * Remainder of the SG where the transfer 5247 * stopped. 5248 */ 5249 resid = (hscb->residual_data_count[2] << 16) 5250 | (hscb->residual_data_count[1] <<8) 5251 | (hscb->residual_data_count[0]); 5252 5253 /* 5254 * Add up the contents of all residual 5255 * SG segments that are after the SG where 5256 * the transfer stopped. 5257 */ 5258 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 5259 sg = scb->sg_count - resid_sgs - 1/*first SG*/; 5260 while (resid_sgs > 0) { 5261 5262 resid += scb->ahc_dma[sg].len; 5263 sg++; 5264 resid_sgs--; 5265 } 5266 if ((scb->flags & SCB_SENSE) == 0) { 5267 5268 scb->ccb->csio.resid = resid; 5269 } else { 5270 5271 scb->ccb->csio.sense_resid = resid; 5272 } 5273 } 5274 5275 /* 5276 * Clean out the residual information in this SCB for its 5277 * next consumer. 5278 */ 5279 hscb->residual_data_count[0] = 0; 5280 hscb->residual_data_count[1] = 0; 5281 hscb->residual_data_count[2] = 0; 5282 hscb->residual_SG_count = 0; 5283 5284#ifdef AHC_DEBUG 5285 if (ahc_debug & AHC_SHOWMISC) { 5286 sc_print_addr(xs->sc_link); 5287 printf("Handled Residual of %ld bytes\n" ,xs->resid); 5288 } 5289#endif 5290} 5291 5292static void 5293ahc_update_pending_syncrates(struct ahc_softc *ahc) 5294{ 5295 /* 5296 * Traverse the pending SCB list and ensure that all of the 5297 * SCBs there have the proper settings. 5298 */ 5299 struct ccb_hdr *ccbh; 5300 int pending_ccb_count; 5301 int i; 5302 u_int saved_scbptr; 5303 5304 /* 5305 * We were able to complete the command successfully, 5306 * so reinstate the timeouts for all other pending 5307 * commands. 5308 */ 5309 ccbh = LIST_FIRST(&ahc->pending_ccbs); 5310 pending_ccb_count = 0; 5311 while (ccbh != NULL) { 5312 struct scb *pending_scb; 5313 struct hardware_scb *pending_hscb; 5314 struct ahc_target_tinfo *tinfo; 5315 struct ahc_devinfo devinfo; 5316 5317 pending_scb = (struct scb *)ccbh->ccb_scb_ptr; 5318 pending_hscb = pending_scb->hscb; 5319 ahc_compile_devinfo(&devinfo, SCB_TARGET(pending_scb), 5320 SCB_LUN(pending_scb), 5321 SCB_CHANNEL(pending_scb), 5322 ROLE_UNKNOWN); 5323 tinfo = &ahc->transinfo[devinfo.target_offset]; 5324 pending_hscb->control &= ~ULTRAENB; 5325 if ((ahc->ultraenb & devinfo.target_mask) != 0) 5326 pending_hscb->control |= ULTRAENB; 5327 pending_hscb->scsirate = tinfo->scsirate; 5328 pending_hscb->scsioffset = tinfo->current.offset; 5329 pending_ccb_count++; 5330 ccbh = LIST_NEXT(ccbh, sim_links.le); 5331 } 5332 5333 if (pending_ccb_count == 0) 5334 return; 5335 5336 saved_scbptr = ahc_inb(ahc, SCBPTR); 5337 /* Ensure that the hscbs down on the card match the new information */ 5338 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5339 u_int scb_tag; 5340 5341 ahc_outb(ahc, SCBPTR, i); 5342 scb_tag = ahc_inb(ahc, SCB_TAG); 5343 if (scb_tag != SCB_LIST_NULL) { 5344 struct scb *pending_scb; 5345 struct hardware_scb *pending_hscb; 5346 struct ahc_target_tinfo *tinfo; 5347 struct ahc_devinfo devinfo; 5348 u_int control; 5349 5350 pending_scb = ahc->scb_data->scbarray[scb_tag]; 5351 pending_hscb = pending_scb->hscb; 5352 ahc_compile_devinfo(&devinfo, SCB_TARGET(pending_scb), 5353 SCB_LUN(pending_scb), 5354 SCB_CHANNEL(pending_scb), 5355 ROLE_UNKNOWN); 5356 tinfo = &ahc->transinfo[devinfo.target_offset]; 5357 control = ahc_inb(ahc, SCB_CONTROL); 5358 control &= ~ULTRAENB; 5359 if ((ahc->ultraenb & devinfo.target_mask) != 0) 5360 control |= ULTRAENB; 5361 ahc_outb(ahc, SCB_CONTROL, control); 5362 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 5363 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 5364 } 5365 } 5366 ahc_outb(ahc, SCBPTR, saved_scbptr); 5367} 5368 5369static void 5370ahc_dump_targcmd(struct target_cmd *cmd) 5371{ 5372 u_int8_t *byte; 5373 u_int8_t *last_byte; 5374 int i; 5375 5376 byte = &cmd->initiator_channel; 5377 /* Debugging info for received commands */ 5378 last_byte = &cmd[1].initiator_channel; 5379 5380 i = 0; 5381 while (byte < last_byte) { 5382 if (i == 0) 5383 printf("\t"); 5384 printf("%#x", *byte++); 5385 i++; 5386 if (i == 8) { 5387 printf("\n"); 5388 i = 0; 5389 } else { 5390 printf(", "); 5391 } 5392 } 5393} 5394 5395static void 5396ahc_shutdown(int howto, void *arg) 5397{ 5398 struct ahc_softc *ahc; 5399 int i; 5400 5401 ahc = (struct ahc_softc *)arg; 5402 5403 ahc_reset(ahc); 5404 ahc_outb(ahc, SCSISEQ, 0); 5405 ahc_outb(ahc, SXFRCTL0, 0); 5406 ahc_outb(ahc, DSPCISTATUS, 0); 5407 5408 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 5409 ahc_outb(ahc, i, 0); 5410} 5411