aic7xxx.c revision 39220
1/* 2 * Generic driver for the aic7xxx based adaptec SCSI controllers 3 * Product specific probe and attach routines can be found in: 4 * i386/eisa/ahc_eisa.c 27/284X and aic7770 motherboard controllers 5 * pci/ahc_pci.c 3985, 3980, 3940, 2940, aic7895, aic7890, 6 * aic7880, aic7870, aic7860, and aic7850 controllers 7 * 8 * Copyright (c) 1994, 1995, 1996, 1997, 1998 Justin T. Gibbs. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification, immediately at the beginning of the file. 17 * 2. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * Where this Software is combined with software released under the terms of 21 * the GNU Public License ("GPL") and the terms of the GPL would require the 22 * combined work to also be released under the terms of the GPL, the terms 23 * and conditions of this License will apply in addition to those of the 24 * GPL with the exception of any terms or conditions of this License that 25 * conflict with, or are expressly prohibited by, the GPL. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 31 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * $Id: aic7xxx.c,v 1.113 1997/04/05 21:41:13 gibbs Exp $ 40 */ 41/* 42 * A few notes on features of the driver. 43 * 44 * SCB paging takes advantage of the fact that devices stay disconnected 45 * from the bus a relatively long time and that while they're disconnected, 46 * having the SCBs for these transactions down on the host adapter is of 47 * little use. Instead of leaving this idle SCB down on the card we copy 48 * it back up into kernel memory and reuse the SCB slot on the card to 49 * schedule another transaction. This can be a real payoff when doing random 50 * I/O to tagged queueing devices since there are more transactions active at 51 * once for the device to sort for optimal seek reduction. The algorithm goes 52 * like this... 53 * 54 * The sequencer maintains two lists of its hardware SCBs. The first is the 55 * singly linked free list which tracks all SCBs that are not currently in 56 * use. The second is the doubly linked disconnected list which holds the 57 * SCBs of transactions that are in the disconnected state sorted most 58 * recently disconnected first. When the kernel queues a transaction to 59 * the card, a hardware SCB to "house" this transaction is retrieved from 60 * either of these two lists. If the SCB came from the disconnected list, 61 * a check is made to see if any data transfer or SCB linking (more on linking 62 * in a bit) information has been changed since it was copied from the host 63 * and if so, DMAs the SCB back up before it can be used. Once a hardware 64 * SCB has been obtained, the SCB is DMAed from the host. Before any work 65 * can begin on this SCB, the sequencer must ensure that either the SCB is 66 * for a tagged transaction or the target is not already working on another 67 * non-tagged transaction. If a conflict arises in the non-tagged case, the 68 * sequencer finds the SCB for the active transactions and sets the SCB_LINKED 69 * field in that SCB to this next SCB to execute. To facilitate finding 70 * active non-tagged SCBs, the last four bytes of up to the first four hardware 71 * SCBs serve as a storage area for the currently active SCB ID for each 72 * target. 73 * 74 * When a device reconnects, a search is made of the hardware SCBs to find 75 * the SCB for this transaction. If the search fails, a hardware SCB is 76 * pulled from either the free or disconnected SCB list and the proper 77 * SCB is DMAed from the host. If the MK_MESSAGE control bit is set 78 * in the control byte of the SCB while it was disconnected, the sequencer 79 * will assert ATN and attempt to issue a message to the host. 80 * 81 * When a command completes, a check for non-zero status and residuals is 82 * made. If either of these conditions exists, the SCB is DMAed back up to 83 * the host so that it can interpret this information. Additionally, in the 84 * case of bad status, the sequencer generates a special interrupt and pauses 85 * itself. This allows the host to setup a request sense command if it 86 * chooses for this target synchronously with the error so that sense 87 * information isn't lost. 88 * 89 */ 90 91#include <opt_aic7xxx.h> 92 93#include <pci.h> 94#include <stddef.h> /* For offsetof */ 95 96#include <sys/param.h> 97#include <sys/systm.h> 98#include <sys/malloc.h> 99#include <sys/buf.h> 100#include <sys/proc.h> 101 102#include <cam/cam.h> 103#include <cam/cam_ccb.h> 104#include <cam/cam_sim.h> 105#include <cam/cam_xpt_sim.h> 106#include <cam/cam_debug.h> 107 108#include <cam/scsi/scsi_all.h> 109#include <cam/scsi/scsi_message.h> 110 111#if NPCI > 0 112#include <machine/bus_memio.h> 113#endif 114#include <machine/bus_pio.h> 115#include <machine/bus.h> 116#include <machine/clock.h> 117 118#include <vm/vm.h> 119#include <vm/vm_param.h> 120#include <vm/pmap.h> 121 122#include <dev/aic7xxx/aic7xxx.h> 123#include <dev/aic7xxx/sequencer.h> 124 125#include <aic7xxx_reg.h> 126#include <aic7xxx_seq.h> 127 128#include <sys/kernel.h> 129 130#ifndef AHC_TMODE_ENABLE 131#define AHC_TMODE_ENABLE 0 132#endif 133 134#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 135#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 136#define ALL_TARGETS (~0) 137#define ALL_LUNS (~0) 138#define ALL_CHANNELS '\0' 139 140#define SIM_IS_SCSIBUS_B(ahc, sim) \ 141 (sim == ahc->sim_b) 142#define SCB_IS_SCSIBUS_B(scb) \ 143 (((scb)->hscb->tcl & SELBUSB) != 0) 144#define SCB_TARGET(scb) \ 145 (((scb)->hscb->tcl & TID) >> 4) 146#define SCB_CHANNEL(scb) \ 147 (SCB_IS_SCSIBUS_B(scb) ? 'B' : 'A') 148#define SCB_LUN(scb) \ 149 ((scb)->hscb->tcl & LID) 150#define SCB_TARGET_OFFSET(scb) \ 151 (SCB_TARGET(scb) + (SCB_IS_SCSIBUS_B(scb) ? 8 : 0)) 152#define SCB_TARGET_MASK(scb) \ 153 (0x01 << (SCB_TARGET_OFFSET(scb))) 154 155#define ccb_scb_ptr spriv_ptr0 156#define ccb_ahc_ptr spriv_ptr1 157 158struct ahc_devinfo { 159 int target_offset; 160 u_int16_t target_mask; 161 u_int8_t target; 162 char channel; 163}; 164 165typedef enum { 166 SEARCH_COMPLETE, 167 SEARCH_COUNT, 168 SEARCH_REMOVE 169} ahc_search_action; 170 171u_long ahc_unit = 0; 172 173#ifdef AHC_DEBUG 174static int ahc_debug = AHC_DEBUG; 175#endif 176 177#if NPCI > 0 178void ahc_pci_intr(struct ahc_softc *ahc); 179#endif 180 181static void ahc_dump_targcmd(struct target_cmd *cmd); 182static void ahc_shutdown(int howto, void *arg); 183static void ahcminphys(struct buf *bp); 184static cam_status 185 ahc_find_tmode_devs(struct ahc_softc *ahc, 186 struct cam_sim *sim, union ccb *ccb, 187 struct tmode_tstate **tstate, 188 struct tmode_lstate **lstate, 189 int notfound_failure); 190static void ahc_action(struct cam_sim *sim, union ccb *ccb); 191static void ahc_async(void *callback_arg, u_int32_t code, 192 struct cam_path *path, void *arg); 193static void ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, 194 int nsegments, int error); 195static void ahc_poll(struct cam_sim *sim); 196static void ahc_setup_data(struct ahc_softc *ahc, 197 struct ccb_scsiio *csio, struct scb *scb); 198static void ahc_freeze_devq(struct ahc_softc *ahc, struct cam_path *path); 199static struct scb * 200 ahc_get_scb(struct ahc_softc *ahc); 201static void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb); 202static struct scb * 203 ahc_alloc_scb(struct ahc_softc *ahc); 204static void ahc_fetch_devinfo(struct ahc_softc *ahc, 205 struct ahc_devinfo *devinfo); 206static void ahc_compile_devinfo(struct ahc_devinfo *devinfo, 207 u_int target, char channel); 208static u_int8_t ahc_abort_wscb(struct ahc_softc *ahc, u_int8_t scbpos, 209 u_int8_t prev); 210static void ahc_done(struct ahc_softc *ahc, struct scb *scbp); 211static void ahc_handle_target_cmd(struct ahc_softc *ahc); 212static void ahc_handle_seqint(struct ahc_softc *ahc, u_int8_t intstat); 213static void ahc_handle_scsiint(struct ahc_softc *ahc, 214 u_int8_t intstat); 215static void ahc_handle_reqinit(struct ahc_softc *ahc, 216 struct scb *scb); 217static int ahc_parse_msg(struct ahc_softc *ahc, struct scb *scb, 218 struct ahc_devinfo *devinfo); 219static void ahc_handle_devreset(struct ahc_softc *ahc, int target, 220 char channel, cam_status status, 221 ac_code acode, char *message, 222 int verbose_only); 223static void ahc_loadseq(struct ahc_softc *ahc); 224static int ahc_check_patch(struct ahc_softc *ahc, 225 struct patch **start_patch, 226 int start_instr, int *skip_addr); 227static void ahc_download_instr(struct ahc_softc *ahc, 228 int instrptr, u_int8_t *dconsts); 229static int ahc_match_scb(struct scb *scb, int target, char channel, 230 int lun, u_int8_t tag); 231#ifdef AHC_DEBUG 232static void ahc_print_scb(struct scb *scb); 233#endif 234static u_int8_t ahc_find_scb(struct ahc_softc *ahc, struct scb *scb); 235static int ahc_search_qinfifo(struct ahc_softc *ahc, int target, 236 char channel, int lun, u_int8_t tag, 237 u_int32_t status, ahc_search_action action); 238static int ahc_reset_channel(struct ahc_softc *ahc, char channel, 239 int initiate_reset); 240static int ahc_abort_scbs(struct ahc_softc *ahc, int target, 241 char channel, int lun, u_int8_t tag, 242 u_int32_t status); 243static u_int8_t ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 244 u_int8_t prev, u_int8_t scbptr); 245static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 246static void ahc_clear_intstat(struct ahc_softc *ahc); 247static void ahc_reset_current_bus(struct ahc_softc *ahc); 248static struct ahc_syncrate * 249 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 250 u_int maxsync); 251static u_int ahc_find_period(struct ahc_softc *ahc, u_int scsirate, 252 u_int maxsync); 253static void ahc_validate_offset(struct ahc_softc *ahc, 254 struct ahc_syncrate *syncrate, 255 u_int *offset, int wide); 256static void ahc_set_syncrate(struct ahc_softc *ahc, 257 struct ahc_devinfo *devinfo, 258 struct cam_path *path, 259 struct ahc_syncrate *syncrate, 260 u_int period, u_int offset, u_int type); 261static void ahc_set_width(struct ahc_softc *ahc, 262 struct ahc_devinfo *devinfo, 263 struct cam_path *path, u_int width, u_int type); 264static void ahc_construct_sdtr(struct ahc_softc *ahc, 265 u_int8_t period, u_int8_t offset); 266 267static void ahc_construct_wdtr(struct ahc_softc *ahc, 268 u_int8_t bus_width); 269 270static void ahc_calc_residual(struct scb *scb); 271 272static void ahc_update_pending_syncrates(struct ahc_softc *ahc); 273 274static void ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb); 275 276static timeout_t 277 ahc_timeout; 278static __inline void pause_sequencer(struct ahc_softc *ahc); 279static __inline void unpause_sequencer(struct ahc_softc *ahc, 280 int unpause_always); 281static __inline void restart_sequencer(struct ahc_softc *ahc); 282static __inline u_int8_t ahc_index_busy_tcl(struct ahc_softc *ahc, 283 u_int8_t tcl, int unbusy); 284 285static __inline void ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb); 286 287static __inline void ahc_freeze_ccb(union ccb* ccb); 288static __inline cam_status ahc_ccb_status(union ccb* ccb); 289static __inline void ahc_set_ccb_status(union ccb* ccb, 290 cam_status status); 291 292static __inline u_int32_t 293ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 294{ 295 return (ahc->hscb_busaddr + (sizeof(struct hardware_scb) * index)); 296} 297 298#define AHC_BUSRESET_DELAY 25 /* Reset delay in us */ 299 300static __inline void 301pause_sequencer(struct ahc_softc *ahc) 302{ 303 ahc_outb(ahc, HCNTRL, ahc->pause); 304 305 /* 306 * Since the sequencer can disable pausing in a critical section, we 307 * must loop until it actually stops. 308 */ 309 while ((ahc_inb(ahc, HCNTRL) & PAUSE) == 0) 310 ; 311} 312 313static __inline void 314unpause_sequencer(struct ahc_softc *ahc, int unpause_always) 315{ 316 if ((ahc->flags & AHC_HANDLING_REQINITS) == 0 317 && (unpause_always 318 || (ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)) 319 ahc_outb(ahc, HCNTRL, ahc->unpause); 320} 321 322/* 323 * Restart the sequencer program from address zero 324 */ 325static __inline void 326restart_sequencer(struct ahc_softc *ahc) 327{ 328 pause_sequencer(ahc); 329 ahc_outb(ahc, SEQCTL, FASTMODE|SEQRESET); 330 unpause_sequencer(ahc, /*unpause_always*/TRUE); 331} 332 333static __inline u_int8_t 334ahc_index_busy_tcl(struct ahc_softc *ahc, u_int8_t tcl, int unbusy) 335{ 336 u_int8_t scbid; 337 338 scbid = ahc->untagged_scbs[tcl]; 339 if (unbusy) 340 ahc->untagged_scbs[tcl] = SCB_LIST_NULL; 341 342 return (scbid); 343} 344 345static __inline void 346ahc_busy_tcl(struct ahc_softc *ahc, struct scb *scb) 347{ 348 ahc->untagged_scbs[scb->hscb->tcl] = scb->hscb->tag; 349} 350 351static __inline void 352ahc_freeze_ccb(union ccb* ccb) 353{ 354 if ((ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) { 355 ccb->ccb_h.status |= CAM_DEV_QFRZN; 356 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 357 } 358} 359 360static __inline cam_status 361ahc_ccb_status(union ccb* ccb) 362{ 363 return (ccb->ccb_h.status & CAM_STATUS_MASK); 364} 365 366static __inline void 367ahc_set_ccb_status(union ccb* ccb, cam_status status) 368{ 369 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 370 ccb->ccb_h.status |= status; 371} 372 373char * 374ahc_name(struct ahc_softc *ahc) 375{ 376 static char name[10]; 377 378 sprintf(name, "ahc%d", ahc->unit); 379 return (name); 380} 381 382#ifdef AHC_DEBUG 383static void 384ahc_print_scb(struct scb *scb) 385{ 386 struct hardware_scb *hscb = scb->hscb; 387 388 printf("scb:%p control:0x%x tcl:0x%x cmdlen:%d cmdpointer:0x%lx\n", 389 scb, 390 hscb->control, 391 hscb->tcl, 392 hscb->cmdlen, 393 hscb->cmdpointer ); 394 printf(" datlen:%d data:0x%lx segs:0x%x segp:0x%lx\n", 395 hscb->datalen, 396 hscb->data, 397 hscb->SG_count, 398 hscb->SG_pointer); 399 printf(" sg_addr:%lx sg_len:%ld\n", 400 scb->ahc_dma[0].addr, 401 scb->ahc_dma[0].len); 402 printf(" cdb:%x %x %x %x %x %x %x %x %x %x %x %x\n", 403 hscb->cmdstore[0], hscb->cmdstore[1], hscb->cmdstore[2], 404 hscb->cmdstore[3], hscb->cmdstore[4], hscb->cmdstore[5], 405 hscb->cmdstore[6], hscb->cmdstore[7], hscb->cmdstore[8], 406 hscb->cmdstore[9], hscb->cmdstore[10], hscb->cmdstore[11]); 407} 408#endif 409 410static struct { 411 u_int8_t errno; 412 char *errmesg; 413} hard_error[] = { 414 { ILLHADDR, "Illegal Host Access" }, 415 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 416 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 417 { SQPARERR, "Sequencer Parity Error" }, 418 { DPARERR, "Data-path Parity Error" }, 419 { MPARERR, "Scratch or SCB Memory Parity Error" }, 420 { PCIERRSTAT, "PCI Error detected" }, 421 { CIOPARERR, "CIOBUS Parity Error" }, 422}; 423 424 425/* 426 * Valid SCSIRATE values. (p. 3-17) 427 * Provides a mapping of tranfer periods in ns to the proper value to 428 * stick in the scsiscfr reg to use that transfer rate. 429 */ 430#define AHC_SYNCRATE_ULTRA2 0 431#define AHC_SYNCRATE_ULTRA 2 432#define AHC_SYNCRATE_FAST 5 433static struct ahc_syncrate ahc_syncrates[] = { 434 /* ultra2 fast/ultra period rate */ 435 { 0x13, 0x000, 10, "40.0" }, 436 { 0x14, 0x000, 11, "33.0" }, 437 { 0x15, 0x100, 12, "20.0" }, 438 { 0x16, 0x110, 15, "16.0" }, 439 { 0x17, 0x120, 18, "13.4" }, 440 { 0x18, 0x000, 25, "10.0" }, 441 { 0x19, 0x010, 31, "8.0" }, 442 { 0x1a, 0x020, 37, "6.67" }, 443 { 0x1b, 0x030, 43, "5.7" }, 444 { 0x10, 0x040, 50, "5.0" }, 445 { 0x00, 0x050, 56, "4.4" }, 446 { 0x00, 0x060, 62, "4.0" }, 447 { 0x00, 0x070, 68, "3.6" }, 448 { 0x00, 0x000, 0, NULL } 449}; 450 451/* 452 * Allocate a controller structure for a new device and initialize it. 453 */ 454struct ahc_softc * 455ahc_alloc(int unit, u_int32_t iobase, vm_offset_t maddr, ahc_chip chip, 456 ahc_feature features, ahc_flag flags, struct scb_data *scb_data) 457{ 458 /* 459 * find unit and check we have that many defined 460 */ 461 struct ahc_softc *ahc; 462 size_t alloc_size; 463 464 /* 465 * Allocate a storage area for us 466 */ 467 if (scb_data == NULL) 468 /* 469 * We are not sharing SCB space with another controller 470 * so allocate our own SCB data space. 471 */ 472 alloc_size = sizeof(struct full_ahc_softc); 473 else 474 alloc_size = sizeof(struct ahc_softc); 475 ahc = malloc(alloc_size, M_DEVBUF, M_NOWAIT); 476 if (!ahc) { 477 printf("ahc%d: cannot malloc!\n", unit); 478 return NULL; 479 } 480 bzero(ahc, alloc_size); 481 if (scb_data == NULL) { 482 struct full_ahc_softc* full_softc = (struct full_ahc_softc*)ahc; 483 ahc->scb_data = &full_softc->scb_data_storage; 484 STAILQ_INIT(&ahc->scb_data->free_scbs); 485 } else 486 ahc->scb_data = scb_data; 487 LIST_INIT(&ahc->pending_ccbs); 488 ahc->unit = unit; 489 490 /* 491 * XXX This should be done by the bus specific probe stubs with 492 * the bus layer providing the bsh and tag. Unfortunately, 493 * we need to clean up how we configure things before this 494 * can happen. 495 */ 496 if (maddr != NULL) { 497 ahc->tag = I386_BUS_SPACE_MEM; 498 ahc->bsh = (bus_space_handle_t)maddr; 499 } else { 500 ahc->tag = I386_BUS_SPACE_IO; 501 ahc->bsh = (bus_space_handle_t)iobase; 502 } 503 ahc->chip = chip; 504 ahc->features = features; 505 ahc->flags = flags; 506 ahc->unpause = (ahc_inb(ahc, HCNTRL) & IRQMS) | INTEN; 507 ahc->pause = ahc->unpause | PAUSE; 508 509 return (ahc); 510} 511 512void 513ahc_free(ahc) 514 struct ahc_softc *ahc; 515{ 516 free(ahc, M_DEVBUF); 517 return; 518} 519 520int 521ahc_reset(struct ahc_softc *ahc) 522{ 523 u_int8_t hcntrl; 524 u_int8_t sblkctl; 525 int wait; 526 527 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 528 /* 529 * Ensure that the reset has finished 530 */ 531 wait = 1000; 532 while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)) 533 DELAY(1000); 534 if (wait == 0) { 535 printf("%s: WARNING - Failed chip reset! " 536 "Trying to initialize anyway.\n", ahc_name(ahc)); 537 } 538 ahc_outb(ahc, HCNTRL, ahc->pause); 539 540 /* Determine channel configuration */ 541 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 542 /* No Twin Channel PCI cards */ 543 if ((ahc->chip & AHC_PCI) != 0) 544 sblkctl &= ~SELBUSB; 545 switch (sblkctl) { 546 case 0: 547 /* Single Narrow Channel */ 548 break; 549 case 2: 550 /* Wide Channel */ 551 ahc->features |= AHC_WIDE; 552 break; 553 case 8: 554 /* Twin Channel */ 555 ahc->features |= AHC_TWIN; 556 break; 557 default: 558 printf(" Unsupported adapter type. Ignoring\n"); 559 return(-1); 560 } 561 return (0); 562} 563 564/* 565 * Look up the valid period to SCSIRATE conversion in our table. 566 * Return the period and offset that should be sent to the target 567 * if this was the beginning of an SDTR. 568 */ 569static struct ahc_syncrate * 570ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, u_int maxsync) 571{ 572 struct ahc_syncrate *syncrate; 573 574 syncrate = &ahc_syncrates[maxsync]; 575 while ((syncrate->rate != NULL) 576 && ((ahc->features & AHC_ULTRA2) == 0 577 || (syncrate->sxfr_ultra2 != 0))) { 578 579 if (*period <= syncrate->period) { 580 /* 581 * When responding to a target that requests 582 * sync, the requested rate may fall between 583 * two rates that we can output, but still be 584 * a rate that we can receive. Because of this, 585 * we want to respond to the target with 586 * the same rate that it sent to us even 587 * if the period we use to send data to it 588 * is lower. Only lower the response period 589 * if we must. 590 */ 591 if (syncrate == &ahc_syncrates[maxsync]) { 592 *period = syncrate->period; 593 } 594 break; 595 } 596 syncrate++; 597 } 598 599 if ((*period == 0) 600 || (syncrate->rate == NULL) 601 || ((ahc->features & AHC_ULTRA2) != 0 602 && (syncrate->sxfr_ultra2 == 0))) { 603 /* Use asynchronous transfers. */ 604 *period = 0; 605 syncrate = NULL; 606 } 607 return (syncrate); 608} 609 610static u_int 611ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 612{ 613 struct ahc_syncrate *syncrate; 614 615 if ((ahc->features & AHC_ULTRA2) != 0) { 616 scsirate &= SXFR_ULTRA2; 617 } else { 618 scsirate &= SXFR; 619 } 620 621 syncrate = &ahc_syncrates[maxsync]; 622 while (syncrate->rate != NULL) { 623 624 if ((ahc->features & AHC_ULTRA2) != 0) { 625 if (syncrate->sxfr_ultra2 == 0) 626 break; 627 else if (scsirate == syncrate->sxfr_ultra2) 628 return (syncrate->period); 629 } else if (scsirate == (syncrate->sxfr & ~ULTRA_SXFR)) { 630 return (syncrate->period); 631 } 632 syncrate++; 633 } 634 return (0); /* async */ 635} 636 637static void 638ahc_validate_offset(struct ahc_softc *ahc, struct ahc_syncrate *syncrate, 639 u_int *offset, int wide) 640{ 641 u_int maxoffset; 642 643 /* Limit offset to what we can do */ 644 if (syncrate == NULL) { 645 maxoffset = 0; 646 } else if ((ahc->features & AHC_ULTRA2) != 0) { 647 maxoffset = MAX_OFFSET_ULTRA2; 648 } else { 649 if (wide) 650 maxoffset = MAX_OFFSET_16BIT; 651 else 652 maxoffset = MAX_OFFSET_8BIT; 653 } 654 *offset = MIN(*offset, maxoffset); 655} 656 657static void 658ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 659 struct cam_path *path, struct ahc_syncrate *syncrate, 660 u_int period, u_int offset, u_int type) 661{ 662 u_int old_period; 663 u_int old_offset; 664 665 if (syncrate == NULL) { 666 period = 0; 667 offset = 0; 668 } 669 670 old_period = ahc->transinfo[devinfo->target_offset].current.period; 671 old_offset = ahc->transinfo[devinfo->target_offset].current.offset; 672 673 if ((type & AHC_TRANS_CUR) != 0 674 && (old_period != period || old_offset != offset)) { 675 struct ccb_trans_settings neg; 676 u_int scsirate; 677 678 scsirate = ahc->transinfo[devinfo->target_offset].scsirate; 679 if ((ahc->features & AHC_ULTRA2) != 0) { 680 681 scsirate &= ~SXFR_ULTRA2; 682 683 if (syncrate != NULL) { 684 scsirate |= syncrate->sxfr_ultra2; 685 } 686 687 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) { 688 ahc_outb(ahc, SCSIOFFSET, offset); 689 } 690 ahc_outb(ahc, TARG_OFFSET + devinfo->target_offset, 691 offset); 692 } else { 693 694 scsirate &= ~(SXFR|SOFS); 695 /* 696 * Ensure Ultra mode is set properly for 697 * this target. 698 */ 699 ahc->ultraenb &= ~devinfo->target_mask; 700 if (syncrate != NULL) { 701 if (syncrate->sxfr & ULTRA_SXFR) { 702 ahc->ultraenb |= devinfo->target_mask; 703 } 704 scsirate |= syncrate->sxfr & SXFR; 705 scsirate |= offset & SOFS; 706 } 707 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) { 708 u_int8_t sxfrctl0; 709 710 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 711 sxfrctl0 &= ~FAST20; 712 if (ahc->ultraenb & devinfo->target_mask) 713 sxfrctl0 |= FAST20; 714 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 715 } 716 } 717 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) 718 ahc_outb(ahc, SCSIRATE, scsirate); 719 720 ahc->transinfo[devinfo->target_offset].scsirate = scsirate; 721 ahc->transinfo[devinfo->target_offset].current.period = period; 722 ahc->transinfo[devinfo->target_offset].current.offset = offset; 723 724 /* Update the syncrates in any pending scbs */ 725 ahc_update_pending_syncrates(ahc); 726 727 /* 728 * Tell the SCSI layer about the 729 * new transfer parameters. 730 */ 731 neg.sync_period = period; 732 neg.sync_offset = offset; 733 neg.valid = CCB_TRANS_SYNC_RATE_VALID 734 | CCB_TRANS_SYNC_OFFSET_VALID; 735 xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1); 736 xpt_async(AC_TRANSFER_NEG, path, &neg); 737 if (bootverbose) { 738 if (neg.sync_offset != 0) { 739 printf("%s: target %d synchronous at %sMHz, " 740 "offset = 0x%x\n", ahc_name(ahc), 741 devinfo->target, syncrate->rate, offset); 742 } else { 743 printf("%s: target %d using " 744 "asynchronous transfers\n", 745 ahc_name(ahc), devinfo->target); 746 } 747 } 748 } 749 750 if ((type & AHC_TRANS_GOAL) != 0) { 751 ahc->transinfo[devinfo->target_offset].goal.period = period; 752 ahc->transinfo[devinfo->target_offset].goal.offset = offset; 753 } 754 755 if ((type & AHC_TRANS_USER) != 0) { 756 ahc->transinfo[devinfo->target_offset].user.period = period; 757 ahc->transinfo[devinfo->target_offset].user.offset = offset; 758 } 759} 760 761static void 762ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 763 struct cam_path *path, u_int width, u_int type) 764{ 765 u_int oldwidth; 766 767 oldwidth = ahc->transinfo[devinfo->target_offset].current.width; 768 769 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 770 struct ccb_trans_settings neg; 771 u_int8_t scsirate; 772 773 scsirate = ahc->transinfo[devinfo->target_offset].scsirate; 774 scsirate &= ~WIDEXFER; 775 if (width == MSG_EXT_WDTR_BUS_16_BIT) 776 scsirate |= WIDEXFER; 777 778 ahc->transinfo[devinfo->target_offset].scsirate = scsirate; 779 780 if ((type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE) 781 ahc_outb(ahc, SCSIRATE, scsirate); 782 783 ahc->transinfo[devinfo->target_offset].current.width = width; 784 785 /* Tell the SCSI layer about the new transfer params */ 786 neg.bus_width = width; 787 neg.valid = CCB_TRANS_BUS_WIDTH_VALID; 788 xpt_setup_ccb(&neg.ccb_h, path, /*priority*/1); 789 xpt_async(AC_TRANSFER_NEG, path, &neg); 790 if (bootverbose) { 791 printf("%s: target %d using %dbit transfers\n", 792 ahc_name(ahc), devinfo->target, 793 8 * (0x01 << neg.bus_width)); 794 } 795 } 796 if ((type & AHC_TRANS_GOAL) != 0) { 797 ahc->transinfo[devinfo->target_offset].goal.width = width; 798 } 799 if ((type & AHC_TRANS_USER) != 0) { 800 ahc->transinfo[devinfo->target_offset].user.width = width; 801 } 802} 803 804/* 805 * Attach all the sub-devices we can find 806 */ 807int 808ahc_attach(struct ahc_softc *ahc) 809{ 810 struct ccb_setasync csa; 811 struct cam_devq *devq; 812 int bus_id; 813 814 /* 815 * Create the device queue for our SIM. 816 */ 817 devq = cam_simq_alloc(ahc->scb_data->maxscbs); 818 if (devq == NULL) 819 return (0); 820 821 /* 822 * Construct our SIM entry 823 */ 824 ahc->sim = cam_sim_alloc(ahc_action, ahc_poll, "ahc", ahc, ahc->unit, 825 1, ahc->scb_data->maxscbs, devq); 826 if (ahc->sim == NULL) { 827 cam_simq_free(devq); 828 return (0); 829 } 830 bus_id = (ahc->flags & AHC_CHANNEL_B_PRIMARY) ? 1 : 0; 831 832 if (xpt_bus_register(ahc->sim, bus_id) != CAM_SUCCESS) { 833 cam_sim_free(ahc->sim, /*free_devq*/TRUE); 834 return (0); 835 } 836 837 if (xpt_create_path(&ahc->path, /*periph*/NULL, 838 cam_sim_path(ahc->sim), CAM_TARGET_WILDCARD, 839 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 840 xpt_bus_deregister(cam_sim_path(ahc->sim)); 841 cam_sim_free(ahc->sim, /*free_devq*/TRUE); 842 return (0); 843 } 844 845 xpt_setup_ccb(&csa.ccb_h, ahc->path, /*priority*/5); 846 csa.ccb_h.func_code = XPT_SASYNC_CB; 847 csa.event_enable = AC_LOST_DEVICE; 848 csa.callback = ahc_async; 849 csa.callback_arg = ahc->sim; 850 xpt_action((union ccb *)&csa); 851 852 if (ahc->features & AHC_TWIN) { 853 ahc->sim_b = cam_sim_alloc(ahc_action, ahc_poll, "ahc", 854 ahc, ahc->unit, 1, 855 ahc->scb_data->maxscbs, devq); 856 857 if (ahc->sim_b == NULL) { 858 printf("ahc_attach: Unable to attach second " 859 "bus due to resource shortage"); 860 /* 861 * Must return success or the first bus 862 * won't get attached either. 863 */ 864 return (1); 865 } 866 867 bus_id = (ahc->flags & AHC_CHANNEL_B_PRIMARY) ? 0 : 1; 868 if (xpt_bus_register(ahc->sim_b, bus_id) != CAM_SUCCESS) { 869 printf("ahc_attach: Unable to attach second " 870 "bus due to resource shortage"); 871 /* 872 * We do not want to destroy the device queue 873 * because the first bus is using it. 874 */ 875 cam_sim_free(ahc->sim_b, /*free_devq*/FALSE); 876 ahc->sim_b = NULL; 877 return (1); 878 } 879 880 if (xpt_create_path(&ahc->path_b, /*periph*/NULL, 881 cam_sim_path(ahc->sim_b), 882 CAM_TARGET_WILDCARD, 883 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 884 xpt_bus_deregister(cam_sim_path(ahc->sim_b)); 885 cam_sim_free(ahc->sim_b, /*free_devq*/FALSE); 886 ahc->sim_b = NULL; 887 return (1); 888 } 889 xpt_setup_ccb(&csa.ccb_h, ahc->path_b, /*priority*/5); 890 csa.ccb_h.func_code = XPT_SASYNC_CB; 891 csa.event_enable = AC_LOST_DEVICE; 892 csa.callback = ahc_async; 893 csa.callback_arg = ahc->sim_b; 894 xpt_action((union ccb *)&csa); 895 } 896 return (1); 897} 898 899static void 900ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 901{ 902 u_int8_t saved_tcl; 903 904 saved_tcl = ahc_inb(ahc, SAVED_TCL); 905 ahc_compile_devinfo(devinfo, (saved_tcl >> 4) & 0x0f, 906 (saved_tcl & SELBUSB) ? 'B': 'A'); 907} 908 909static void 910ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int target, char channel) 911{ 912 devinfo->target = target; 913 devinfo->target_offset = target; 914 devinfo->channel = channel; 915 if (channel == 'B') 916 devinfo->target_offset += 8; 917 devinfo->target_mask = (0x01 << devinfo->target_offset); 918} 919 920/* 921 * Catch an interrupt from the adapter 922 */ 923void 924ahc_intr(void *arg) 925{ 926 struct ahc_softc *ahc; 927 u_int8_t intstat; 928 929 ahc = (struct ahc_softc *)arg; 930 931 intstat = ahc_inb(ahc, INTSTAT); 932 933 /* 934 * Any interrupts to process? 935 */ 936#if NPCI > 0 937 if ((intstat & INT_PEND) == 0) { 938 if ((ahc->chip & AHC_PCI) != 0 939 && (ahc->unsolicited_ints > 500)) { 940 if ((ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0) 941 ahc_pci_intr(ahc); 942 ahc->unsolicited_ints = 0; 943 } else { 944 ahc->unsolicited_ints++; 945 } 946 return; 947 } else { 948 ahc->unsolicited_ints = 0; 949 } 950#else 951 if ((intstat & INT_PEND) == 0) 952 return; 953#endif 954 955 if (intstat & CMDCMPLT) { 956 struct scb *scb; 957 u_int8_t scb_index; 958 959 ahc_outb(ahc, CLRINT, CLRCMDINT); 960 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 961 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 962 ahc->qoutfifo[ahc->qoutfifonext++] = SCB_LIST_NULL; 963 964 if (scb_index == TARGET_CMD_CMPLT) { 965 ahc_handle_target_cmd(ahc); 966 continue; 967 } 968 969 scb = ahc->scb_data->scbarray[scb_index]; 970 if (!scb || !(scb->flags & SCB_ACTIVE)) { 971 printf("%s: WARNING no command for scb %d " 972 "(cmdcmplt)\nQOUTPOS = %d\n", 973 ahc_name(ahc), scb_index, 974 ahc->qoutfifonext - 1); 975 continue; 976 } 977 978 /* 979 * Save off the residual 980 * if there is one. 981 */ 982 if (scb->hscb->residual_SG_count != 0) 983 ahc_calc_residual(scb); 984 ahc_done(ahc, scb); 985 } 986 } 987 if (intstat & BRKADRINT) { 988 /* 989 * We upset the sequencer :-( 990 * Lookup the error message 991 */ 992 int i, error, num_errors; 993 994 error = ahc_inb(ahc, ERROR); 995 num_errors = sizeof(hard_error)/sizeof(hard_error[0]); 996 for (i = 0; error != 1 && i < num_errors; i++) 997 error >>= 1; 998 panic("%s: brkadrint, %s at seqaddr = 0x%x\n", 999 ahc_name(ahc), hard_error[i].errmesg, 1000 ahc_inb(ahc, SEQADDR0) | 1001 (ahc_inb(ahc, SEQADDR1) << 8)); 1002 1003 /* Tell everyone that this HBA is no longer availible */ 1004 ahc_abort_scbs(ahc, ALL_TARGETS, ALL_CHANNELS, 1005 ALL_LUNS, SCB_LIST_NULL, CAM_NO_HBA); 1006 } 1007 if (intstat & SEQINT) 1008 ahc_handle_seqint(ahc, intstat); 1009 1010 if (intstat & SCSIINT) 1011 ahc_handle_scsiint(ahc, intstat); 1012} 1013 1014static void 1015ahc_handle_target_cmd(struct ahc_softc *ahc) 1016{ 1017 struct tmode_tstate *tstate; 1018 struct tmode_lstate *lstate; 1019 struct ccb_accept_tio *atio; 1020 struct target_cmd *cmd; 1021 u_int8_t *byte; 1022 int initiator; 1023 int target; 1024 int lun; 1025 1026 cmd = &ahc->targetcmds[ahc->next_targetcmd]; 1027 ahc->next_targetcmd++; 1028 if (ahc->next_targetcmd >= ahc->num_targetcmds) 1029 ahc->next_targetcmd = 0; 1030 1031 initiator = cmd->icl >> 4; 1032 target = cmd->targ_id; 1033 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 1034 1035 xpt_print_path(ahc->path); 1036 printf("Received Target Command (%d:%d:%d)\n", 1037 initiator, target, lun); 1038 ahc_dump_targcmd(cmd); 1039 1040 byte = cmd->bytes; 1041 tstate = ahc->enabled_targets[target]; 1042 lstate = NULL; 1043 if (tstate != NULL && lun < 8) 1044 lstate = tstate->enabled_luns[lun]; 1045 1046 /* 1047 * XXX Need to have a default TMODE devce that attaches to luns 1048 * that wouldn't otherwise be enabled and returns the proper 1049 * inquiry information. After all, we don't want to duplicate 1050 * this code in each driver. For now, simply drop it on the 1051 * floor. 1052 */ 1053 if (lstate == NULL) { 1054 printf("Incoming Command on disabled lun\n"); 1055 return; 1056 } 1057 1058 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 1059 /* XXX Should reconnect and return BUSY status */ 1060 if (atio == NULL) { 1061 printf("No ATIOs for incoming command\n"); 1062 return; 1063 } 1064 1065 /* 1066 * Package it up and send it off to 1067 * whomever has this lun enabled. 1068 */ 1069 atio->init_id = initiator; 1070 if (byte[0] != 0xFF) { 1071 /* Tag was included */ 1072 atio->tag_action = *byte++; 1073 atio->tag_id = *byte++; 1074 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 1075 } else { 1076 byte++; 1077 atio->ccb_h.flags = 0; 1078 } 1079 1080 /* Okay. Now determine the cdb size based on the command code */ 1081 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 1082 case 0: 1083 atio->cdb_len = 6; 1084 break; 1085 case 1: 1086 case 2: 1087 atio->cdb_len = 10; 1088 break; 1089 case 4: 1090 atio->cdb_len = 16; 1091 break; 1092 case 5: 1093 atio->cdb_len = 12; 1094 break; 1095 case 3: 1096 default: 1097 /* Only copy the opcode. */ 1098 atio->cdb_len = 1; 1099 printf("Reserved or VU command code type encountered\n"); 1100 break; 1101 } 1102 bcopy(byte, atio->cdb_io.cdb_bytes, atio->cdb_len); 1103 1104 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 1105 atio->ccb_h.status |= CAM_CDB_RECVD; 1106 1107 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 1108 /* 1109 * We weren't allowed to disconnect. 1110 * We're hanging on the bus until a 1111 * continue target I/O comes in response 1112 * to this accept tio. 1113 */ 1114 xpt_print_path(atio->ccb_h.path); 1115 printf("Incoming Command did not disconnect %x\n", lstate); 1116 ahc->pending_device = lstate; 1117 } 1118 xpt_done((union ccb*)atio); 1119} 1120 1121static void 1122ahc_handle_seqint(struct ahc_softc *ahc, u_int8_t intstat) 1123{ 1124 struct scb *scb; 1125 struct ahc_devinfo devinfo; 1126 1127 ahc_fetch_devinfo(ahc, &devinfo); 1128 1129 /* 1130 * Clear the upper byte that holds SEQINT status 1131 * codes and clear the SEQINT bit. We will unpause 1132 * the sequencer, if appropriate, after servicing 1133 * the request. 1134 */ 1135 ahc_outb(ahc, CLRINT, CLRSEQINT); 1136 switch (intstat & SEQINT_MASK) { 1137 case NO_MATCH: 1138 { 1139 /* Ensure we don't leave the selection hardware on */ 1140 ahc_outb(ahc, SCSISEQ, 1141 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1142 printf("%s:%c:%d: no active SCB for reconnecting " 1143 "target - issuing BUS DEVICE RESET\n", 1144 ahc_name(ahc), devinfo.channel, devinfo.target); 1145 printf("SAVED_TCL == 0x%x, ARG_1 == 0x%x, SEQ_FLAGS == 0x%x\n", 1146 ahc_inb(ahc, SAVED_TCL), ahc_inb(ahc, ARG_1), 1147 ahc_inb(ahc, SEQ_FLAGS)); 1148 break; 1149 } 1150 case SEND_REJECT: 1151 { 1152 u_int8_t rejbyte = ahc_inb(ahc, ACCUM); 1153 printf("%s:%c:%d: Warning - unknown message received from " 1154 "target (0x%x). Rejecting\n", 1155 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1156 break; 1157 } 1158 case NO_IDENT: 1159 { 1160 /* 1161 * The reconnecting target either did not send an identify 1162 * message, or did, but we didn't find and SCB to match and 1163 * before it could respond to our ATN/abort, it hit a dataphase. 1164 * The only safe thing to do is to blow it away with a bus 1165 * reset. 1166 */ 1167 int found; 1168 1169 printf("%s:%c:%d: Target did not send an IDENTIFY message. " 1170 "LASTPHASE = 0x%x, SAVED_TCL == 0x%x\n", 1171 ahc_name(ahc), devinfo.channel, devinfo.target, 1172 ahc_inb(ahc, LASTPHASE), ahc_inb(ahc, SAVED_TCL)); 1173 found = ahc_reset_channel(ahc, devinfo.channel, 1174 /*initiate reset*/TRUE); 1175 printf("%s: Issued Channel %c Bus Reset. " 1176 "%d SCBs aborted\n", ahc_name(ahc), devinfo.channel, 1177 found); 1178 break; 1179 } 1180 case BAD_PHASE: 1181 if (ahc_inb(ahc, LASTPHASE) == P_BUSFREE) { 1182 printf("%s:%c:%d: Missed busfree.\n", ahc_name(ahc), 1183 devinfo.channel, devinfo.target); 1184 restart_sequencer(ahc); 1185 return; 1186 } else { 1187 printf("%s:%c:%d: unknown scsi bus phase. Attempting " 1188 "to continue\n", ahc_name(ahc), devinfo.channel, 1189 devinfo.target); 1190 } 1191 break; 1192 case EXTENDED_MSG: 1193 { 1194 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 1195 ahc->msg_len = 0; 1196 ahc->msg_index = 0; 1197 1198 /* 1199 * To actually receive the message, simply turn on 1200 * REQINIT interrupts and let our interrupt handler 1201 * do the rest (REQINIT should already be true). 1202 */ 1203 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENREQINIT); 1204 ahc->flags |= AHC_HANDLING_REQINITS; 1205 return; 1206 } 1207 case REJECT_MSG: 1208 { 1209 /* 1210 * What we care about here is if we had an 1211 * outstanding SDTR or WDTR message for this 1212 * target. If we did, this is a signal that 1213 * the target is refusing negotiation. 1214 */ 1215 1216 u_int8_t scb_index; 1217 u_int8_t last_msg; 1218 1219 scb_index = ahc_inb(ahc, SCB_TAG); 1220 scb = ahc->scb_data->scbarray[scb_index]; 1221 1222 last_msg = ahc_inb(ahc, LAST_MSG); 1223 1224 if ((last_msg == MSG_IDENTIFYFLAG) 1225 && (scb->hscb->control & MSG_SIMPLE_Q_TAG) != 0) { 1226 struct ccb_trans_settings neg; 1227 1228 printf("%s:%c:%d: refuses tagged commands. Performing " 1229 "non-tagged I/O\n", ahc_name(ahc), 1230 devinfo.channel, devinfo.target); 1231 1232 ahc->tagenable &= ~devinfo.target_mask; 1233 neg.flags = 0; 1234 neg.valid = CCB_TRANS_TQ_VALID; 1235 xpt_setup_ccb(&neg.ccb_h, scb->ccb->ccb_h.path, 1236 /*priority*/1); 1237 xpt_async(AC_TRANSFER_NEG, scb->ccb->ccb_h.path, &neg); 1238 /* 1239 * Resend the identify for this CCB as the target 1240 * may believe that the selection is invalid otherwise. 1241 */ 1242 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) 1243 & ~MSG_SIMPLE_Q_TAG); 1244 scb->hscb->control &= ~MSG_SIMPLE_Q_TAG; 1245 scb->ccb->ccb_h.flags &= ~CAM_TAG_ACTION_VALID; 1246 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 1247 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 1248 1249 /* 1250 * Requeue all tagged commands for this target 1251 * currently in our posession so they can be 1252 * converted to untagged commands. 1253 */ 1254 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 1255 SCB_CHANNEL(scb), 1256 SCB_LUN(scb), 1257 /*tag*/SCB_LIST_NULL, 1258 CAM_REQUEUE_REQ, 1259 SEARCH_COMPLETE); 1260 } else if ((last_msg == MSG_IDENTIFYFLAG 1261 || last_msg == HOST_MSG) 1262 && (scb->flags & SCB_MSGOUT_WDTR) != 0) { 1263 struct ahc_target_tinfo *tinfo; 1264 1265 /* note 8bit xfers and clear flag */ 1266 printf("%s:%c:%d: refuses WIDE negotiation. Using " 1267 "8bit transfers\n", ahc_name(ahc), 1268 devinfo.channel, devinfo.target); 1269 scb->flags &= ~SCB_MSGOUT_BITS; 1270 ahc->wdtrpending &= ~devinfo.target_mask; 1271 ahc_set_width(ahc, &devinfo, scb->ccb->ccb_h.path, 1272 MSG_EXT_WDTR_BUS_8_BIT, 1273 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 1274 ahc_set_syncrate(ahc, &devinfo, scb->ccb->ccb_h.path, 1275 /*syncrate*/NULL, /*period*/0, 1276 /*offset*/0, AHC_TRANS_ACTIVE); 1277 tinfo = &ahc->transinfo[devinfo.target_offset]; 1278 if (tinfo->goal.period) { 1279 /* Start the sync negotiation */ 1280 ahc->sdtrpending |= devinfo.target_mask; 1281 scb->flags |= SCB_MSGOUT_SDTR; 1282 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1283 ahc_outb(ahc, SCSISIGO, 1284 ahc_inb(ahc, SCSISIGO) | ATNO); 1285 } 1286 } else if ((last_msg == MSG_IDENTIFYFLAG 1287 || last_msg == HOST_MSG) 1288 && (scb->flags & SCB_MSGOUT_SDTR) != 0) { 1289 1290 /* note asynch xfers and clear flag */ 1291 ahc_set_syncrate(ahc, &devinfo, scb->ccb->ccb_h.path, 1292 /*syncrate*/NULL, /*period*/0, 1293 /*offset*/0, 1294 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 1295 scb->flags &= ~SCB_MSGOUT_BITS; 1296 ahc->sdtrpending &= ~devinfo.target_mask; 1297 printf("%s:%c:%d: refuses synchronous negotiation. " 1298 "Using asynchronous transfers\n", 1299 ahc_name(ahc), 1300 devinfo.channel, devinfo.target); 1301 } else { 1302 /* 1303 * Otherwise, we ignore it. 1304 */ 1305#ifdef AHC_DEBUG 1306 if (ahc_debug & AHC_SHOWMISC) 1307 printf("%s:%c:%d: Message reject -- ignored\n", 1308 ahc_name(ahc), devinfo.channel, 1309 devinfo.target); 1310#endif 1311 break; 1312 } 1313 break; 1314 } 1315 case BAD_STATUS: 1316 { 1317 u_int8_t scb_index; 1318 struct hardware_scb *hscb; 1319 struct ccb_scsiio *csio; 1320 /* 1321 * The sequencer will notify us when a command 1322 * has an error that would be of interest to 1323 * the kernel. This allows us to leave the sequencer 1324 * running in the common case of command completes 1325 * without error. The sequencer will already have 1326 * dma'd the SCB back up to us, so we can reference 1327 * the in kernel copy directly. 1328 */ 1329 scb_index = ahc_inb(ahc, SCB_TAG); 1330 scb = ahc->scb_data->scbarray[scb_index]; 1331 hscb = scb->hscb; 1332 1333 /* 1334 * Set the default return value to 0 (don't 1335 * send sense). The sense code will change 1336 * this if needed. 1337 */ 1338 ahc_outb(ahc, RETURN_1, 0); 1339 if (!(scb && (scb->flags & SCB_ACTIVE))) { 1340 printf("%s:%c:%d: ahc_intr - referenced scb " 1341 "not valid during seqint 0x%x scb(%d)\n", 1342 ahc_name(ahc), devinfo.channel, 1343 devinfo.target, intstat, scb_index); 1344 goto unpause; 1345 } 1346 1347 /* Don't want to clobber the original sense code */ 1348 if ((scb->flags & SCB_SENSE) != 0) { 1349 /* 1350 * Clear the SCB_SENSE Flag and have 1351 * the sequencer do a normal command 1352 * complete. 1353 */ 1354 scb->flags &= ~SCB_SENSE; 1355 ahc_set_ccb_status(scb->ccb, CAM_AUTOSENSE_FAIL); 1356 break; 1357 } 1358 ahc_set_ccb_status(scb->ccb, CAM_SCSI_STATUS_ERROR); 1359 csio = &scb->ccb->csio; 1360 csio->scsi_status = hscb->status; 1361 switch (hscb->status) { 1362 case SCSI_STATUS_OK: 1363 printf("%s: Interrupted for staus of 0???\n", 1364 ahc_name(ahc)); 1365 break; 1366 case SCSI_STATUS_CMD_TERMINATED: 1367 case SCSI_STATUS_CHECK_COND: 1368#ifdef AHC_DEBUG 1369 if (ahc_debug & AHC_SHOWSENSE) { 1370 xpt_print_path(csio->ccb_h.path); 1371 printf("SCB %d: requests Check Status\n", 1372 scb->hscb->tag); 1373 } 1374#endif 1375 1376 if ((csio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 1377 struct ahc_dma_seg *sg = scb->ahc_dma; 1378 struct scsi_sense *sc = 1379 (struct scsi_sense *)(&hscb->cmdstore); 1380 struct ahc_target_tinfo *tinfo; 1381 1382 /* 1383 * Save off the residual if there is one. 1384 */ 1385 if (hscb->residual_SG_count != 0) 1386 ahc_calc_residual(scb); 1387 1388#ifdef AHC_DEBUG 1389 if (ahc_debug & AHC_SHOWSENSE) { 1390 xpt_print_path(csio->ccb_h.path); 1391 printf("Sending Sense\n"); 1392 } 1393#endif 1394 /* 1395 * bzero from the sense data before having 1396 * the drive fill it. The SCSI spec mandates 1397 * that any untransfered data should be 1398 * assumed to be zero. 1399 */ 1400 bzero(&csio->sense_data, 1401 sizeof(csio->sense_data)); 1402 sc->opcode = REQUEST_SENSE; 1403 sc->byte2 = SCB_LUN(scb) << 5; 1404 sc->unused[0] = 0; 1405 sc->unused[1] = 0; 1406 sc->length = csio->sense_len; 1407 sc->control = 0; 1408 1409 sg->addr = vtophys(&csio->sense_data); 1410 sg->len = csio->sense_len; 1411 1412 /* 1413 * Would be nice to preserve DISCENB here, 1414 * but due to the way we page SCBs, we can't. 1415 */ 1416 hscb->control = 0; 1417 /* 1418 * This request sense could be because the 1419 * the device lost power or in some other 1420 * way has lost our transfer negotiations. 1421 * Renegotiate if appropriate. 1422 */ 1423 ahc_set_width(ahc, &devinfo, 1424 scb->ccb->ccb_h.path, 1425 MSG_EXT_WDTR_BUS_8_BIT, 1426 AHC_TRANS_CUR); 1427 ahc_set_syncrate(ahc, &devinfo, 1428 scb->ccb->ccb_h.path, 1429 /*syncrate*/NULL, /*period*/0, 1430 /*offset*/0, AHC_TRANS_CUR); 1431 scb->flags &= ~SCB_MSGOUT_BITS; 1432 tinfo = &ahc->transinfo[devinfo.target_offset]; 1433 if (tinfo->goal.width) { 1434 ahc->wdtrpending |= devinfo.target_mask; 1435 hscb->control |= MK_MESSAGE; 1436 scb->flags |= SCB_MSGOUT_WDTR; 1437 } else if (tinfo->goal.period) { 1438 ahc->sdtrpending |= devinfo.target_mask; 1439 hscb->control |= MK_MESSAGE; 1440 scb->flags |= SCB_MSGOUT_SDTR; 1441 } 1442 hscb->status = 0; 1443 hscb->SG_count = 1; 1444 hscb->SG_pointer = scb->ahc_dmaphys; 1445 hscb->data = sg->addr; 1446 hscb->datalen = sg->len; 1447 hscb->cmdpointer = hscb->cmdstore_busaddr; 1448 hscb->cmdlen = sizeof(*sc); 1449 scb->sg_count = hscb->SG_count; 1450 scb->flags |= SCB_SENSE; 1451 /* 1452 * Ensure the target is busy since this 1453 * will be an untagged request. 1454 */ 1455 ahc_busy_tcl(ahc, scb); 1456 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1457 1458 /* 1459 * Ensure we have enough time to actually 1460 * retrieve the sense. 1461 */ 1462 untimeout(ahc_timeout, (caddr_t)scb, 1463 scb->ccb->ccb_h.timeout_ch); 1464 scb->ccb->ccb_h.timeout_ch = 1465 timeout(ahc_timeout, (caddr_t)scb, 5 * hz); 1466 /* Freeze the queue while the sense occurs. */ 1467 ahc_freeze_devq(ahc, scb->ccb->ccb_h.path); 1468 ahc_freeze_ccb(scb->ccb); 1469 break; 1470 } 1471 break; 1472 case SCSI_STATUS_BUSY: 1473 case SCSI_STATUS_QUEUE_FULL: 1474 /* 1475 * Requeue any transactions that haven't been 1476 * sent yet. 1477 */ 1478 ahc_freeze_devq(ahc, scb->ccb->ccb_h.path); 1479 ahc_freeze_ccb(scb->ccb); 1480 break; 1481 } 1482 break; 1483 } 1484 case TARGET_SYNC_CMD: 1485 { 1486 /* 1487 * We've already processed the command. If the command 1488 * is still pending, don't unpause the sequencer until 1489 * it returns. 1490 */ 1491 xpt_print_path(ahc->path); 1492 printf("Saw a target sync cmd\n"); 1493 if (ahc->pending_device != NULL) { 1494 printf(" Pending device too.\n"); 1495 return; 1496 } 1497 break; 1498 } 1499 case TARGET_MSG_HELP: 1500 { 1501 /* 1502 * XXX Handle BDR, Abort, Abort Tag, and transfer negotiations. 1503 */ 1504 restart_sequencer(ahc); 1505 return; 1506 } 1507 case AWAITING_MSG: 1508 { 1509 int scb_index; 1510 1511 scb_index = ahc_inb(ahc, SCB_TAG); 1512 scb = ahc->scb_data->scbarray[scb_index]; 1513 1514 /* 1515 * To facilitate adding multiple messages together, 1516 * each routine should increment the index and len 1517 * variables instead of setting them explicitly. 1518 */ 1519 ahc->msg_index = 0; 1520 ahc->msg_len = 0; 1521 1522 /* 1523 * This SCB had MK_MESSAGE set in its control byte or 1524 * we have explicitly set HOST_MSG in MSG_OUT, 1525 * informing the sequencer that we want to send a 1526 * special message to this target. 1527 */ 1528 if ((scb->flags & SCB_DEVICE_RESET) == 0 1529 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG 1530 && (scb->hscb->control & TAG_ENB) != 0) { 1531 ahc->msg_buf[ahc->msg_index++] = 1532 scb->ccb->csio.tag_action; 1533 ahc->msg_buf[ahc->msg_index++] = 1534 scb->hscb->tag; 1535 ahc->msg_len += 2; 1536 } 1537 1538 if (scb->flags & SCB_DEVICE_RESET) { 1539 ahc->msg_buf[ahc->msg_index++] = MSG_BUS_DEV_RESET; 1540 ahc->msg_len++; 1541 xpt_print_path(scb->ccb->ccb_h.path); 1542 printf("Bus Device Reset Message Sent\n"); 1543 } else if (scb->flags & SCB_ABORT) { 1544 if ((scb->hscb->control & TAG_ENB) != 0) 1545 ahc->msg_buf[ahc->msg_index++] = MSG_ABORT_TAG; 1546 else 1547 ahc->msg_buf[ahc->msg_index++] = MSG_ABORT; 1548 ahc->msg_len++; 1549 xpt_print_path(scb->ccb->ccb_h.path); 1550 printf("Abort Message Sent\n"); 1551 } else if (scb->flags & SCB_MSGOUT_WDTR) { 1552 struct ahc_target_tinfo *tinfo; 1553 1554 tinfo = &ahc->transinfo[devinfo.target_offset]; 1555 ahc_construct_wdtr(ahc, tinfo->goal.width); 1556 } else if (scb->flags & SCB_MSGOUT_SDTR) { 1557 struct ahc_target_tinfo *tinfo; 1558 u_int period; 1559 u_int maxsync; 1560 1561 /* 1562 * Now that the target is actually selected, we 1563 * can further refine our sync rate based on the 1564 * output transceiver mode. 1565 */ 1566 if ((ahc->features & AHC_ULTRA2) != 0) { 1567 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1568 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1569 maxsync = AHC_SYNCRATE_ULTRA2; 1570 } else { 1571 maxsync = AHC_SYNCRATE_ULTRA; 1572 } 1573 } else if ((ahc->features & AHC_ULTRA) != 0) { 1574 maxsync = AHC_SYNCRATE_ULTRA; 1575 } else { 1576 maxsync = AHC_SYNCRATE_FAST; 1577 } 1578 tinfo = &ahc->transinfo[devinfo.target_offset]; 1579 period = tinfo->goal.period; 1580 ahc_find_syncrate(ahc, &period, maxsync); 1581 ahc_construct_sdtr(ahc, period, tinfo->goal.offset); 1582 } else { 1583 printf("ahc_intr: AWAITING_MSG for an SCB that " 1584 "does not have a waiting message"); 1585 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 1586 "SCB flags = %x", scb_index, scb->hscb->control, 1587 ahc_inb(ahc, MSG_OUT), scb->flags); 1588 } 1589 1590 /* 1591 * Record the fact that we attempted to send a message. 1592 */ 1593 scb->flags |= SCB_MSGOUT_SENT; 1594 1595 /* 1596 * To actually send the message, simply turn on 1597 * REQINIT interrupts and let our interrupt handler 1598 * do the rest (REQINIT should already be true). 1599 */ 1600 ahc->msg_index = 0; 1601 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1602 ahc->flags |= AHC_HANDLING_REQINITS; 1603 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENREQINIT); 1604 1605 return; 1606 } 1607 case DATA_OVERRUN: 1608 { 1609 /* 1610 * When the sequencer detects an overrun, it 1611 * places the controller in "BITBUCKET" mode 1612 * and allows the target to complete its transfer. 1613 * Unfortunately, none of the counters get updated 1614 * when the controller is in this mode, so we have 1615 * no way of knowing how large the overrun was. 1616 */ 1617 u_int8_t scbindex = ahc_inb(ahc, SCB_TAG); 1618 u_int8_t lastphase = ahc_inb(ahc, LASTPHASE); 1619 int i; 1620 1621 scb = ahc->scb_data->scbarray[scbindex]; 1622 xpt_print_path(scb->ccb->ccb_h.path); 1623 printf("data overrun detected in %s phase." 1624 " Tag == 0x%x.\n", 1625 lastphase == P_DATAIN ? "Data-In" : "Data-Out", 1626 scb->hscb->tag); 1627 xpt_print_path(scb->ccb->ccb_h.path); 1628 printf("%s seen Data Phase. Length = %d. NumSGs = %d.\n", 1629 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 1630 scb->ccb->csio.dxfer_len, scb->sg_count); 1631 for (i = 0; i < scb->sg_count - 1; i++) { 1632 printf("sg[%d] - Addr 0x%x : Length %d\n", 1633 i, 1634 scb->ahc_dma[i].addr, 1635 scb->ahc_dma[i].len); 1636 } 1637 /* 1638 * Set this and it will take affect when the 1639 * target does a command complete. 1640 */ 1641 ahc_freeze_devq(ahc, scb->ccb->ccb_h.path); 1642 ahc_set_ccb_status(scb->ccb, CAM_DATA_RUN_ERR); 1643 ahc_freeze_ccb(scb->ccb); 1644 break; 1645 } 1646 case TRACEPOINT: 1647 { 1648 printf("TRACEPOINT: RETURN_2 = %d\n", ahc_inb(ahc, RETURN_2)); 1649#if 0 1650 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 1651 printf("SSTAT0 == 0x%x\n", ahc_inb(ahc, SSTAT0)); 1652 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 1653 printf("TRACEPOINT: CCHCNT = %d, SG_COUNT = %d\n", 1654 ahc_inb(ahc, CCHCNT), ahc_inb(ahc, SG_COUNT)); 1655 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 1656 printf("TRACEPOINT1: CCHADDR = %d, CCHCNT = %d, SCBPTR = %d\n", 1657 ahc_inb(ahc, CCHADDR) 1658 | (ahc_inb(ahc, CCHADDR+1) << 8) 1659 | (ahc_inb(ahc, CCHADDR+2) << 16) 1660 | (ahc_inb(ahc, CCHADDR+3) << 24), 1661 ahc_inb(ahc, CCHCNT) 1662 | (ahc_inb(ahc, CCHCNT+1) << 8) 1663 | (ahc_inb(ahc, CCHCNT+2) << 16), 1664 ahc_inb(ahc, SCBPTR)); 1665 printf("TRACEPOINT: WAITING_SCBH = %d\n", ahc_inb(ahc, WAITING_SCBH)); 1666 printf("TRACEPOINT: SCB_TAG = %d\n", ahc_inb(ahc, SCB_TAG)); 1667#endif 1668 break; 1669 } 1670#if NOT_YET 1671 /* XXX Fill these in later */ 1672 case MESG_BUFFER_BUSY: 1673 break; 1674 case MSGIN_PHASEMIS: 1675 break; 1676#endif 1677 default: 1678 printf("ahc_intr: seqint, " 1679 "intstat == 0x%x, scsisigi = 0x%x\n", 1680 intstat, ahc_inb(ahc, SCSISIGI)); 1681 break; 1682 } 1683 1684unpause: 1685 /* 1686 * The sequencer is paused immediately on 1687 * a SEQINT, so we should restart it when 1688 * we're done. 1689 */ 1690 unpause_sequencer(ahc, /*unpause_always*/TRUE); 1691} 1692 1693static void 1694ahc_handle_scsiint(struct ahc_softc *ahc, u_int8_t intstat) 1695{ 1696 u_int8_t scb_index; 1697 u_int8_t status; 1698 struct scb *scb; 1699 1700 scb_index = ahc_inb(ahc, SCB_TAG); 1701 status = ahc_inb(ahc, SSTAT1); 1702 1703 if (scb_index < ahc->scb_data->numscbs) { 1704 scb = ahc->scb_data->scbarray[scb_index]; 1705 if ((scb->flags & SCB_ACTIVE) == 0) 1706 scb = NULL; 1707 } else 1708 scb = NULL; 1709 1710 if ((status & SCSIRSTI) != 0) { 1711 char channel; 1712 channel = 'A'; 1713 if ((ahc->features & AHC_TWIN) != 0 1714 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 1715 channel = 'B'; 1716 printf("%s: Someone reset channel %c\n", 1717 ahc_name(ahc), channel); 1718 ahc_reset_channel(ahc, channel, /* Initiate Reset */FALSE); 1719 } else if ((status & BUSFREE) != 0 && (status & SELTO) == 0) { 1720 /* 1721 * First look at what phase we were last in. 1722 * If its message out, chances are pretty good 1723 * that the busfree was in response to one of 1724 * our abort requests. 1725 */ 1726 u_int8_t lastphase = ahc_inb(ahc, LASTPHASE); 1727 u_int8_t saved_tcl = ahc_inb(ahc, SAVED_TCL); 1728 u_int8_t target = (saved_tcl >> 4) & 0x0f; 1729 char channel = saved_tcl & SELBUSB ? 'B': 'A'; 1730 int printerror = 1; 1731 1732 ahc_outb(ahc, SCSISEQ, 1733 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1734 if (lastphase == P_MESGOUT) { 1735 u_int message; 1736 u_int tag; 1737 1738 message = ahc_inb(ahc, SINDEX); 1739 1740 tag = SCB_LIST_NULL; 1741 switch (message) { 1742 case MSG_ABORT_TAG: 1743 tag = scb->hscb->tag; 1744 /* FALLTRHOUGH */ 1745 case MSG_ABORT: 1746 xpt_print_path(scb->ccb->ccb_h.path); 1747 printf("SCB %d - Abort %s Completed.\n", 1748 tag == SCB_LIST_NULL ? "" : "Tag", 1749 scb->hscb->tag); 1750 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 1751 ahc_set_ccb_status(scb->ccb, 1752 CAM_REQ_ABORTED); 1753 ahc_done(ahc, scb); 1754 } 1755 printerror = 0; 1756 break; 1757 case MSG_BUS_DEV_RESET: 1758 ahc_handle_devreset(ahc, target, channel, 1759 CAM_BDR_SENT, AC_SENT_BDR, 1760 "Bus Device Reset Sent", 1761 /*verbose_only*/FALSE); 1762 printerror = 0; 1763 break; 1764 default: 1765 break; 1766 } 1767 } 1768 if (printerror != 0) { 1769 if (scb != NULL) { 1770 u_int8_t tag; 1771 1772 if ((scb->hscb->control & TAG_ENB) != 0) 1773 tag = scb->hscb->tag; 1774 else 1775 tag = SCB_LIST_NULL; 1776 ahc_abort_scbs(ahc, target, channel, 1777 SCB_LUN(scb), tag, 1778 CAM_UNEXP_BUSFREE); 1779 } else { 1780 ahc_abort_scbs(ahc, target, channel, 1781 ALL_LUNS, SCB_LIST_NULL, 1782 CAM_UNEXP_BUSFREE); 1783 printf("%s: ", ahc_name(ahc)); 1784 } 1785 printf("Unexpected busfree. LASTPHASE == 0x%x\n" 1786 "SEQADDR == 0x%x\n", 1787 lastphase, ahc_inb(ahc, SEQADDR0) 1788 | (ahc_inb(ahc, SEQADDR1) << 8)); 1789 } 1790 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 1791 ahc_outb(ahc, SIMODE1, 1792 ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENREQINIT)); 1793 ahc->flags &= ~AHC_HANDLING_REQINITS; 1794 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1795 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1796 restart_sequencer(ahc); 1797 } else if ((status & SELTO) != 0) { 1798 u_int8_t scbptr; 1799 u_int8_t nextscb; 1800 1801 scbptr = ahc_inb(ahc, WAITING_SCBH); 1802 ahc_outb(ahc, SCBPTR, scbptr); 1803 scb_index = ahc_inb(ahc, SCB_TAG); 1804 1805 if (scb_index < ahc->scb_data->numscbs) { 1806 scb = ahc->scb_data->scbarray[scb_index]; 1807 if ((scb->flags & SCB_ACTIVE) == 0) 1808 scb = NULL; 1809 } else 1810 scb = NULL; 1811 1812 if (scb == NULL) { 1813 printf("%s: ahc_intr - referenced scb not " 1814 "valid during SELTO scb(%d, %d)\n", 1815 ahc_name(ahc), scbptr, scb_index); 1816 } else { 1817 /* 1818 * Clear any pending messages for the timed out 1819 * target. 1820 */ 1821 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 1822 ahc_handle_devreset(ahc, SCB_TARGET(scb), 1823 SCB_CHANNEL(scb), CAM_SEL_TIMEOUT, 1824 /*ac_code*/0, "Selection Timeout", 1825 /*verbose_only*/TRUE); 1826 } 1827 /* Stop the selection */ 1828 ahc_outb(ahc, SCSISEQ, 0); 1829 1830 ahc_outb(ahc, SIMODE1, 1831 ahc_inb(ahc, SIMODE1) & ~ENREQINIT); 1832 ahc->flags &= ~AHC_HANDLING_REQINITS; 1833 1834 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE); 1835 1836 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1837 1838 restart_sequencer(ahc); 1839 } else if (scb == NULL) { 1840 printf("%s: ahc_intr - referenced scb not " 1841 "valid during scsiint 0x%x scb(%d)\n" 1842 "SIMODE0 = 0x%x, SIMODE1 = 0x%x, SSTAT0 = 0x%x\n" 1843 "SEQADDR = 0x%x\n", ahc_name(ahc), 1844 status, scb_index, ahc_inb(ahc, SIMODE0), 1845 ahc_inb(ahc, SIMODE1), ahc_inb(ahc, SSTAT0), 1846 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1847 ahc_outb(ahc, CLRSINT1, status); 1848 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1849 unpause_sequencer(ahc, /*unpause_always*/TRUE); 1850 scb = NULL; 1851 } else if ((status & SCSIPERR) != 0) { 1852 /* 1853 * Determine the bus phase and 1854 * queue an appropriate message 1855 */ 1856 char *phase; 1857 u_int8_t mesg_out = MSG_NOOP; 1858 u_int8_t lastphase = ahc_inb(ahc, LASTPHASE); 1859 1860 xpt_print_path(scb->ccb->ccb_h.path); 1861 1862 switch (lastphase) { 1863 case P_DATAOUT: 1864 phase = "Data-Out"; 1865 break; 1866 case P_DATAIN: 1867 phase = "Data-In"; 1868 mesg_out = MSG_INITIATOR_DET_ERR; 1869 break; 1870 case P_COMMAND: 1871 phase = "Command"; 1872 break; 1873 case P_MESGOUT: 1874 phase = "Message-Out"; 1875 break; 1876 case P_STATUS: 1877 phase = "Status"; 1878 mesg_out = MSG_INITIATOR_DET_ERR; 1879 break; 1880 case P_MESGIN: 1881 phase = "Message-In"; 1882 mesg_out = MSG_PARITY_ERROR; 1883 break; 1884 default: 1885 phase = "unknown"; 1886 break; 1887 } 1888 printf("parity error during %s phase.\n", phase); 1889 1890 printf("SEQADDR == 0x%x\n", ahc_inb(ahc, SEQADDR0) 1891 | (ahc_inb(ahc, SEQADDR1) << 8)); 1892 1893 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 1894 1895 /* 1896 * We've set the hardware to assert ATN if we 1897 * get a parity error on "in" phases, so all we 1898 * need to do is stuff the message buffer with 1899 * the appropriate message. "In" phases have set 1900 * mesg_out to something other than MSG_NOP. 1901 */ 1902 if (mesg_out != MSG_NOOP) { 1903 ahc_outb(ahc, MSG_OUT, mesg_out); 1904 } 1905 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1906 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1907 unpause_sequencer(ahc, /*unpause_always*/TRUE); 1908 } else if ((status & REQINIT) != 0 1909 && (ahc->flags & AHC_HANDLING_REQINITS) != 0) { 1910 ahc_handle_reqinit(ahc, scb); 1911 } else { 1912 xpt_print_path(scb->ccb->ccb_h.path); 1913 printf("Unknown SCSIINT. Status = 0x%x\n", status); 1914 ahc_outb(ahc, CLRSINT1, status); 1915 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1916 unpause_sequencer(ahc, /*unpause_always*/TRUE); 1917 } 1918} 1919 1920static void 1921ahc_handle_reqinit(struct ahc_softc *ahc, struct scb *scb) 1922{ 1923 struct ahc_devinfo devinfo; 1924 u_int8_t simode1; 1925 1926 ahc_fetch_devinfo(ahc, &devinfo); 1927 1928 switch (ahc->msg_type) { 1929 case MSG_TYPE_INITIATOR_MSGOUT: 1930 { 1931 int lastbyte; 1932 int phasemis; 1933 u_int8_t bus_phase; 1934 1935 if (ahc->msg_len == 0) 1936 panic("REQINIT interrupt with no active message"); 1937 1938 lastbyte = (ahc->msg_index == ahc->msg_len - 1); 1939 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1940 phasemis = bus_phase != P_MESGOUT; 1941 1942 if (lastbyte || phasemis) { 1943 /* Time to end our message session */ 1944 ahc->msg_len = 0; 1945 ahc->msg_type = MSG_TYPE_NONE; 1946 simode1 = ahc_inb(ahc, SIMODE1) & ~ENREQINIT; 1947 ahc_outb(ahc, SIMODE1, simode1); 1948 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1949 ahc->flags &= ~AHC_HANDLING_REQINITS; 1950 1951 if (phasemis == 0) { 1952 ahc_outb(ahc, SINDEX, 1953 ahc->msg_buf[ahc->msg_index]); 1954 ahc_outb(ahc, RETURN_1, 0); 1955 } else { 1956 ahc_outb(ahc, RETURN_1, MSGOUT_PHASEMIS); 1957 } 1958 1959 unpause_sequencer(ahc, /* unpause_always */TRUE); 1960 } else { 1961 /* 1962 * Clear our interrupt status and present the byte 1963 * on the bus, but don't unpause the sequencer. 1964 */ 1965 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 1966 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1967 ahc_outb(ahc, SCSIDATL, ahc->msg_buf[ahc->msg_index++]); 1968 } 1969 break; 1970 } 1971 case MSG_TYPE_INITIATOR_MSGIN: 1972 { 1973 int phasemis; 1974 int done; 1975 1976 phasemis = (ahc_inb(ahc, SCSISIGI) & PHASE_MASK) != P_MESGIN; 1977 1978 if (phasemis == 0) { 1979 1980 ahc->msg_len++; 1981 /* Pull the byte in without acking it */ 1982 ahc->msg_buf[ahc->msg_index] = ahc_inb(ahc, SCSIBUSL); 1983 done = ahc_parse_msg(ahc, scb, &devinfo); 1984 /* Ack the byte */ 1985 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 1986 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1987 ahc_inb(ahc, SCSIDATL); 1988 ahc->msg_index++; 1989 } 1990 if (phasemis || done) { 1991 /* Time to end our message session */ 1992 ahc->msg_len = 0; 1993 ahc->msg_type = MSG_TYPE_NONE; 1994 simode1 = ahc_inb(ahc, SIMODE1) & ~ENREQINIT; 1995 ahc->flags &= ~AHC_HANDLING_REQINITS; 1996 ahc_outb(ahc, SIMODE1, simode1); 1997 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1998 unpause_sequencer(ahc, /* unpause_always */TRUE); 1999 } 2000 break; 2001 } 2002 default: 2003 panic("Unknown REQINIT message type"); 2004 } 2005} 2006 2007static int 2008ahc_parse_msg(struct ahc_softc *ahc, struct scb *scb, 2009 struct ahc_devinfo *devinfo) 2010{ 2011 int reject; 2012 int done; 2013 u_int targ_scsirate; 2014 2015 done = FALSE; 2016 reject = FALSE; 2017 targ_scsirate = ahc->transinfo[devinfo->target_offset].scsirate; 2018 /* 2019 * Parse as much of the message as is availible, 2020 * rejecting it if we don't support it. When 2021 * the entire message is availible and has been 2022 * handled, return TRUE indicating that we have 2023 * parsed an entire message. 2024 */ 2025 if (ahc->msg_buf[0] != MSG_EXTENDED) { 2026 reject = TRUE; 2027 } 2028 2029 /* 2030 * Just accept the length byte outright and perform 2031 * more checking once we know the message type. 2032 */ 2033 if (!reject && (ahc->msg_len > 2)) { 2034 switch (ahc->msg_buf[2]) { 2035 case MSG_EXT_SDTR: 2036 { 2037 struct ahc_syncrate *syncrate; 2038 u_int period; 2039 u_int offset; 2040 u_int saved_offset; 2041 u_int maxsync; 2042 2043 if (ahc->msg_buf[1] != MSG_EXT_SDTR_LEN) { 2044 reject = TRUE; 2045 break; 2046 } 2047 2048 /* 2049 * Wait until we have both args before validating 2050 * and acting on this message. 2051 */ 2052 if (ahc->msg_len < (MSG_EXT_SDTR_LEN + /*preamble*/2)) 2053 break; 2054 2055 period = ahc->msg_buf[3]; 2056 saved_offset = offset = ahc->msg_buf[4]; 2057 if ((ahc->features & AHC_ULTRA2) != 0) { 2058 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 2059 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 2060 maxsync = AHC_SYNCRATE_ULTRA2; 2061 } else { 2062 maxsync = AHC_SYNCRATE_ULTRA; 2063 } 2064 } else if ((ahc->features & AHC_ULTRA) != 0) { 2065 maxsync = AHC_SYNCRATE_ULTRA; 2066 } else { 2067 maxsync = AHC_SYNCRATE_FAST; 2068 } 2069 syncrate = ahc_find_syncrate(ahc, &period, maxsync); 2070 ahc_validate_offset(ahc, syncrate, &offset, 2071 targ_scsirate & WIDEXFER); 2072 ahc_set_syncrate(ahc, devinfo, scb->ccb->ccb_h.path, 2073 syncrate, period, offset, 2074 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 2075 2076 /* 2077 * See if we initiated Sync Negotiation 2078 * and didn't have to fall down to async 2079 * transfers. 2080 */ 2081 if ((scb->flags & (SCB_MSGOUT_SDTR|SCB_MSGOUT_SENT)) 2082 == (SCB_MSGOUT_SDTR|SCB_MSGOUT_SENT)) { 2083 /* We started it */ 2084 if (saved_offset != offset) { 2085 /* Went too low - force async */ 2086 reject = TRUE; 2087 } 2088 scb->flags &= ~SCB_MSGOUT_BITS; 2089 ahc->sdtrpending &= ~devinfo->target_mask; 2090 } else { 2091 /* 2092 * Send our own SDTR in reply 2093 */ 2094 scb->flags &= ~SCB_MSGOUT_BITS; 2095 scb->flags |= SCB_MSGOUT_SDTR; 2096 ahc->sdtrpending |= devinfo->target_mask; 2097 xpt_print_path(scb->ccb->ccb_h.path); 2098 printf("Sending SDTR!!\n"); 2099 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2100 ahc_outb(ahc, SCSISIGO, 2101 ahc_inb(ahc, SCSISIGO) | ATNO); 2102 } 2103 done = TRUE; 2104 break; 2105 } 2106 case MSG_EXT_WDTR: 2107 { 2108 struct ccb_trans_settings neg; 2109 u_int8_t bus_width; 2110 2111 if (ahc->msg_buf[1] != MSG_EXT_WDTR_LEN) { 2112 reject = TRUE; 2113 break; 2114 } 2115 2116 /* 2117 * Wait until we have our arg before validating 2118 * and acting on this message. 2119 */ 2120 if (ahc->msg_len < (MSG_EXT_WDTR_LEN + /*preamble*/2)) 2121 break; 2122 2123 bus_width = ahc->msg_buf[3]; 2124 if ((scb->flags & (SCB_MSGOUT_WDTR|SCB_MSGOUT_SENT)) 2125 == (SCB_MSGOUT_WDTR|SCB_MSGOUT_SENT)) { 2126 /* 2127 * Don't send a WDTR back to the 2128 * target, since we asked first. 2129 */ 2130 switch (bus_width){ 2131 default: 2132 /* 2133 * How can we do anything greater 2134 * than 16bit transfers on a 16bit 2135 * bus? 2136 */ 2137 reject = TRUE; 2138 printf("%s: target %d requested %dBit " 2139 "transfers. Rejecting...\n", 2140 ahc_name(ahc), devinfo->target, 2141 8 * (0x01 << bus_width)); 2142 /* FALLTHROUGH */ 2143 case MSG_EXT_WDTR_BUS_8_BIT: 2144 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2145 break; 2146 case MSG_EXT_WDTR_BUS_16_BIT: 2147 break; 2148 } 2149 scb->flags &= ~SCB_MSGOUT_WDTR; 2150 ahc->wdtrpending &= ~devinfo->target_mask; 2151 } else { 2152 /* 2153 * Send our own WDTR in reply 2154 */ 2155 printf("Sending WDTR!\n"); 2156 scb->flags &= ~SCB_MSGOUT_BITS; 2157 scb->flags |= SCB_MSGOUT_WDTR; 2158 switch (bus_width) { 2159 default: 2160 if (ahc->features & AHC_WIDE) { 2161 /* Respond Wide */ 2162 bus_width = 2163 MSG_EXT_WDTR_BUS_16_BIT; 2164 break; 2165 } 2166 /* FALLTHROUGH */ 2167 case MSG_EXT_WDTR_BUS_8_BIT: 2168 bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2169 break; 2170 } 2171 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2172 ahc_outb(ahc, SCSISIGO, 2173 ahc_inb(ahc, SCSISIGO) | ATNO); 2174 ahc->wdtrpending |= devinfo->target_mask; 2175 } 2176 ahc_set_width(ahc, devinfo, scb->ccb->ccb_h.path, 2177 bus_width, 2178 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL); 2179 2180 /* After a wide message, we are async */ 2181 ahc_set_syncrate(ahc, devinfo, scb->ccb->ccb_h.path, 2182 /*syncrate*/NULL, /*period*/0, 2183 /*offset*/0, AHC_TRANS_ACTIVE); 2184 if ((ahc->wdtrpending & devinfo->target_mask) == 0 2185 && (reject == 0)) { 2186 struct ahc_target_tinfo *tinfo; 2187 2188 scb->flags &= ~SCB_MSGOUT_WDTR; 2189 tinfo = &ahc->transinfo[devinfo->target_offset]; 2190 if (tinfo->goal.period) { 2191 /* Start the sync negotiation */ 2192 ahc->sdtrpending |= 2193 devinfo->target_mask; 2194 scb->flags |= SCB_MSGOUT_SDTR; 2195 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2196 ahc_outb(ahc, SCSISIGO, 2197 ahc_inb(ahc, SCSISIGO) | ATNO); 2198 } 2199 } 2200 done = TRUE; 2201 break; 2202 } 2203 default: 2204 /* Unknown extended message. Reject it. */ 2205 reject = TRUE; 2206 break; 2207 } 2208 } 2209 2210 if (reject) { 2211 /* 2212 * Assert attention and setup to 2213 * reject the message. 2214 */ 2215 ahc_outb(ahc, MSG_OUT, MSG_MESSAGE_REJECT); 2216 ahc_outb(ahc, SCSISIGO, ahc_inb(ahc, SCSISIGO) | ATNO); 2217 done = TRUE; 2218 } 2219 return (done); 2220} 2221 2222static void 2223ahc_handle_devreset(struct ahc_softc *ahc, int target, char channel, 2224 cam_status status, ac_code acode, char *message, 2225 int verbose_only) 2226{ 2227 struct ahc_devinfo devinfo; 2228 struct cam_path *path; 2229 path_id_t path_id; 2230 u_int16_t targ_mask; 2231 u_int8_t targ_scsirate; 2232 int scratch_offset = target; 2233 int found; 2234 int error; 2235 2236 ahc_compile_devinfo(&devinfo, target, channel); 2237 2238 if (channel == 'B') 2239 path_id = cam_sim_path(ahc->sim_b); 2240 else 2241 path_id = cam_sim_path(ahc->sim); 2242 2243 error = xpt_create_path(&path, /*periph*/NULL, path_id, target, 2244 CAM_LUN_WILDCARD); 2245 /* 2246 * Go back to async/narrow transfers and renegotiate. 2247 */ 2248 if (error == CAM_REQ_CMP) { 2249 ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, 2250 AHC_TRANS_CUR); 2251 ahc_set_syncrate(ahc, &devinfo, path, /*syncrate*/NULL, 2252 /*period*/0, /*offset*/0, AHC_TRANS_CUR); 2253 } 2254 found = ahc_abort_scbs(ahc, target, channel, ALL_LUNS, 2255 SCB_LIST_NULL, status); 2256 2257 if (error == CAM_REQ_CMP && acode != 0) 2258 xpt_async(AC_SENT_BDR, path, NULL); 2259 2260 if (error == CAM_REQ_CMP) 2261 xpt_free_path(path); 2262 2263 if (message != NULL 2264 && (verbose_only == 0 || bootverbose != 0)) 2265 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 2266 message, channel, target, found); 2267} 2268/* 2269 * We have an scb which has been processed by the 2270 * adaptor, now we look to see how the operation 2271 * went. 2272 */ 2273static void 2274ahc_done(struct ahc_softc *ahc, struct scb *scb) 2275{ 2276 union ccb *ccb; 2277 2278 CAM_DEBUG(scb->ccb->ccb_h.path, CAM_DEBUG_TRACE, 2279 ("ahc_done - scb %d\n", scb->hscb->tag)); 2280 2281 ccb = scb->ccb; 2282 LIST_REMOVE(&ccb->ccb_h, sim_links.le); 2283 2284 untimeout(ahc_timeout, (caddr_t)scb, ccb->ccb_h.timeout_ch); 2285 2286 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2287 bus_dmasync_op_t op; 2288 2289 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2290 op = BUS_DMASYNC_POSTREAD; 2291 else 2292 op = BUS_DMASYNC_POSTWRITE; 2293 bus_dmamap_sync(ahc->dmat, scb->dmamap, op); 2294 bus_dmamap_unload(ahc->dmat, scb->dmamap); 2295 } 2296 2297 /* 2298 * Unbusy this target/channel/lun. 2299 * XXX if we are holding two commands per lun, 2300 * send the next command. 2301 */ 2302 ahc_index_busy_tcl(ahc, scb->hscb->tcl, /*unbusy*/TRUE); 2303 2304 if (ccb->ccb_h.func_code == XPT_CONT_TARGET_IO) { 2305 xpt_print_path(ccb->ccb_h.path); 2306 printf("CONT_TARGET_IO complete\n"); 2307 ccb->ccb_h.status = CAM_REQ_CMP; 2308 ahc_free_scb(ahc, scb); 2309 xpt_done(ccb); 2310 return; 2311 } 2312 2313 /* 2314 * If the recovery SCB completes, we have to be 2315 * out of our timeout. 2316 */ 2317 if ((scb->flags & SCB_RECOVERY_SCB) != 0) { 2318 2319 struct ccb_hdr *ccbh; 2320 2321 /* 2322 * We were able to complete the command successfully, 2323 * so reinstate the timeouts for all other pending 2324 * commands. 2325 */ 2326 ccbh = ahc->pending_ccbs.lh_first; 2327 while (ccbh != NULL) { 2328 struct scb *pending_scb; 2329 2330 pending_scb = (struct scb *)ccbh->ccb_scb_ptr; 2331 ccbh->timeout_ch = 2332 timeout(ahc_timeout, pending_scb, 2333 (ccbh->timeout * hz)/1000); 2334 ccbh = LIST_NEXT(ccbh, sim_links.le); 2335 } 2336 2337 /* 2338 * Ensure that we didn't put a second instance of this 2339 * SCB into the QINFIFO. 2340 */ 2341 ahc_search_qinfifo(ahc, SCB_TARGET(scb), SCB_CHANNEL(scb), 2342 SCB_LUN(scb), scb->hscb->tag, /*status*/0, 2343 SEARCH_REMOVE); 2344 if (ahc_ccb_status(ccb) == CAM_BDR_SENT) 2345 ahc_set_ccb_status(ccb, CAM_CMD_TIMEOUT); 2346 xpt_print_path(ccb->ccb_h.path); 2347 printf("no longer in timeout, status = %x\n", 2348 ccb->ccb_h.status); 2349 } 2350 2351 if ((scb->flags & (SCB_MSGOUT_WDTR|SCB_MSGOUT_SDTR)) != 0) { 2352 /* 2353 * Turn off the pending flags for any DTR messages 2354 * regardless of whether they completed successfully 2355 * or not. This ensures that we don't have lingering 2356 * state after we abort an SCB. 2357 */ 2358 u_int16_t mask; 2359 2360 mask = (0x01 << (SCB_TARGET(scb) 2361 | (SCB_IS_SCSIBUS_B(scb) ? SELBUSB : 0))); 2362 if (scb->flags & SCB_MSGOUT_WDTR) 2363 ahc->wdtrpending &= ~mask; 2364 if (scb->flags & SCB_MSGOUT_SDTR) 2365 ahc->sdtrpending &= ~mask; 2366 } 2367 /* Don't clobber any existing error state */ 2368 if (ahc_ccb_status(ccb) == CAM_REQ_INPROG) { 2369 ccb->ccb_h.status |= CAM_REQ_CMP; 2370 } else if ((scb->flags & SCB_SENSE) != 0) { 2371 /* We performed autosense retrieval */ 2372 scb->ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 2373 } 2374 ccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2375 ahc_free_scb(ahc, scb); 2376 xpt_done(ccb); 2377} 2378 2379/* 2380 * Determine the number of SCBs available on the controller 2381 */ 2382int 2383ahc_probe_scbs(struct ahc_softc *ahc) { 2384 int i; 2385 2386 for (i = 0; i < AHC_SCB_MAX; i++) { 2387 ahc_outb(ahc, SCBPTR, i); 2388 ahc_outb(ahc, SCB_CONTROL, i); 2389 if (ahc_inb(ahc, SCB_CONTROL) != i) 2390 break; 2391 ahc_outb(ahc, SCBPTR, 0); 2392 if (ahc_inb(ahc, SCB_CONTROL) != 0) 2393 break; 2394 } 2395 2396 return (i); 2397} 2398 2399/* 2400 * Start the board, ready for normal operation 2401 */ 2402int 2403ahc_init(struct ahc_softc *ahc) 2404{ 2405 int max_targ = 15; 2406 int i; 2407 int term; 2408 u_int8_t scsi_conf, sxfrctl1; 2409 2410#ifdef AHC_PRINT_SRAM 2411 printf("Scratch Ram:"); 2412 for (i = 0x20; i < 0x5f; i++) { 2413 if (((i % 8) == 0) && (i != 0)) { 2414 printf ("\n "); 2415 } 2416 printf (" 0x%x", ahc_inb(ahc, i)); 2417 } 2418 if ((ahc->features & AHC_MORE_SRAM) != 0) { 2419 for (i = 0x70; i < 0x7f; i++) { 2420 if (((i % 8) == 0) && (i != 0)) { 2421 printf ("\n "); 2422 } 2423 printf (" 0x%x", ahc_inb(ahc, i)); 2424 } 2425 } 2426 printf ("\n"); 2427#endif 2428 2429 /* 2430 * Assume we have a board at this stage and it has been reset. 2431 */ 2432 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 2433 ahc->our_id = ahc->our_id_b = 7; 2434 } 2435 2436 /* 2437 * XXX Would be better to use a per device flag, but PCI and EISA 2438 * devices don't have them yet. 2439 */ 2440 if ((AHC_TMODE_ENABLE & (0x01 << ahc->unit)) != 0) 2441 ahc->flags |= AHC_TARGETMODE; 2442 2443 if ((ahc->features & AHC_TWIN) != 0) { 2444 printf("Twin Channel, A SCSI Id=%d, B SCSI Id=%d, ", 2445 ahc->our_id, ahc->our_id_b); 2446 } else { 2447 if ((ahc->features & AHC_WIDE) != 0) { 2448 printf("Wide "); 2449 } else { 2450 printf("Single "); 2451 } 2452 printf("Channel %c, SCSI Id=%d, ", ahc->channel, ahc->our_id); 2453 } 2454 2455 ahc_outb(ahc, SEQ_FLAGS, 0); 2456 2457 /* Determine the number of SCBs and initialize them */ 2458 2459 if (ahc->scb_data->maxhscbs == 0) { 2460 ahc->scb_data->maxhscbs = ahc_probe_scbs(ahc); 2461 /* SCB 0 heads the free list */ 2462 ahc_outb(ahc, FREE_SCBH, 0); 2463 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2464 ahc_outb(ahc, SCBPTR, i); 2465 2466 /* Clear the control byte. */ 2467 ahc_outb(ahc, SCB_CONTROL, 0); 2468 2469 /* Set the next pointer */ 2470 ahc_outb(ahc, SCB_NEXT, i+1); 2471 2472 /* Make the tag number invalid */ 2473 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 2474 } 2475 2476 /* Make that the last SCB terminates the free list */ 2477 ahc_outb(ahc, SCBPTR, i-1); 2478 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 2479 2480 /* Ensure we clear the 0 SCB's control byte. */ 2481 ahc_outb(ahc, SCBPTR, 0); 2482 ahc_outb(ahc, SCB_CONTROL, 0); 2483 2484 ahc->scb_data->maxhscbs = i; 2485 } 2486 2487 if (ahc->scb_data->maxhscbs == 0) 2488 panic("%s: No SCB space found", ahc_name(ahc)); 2489 2490 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX) { 2491 ahc->flags |= AHC_PAGESCBS; 2492 ahc->scb_data->maxscbs = AHC_SCB_MAX; 2493 if ((ahc->flags & AHC_TARGETMODE) != 0) { 2494 /* Steal one slot for TMODE commands */ 2495 ahc->scb_data->maxscbs--; 2496 } 2497 printf("%d/%d SCBs\n", ahc->scb_data->maxhscbs, 2498 ahc->scb_data->maxscbs); 2499 } else { 2500 ahc->scb_data->maxscbs = ahc->scb_data->maxhscbs; 2501 if ((ahc->flags & AHC_TARGETMODE) != 0) { 2502 /* Steal one slot for TMODE commands */ 2503 ahc->scb_data->maxscbs--; 2504 } 2505 ahc->flags &= ~AHC_PAGESCBS; 2506 printf("%d SCBs\n", ahc->scb_data->maxhscbs); 2507 } 2508 2509#ifdef AHC_DEBUG 2510 if (ahc_debug & AHC_SHOWMISC) { 2511 printf("%s: hardware scb %d bytes; kernel scb %d bytes; " 2512 "ahc_dma %d bytes\n", 2513 ahc_name(ahc), 2514 sizeof(struct hardware_scb), 2515 sizeof(struct scb), 2516 sizeof(struct ahc_dma_seg)); 2517 } 2518#endif /* AHC_DEBUG */ 2519 2520 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 2521 if (ahc->features & AHC_TWIN) { 2522 2523 /* 2524 * The device is gated to channel B after a chip reset, 2525 * so set those values first 2526 */ 2527 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 2528 if ((ahc->features & AHC_ULTRA2) != 0) 2529 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id_b); 2530 else 2531 ahc_outb(ahc, SCSIID, ahc->our_id_b); 2532 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 2533 sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 2534 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 2535 |term 2536 |ENSTIMER|ACTNEGEN); 2537 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 2538 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 2539 2540 if (scsi_conf & RESET_SCSI) { 2541 /* Reset the bus */ 2542 if (bootverbose) 2543 printf("%s: Resetting Channel B\n", 2544 ahc_name(ahc)); 2545 ahc_reset_current_bus(ahc); 2546 } 2547 2548 /* Select Channel A */ 2549 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 2550 } 2551 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 2552 if ((ahc->features & AHC_ULTRA2) != 0) 2553 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 2554 else 2555 ahc_outb(ahc, SCSIID, ahc->our_id); 2556 scsi_conf = ahc_inb(ahc, SCSICONF); 2557 sxfrctl1 = ahc_inb(ahc, SXFRCTL1); 2558 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 2559 |term 2560 |ENSTIMER|ACTNEGEN); 2561 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 2562 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 2563 2564 if ((ahc->features & AHC_ULTRA2) != 0) { 2565 /* Wait for our transceiver status to settle */ 2566 i = 1000000; 2567 while (--i && ((ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0)) 2568 DELAY(100); 2569 2570 if (i == 0) 2571 panic("%s: Transceiver state never settled\n", 2572 ahc_name(ahc)); 2573 } 2574 2575 if (scsi_conf & RESET_SCSI) { 2576 /* Reset the bus */ 2577 if (bootverbose) 2578 printf("%s: Resetting Channel %c\n", ahc_name(ahc), 2579 ahc->channel); 2580 2581 ahc_reset_current_bus(ahc); 2582 } 2583 2584 /* 2585 * Look at the information that board initialization or 2586 * the board bios has left us. In the lower four bits of each 2587 * target's scratch space any value other than 0 indicates 2588 * that we should initiate synchronous transfers. If it's zero, 2589 * the user or the BIOS has decided to disable synchronous 2590 * negotiation to that target so we don't activate the needsdtr 2591 * flag. 2592 */ 2593 ahc->ultraenb = 0; 2594 ahc->tagenable = ALL_TARGETS; 2595 2596 /* Grab the disconnection disable table and invert it for our needs */ 2597 if (ahc->flags & AHC_USEDEFAULTS) { 2598 printf("%s: Host Adapter Bios disabled. Using default SCSI " 2599 "device parameters\n", ahc_name(ahc)); 2600 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B; 2601 ahc->discenable = ALL_TARGETS; 2602 if ((ahc->features & AHC_ULTRA) != 0) 2603 ahc->ultraenb = 0xffff; 2604 } else { 2605 ahc->discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 2606 | ahc_inb(ahc, DISC_DSB)); 2607 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 2608 ahc->ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 2609 | ahc_inb(ahc, ULTRA_ENB); 2610 } 2611 2612 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 2613 max_targ = 7; 2614 2615 for (i = 0; i <= max_targ; i++) { 2616 struct ahc_target_tinfo *transinfo; 2617 2618 transinfo = &ahc->transinfo[i]; 2619 /* Default to async narrow across the board */ 2620 bzero(transinfo, sizeof(*transinfo)); 2621 if (ahc->flags & AHC_USEDEFAULTS) { 2622 if ((ahc->features & AHC_WIDE) != 0) 2623 transinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 2624 2625 /* 2626 * These will be truncated when we determine the 2627 * connection type we have with the target. 2628 */ 2629 transinfo->user.period = ahc_syncrates->period; 2630 transinfo->user.offset = ~0; 2631 } else { 2632 u_int scsirate; 2633 u_int16_t mask; 2634 2635 /* Take the settings leftover in scratch RAM. */ 2636 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 2637 mask = (0x01 << i); 2638 if ((ahc->features & AHC_ULTRA2) != 0) { 2639 u_int offset; 2640 2641 if ((scsirate & SOFS) == 0x0F) { 2642 /* 2643 * Haven't negotiated yet, 2644 * so the format is different. 2645 */ 2646 scsirate = (scsirate & SXFR) >> 4 2647 | (ahc->ultraenb & mask) 2648 ? 0x18 : 0x10 2649 | (scsirate & WIDEXFER); 2650 offset = MAX_OFFSET_ULTRA2; 2651 } else 2652 offset = ahc_inb(ahc, TARG_OFFSET + i); 2653 ahc_find_period(ahc, scsirate, 2654 AHC_SYNCRATE_ULTRA2); 2655 if (offset == 0) 2656 transinfo->user.period = 0; 2657 else 2658 transinfo->user.offset = ~0; 2659 } else if ((scsirate & SOFS) != 0) { 2660 transinfo->user.period = 2661 ahc_find_period(ahc, scsirate, 2662 (ahc->ultraenb & mask) 2663 ? AHC_SYNCRATE_ULTRA 2664 : AHC_SYNCRATE_FAST); 2665 if ((scsirate & SOFS) != 0 2666 && transinfo->user.period != 0) { 2667 transinfo->user.offset = ~0; 2668 } 2669 } 2670 if ((scsirate & WIDEXFER) != 0 2671 && (ahc->features & AHC_WIDE) != 0) { 2672 transinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 2673 } 2674 2675 } 2676 } 2677 ahc->sdtrpending = 0; 2678 ahc->wdtrpending = 0; 2679 2680#ifdef AHC_DEBUG 2681 if (ahc_debug & AHC_SHOWMISC) 2682 printf("NEEDSDTR == 0x%x\nNEEDWDTR == 0x%x\n" 2683 "DISCENABLE == 0x%x\nULTRAENB == 0x%x\n", 2684 ahc->needsdtr_orig, ahc->needwdtr_orig, 2685 ahc->discenable, ahc->ultraenb); 2686#endif 2687 /* 2688 * Allocate enough "hardware scbs" to handle 2689 * the maximum number of concurrent transactions 2690 * we can have active. We have to use contigmalloc 2691 * if this array crosses a page boundary since the 2692 * sequencer depends on this array being physically 2693 * contiguous. 2694 */ 2695 if (ahc->scb_data->hscbs == NULL) { 2696 size_t array_size; 2697 2698 array_size = ahc->scb_data->maxscbs*sizeof(struct hardware_scb); 2699 if (array_size > PAGE_SIZE) { 2700 ahc->scb_data->hscbs = (struct hardware_scb *) 2701 contigmalloc(array_size, M_DEVBUF, 2702 M_NOWAIT, 0ul, 0xffffffff, 2703 PAGE_SIZE, 0x10000); 2704 } else { 2705 ahc->scb_data->hscbs = (struct hardware_scb *) 2706 malloc(array_size, M_DEVBUF, M_NOWAIT); 2707 } 2708 2709 if (ahc->scb_data->hscbs == NULL) { 2710 printf("%s: unable to allocate hardware SCB array. " 2711 "Failing attach\n", ahc_name(ahc)); 2712 return (-1); 2713 } 2714 /* At least the control byte of each hscb needs to be zeroed */ 2715 bzero(ahc->scb_data->hscbs, array_size); 2716 } 2717 2718 if ((ahc->flags & AHC_TARGETMODE) != 0) { 2719 size_t array_size; 2720 2721 ahc->num_targetcmds = 32; 2722 array_size = ahc->num_targetcmds * sizeof(struct target_cmd); 2723 ahc->targetcmds = malloc(array_size, M_DEVBUF, M_NOWAIT); 2724 2725 if (ahc->targetcmds == NULL) { 2726 printf("%s: unable to allocate targetcmd array. " 2727 "Failing attach\n", ahc_name(ahc)); 2728 return (-1); 2729 } 2730 2731 bzero(ahc->targetcmds, array_size); 2732 ahc_outb(ahc, TMODE_CMDADDR_NEXT, 0); 2733 } 2734 2735 /* 2736 * Tell the sequencer where it can find the our arrays in memory. 2737 */ 2738 { 2739 u_int32_t physaddr; 2740 2741 /* Tell the sequencer where it can find the hscb array. */ 2742 physaddr = vtophys(ahc->scb_data->hscbs); 2743 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 2744 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 2745 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 2746 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 2747 ahc->hscb_busaddr = physaddr; 2748 2749 physaddr = vtophys(ahc->qoutfifo); 2750 ahc_outb(ahc, SCBID_ADDR, physaddr & 0xFF); 2751 ahc_outb(ahc, SCBID_ADDR + 1, (physaddr >> 8) & 0xFF); 2752 ahc_outb(ahc, SCBID_ADDR + 2, (physaddr >> 16) & 0xFF); 2753 ahc_outb(ahc, SCBID_ADDR + 3, (physaddr >> 24) & 0xFF); 2754 2755 if ((ahc->flags & AHC_TARGETMODE) != 0) { 2756 physaddr = vtophys(ahc->targetcmds); 2757 ahc_outb(ahc, TMODE_CMDADDR, physaddr & 0xFF); 2758 ahc_outb(ahc, TMODE_CMDADDR + 1, 2759 (physaddr >> 8) & 0xFF); 2760 ahc_outb(ahc, TMODE_CMDADDR + 2, 2761 (physaddr >> 16) & 0xFF); 2762 ahc_outb(ahc, TMODE_CMDADDR + 3, 2763 (physaddr >> 24) & 0xFF); 2764 2765 ahc_outb(ahc, CMDSIZE_TABLE, 5); 2766 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 2767 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 2768 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 2769 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 2770 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 2771 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 2772 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 2773 } 2774 2775 /* There are no untagged SCBs active yet. */ 2776 for (i = 0; i < sizeof(ahc->untagged_scbs); i++) { 2777 ahc->untagged_scbs[i] = SCB_LIST_NULL; 2778 } 2779 for (i = 0; i < sizeof(ahc->qoutfifo); i++) { 2780 ahc->qoutfifo[i] = SCB_LIST_NULL; 2781 } 2782 } 2783 2784 /* Our Q FIFOs are empty. */ 2785 ahc_outb(ahc, KERNEL_QINPOS, 0); 2786 ahc_outb(ahc, QINPOS, 0); 2787 ahc_outb(ahc, QOUTPOS, 0); 2788 2789 /* 2790 * Use the built in queue management registers 2791 * if they are available. 2792 */ 2793 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 2794 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 2795 ahc_outb(ahc, SDSCB_QOFF, 0); 2796 ahc_outb(ahc, SNSCB_QOFF, 0); 2797 ahc_outb(ahc, HNSCB_QOFF, 0); 2798 } 2799 2800 2801 /* We don't have any waiting selections */ 2802 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 2803 2804 /* Our disconnection list is empty too */ 2805 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 2806 2807 /* Message out buffer starts empty */ 2808 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2809 2810 /* 2811 * Load the Sequencer program and Enable the adapter 2812 * in "fast" mode. 2813 */ 2814 if (bootverbose) 2815 printf("%s: Downloading Sequencer Program...", 2816 ahc_name(ahc)); 2817 2818 ahc_loadseq(ahc); 2819 2820 /* We have to wait until after any system dumps... */ 2821 at_shutdown(ahc_shutdown, ahc, SHUTDOWN_FINAL); 2822 2823 return (0); 2824} 2825 2826static void 2827ahcminphys(struct buf *bp) 2828{ 2829/* 2830 * Even though the card can transfer up to 16megs per command 2831 * we are limited by the number of segments in the dma segment 2832 * list that we can hold. The worst case is that all pages are 2833 * discontinuous physically, hense the "page per segment" limit 2834 * enforced here. 2835 */ 2836 if (bp->b_bcount > ((AHC_NSEG - 1) * PAGE_SIZE)) { 2837 bp->b_bcount = ((AHC_NSEG - 1) * PAGE_SIZE); 2838 } 2839} 2840 2841static cam_status 2842ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 2843 struct tmode_tstate **tstate, struct tmode_lstate **lstate, 2844 int notfound_failure) 2845{ 2846 int our_id; 2847 2848 /* 2849 * If we are not configured for target mode, someone 2850 * is really confused to be sending this to us. 2851 */ 2852 if ((ahc->flags & AHC_TARGETMODE) == 0) 2853 return (CAM_REQ_INVALID); 2854 2855 /* Range check target and lun */ 2856 if (cam_sim_bus(sim) == 0) 2857 our_id = ahc->our_id; 2858 else 2859 our_id = ahc->our_id_b; 2860 if (ccb->ccb_h.target_id > ((ahc->features & AHC_WIDE) ? 15 : 7) 2861 || ((ahc->features & AHC_MULTI_TID) == 0 2862 && (ccb->ccb_h.target_id != our_id))) 2863 return (CAM_TID_INVALID); 2864 2865 if (ccb->ccb_h.target_lun > 8) 2866 return (CAM_LUN_INVALID); 2867 2868 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 2869 *lstate = NULL; 2870 if (*tstate != NULL) 2871 *lstate = (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 2872 2873 if (notfound_failure != 0 && *lstate == NULL) 2874 return (CAM_PATH_INVALID); 2875 2876 return (CAM_REQ_CMP); 2877} 2878 2879static void 2880ahc_action(struct cam_sim *sim, union ccb *ccb) 2881{ 2882 struct ahc_softc *ahc; 2883 struct tmode_lstate *lstate; 2884 int target_id; 2885 int s; 2886 2887 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahc_action\n")); 2888 2889 ahc = (struct ahc_softc *)cam_sim_softc(sim); 2890 2891 target_id = ccb->ccb_h.target_id; 2892 2893 switch (ccb->ccb_h.func_code) { 2894 /* Common cases first */ 2895 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2896 case XPT_CONT_TARGET_IO:/* Continue Host Target I/O Connection*/ 2897 { 2898 struct tmode_tstate *tstate; 2899 cam_status status; 2900 2901 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, 2902 &lstate, TRUE); 2903 2904 if (status != CAM_REQ_CMP) { 2905 ccb->ccb_h.status = status; 2906 xpt_done(ccb); 2907 break; 2908 } 2909 if (ccb->ccb_h.func_code == XPT_ACCEPT_TARGET_IO) { 2910 SLIST_INSERT_HEAD(&lstate->accept_tios, &ccb->ccb_h, 2911 sim_links.sle); 2912 ccb->ccb_h.status = CAM_REQ_INPROG; 2913 break; 2914 } 2915 2916 /* 2917 * The target_id represents the target we attempt to 2918 * select. In target mode, this is the initiator of 2919 * the original command. 2920 */ 2921 target_id = ccb->csio.init_id; 2922 xpt_print_path(ccb->ccb_h.path); 2923 printf("Sending a continue TIO\n"); 2924 /* FALLTHROUGH */ 2925 } 2926 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 2927 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2928 { 2929 struct scb *scb; 2930 struct hardware_scb *hscb; 2931 struct ahc_target_tinfo *tinfo; 2932 u_int16_t mask; 2933 2934 /* 2935 * get an scb to use. 2936 */ 2937 if ((scb = ahc_get_scb(ahc)) == NULL) { 2938 int s; 2939 2940 s = splcam(); 2941 ahc->flags |= AHC_RESOURCE_SHORTAGE; 2942 splx(s); 2943 xpt_freeze_simq(ahc->sim, /*count*/1); 2944 ahc_set_ccb_status(ccb, CAM_REQUEUE_REQ); 2945 xpt_done(ccb); 2946 return; 2947 } 2948 2949 hscb = scb->hscb; 2950 2951 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_SUBTRACE, 2952 ("start scb(%p)\n", scb)); 2953 scb->ccb = ccb; 2954 /* 2955 * So we can find the SCB when an abort is requested 2956 */ 2957 ccb->ccb_h.ccb_scb_ptr = scb; 2958 ccb->ccb_h.ccb_ahc_ptr = ahc; 2959 2960 /* 2961 * Put all the arguments for the xfer in the scb 2962 */ 2963 hscb->tcl = ((target_id << 4) & 0xF0) 2964 | (SIM_IS_SCSIBUS_B(ahc, sim) ? SELBUSB : 0) 2965 | (ccb->ccb_h.target_lun & 0x07); 2966 2967 mask = SCB_TARGET_MASK(scb); 2968 tinfo = &ahc->transinfo[SCB_TARGET_OFFSET(scb)]; 2969 2970 hscb->scsirate = tinfo->scsirate; 2971 hscb->scsioffset = tinfo->current.offset; 2972 if ((ahc->ultraenb & mask) != 0) 2973 hscb->control |= ULTRAENB; 2974 2975 if ((ahc->discenable & mask) != 0 2976 && (ccb->ccb_h.flags & CAM_DIS_DISCONNECT) == 0) 2977 hscb->control |= DISCENB; 2978 2979 if (ccb->ccb_h.func_code == XPT_RESET_DEV) { 2980 hscb->cmdpointer = NULL; 2981 scb->flags |= SCB_DEVICE_RESET; 2982 hscb->control |= MK_MESSAGE; 2983 ahc_execute_scb(scb, NULL, 0, 0); 2984 } else { 2985 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2986 if (tinfo->current.width != tinfo->goal.width) { 2987 if ((ahc->wdtrpending & mask) == 0) { 2988 ahc->wdtrpending |= mask; 2989 hscb->control |= MK_MESSAGE; 2990 scb->flags |= SCB_MSGOUT_WDTR; 2991 } 2992 } else if ((tinfo->current.period 2993 != tinfo->goal.period) 2994 && (ahc->sdtrpending & mask) == 0) { 2995 ahc->sdtrpending |= mask; 2996 hscb->control |= MK_MESSAGE; 2997 scb->flags |= SCB_MSGOUT_SDTR; 2998 } 2999 } else { 3000 if (ahc->pending_device == lstate) { 3001 scb->flags |= SCB_TARGET_IMMEDIATE; 3002 ahc->pending_device = NULL; 3003 } 3004 hscb->control |= TARGET_SCB; 3005 hscb->cmdpointer = IDENTIFY_SEEN; 3006 if ((ccb->ccb_h.flags & CAM_SEND_STATUS) != 0) { 3007 hscb->cmdpointer |= SPHASE_PENDING; 3008 hscb->status = ccb->csio.scsi_status; 3009 } 3010 3011 /* Overloaded with tag ID */ 3012 hscb->cmdlen = ccb->csio.tag_id; 3013 /* 3014 * Overloaded with our target ID to 3015 * use for reselection. 3016 */ 3017 hscb->next = ccb->ccb_h.target_id; 3018 } 3019 if (ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) 3020 hscb->control |= ccb->csio.tag_action; 3021 3022 ahc_setup_data(ahc, &ccb->csio, scb); 3023 } 3024 break; 3025 } 3026 case XPT_NOTIFY_ACK: 3027 case XPT_IMMED_NOTIFY: 3028 { 3029 struct tmode_tstate *tstate; 3030 struct tmode_lstate *lstate; 3031 cam_status status; 3032 3033 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, 3034 &lstate, TRUE); 3035 3036 if (status != CAM_REQ_CMP) { 3037 ccb->ccb_h.status = status; 3038 xpt_done(ccb); 3039 break; 3040 } 3041 if (ccb->ccb_h.func_code == XPT_NOTIFY_ACK) { 3042 /* Clear notification state */ 3043 } 3044 SLIST_INSERT_HEAD(&lstate->immed_notifies, &ccb->ccb_h, 3045 sim_links.sle); 3046 ccb->ccb_h.status = CAM_REQ_INPROG; 3047 break; 3048 } 3049 case XPT_EN_LUN: /* Enable LUN as a target */ 3050 { 3051 struct tmode_tstate *tstate; 3052 struct tmode_lstate *lstate; 3053 struct ccb_en_lun *cel; 3054 cam_status status; 3055 int target; 3056 int lun; 3057 3058 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 3059 /* notfound_failure*/FALSE); 3060 3061 if (status != CAM_REQ_CMP) { 3062 ccb->ccb_h.status = status; 3063 xpt_done(ccb); 3064 break; 3065 } 3066 3067 cel = &ccb->cel; 3068 target = ccb->ccb_h.target_id; 3069 lun = ccb->ccb_h.target_lun; 3070 if (cel->enable != 0) { 3071 /* Are we already enabled?? */ 3072 if (lstate != NULL) { 3073 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 3074 xpt_done(ccb); 3075 break; 3076 } 3077 3078 if (cel->grp6_len != 0 3079 || cel->grp7_len != 0) { 3080 /* 3081 * Don't (yet?) support vendor 3082 * specific commands. 3083 */ 3084 ccb->ccb_h.status = CAM_REQ_INVALID; 3085 xpt_done(ccb); 3086 break; 3087 } 3088 3089 /* 3090 * Seems to be okay. 3091 * Setup our data structures. 3092 */ 3093 if (tstate == NULL) { 3094 tstate = malloc(sizeof(*tstate), 3095 M_DEVBUF, M_NOWAIT); 3096 if (tstate == NULL) { 3097 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 3098 xpt_done(ccb); 3099 break; 3100 } 3101 bzero(tstate, sizeof(*tstate)); 3102 ahc->enabled_targets[target] = tstate; 3103 } 3104 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 3105 if (lstate == NULL) { 3106 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 3107 xpt_done(ccb); 3108 break; 3109 } 3110 bzero(lstate, sizeof(*lstate)); 3111 SLIST_INIT(&lstate->accept_tios); 3112 SLIST_INIT(&lstate->immed_notifies); 3113 tstate->enabled_luns[lun] = lstate; 3114 if ((ahc->features & AHC_MULTI_TID) != 0) { 3115 u_int16_t targid_mask; 3116 3117 pause_sequencer(ahc); 3118 targid_mask = ahc_inb(ahc, TARGID) 3119 | (ahc_inb(ahc, TARGID + 1) << 8); 3120 3121 targid_mask |= (0x01 << target); 3122 ahc_outb(ahc, TARGID, targid_mask); 3123 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 3124 unpause_sequencer(ahc, /*always?*/FALSE); 3125 } 3126 ccb->ccb_h.status = CAM_REQ_CMP; 3127 xpt_print_path(ccb->ccb_h.path); 3128 printf("Lun now enabled for target mode\n"); 3129 xpt_done(ccb); 3130 break; 3131 } else { 3132 /* XXX Fully Implement Disable */ 3133 if (lstate == NULL) { 3134 ccb->ccb_h.status = CAM_LUN_INVALID; 3135 xpt_done(ccb); 3136 break; 3137 } 3138 ccb->ccb_h.status = CAM_REQ_CMP; 3139 xpt_done(ccb); 3140 break; 3141 } 3142 break; 3143 } 3144 case XPT_ABORT: /* Abort the specified CCB */ 3145 /* XXX Implement */ 3146 ccb->ccb_h.status = CAM_REQ_INVALID; 3147 xpt_done(ccb); 3148 break; 3149 case XPT_SET_TRAN_SETTINGS: 3150 { 3151 struct ahc_devinfo devinfo; 3152 struct ccb_trans_settings *cts; 3153 struct ahc_target_tinfo *tinfo; 3154 u_int update_type; 3155 int s; 3156 3157 cts = &ccb->cts; 3158 ahc_compile_devinfo(&devinfo, cts->ccb_h.target_id, 3159 SIM_IS_SCSIBUS_B(ahc, sim) ? 'B' : 'A'); 3160 tinfo = &ahc->transinfo[devinfo.target_offset]; 3161 update_type = 0; 3162 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 3163 update_type |= AHC_TRANS_GOAL; 3164 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 3165 update_type |= AHC_TRANS_USER; 3166 3167 s = splcam(); 3168 3169 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 3170 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0) 3171 ahc->discenable |= devinfo.target_mask; 3172 else 3173 ahc->discenable &= ~devinfo.target_mask; 3174 } 3175 3176 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 3177 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0) 3178 ahc->tagenable |= devinfo.target_mask; 3179 else 3180 ahc->tagenable &= ~devinfo.target_mask; 3181 } 3182 3183 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) { 3184 switch (cts->bus_width) { 3185 case MSG_EXT_WDTR_BUS_16_BIT: 3186 if ((ahc->features & AHC_WIDE) != 0) 3187 break; 3188 /* FALLTHROUGH to 8bit */ 3189 case MSG_EXT_WDTR_BUS_32_BIT: 3190 case MSG_EXT_WDTR_BUS_8_BIT: 3191 default: 3192 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT; 3193 break; 3194 } 3195 if ((update_type & AHC_TRANS_GOAL) != 0) 3196 tinfo->goal.width = cts->bus_width; 3197 if ((update_type & AHC_TRANS_USER) != 0) 3198 tinfo->user.width = cts->bus_width; 3199 } 3200 3201 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) { 3202 struct ahc_syncrate *syncrate; 3203 u_int maxsync; 3204 3205 if ((ahc->features & AHC_ULTRA2) != 0) 3206 maxsync = AHC_SYNCRATE_ULTRA2; 3207 else if ((ahc->features & AHC_ULTRA) != 0) 3208 maxsync = AHC_SYNCRATE_ULTRA; 3209 else 3210 maxsync = AHC_SYNCRATE_FAST; 3211 3212 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0) { 3213 if (cts->sync_offset != 0) 3214 cts->sync_offset = ~0; 3215 } else { 3216 cts->sync_offset = 0; 3217 } 3218 3219 syncrate = ahc_find_syncrate(ahc, &cts->sync_period, 3220 maxsync); 3221 ahc_validate_offset(ahc, syncrate, &cts->sync_offset, 3222 tinfo->goal.width); 3223 3224 /* We use a period of 0 to represent async */ 3225 if (cts->sync_offset == 0) 3226 cts->sync_period = 0; 3227 3228 if ((update_type & AHC_TRANS_GOAL) != 0) { 3229 tinfo->goal.period = cts->sync_period; 3230 tinfo->goal.offset = cts->sync_offset; 3231 } 3232 if ((update_type & AHC_TRANS_USER) != 0) { 3233 tinfo->user.period = cts->sync_period; 3234 tinfo->user.offset = cts->sync_offset; 3235 } 3236 } 3237 splx(s); 3238 ccb->ccb_h.status = CAM_REQ_CMP; 3239 xpt_done(ccb); 3240 break; 3241 } 3242 case XPT_GET_TRAN_SETTINGS: 3243 /* Get default/user set transfer settings for the target */ 3244 { 3245 struct ahc_devinfo devinfo; 3246 struct ccb_trans_settings *cts; 3247 struct ahc_target_tinfo *targ_info; 3248 struct ahc_transinfo *tinfo; 3249 int s; 3250 3251 cts = &ccb->cts; 3252 ahc_compile_devinfo(&devinfo, cts->ccb_h.target_id, 3253 SIM_IS_SCSIBUS_B(ahc, sim) ? 'B' : 'A'); 3254 targ_info = &ahc->transinfo[devinfo.target_offset]; 3255 3256 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 3257 tinfo = &targ_info->current; 3258 else 3259 tinfo = &targ_info->user; 3260 3261 s = splcam(); 3262 3263 cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB); 3264 if ((ahc->discenable & devinfo.target_mask) != 0) 3265 cts->flags |= CCB_TRANS_DISC_ENB; 3266 3267 if ((ahc->tagenable & devinfo.target_mask) != 0) 3268 cts->flags |= CCB_TRANS_TAG_ENB; 3269 3270 cts->sync_period = tinfo->period; 3271 cts->sync_offset = tinfo->offset; 3272 cts->bus_width = tinfo->width; 3273 3274 splx(s); 3275 3276 cts->valid = CCB_TRANS_SYNC_RATE_VALID 3277 | CCB_TRANS_SYNC_OFFSET_VALID 3278 | CCB_TRANS_BUS_WIDTH_VALID 3279 | CCB_TRANS_DISC_VALID 3280 | CCB_TRANS_TQ_VALID; 3281 3282 ccb->ccb_h.status = CAM_REQ_CMP; 3283 xpt_done(ccb); 3284 break; 3285 } 3286 case XPT_CALC_GEOMETRY: 3287 { 3288 struct ccb_calc_geometry *ccg; 3289 u_int32_t size_mb; 3290 u_int32_t secs_per_cylinder; 3291 int extended; 3292 3293 ccg = &ccb->ccg; 3294 size_mb = ccg->volume_size 3295 / ((1024L * 1024L) / ccg->block_size); 3296 extended = SIM_IS_SCSIBUS_B(ahc, sim) 3297 ? ahc->flags & AHC_EXTENDED_TRANS_B 3298 : ahc->flags & AHC_EXTENDED_TRANS_A; 3299 3300 if (size_mb > 1024 && extended) { 3301 ccg->heads = 255; 3302 ccg->secs_per_track = 63; 3303 } else { 3304 ccg->heads = 64; 3305 ccg->secs_per_track = 32; 3306 } 3307 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 3308 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 3309 ccb->ccb_h.status = CAM_REQ_CMP; 3310 xpt_done(ccb); 3311 break; 3312 } 3313 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 3314 { 3315 struct cam_path *path; 3316 char channel; 3317 int found; 3318 3319 s = splcam(); 3320 if (SIM_IS_SCSIBUS_B(ahc, sim)) { 3321 channel = 'B'; 3322 path = ahc->path_b; 3323 } else { 3324 channel = 'A'; 3325 path = ahc->path; 3326 } 3327 found = ahc_reset_channel(ahc, channel, /*initiate reset*/TRUE); 3328 splx(s); 3329 if (bootverbose) { 3330 xpt_print_path(path); 3331 printf("SCSI bus reset delivered. " 3332 "%d SCBs aborted.\n", found); 3333 } 3334 ccb->ccb_h.status = CAM_REQ_CMP; 3335 xpt_done(ccb); 3336 break; 3337 } 3338 case XPT_TERM_IO: /* Terminate the I/O process */ 3339 /* XXX Implement */ 3340 ccb->ccb_h.status = CAM_REQ_INVALID; 3341 xpt_done(ccb); 3342 break; 3343 case XPT_PATH_INQ: /* Path routing inquiry */ 3344 { 3345 struct ccb_pathinq *cpi = &ccb->cpi; 3346 3347 cpi->version_num = 1; /* XXX??? */ 3348 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE; 3349 if ((ahc->features & AHC_WIDE) != 0) 3350 cpi->hba_inquiry |= PI_WIDE_16; 3351 if ((ahc->flags & AHC_TARGETMODE) != 0) { 3352 cpi->target_sprt = PIT_PROCESSOR 3353 | PIT_DISCONNECT 3354 | PIT_TERM_IO; 3355 } else { 3356 cpi->target_sprt = 0; 3357 } 3358 cpi->hba_misc = 0; 3359 cpi->hba_eng_cnt = 0; 3360 cpi->max_target = (ahc->features & AHC_WIDE) ? 15 : 7; 3361 cpi->max_lun = 7; 3362 if (SIM_IS_SCSIBUS_B(ahc, sim)) 3363 cpi->initiator_id = ahc->our_id_b; 3364 else 3365 cpi->initiator_id = ahc->our_id; 3366 cpi->bus_id = cam_sim_bus(sim); 3367 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3368 strncpy(cpi->hba_vid, "Adaptec", HBA_IDLEN); 3369 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 3370 cpi->unit_number = cam_sim_unit(sim); 3371 cpi->ccb_h.status = CAM_REQ_CMP; 3372 xpt_done(ccb); 3373 break; 3374 } 3375 default: 3376 ccb->ccb_h.status = CAM_REQ_INVALID; 3377 xpt_done(ccb); 3378 break; 3379 } 3380} 3381 3382static void 3383ahc_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg) 3384{ 3385 struct ahc_softc *ahc; 3386 struct cam_sim *sim; 3387 3388 sim = (struct cam_sim *)callback_arg; 3389 ahc = (struct ahc_softc *)cam_sim_softc(sim); 3390 switch (code) { 3391 case AC_LOST_DEVICE: 3392 { 3393 struct ahc_devinfo devinfo; 3394 3395 ahc_compile_devinfo(&devinfo, xpt_path_target_id(path), 3396 SIM_IS_SCSIBUS_B(ahc, sim) ? 'B' : 'A'); 3397 3398 /* 3399 * Revert to async/narrow transfers 3400 * for the next device. 3401 */ 3402 pause_sequencer(ahc); 3403 ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, 3404 AHC_TRANS_GOAL|AHC_TRANS_CUR); 3405 ahc_set_syncrate(ahc, &devinfo, path, /*syncrate*/NULL, 3406 /*period*/0, /*offset*/0, 3407 AHC_TRANS_GOAL|AHC_TRANS_CUR); 3408 unpause_sequencer(ahc, /*unpause always*/FALSE); 3409 break; 3410 } 3411 default: 3412 break; 3413 } 3414} 3415 3416static void 3417ahc_execute_scb(void *arg, bus_dma_segment_t *dm_segs, int nsegments, 3418 int error) 3419{ 3420 struct scb *scb; 3421 union ccb *ccb; 3422 struct ahc_softc *ahc; 3423 int s; 3424 3425 scb = (struct scb *)arg; 3426 ccb = scb->ccb; 3427 ahc = (struct ahc_softc *)ccb->ccb_h.ccb_ahc_ptr; 3428 3429 if (nsegments != 0) { 3430 struct ahc_dma_seg *sg; 3431 bus_dma_segment_t *end_seg; 3432 bus_dmasync_op_t op; 3433 3434 end_seg = dm_segs + nsegments; 3435 3436 /* Copy the first SG into the data pointer area */ 3437 scb->hscb->SG_pointer = scb->ahc_dmaphys; 3438 scb->hscb->data = dm_segs->ds_addr; 3439 scb->hscb->datalen = dm_segs->ds_len; 3440 dm_segs++; 3441 3442 /* Copy the remaining segments into our SG list */ 3443 sg = scb->ahc_dma; 3444 while (dm_segs < end_seg) { 3445 sg->addr = dm_segs->ds_addr; 3446 sg->len = dm_segs->ds_len; 3447 sg++; 3448 dm_segs++; 3449 } 3450 3451 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 3452 op = BUS_DMASYNC_PREREAD; 3453 else 3454 op = BUS_DMASYNC_PREWRITE; 3455 3456 bus_dmamap_sync(ahc->dmat, scb->dmamap, op); 3457 } else { 3458 scb->hscb->SG_pointer = 0; 3459 scb->hscb->data = 0; 3460 scb->hscb->datalen = 0; 3461 } 3462 3463 scb->sg_count = scb->hscb->SG_count = nsegments; 3464 3465 s = splcam(); 3466 3467 /* 3468 * Last time we need to check if this SCB needs to 3469 * be aborted. 3470 */ 3471 if (ahc_ccb_status(ccb) != CAM_REQ_INPROG) { 3472 if (nsegments != 0) 3473 bus_dmamap_unload(ahc->dmat, scb->dmamap); 3474 ahc_free_scb(ahc, scb); 3475 xpt_done(ccb); 3476 splx(s); 3477 return; 3478 } 3479 3480 /* Busy this tcl if we are untagged */ 3481 if ((scb->hscb->control & TAG_ENB) == 0) 3482 ahc_busy_tcl(ahc, scb); 3483 3484 LIST_INSERT_HEAD(&ahc->pending_ccbs, &ccb->ccb_h, 3485 sim_links.le); 3486 3487 scb->flags |= SCB_ACTIVE; 3488 ccb->ccb_h.status |= CAM_SIM_QUEUED; 3489 3490 ccb->ccb_h.timeout_ch = 3491 timeout(ahc_timeout, (caddr_t)scb, 3492 (ccb->ccb_h.timeout * hz) / 1000); 3493 3494 if ((scb->flags & SCB_TARGET_IMMEDIATE) != 0) { 3495 xpt_print_path(ccb->ccb_h.path); 3496 printf("Returning an immediate CTIO\n"); 3497 if ((ahc->flags & AHC_PAGESCBS) == 0) 3498 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 3499 ahc_outb(ahc, SCB_TAG, scb->hscb->tag); 3500 unpause_sequencer(ahc, /*unpause_always*/TRUE); 3501 } else { 3502 3503 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 3504 3505 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 3506 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 3507 } else { 3508 pause_sequencer(ahc); 3509 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 3510 unpause_sequencer(ahc, /*unpause_always*/FALSE); 3511 } 3512 } 3513 3514 splx(s); 3515} 3516 3517static void 3518ahc_poll(struct cam_sim *sim) 3519{ 3520 ahc_intr(cam_sim_softc(sim)); 3521} 3522 3523static void 3524ahc_setup_data(struct ahc_softc *ahc, struct ccb_scsiio *csio, 3525 struct scb *scb) 3526{ 3527 struct hardware_scb *hscb; 3528 struct ccb_hdr *ccb_h; 3529 3530 hscb = scb->hscb; 3531 ccb_h = &csio->ccb_h; 3532 3533 if (ccb_h->func_code == XPT_SCSI_IO) { 3534 hscb->cmdlen = csio->cdb_len; 3535 if ((ccb_h->flags & CAM_CDB_POINTER) != 0) { 3536 if ((ccb_h->flags & CAM_CDB_PHYS) == 0) 3537 if (hscb->cmdlen <= 16) { 3538 memcpy(hscb->cmdstore, 3539 csio->cdb_io.cdb_ptr, 3540 hscb->cmdlen); 3541 hscb->cmdpointer = 3542 hscb->cmdstore_busaddr; 3543 } else 3544 hscb->cmdpointer = 3545 vtophys(csio->cdb_io.cdb_ptr); 3546 else 3547 hscb->cmdpointer = 3548 (u_int32_t)csio->cdb_io.cdb_ptr; 3549 } else { 3550 /* 3551 * CCB CDB Data Storage area is only 16 bytes 3552 * so no additional testing is required 3553 */ 3554 memcpy(hscb->cmdstore, csio->cdb_io.cdb_bytes, 3555 hscb->cmdlen); 3556 hscb->cmdpointer = hscb->cmdstore_busaddr; 3557 } 3558 } 3559 3560 /* Only use S/G if there is a transfer */ 3561 if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 3562 if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) { 3563 /* We've been given a pointer to a single buffer */ 3564 if ((ccb_h->flags & CAM_DATA_PHYS) == 0) { 3565 int s; 3566 int error; 3567 3568 s = splsoftvm(); 3569 error = bus_dmamap_load(ahc->dmat, 3570 scb->dmamap, 3571 csio->data_ptr, 3572 csio->dxfer_len, 3573 ahc_execute_scb, 3574 scb, /*flags*/0); 3575 if (error == EINPROGRESS) { 3576 /* 3577 * So as to maintain ordering, 3578 * freeze the controller queue 3579 * until our mapping is 3580 * returned. 3581 */ 3582 xpt_freeze_simq(ahc->sim, 3583 /*count*/1); 3584 scb->ccb->ccb_h.status |= 3585 CAM_RELEASE_SIMQ; 3586 } 3587 splx(s); 3588 } else { 3589 struct bus_dma_segment seg; 3590 3591 /* Pointer to physical buffer */ 3592 if (csio->dxfer_len > AHC_MAXTRANSFER_SIZE) 3593 panic("ahc_setup_data - Transfer size " 3594 "larger than can device max"); 3595 3596 seg.ds_addr = (bus_addr_t)csio->data_ptr; 3597 seg.ds_len = csio->dxfer_len; 3598 ahc_execute_scb(scb, &seg, 1, 0); 3599 } 3600 } else { 3601 struct bus_dma_segment *segs; 3602 3603 if ((ccb_h->flags & CAM_DATA_PHYS) != 0) 3604 panic("ahc_setup_data - Physical segment " 3605 "pointers unsupported"); 3606 3607 if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0) 3608 panic("ahc_setup_data - Virtual segment " 3609 "addresses unsupported"); 3610 3611 /* Just use the segments provided */ 3612 segs = (struct bus_dma_segment *)csio->data_ptr; 3613 ahc_execute_scb(scb, segs, csio->sglist_cnt, 0); 3614 } 3615 if (ccb_h->func_code == XPT_CONT_TARGET_IO) { 3616 hscb->cmdpointer |= DPHASE_PENDING; 3617 if ((ccb_h->flags & CAM_DIR_MASK) == CAM_DIR_IN) 3618 hscb->cmdpointer |= (TARGET_DATA_IN << 8); 3619 } 3620 } else { 3621 ahc_execute_scb(scb, NULL, 0, 0); 3622 } 3623} 3624 3625static void 3626ahc_freeze_devq(struct ahc_softc *ahc, struct cam_path *path) 3627{ 3628 int target; 3629 char channel; 3630 int lun; 3631 3632 target = xpt_path_target_id(path); 3633 lun = xpt_path_lun_id(path); 3634 channel = xpt_path_sim(path)->bus_id == 0 ? 'A' : 'B'; 3635 3636 ahc_search_qinfifo(ahc, target, channel, lun, 3637 /*tag*/SCB_LIST_NULL, CAM_REQUEUE_REQ, 3638 SEARCH_COMPLETE); 3639} 3640 3641/* 3642 * An scb (and hence an scb entry on the board) is put onto the 3643 * free list. 3644 */ 3645static void 3646ahc_free_scb(struct ahc_softc *ahc, struct scb *scb) 3647{ 3648 struct hardware_scb *hscb; 3649 int opri; 3650 3651 hscb = scb->hscb; 3652 3653 opri = splcam(); 3654 3655 if ((ahc->flags & AHC_RESOURCE_SHORTAGE) != 0 3656 && (scb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) { 3657 scb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 3658 ahc->flags &= ~AHC_RESOURCE_SHORTAGE; 3659 } 3660 3661 /* Clean up for the next user */ 3662 scb->flags = SCB_FREE; 3663 hscb->control = 0; 3664 hscb->status = 0; 3665 3666 STAILQ_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links); 3667 splx(opri); 3668} 3669 3670/* 3671 * Get a free scb, either one already assigned to a hardware slot 3672 * on the adapter or one that will require an SCB to be paged out before 3673 * use. If there are none, see if we can allocate a new SCB. Otherwise 3674 * either return an error or sleep. 3675 */ 3676static struct scb * 3677ahc_get_scb(struct ahc_softc *ahc) 3678{ 3679 struct scb *scbp; 3680 int opri; 3681 3682 opri = splcam(); 3683 if ((scbp = STAILQ_FIRST(&ahc->scb_data->free_scbs))) { 3684 STAILQ_REMOVE_HEAD(&ahc->scb_data->free_scbs, links); 3685 } else if (ahc->scb_data->numscbs < ahc->scb_data->maxscbs) { 3686 scbp = ahc_alloc_scb(ahc); 3687 if (scbp == NULL) 3688 printf("%s: Can't malloc SCB\n", ahc_name(ahc)); 3689 } 3690 3691 splx(opri); 3692 3693 return (scbp); 3694} 3695 3696 3697static struct scb * 3698ahc_alloc_scb(struct ahc_softc *ahc) 3699{ 3700 static struct ahc_dma_seg *next_sg_array = NULL; 3701 static int sg_arrays_free = 0; 3702 struct scb *newscb; 3703 int error; 3704 3705 newscb = (struct scb *) malloc(sizeof(struct scb), M_DEVBUF, M_NOWAIT); 3706 if (newscb != NULL) { 3707 bzero(newscb, sizeof(struct scb)); 3708 error = bus_dmamap_create(ahc->dmat, /*flags*/0, 3709 &newscb->dmamap); 3710 if (error != 0) 3711 printf("%s: Unable to allocate SCB dmamap - error %d\n", 3712 ahc_name(ahc), error); 3713 3714 if (error == 0 && next_sg_array == NULL) { 3715 size_t alloc_size = sizeof(struct ahc_dma_seg) 3716 * AHC_NSEG; 3717 sg_arrays_free = PAGE_SIZE / alloc_size; 3718 alloc_size *= sg_arrays_free; 3719 if (alloc_size == 0) 3720 panic("%s: SG list doesn't fit in a page", 3721 ahc_name(ahc)); 3722 next_sg_array = (struct ahc_dma_seg *) 3723 malloc(alloc_size, M_DEVBUF, M_NOWAIT); 3724 } 3725 if (error == 0 && next_sg_array != NULL) { 3726 struct hardware_scb *hscb; 3727 3728 newscb->ahc_dma = next_sg_array; 3729 newscb->ahc_dmaphys = vtophys(next_sg_array); 3730 sg_arrays_free--; 3731 if (sg_arrays_free == 0) 3732 next_sg_array = NULL; 3733 else 3734 next_sg_array = &next_sg_array[AHC_NSEG]; 3735 hscb = &ahc->scb_data->hscbs[ahc->scb_data->numscbs]; 3736 newscb->hscb = hscb; 3737 hscb->control = 0; 3738 hscb->status = 0; 3739 hscb->tag = ahc->scb_data->numscbs; 3740 hscb->residual_data_count[2] = 0; 3741 hscb->residual_data_count[1] = 0; 3742 hscb->residual_data_count[0] = 0; 3743 hscb->residual_SG_count = 0; 3744 hscb->cmdstore_busaddr = 3745 ahc_hscb_busaddr(ahc, hscb->tag) 3746 + offsetof(struct hardware_scb, cmdstore); 3747 /* 3748 * Place in the scbarray 3749 * Never is removed. 3750 */ 3751 ahc->scb_data->scbarray[hscb->tag] = newscb; 3752 ahc->scb_data->numscbs++; 3753 } else { 3754 free(newscb, M_DEVBUF); 3755 newscb = NULL; 3756 } 3757 } 3758 return newscb; 3759} 3760 3761static void 3762ahc_loadseq(struct ahc_softc *ahc) 3763{ 3764 struct patch *cur_patch; 3765 int i; 3766 int downloaded; 3767 int skip_addr; 3768 u_int8_t download_consts[4]; 3769 3770 /* Setup downloadable constant table */ 3771 download_consts[TMODE_NUMCMDS] = ahc->num_targetcmds; 3772 3773 cur_patch = patches; 3774 downloaded = 0; 3775 skip_addr = 0; 3776 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 3777 ahc_outb(ahc, SEQADDR0, 0); 3778 ahc_outb(ahc, SEQADDR1, 0); 3779 3780 for (i = 0; i < sizeof(seqprog)/4; i++) { 3781 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 3782 /* 3783 * Don't download this instruction as it 3784 * is in a patch that was removed. 3785 */ 3786 continue; 3787 } 3788 ahc_download_instr(ahc, i, download_consts); 3789 downloaded++; 3790 } 3791 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 3792 restart_sequencer(ahc); 3793 3794 if (bootverbose) 3795 printf(" %d instructions downloaded\n", downloaded); 3796} 3797 3798static int 3799ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 3800 int start_instr, int *skip_addr) 3801{ 3802 struct patch *cur_patch; 3803 struct patch *last_patch; 3804 int patch_index; 3805 int num_patches; 3806 3807 num_patches = sizeof(patches)/sizeof(struct patch); 3808 last_patch = &patches[num_patches]; 3809 cur_patch = *start_patch; 3810 3811 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 3812 3813 if (cur_patch->patch_func(ahc) == 0) { 3814 int skip; 3815 3816 /* Start rejecting code */ 3817 *skip_addr = start_instr + cur_patch->skip_instr; 3818 cur_patch += cur_patch->skip_patch; 3819 } else { 3820 /* Accepted this patch. Advance to the next 3821 * one and wait for our intruction pointer to 3822 * hit this point. 3823 */ 3824 cur_patch++; 3825 } 3826 } 3827 3828 *start_patch = cur_patch; 3829 if (start_instr < *skip_addr) 3830 /* Still skipping */ 3831 return (0); 3832 3833 return (1); 3834} 3835 3836static void 3837ahc_download_instr(struct ahc_softc *ahc, int instrptr, u_int8_t *dconsts) 3838{ 3839 union ins_formats instr; 3840 struct ins_format1 *fmt1_ins; 3841 struct ins_format3 *fmt3_ins; 3842 int fmt3; 3843 u_int8_t opcode; 3844 3845 /* Structure copy */ 3846 instr = *(union ins_formats*)&seqprog[instrptr * 4]; 3847 3848 fmt1_ins = &instr.format1; 3849 fmt3_ins = NULL; 3850 3851 /* Pull the opcode */ 3852 opcode = instr.format1.opcode; 3853 switch (opcode) { 3854 case AIC_OP_JMP: 3855 case AIC_OP_JC: 3856 case AIC_OP_JNC: 3857 case AIC_OP_CALL: 3858 case AIC_OP_JNE: 3859 case AIC_OP_JNZ: 3860 case AIC_OP_JE: 3861 case AIC_OP_JZ: 3862 { 3863 struct patch *cur_patch; 3864 int address_offset; 3865 u_int address; 3866 int skip_addr; 3867 int i; 3868 3869 fmt3_ins = &instr.format3; 3870 address_offset = 0; 3871 address = fmt3_ins->address; 3872 cur_patch = patches; 3873 skip_addr = 0; 3874 3875 for (i = 0; i < address;) { 3876 3877 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 3878 3879 if (skip_addr > i) { 3880 int end_addr; 3881 3882 end_addr = MIN(address, skip_addr); 3883 address_offset += end_addr - i; 3884 i = skip_addr; 3885 } else { 3886 i++; 3887 } 3888 } 3889 address -= address_offset; 3890 fmt3_ins->address = address; 3891 /* FALLTHROUGH */ 3892 } 3893 case AIC_OP_OR: 3894 case AIC_OP_AND: 3895 case AIC_OP_XOR: 3896 case AIC_OP_ADD: 3897 case AIC_OP_ADC: 3898 case AIC_OP_BMOV: 3899 if (fmt1_ins->parity != 0) { 3900 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 3901 } 3902 fmt1_ins->parity = 0; 3903 /* FALLTHROUGH */ 3904 case AIC_OP_ROL: 3905 if ((ahc->features & AHC_ULTRA2) != 0) { 3906 int i, count; 3907 3908 /* Calculate odd parity for the instruction */ 3909 for (i = 0, count = 0; i < 31; i++) { 3910 u_int32_t mask; 3911 3912 mask = 0x01 << i; 3913 if ((instr.integer & mask) != 0) 3914 count++; 3915 } 3916 if ((count & 0x01) == 0) 3917 instr.format1.parity = 1; 3918 } else { 3919 /* Compress the instruction for older sequencers */ 3920 if (fmt3_ins != NULL) { 3921 instr.integer = 3922 fmt3_ins->immediate 3923 | (fmt3_ins->source << 8) 3924 | (fmt3_ins->address << 16) 3925 | (fmt3_ins->opcode << 25); 3926 } else { 3927 instr.integer = 3928 fmt1_ins->immediate 3929 | (fmt1_ins->source << 8) 3930 | (fmt1_ins->destination << 16) 3931 | (fmt1_ins->ret << 24) 3932 | (fmt1_ins->opcode << 25); 3933 } 3934 } 3935 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 3936 break; 3937 default: 3938 panic("Unknown opcode encountered in seq program"); 3939 break; 3940 } 3941} 3942 3943static void 3944ahc_set_recoveryscb(struct ahc_softc *ahc, struct scb *scb) { 3945 3946 if ((scb->flags & SCB_RECOVERY_SCB) == 0) { 3947 struct ccb_hdr *ccbh; 3948 3949 scb->flags |= SCB_RECOVERY_SCB; 3950 3951 /* 3952 * Take all queued, but not sent SCBs out of the equation. 3953 * Also ensure that no new CCBs are queued to us while we 3954 * try to fix this problem. 3955 */ 3956 if ((scb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) { 3957 xpt_freeze_simq(ahc->sim, /*count*/1); 3958 scb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 3959 } 3960 3961 /* 3962 * Go through all of our pending SCBs and remove 3963 * any scheduled timeouts for them. We will reschedule 3964 * them after we've successfully fixed this problem. 3965 */ 3966 ccbh = ahc->pending_ccbs.lh_first; 3967 while (ccbh != NULL) { 3968 struct scb *pending_scb; 3969 3970 pending_scb = (struct scb *)ccbh->ccb_scb_ptr; 3971 untimeout(ahc_timeout, pending_scb, ccbh->timeout_ch); 3972 ccbh = ccbh->sim_links.le.le_next; 3973 } 3974 } 3975} 3976 3977static void 3978ahc_timeout(void *arg) 3979{ 3980 struct scb *scb; 3981 struct ahc_softc *ahc; 3982 int s, found; 3983 u_int8_t bus_state; 3984 int target; 3985 int lun; 3986 char channel; 3987 3988 scb = (struct scb *)arg; 3989 ahc = (struct ahc_softc *)scb->ccb->ccb_h.ccb_ahc_ptr; 3990 3991 s = splcam(); 3992 3993 /* 3994 * Ensure that the card doesn't do anything 3995 * behind our back. Also make sure that we 3996 * didn't "just" miss an interrupt that would 3997 * affect this timeout. 3998 */ 3999 do { 4000 ahc_intr(ahc); 4001 pause_sequencer(ahc); 4002 } while (ahc_inb(ahc, INTSTAT) & INT_PEND); 4003 4004 if ((scb->flags & SCB_ACTIVE) == 0) { 4005 /* Previous timeout took care of me already */ 4006 printf("Timedout SCB handled by another timeout\n"); 4007 unpause_sequencer(ahc, /*unpause_always*/TRUE); 4008 splx(s); 4009 return; 4010 } 4011 4012 target = SCB_TARGET(scb); 4013 channel = SCB_CHANNEL(scb); 4014 lun = SCB_LUN(scb); 4015 4016 xpt_print_path(scb->ccb->ccb_h.path); 4017 printf("SCB 0x%x - timed out ", scb->hscb->tag); 4018 /* 4019 * Take a snapshot of the bus state and print out 4020 * some information so we can track down driver bugs. 4021 */ 4022 bus_state = ahc_inb(ahc, LASTPHASE); 4023 4024 switch(bus_state) 4025 { 4026 case P_DATAOUT: 4027 printf("in dataout phase"); 4028 break; 4029 case P_DATAIN: 4030 printf("in datain phase"); 4031 break; 4032 case P_COMMAND: 4033 printf("in command phase"); 4034 break; 4035 case P_MESGOUT: 4036 printf("in message out phase"); 4037 break; 4038 case P_STATUS: 4039 printf("in status phase"); 4040 break; 4041 case P_MESGIN: 4042 printf("in message in phase"); 4043 break; 4044 case P_BUSFREE: 4045 printf("while idle, LASTPHASE == 0x%x", 4046 bus_state); 4047 break; 4048 default: 4049 /* 4050 * We aren't in a valid phase, so assume we're 4051 * idle. 4052 */ 4053 printf("invalid phase, LASTPHASE == 0x%x", 4054 bus_state); 4055 bus_state = P_BUSFREE; 4056 break; 4057 } 4058 4059 printf(", SCSISIGI == 0x%x\n", ahc_inb(ahc, SCSISIGI)); 4060 4061 printf("SEQADDR == 0x%x\n", ahc_inb(ahc, SEQADDR0) 4062 | (ahc_inb(ahc, SEQADDR1) << 8)); 4063 printf("SSTAT1 == 0x%x\n", ahc_inb(ahc, SSTAT1)); 4064#if 0 4065 printf("SCSIRATE == 0x%x\n", ahc_inb(ahc, SCSIRATE)); 4066 printf("CCSCBCTL == 0x%x\n", ahc_inb(ahc, CCSCBCTL)); 4067 printf("CCSCBCNT == 0x%x\n", ahc_inb(ahc, CCSCBCNT)); 4068 printf("DFCNTRL == 0x%x\n", ahc_inb(ahc, DFCNTRL)); 4069 printf("DFSTATUS == 0x%x\n", ahc_inb(ahc, DFSTATUS)); 4070 printf("CCHCNT == 0x%x\n", ahc_inb(ahc, CCHCNT)); 4071#endif 4072 /* Decide our course of action */ 4073 if (scb->flags & SCB_DEVICE_RESET) { 4074 /* 4075 * Been down this road before. 4076 * Do a full bus reset. 4077 */ 4078bus_reset: 4079 ahc_set_ccb_status(scb->ccb, CAM_CMD_TIMEOUT); 4080 found = ahc_reset_channel(ahc, channel, /*Initiate Reset*/TRUE); 4081 printf("%s: Issued Channel %c Bus Reset. " 4082 "%d SCBs aborted\n", ahc_name(ahc), channel, found); 4083 } else { 4084 /* 4085 * Send a Bus Device Reset message: 4086 * The target that is holding up the bus may not 4087 * be the same as the one that triggered this timeout 4088 * (different commands have different timeout lengths). 4089 * Our strategy here is to queue a BDR message 4090 * to the timed out target if the bus is idle. 4091 * Otherwise, if we have an active target we stuff the 4092 * message buffer with a BDR message and assert ATN 4093 * in the hopes that the target will let go of the bus 4094 * and go to the mesgout phase. If this fails, we'll 4095 * get another timeout 2 seconds later which will attempt 4096 * a bus reset. 4097 */ 4098 u_int8_t active_scb_index; 4099 4100 active_scb_index = ahc_inb(ahc, SCB_TAG); 4101 4102 if (bus_state != P_BUSFREE 4103 && (active_scb_index < ahc->scb_data->numscbs)) { 4104 struct scb *active_scb; 4105 4106 /* 4107 * If the active SCB is not from our device, 4108 * assume that another device is hogging the bus 4109 * and wait for it's timeout to expire before 4110 * taking addition action. 4111 */ 4112 active_scb = ahc->scb_data->scbarray[active_scb_index]; 4113 if (active_scb->hscb->tcl != scb->hscb->tcl 4114 && (scb->flags & SCB_OTHERTCL_TIMEOUT) == 0) { 4115 struct ccb_hdr *ccbh; 4116 u_int newtimeout; 4117 4118 scb->flags |= SCB_OTHERTCL_TIMEOUT; 4119 newtimeout = MAX(active_scb->ccb->ccb_h.timeout, 4120 scb->ccb->ccb_h.timeout); 4121 ccbh = &scb->ccb->ccb_h; 4122 scb->ccb->ccb_h.timeout_ch = 4123 timeout(ahc_timeout, scb, 4124 (newtimeout * hz) / 1000); 4125 splx(s); 4126 return; 4127 } 4128 ahc_set_recoveryscb(ahc, active_scb); 4129 ahc_outb(ahc, MSG_OUT, MSG_BUS_DEV_RESET); 4130 ahc_outb(ahc, SCSISIGO, bus_state|ATNO); 4131 xpt_print_path(active_scb->ccb->ccb_h.path); 4132 printf("BDR message in message buffer\n"); 4133 active_scb->flags |= SCB_DEVICE_RESET; 4134 active_scb->ccb->ccb_h.timeout_ch = 4135 timeout(ahc_timeout, (caddr_t)active_scb, 2 * hz); 4136 unpause_sequencer(ahc, /*unpause_always*/TRUE); 4137 } else { 4138 int disconnected; 4139 4140 if (ahc_search_qinfifo(ahc, target, channel, lun, 4141 scb->hscb->tag, /*status*/0, 4142 SEARCH_COUNT) > 0) { 4143 disconnected = FALSE; 4144 } else { 4145 disconnected = TRUE; 4146 } 4147 4148 if (disconnected) { 4149 u_int8_t hscb_index; 4150 4151 ahc_set_recoveryscb(ahc, scb); 4152 /* 4153 * Simply set the MK_MESSAGE control bit. 4154 */ 4155 scb->hscb->control |= MK_MESSAGE; 4156 scb->flags |= SCB_QUEUED_MSG 4157 | SCB_DEVICE_RESET; 4158 hscb_index = ahc_find_scb(ahc, scb); 4159 if (hscb_index != SCB_LIST_NULL) { 4160 u_int8_t scb_control; 4161 u_int8_t saved_scbptr; 4162 4163 saved_scbptr = ahc_inb(ahc, SCBPTR); 4164 ahc_outb(ahc, SCBPTR, hscb_index); 4165 scb_control = ahc_inb(ahc, SCB_CONTROL); 4166 ahc_outb(ahc, SCB_CONTROL, 4167 scb_control | MK_MESSAGE); 4168 ahc_outb(ahc, SCBPTR, saved_scbptr); 4169 } 4170 /* 4171 * Actually re-queue this SCB in case we can 4172 * select the device before it reconnects. 4173 * Clear out any entries in the QINFIFO first 4174 * so we are the next SCB for this target 4175 * to run. 4176 */ 4177 ahc_search_qinfifo(ahc, SCB_TARGET(scb), 4178 channel, SCB_LUN(scb), 4179 SCB_LIST_NULL, 4180 CAM_REQUEUE_REQ, 4181 SEARCH_COMPLETE); 4182 xpt_print_path(scb->ccb->ccb_h.path); 4183 printf("Queuing a BDR SCB\n"); 4184 ahc->qinfifo[ahc->qinfifonext++] = 4185 scb->hscb->tag; 4186 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4187 ahc_outb(ahc, HNSCB_QOFF, 4188 ahc->qinfifonext); 4189 } else { 4190 ahc_outb(ahc, KERNEL_QINPOS, 4191 ahc->qinfifonext); 4192 } 4193 scb->ccb->ccb_h.timeout_ch = 4194 timeout(ahc_timeout, (caddr_t)scb, 2 * hz); 4195 unpause_sequencer(ahc, /*unpause_always*/FALSE); 4196 } else { 4197 /* Go "immediatly" to the bus reset */ 4198 /* This shouldn't happen */ 4199 ahc_set_recoveryscb(ahc, scb); 4200 xpt_print_path(scb->ccb->ccb_h.path); 4201 printf("SCB %d: Immediate reset. " 4202 "Flags = 0x%x\n", scb->hscb->tag, 4203 scb->flags); 4204 goto bus_reset; 4205 } 4206 } 4207 } 4208 splx(s); 4209} 4210 4211/* 4212 * Look through the SCB array of the card and attempt to find the 4213 * hardware SCB that corresponds to the passed in SCB. Return 4214 * SCB_LIST_NULL if unsuccessful. This routine assumes that the 4215 * card is already paused. 4216 */ 4217static u_int8_t 4218ahc_find_scb(struct ahc_softc *ahc, struct scb *scb) 4219{ 4220 u_int8_t saved_scbptr; 4221 u_int8_t curindex; 4222 4223 saved_scbptr = ahc_inb(ahc, SCBPTR); 4224 for (curindex = 0; curindex < ahc->scb_data->maxhscbs; curindex++) { 4225 ahc_outb(ahc, SCBPTR, curindex); 4226 if (ahc_inb(ahc, SCB_TAG) == scb->hscb->tag) 4227 break; 4228 } 4229 ahc_outb(ahc, SCBPTR, saved_scbptr); 4230 if (curindex >= ahc->scb_data->maxhscbs) 4231 curindex = SCB_LIST_NULL; 4232 4233 return curindex; 4234} 4235 4236static int 4237ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 4238 int lun, u_int8_t tag, u_int32_t status, 4239 ahc_search_action action) 4240{ 4241 struct scb *scbp; 4242 u_int8_t qinpos; 4243 u_int8_t qintail; 4244 int found; 4245 4246 qinpos = ahc_inb(ahc, QINPOS); 4247 qintail = ahc->qinfifonext; 4248 found = 0; 4249 4250 /* 4251 * Start with an empty queue. Entries that are not chosen 4252 * for removal will be re-added to the queue as we go. 4253 */ 4254 ahc->qinfifonext = qinpos; 4255 4256 while (qinpos != qintail) { 4257 scbp = ahc->scb_data->scbarray[ahc->qinfifo[qinpos]]; 4258 if (ahc_match_scb(scbp, target, channel, lun, tag)) { 4259 /* 4260 * We found an scb that needs to be removed. 4261 */ 4262 switch (action) { 4263 case SEARCH_COMPLETE: 4264 if (ahc_ccb_status(scbp->ccb) == CAM_REQ_INPROG) 4265 ahc_set_ccb_status(scbp->ccb, status); 4266 ahc_freeze_ccb(scbp->ccb); 4267 ahc_done(ahc, scbp); 4268 break; 4269 case SEARCH_COUNT: 4270 ahc->qinfifo[ahc->qinfifonext++] = 4271 scbp->hscb->tag; 4272 break; 4273 case SEARCH_REMOVE: 4274 break; 4275 } 4276 found++; 4277 } else { 4278 ahc->qinfifo[ahc->qinfifonext++] = scbp->hscb->tag; 4279 } 4280 qinpos++; 4281 } 4282 4283 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4284 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4285 } else { 4286 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4287 } 4288 4289 return (found); 4290} 4291 4292 4293/* 4294 * Abort all SCBs that match the given description (target/channel/lun/tag), 4295 * setting their status to the passed in status if the status has not already 4296 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 4297 * is paused before it is called. 4298 */ 4299static int 4300ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 4301 int lun, u_int8_t tag, u_int32_t status) 4302{ 4303 struct scb *scbp; 4304 u_int8_t active_scb; 4305 int i; 4306 int found; 4307 4308 /* restore this when we're done */ 4309 active_scb = ahc_inb(ahc, SCBPTR); 4310 4311 found = ahc_search_qinfifo(ahc, target, channel, lun, tag, 4312 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 4313 4314 /* 4315 * Search waiting for selection list. 4316 */ 4317 { 4318 u_int8_t next, prev; 4319 4320 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 4321 prev = SCB_LIST_NULL; 4322 4323 while (next != SCB_LIST_NULL) { 4324 u_int8_t scb_index; 4325 4326 ahc_outb(ahc, SCBPTR, next); 4327 scb_index = ahc_inb(ahc, SCB_TAG); 4328 if (scb_index >= ahc->scb_data->numscbs) { 4329 panic("Waiting List inconsistency. " 4330 "SCB index == %d, yet numscbs == %d.", 4331 scb_index, ahc->scb_data->numscbs); 4332 } 4333 scbp = ahc->scb_data->scbarray[scb_index]; 4334 if (ahc_match_scb(scbp, target, channel, lun, tag)) { 4335 4336 next = ahc_abort_wscb(ahc, next, prev); 4337 } else { 4338 4339 prev = next; 4340 next = ahc_inb(ahc, SCB_NEXT); 4341 } 4342 } 4343 } 4344 /* 4345 * Go through the disconnected list and remove any entries we 4346 * have queued for completion, 0'ing their control byte too. 4347 */ 4348 { 4349 u_int8_t next, prev; 4350 4351 next = ahc_inb(ahc, DISCONNECTED_SCBH); 4352 prev = SCB_LIST_NULL; 4353 4354 while (next != SCB_LIST_NULL) { 4355 u_int8_t scb_index; 4356 4357 ahc_outb(ahc, SCBPTR, next); 4358 scb_index = ahc_inb(ahc, SCB_TAG); 4359 if (scb_index >= ahc->scb_data->numscbs) { 4360 panic("Disconnected List inconsistency. " 4361 "SCB index == %d, yet numscbs == %d.", 4362 scb_index, ahc->scb_data->numscbs); 4363 } 4364 scbp = ahc->scb_data->scbarray[scb_index]; 4365 if (ahc_match_scb(scbp, target, channel, lun, tag)) { 4366 next = ahc_rem_scb_from_disc_list(ahc, prev, 4367 next); 4368 } else { 4369 prev = next; 4370 next = ahc_inb(ahc, SCB_NEXT); 4371 } 4372 } 4373 } 4374 /* 4375 * Go through the hardware SCB array looking for commands that 4376 * were active but not on any list. 4377 */ 4378 for(i = 0; i < ahc->scb_data->maxhscbs; i++) { 4379 u_int8_t scbid; 4380 4381 ahc_outb(ahc, SCBPTR, i); 4382 scbid = ahc_inb(ahc, SCB_TAG); 4383 if (scbid < ahc->scb_data->numscbs) { 4384 scbp = ahc->scb_data->scbarray[scbid]; 4385 if (ahc_match_scb(scbp, target, channel, lun, tag)) { 4386 ahc_add_curscb_to_free_list(ahc); 4387 } 4388 } 4389 } 4390 /* 4391 * Go through the pending CCB list and look for 4392 * commands for this target that are still active. 4393 * These are other tagged commands that were 4394 * disconnected when the reset occured. 4395 */ 4396 { 4397 struct ccb_hdr *ccb_h; 4398 4399 4400 ccb_h = ahc->pending_ccbs.lh_first; 4401 4402 while (ccb_h != NULL) { 4403 scbp = (struct scb *)ccb_h->ccb_scb_ptr; 4404 ccb_h = ccb_h->sim_links.le.le_next; 4405 if (ahc_match_scb(scbp, target, channel, lun, tag)) { 4406 if (ahc_ccb_status(scbp->ccb) == CAM_REQ_INPROG) 4407 ahc_set_ccb_status(scbp->ccb, status); 4408 ahc_freeze_ccb(scbp->ccb); 4409 ahc_done(ahc, scbp); 4410 found++; 4411 } 4412 } 4413 } 4414 ahc_outb(ahc, SCBPTR, active_scb); 4415 return found; 4416} 4417 4418static u_int8_t 4419ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int8_t prev, u_int8_t scbptr) 4420{ 4421 u_int8_t next; 4422 4423 ahc_outb(ahc, SCBPTR, scbptr); 4424 next = ahc_inb(ahc, SCB_NEXT); 4425 4426 ahc_outb(ahc, SCB_CONTROL, 0); 4427 4428 ahc_add_curscb_to_free_list(ahc); 4429 4430 if (prev != SCB_LIST_NULL) { 4431 ahc_outb(ahc, SCBPTR, prev); 4432 ahc_outb(ahc, SCB_NEXT, next); 4433 } else 4434 ahc_outb(ahc, DISCONNECTED_SCBH, next); 4435 4436 return next; 4437} 4438 4439static void 4440ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 4441{ 4442 /* Invalidate the tag so that ahc_find_scb doesn't think it's active */ 4443 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4444 4445 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 4446 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 4447} 4448 4449/* 4450 * Manipulate the waiting for selection list and return the 4451 * scb that follows the one that we remove. 4452 */ 4453static u_int8_t 4454ahc_abort_wscb(struct ahc_softc *ahc, u_int8_t scbpos, u_int8_t prev) 4455{ 4456 u_int8_t curscb, next; 4457 4458 /* 4459 * Select the SCB we want to abort and 4460 * pull the next pointer out of it. 4461 */ 4462 curscb = ahc_inb(ahc, SCBPTR); 4463 ahc_outb(ahc, SCBPTR, scbpos); 4464 next = ahc_inb(ahc, SCB_NEXT); 4465 4466 /* Clear the necessary fields */ 4467 ahc_outb(ahc, SCB_CONTROL, 0); 4468 4469 ahc_add_curscb_to_free_list(ahc); 4470 4471 /* update the waiting list */ 4472 if (prev == SCB_LIST_NULL) { 4473 /* First in the list */ 4474 ahc_outb(ahc, WAITING_SCBH, next); 4475 4476 /* 4477 * Ensure we aren't attempting to perform 4478 * selection for this entry. 4479 */ 4480 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 4481 } else { 4482 /* 4483 * Select the scb that pointed to us 4484 * and update its next pointer. 4485 */ 4486 ahc_outb(ahc, SCBPTR, prev); 4487 ahc_outb(ahc, SCB_NEXT, next); 4488 } 4489 4490 /* 4491 * Point us back at the original scb position. 4492 */ 4493 ahc_outb(ahc, SCBPTR, curscb); 4494 return next; 4495} 4496 4497static void 4498ahc_clear_intstat(struct ahc_softc *ahc) 4499{ 4500 /* Clear any interrupt conditions this may have caused */ 4501 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 4502 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 4503 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 4504 CLRREQINIT); 4505 ahc_outb(ahc, CLRINT, CLRSCSIINT); 4506} 4507 4508static void 4509ahc_reset_current_bus(struct ahc_softc *ahc) 4510{ 4511 u_int8_t scsiseq; 4512 4513 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 4514 scsiseq = ahc_inb(ahc, SCSISEQ); 4515 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 4516 DELAY(AHC_BUSRESET_DELAY); 4517 /* Turn off the bus reset */ 4518 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 4519 4520 ahc_clear_intstat(ahc); 4521 4522 /* Re-enable reset interrupts */ 4523 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 4524} 4525 4526static int 4527ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 4528{ 4529 u_int target, max_target; 4530 int found; 4531 u_int8_t sblkctl; 4532 char cur_channel; 4533 struct cam_path *path; 4534 4535 pause_sequencer(ahc); 4536 /* 4537 * Clean up all the state information for the 4538 * pending transactions on this bus. 4539 */ 4540 found = ahc_abort_scbs(ahc, ALL_TARGETS, channel, ALL_LUNS, 4541 SCB_LIST_NULL, CAM_SCSI_BUS_RESET); 4542 path = channel == 'B' ? ahc->path_b : ahc->path; 4543 4544 /* Notify the XPT that a bus reset occurred */ 4545 xpt_async(AC_BUS_RESET, path, NULL); 4546 4547 /* 4548 * Revert to async/narrow transfers until we renegotiate. 4549 */ 4550 max_target = (ahc->features & AHC_WIDE) ? 15 : 7; 4551 for (target = 0; target <= max_target; target++) { 4552 struct ahc_devinfo devinfo; 4553 4554 ahc_compile_devinfo(&devinfo, target, channel); 4555 ahc_set_width(ahc, &devinfo, path, MSG_EXT_WDTR_BUS_8_BIT, 4556 AHC_TRANS_CUR); 4557 ahc_set_syncrate(ahc, &devinfo, path, /*syncrate*/NULL, 4558 /*period*/0, /*offset*/0, AHC_TRANS_CUR); 4559 } 4560 4561 /* 4562 * Reset the bus if we are initiating this reset and 4563 * restart/unpause the sequencer 4564 */ 4565 sblkctl = ahc_inb(ahc, SBLKCTL); 4566 cur_channel = 'A'; 4567 if ((ahc->features & AHC_TWIN) != 0 4568 && ((sblkctl & SELBUSB) != 0)) 4569 cur_channel = 'B'; 4570 if (cur_channel != channel) { 4571 /* Case 1: Command for another bus is active 4572 * Stealthily reset the other bus without 4573 * upsetting the current bus. 4574 */ 4575 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 4576 ahc_outb(ahc, SIMODE1, 4577 ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENREQINIT)); 4578 ahc_outb(ahc, SCSISEQ, 4579 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 4580 if (initiate_reset) 4581 ahc_reset_current_bus(ahc); 4582 ahc_clear_intstat(ahc); 4583 ahc_outb(ahc, SBLKCTL, sblkctl); 4584 unpause_sequencer(ahc, /*unpause_always*/FALSE); 4585 } else { 4586 /* Case 2: A command from this bus is active or we're idle */ 4587 ahc_outb(ahc, SIMODE1, 4588 ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENREQINIT)); 4589 ahc->flags &= ~AHC_HANDLING_REQINITS; 4590 ahc->msg_type = MSG_TYPE_NONE; 4591 ahc_outb(ahc, SCSISEQ, 4592 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 4593 if (initiate_reset) 4594 ahc_reset_current_bus(ahc); 4595 ahc_clear_intstat(ahc); 4596 restart_sequencer(ahc); 4597 } 4598 return found; 4599} 4600 4601static int 4602ahc_match_scb (struct scb *scb, int target, char channel, 4603 int lun, u_int8_t tag) 4604{ 4605 int targ = SCB_TARGET(scb); 4606 char chan = SCB_CHANNEL(scb); 4607 int slun = SCB_LUN(scb); 4608 int match; 4609 4610 match = ((chan == channel) || (channel == ALL_CHANNELS)); 4611 if (match != 0) 4612 match = ((targ == target) || (target == ALL_TARGETS)); 4613 if (match != 0) 4614 match = ((lun == slun) || (lun == ALL_LUNS)); 4615 if (match != 0) 4616 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 4617 4618 return match; 4619} 4620 4621static void 4622ahc_construct_sdtr(struct ahc_softc *ahc, u_int8_t period, u_int8_t offset) 4623{ 4624 ahc->msg_buf[ahc->msg_index++] = MSG_EXTENDED; 4625 ahc->msg_buf[ahc->msg_index++] = MSG_EXT_SDTR_LEN; 4626 ahc->msg_buf[ahc->msg_index++] = MSG_EXT_SDTR; 4627 ahc->msg_buf[ahc->msg_index++] = period; 4628 ahc->msg_buf[ahc->msg_index++] = offset; 4629 ahc->msg_len += 5; 4630} 4631 4632static void 4633ahc_construct_wdtr(struct ahc_softc *ahc, u_int8_t bus_width) 4634{ 4635 ahc->msg_buf[ahc->msg_index++] = MSG_EXTENDED; 4636 ahc->msg_buf[ahc->msg_index++] = MSG_EXT_WDTR_LEN; 4637 ahc->msg_buf[ahc->msg_index++] = MSG_EXT_WDTR; 4638 ahc->msg_buf[ahc->msg_index++] = bus_width; 4639 ahc->msg_len += 4; 4640} 4641 4642static void 4643ahc_calc_residual(struct scb *scb) 4644{ 4645 struct hardware_scb *hscb; 4646 4647 hscb = scb->hscb; 4648 4649 /* 4650 * If the disconnected flag is still set, this is bogus 4651 * residual information left over from a sequencer 4652 * pagin/pageout, so ignore this case. 4653 */ 4654 if ((scb->hscb->control & DISCONNECTED) == 0) { 4655 u_int32_t resid; 4656 int resid_sgs; 4657 int sg; 4658 4659 /* 4660 * Remainder of the SG where the transfer 4661 * stopped. 4662 */ 4663 resid = (hscb->residual_data_count[2] << 16) 4664 | (hscb->residual_data_count[1] <<8) 4665 | (hscb->residual_data_count[0]); 4666 4667 /* 4668 * Add up the contents of all residual 4669 * SG segments that are after the SG where 4670 * the transfer stopped. 4671 */ 4672 resid_sgs = scb->hscb->residual_SG_count - 1/*current*/; 4673 sg = scb->sg_count - resid_sgs - 1/*first SG*/; 4674 while (resid_sgs > 0) { 4675 4676 resid += scb->ahc_dma[sg].len; 4677 sg++; 4678 resid_sgs--; 4679 } 4680 if ((scb->flags & SCB_SENSE) == 0) { 4681 4682 scb->ccb->csio.resid = resid; 4683 } else { 4684 4685 scb->ccb->csio.sense_resid = resid; 4686 } 4687 } 4688 4689 /* 4690 * Clean out the residual information in this SCB for its 4691 * next consumer. 4692 */ 4693 hscb->residual_data_count[0] = 0; 4694 hscb->residual_data_count[1] = 0; 4695 hscb->residual_data_count[2] = 0; 4696 hscb->residual_SG_count = 0; 4697 4698#ifdef AHC_DEBUG 4699 if (ahc_debug & AHC_SHOWMISC) { 4700 sc_print_addr(xs->sc_link); 4701 printf("Handled Residual of %ld bytes\n" ,xs->resid); 4702 } 4703#endif 4704} 4705 4706static void 4707ahc_update_pending_syncrates(struct ahc_softc *ahc) 4708{ 4709 /* 4710 * Traverse the pending SCB list and ensure that all of the 4711 * SCBs there have the proper settings. 4712 */ 4713 struct ccb_hdr *ccbh; 4714 int pending_ccb_count; 4715 int i; 4716 u_int saved_scbptr; 4717 4718 /* 4719 * We were able to complete the command successfully, 4720 * so reinstate the timeouts for all other pending 4721 * commands. 4722 */ 4723 ccbh = LIST_FIRST(&ahc->pending_ccbs); 4724 pending_ccb_count = 0; 4725 while (ccbh != NULL) { 4726 struct scb *pending_scb; 4727 struct hardware_scb *pending_hscb; 4728 struct ahc_target_tinfo *tinfo; 4729 struct ahc_devinfo devinfo; 4730 4731 pending_scb = (struct scb *)ccbh->ccb_scb_ptr; 4732 pending_hscb = pending_scb->hscb; 4733 ahc_compile_devinfo(&devinfo, SCB_TARGET(pending_scb), 4734 SCB_CHANNEL(pending_scb)); 4735 tinfo = &ahc->transinfo[devinfo.target_offset]; 4736 pending_hscb->control &= ~ULTRAENB; 4737 if ((ahc->ultraenb & devinfo.target_mask) != 0) 4738 pending_hscb->control |= ULTRAENB; 4739 pending_hscb->scsirate = tinfo->scsirate; 4740 pending_hscb->scsioffset = tinfo->current.offset; 4741 pending_ccb_count++; 4742 ccbh = LIST_NEXT(ccbh, sim_links.le); 4743 } 4744 4745 if (pending_ccb_count == 0) 4746 return; 4747 4748 saved_scbptr = ahc_inb(ahc, SCBPTR); 4749 /* Ensure that the hscbs down on the card match the new information */ 4750 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4751 u_int scb_tag; 4752 4753 ahc_outb(ahc, SCBPTR, i); 4754 scb_tag = ahc_inb(ahc, SCB_TAG); 4755 if (scb_tag != SCB_LIST_NULL) { 4756 struct scb *pending_scb; 4757 struct hardware_scb *pending_hscb; 4758 struct ahc_target_tinfo *tinfo; 4759 struct ahc_devinfo devinfo; 4760 u_int control; 4761 4762 pending_scb = ahc->scb_data->scbarray[scb_tag]; 4763 pending_hscb = pending_scb->hscb; 4764 ahc_compile_devinfo(&devinfo, SCB_TARGET(pending_scb), 4765 SCB_CHANNEL(pending_scb)); 4766 tinfo = &ahc->transinfo[devinfo.target_offset]; 4767 control = ahc_inb(ahc, SCB_CONTROL); 4768 control &= ~ULTRAENB; 4769 if ((ahc->ultraenb & devinfo.target_mask) != 0) 4770 control |= ULTRAENB; 4771 ahc_outb(ahc, SCB_CONTROL, control); 4772 ahc_outb(ahc, SCB_SCSIRATE, tinfo->scsirate); 4773 ahc_outb(ahc, SCB_SCSIOFFSET, tinfo->current.offset); 4774 } 4775 } 4776 ahc_outb(ahc, SCBPTR, saved_scbptr); 4777} 4778 4779static void 4780ahc_dump_targcmd(struct target_cmd *cmd) 4781{ 4782 u_int8_t *byte; 4783 u_int8_t *last_byte; 4784 int initiator; 4785 int target; 4786 int lun; 4787 int i; 4788 4789 byte = &cmd->icl; 4790 /* Debugging info for received commands */ 4791 last_byte = &cmd[1].icl; 4792 4793 i = 0; 4794 while (byte < last_byte) { 4795 if (i == 0) 4796 printf("\t"); 4797 printf("%#x", *byte++); 4798 i++; 4799 if (i == 8) { 4800 printf("\n"); 4801 i = 0; 4802 } else { 4803 printf(", "); 4804 } 4805 } 4806} 4807 4808static void 4809ahc_shutdown(int howto, void *arg) 4810{ 4811 struct ahc_softc *ahc; 4812 int i; 4813 4814 ahc = (struct ahc_softc *)arg; 4815 4816 ahc_reset(ahc); 4817 ahc_outb(ahc, SCSISEQ, 0); 4818 ahc_outb(ahc, SXFRCTL0, 0); 4819 ahc_outb(ahc, DSPCISTATUS, 0); 4820 4821 for (i = TARG_SCSIRATE; i < HA_274_BIOSCTRL; i++) 4822 ahc_outb(ahc, i, 0); 4823} 4824