aic7xxx.c revision 115333
1/* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#130 $ 41 * 42 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.c 115333 2003-05-26 21:24:01Z gibbs $ 43 */ 44 45#ifdef __linux__ 46#include "aic7xxx_osm.h" 47#include "aic7xxx_inline.h" 48#include "aicasm/aicasm_insformat.h" 49#else 50#include <dev/aic7xxx/aic7xxx_osm.h> 51#include <dev/aic7xxx/aic7xxx_inline.h> 52#include <dev/aic7xxx/aicasm/aicasm_insformat.h> 53#endif 54 55/****************************** Softc Data ************************************/ 56struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); 57 58/***************************** Lookup Tables **********************************/ 59char *ahc_chip_names[] = 60{ 61 "NONE", 62 "aic7770", 63 "aic7850", 64 "aic7855", 65 "aic7859", 66 "aic7860", 67 "aic7870", 68 "aic7880", 69 "aic7895", 70 "aic7895C", 71 "aic7890/91", 72 "aic7896/97", 73 "aic7892", 74 "aic7899" 75}; 76static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names); 77 78/* 79 * Hardware error codes. 80 */ 81struct ahc_hard_error_entry { 82 uint8_t errno; 83 char *errmesg; 84}; 85 86static struct ahc_hard_error_entry ahc_hard_errors[] = { 87 { ILLHADDR, "Illegal Host Access" }, 88 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 89 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 90 { SQPARERR, "Sequencer Parity Error" }, 91 { DPARERR, "Data-path Parity Error" }, 92 { MPARERR, "Scratch or SCB Memory Parity Error" }, 93 { PCIERRSTAT, "PCI Error detected" }, 94 { CIOPARERR, "CIOBUS Parity Error" }, 95}; 96static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors); 97 98static struct ahc_phase_table_entry ahc_phase_table[] = 99{ 100 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 101 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 102 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 103 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 104 { P_COMMAND, MSG_NOOP, "in Command phase" }, 105 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 106 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 107 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 108 { P_BUSFREE, MSG_NOOP, "while idle" }, 109 { 0, MSG_NOOP, "in unknown phase" } 110}; 111 112/* 113 * In most cases we only wish to itterate over real phases, so 114 * exclude the last element from the count. 115 */ 116static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1; 117 118/* 119 * Valid SCSIRATE values. (p. 3-17) 120 * Provides a mapping of tranfer periods in ns to the proper value to 121 * stick in the scsixfer reg. 122 */ 123static struct ahc_syncrate ahc_syncrates[] = 124{ 125 /* ultra2 fast/ultra period rate */ 126 { 0x42, 0x000, 9, "80.0" }, 127 { 0x03, 0x000, 10, "40.0" }, 128 { 0x04, 0x000, 11, "33.0" }, 129 { 0x05, 0x100, 12, "20.0" }, 130 { 0x06, 0x110, 15, "16.0" }, 131 { 0x07, 0x120, 18, "13.4" }, 132 { 0x08, 0x000, 25, "10.0" }, 133 { 0x19, 0x010, 31, "8.0" }, 134 { 0x1a, 0x020, 37, "6.67" }, 135 { 0x1b, 0x030, 43, "5.7" }, 136 { 0x1c, 0x040, 50, "5.0" }, 137 { 0x00, 0x050, 56, "4.4" }, 138 { 0x00, 0x060, 62, "4.0" }, 139 { 0x00, 0x070, 68, "3.6" }, 140 { 0x00, 0x000, 0, NULL } 141}; 142 143/* Our Sequencer Program */ 144#include "aic7xxx_seq.h" 145 146/**************************** Function Declarations ***************************/ 147static void ahc_force_renegotiation(struct ahc_softc *ahc, 148 struct ahc_devinfo *devinfo); 149static struct ahc_tmode_tstate* 150 ahc_alloc_tstate(struct ahc_softc *ahc, 151 u_int scsi_id, char channel); 152#ifdef AHC_TARGET_MODE 153static void ahc_free_tstate(struct ahc_softc *ahc, 154 u_int scsi_id, char channel, int force); 155#endif 156static struct ahc_syncrate* 157 ahc_devlimited_syncrate(struct ahc_softc *ahc, 158 struct ahc_initiator_tinfo *, 159 u_int *period, 160 u_int *ppr_options, 161 role_t role); 162static void ahc_update_pending_scbs(struct ahc_softc *ahc); 163static void ahc_fetch_devinfo(struct ahc_softc *ahc, 164 struct ahc_devinfo *devinfo); 165static void ahc_scb_devinfo(struct ahc_softc *ahc, 166 struct ahc_devinfo *devinfo, 167 struct scb *scb); 168static void ahc_assert_atn(struct ahc_softc *ahc); 169static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 170 struct ahc_devinfo *devinfo, 171 struct scb *scb); 172static void ahc_build_transfer_msg(struct ahc_softc *ahc, 173 struct ahc_devinfo *devinfo); 174static void ahc_construct_sdtr(struct ahc_softc *ahc, 175 struct ahc_devinfo *devinfo, 176 u_int period, u_int offset); 177static void ahc_construct_wdtr(struct ahc_softc *ahc, 178 struct ahc_devinfo *devinfo, 179 u_int bus_width); 180static void ahc_construct_ppr(struct ahc_softc *ahc, 181 struct ahc_devinfo *devinfo, 182 u_int period, u_int offset, 183 u_int bus_width, u_int ppr_options); 184static void ahc_clear_msg_state(struct ahc_softc *ahc); 185static void ahc_handle_proto_violation(struct ahc_softc *ahc); 186static void ahc_handle_message_phase(struct ahc_softc *ahc); 187typedef enum { 188 AHCMSG_1B, 189 AHCMSG_2B, 190 AHCMSG_EXT 191} ahc_msgtype; 192static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 193 u_int msgval, int full); 194static int ahc_parse_msg(struct ahc_softc *ahc, 195 struct ahc_devinfo *devinfo); 196static int ahc_handle_msg_reject(struct ahc_softc *ahc, 197 struct ahc_devinfo *devinfo); 198static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 199 struct ahc_devinfo *devinfo); 200static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 201static void ahc_handle_devreset(struct ahc_softc *ahc, 202 struct ahc_devinfo *devinfo, 203 cam_status status, char *message, 204 int verbose_level); 205#if AHC_TARGET_MODE 206static void ahc_setup_target_msgin(struct ahc_softc *ahc, 207 struct ahc_devinfo *devinfo, 208 struct scb *scb); 209#endif 210 211static bus_dmamap_callback_t ahc_dmamap_cb; 212static void ahc_build_free_scb_list(struct ahc_softc *ahc); 213static int ahc_init_scbdata(struct ahc_softc *ahc); 214static void ahc_fini_scbdata(struct ahc_softc *ahc); 215static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 216 struct scb *prev_scb, 217 struct scb *scb); 218static int ahc_qinfifo_count(struct ahc_softc *ahc); 219static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 220 u_int prev, u_int scbptr); 221static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 222static u_int ahc_rem_wscb(struct ahc_softc *ahc, 223 u_int scbpos, u_int prev); 224static void ahc_reset_current_bus(struct ahc_softc *ahc); 225#ifdef AHC_DUMP_SEQ 226static void ahc_dumpseq(struct ahc_softc *ahc); 227#endif 228static int ahc_loadseq(struct ahc_softc *ahc); 229static int ahc_check_patch(struct ahc_softc *ahc, 230 struct patch **start_patch, 231 u_int start_instr, u_int *skip_addr); 232static void ahc_download_instr(struct ahc_softc *ahc, 233 u_int instrptr, uint8_t *dconsts); 234#ifdef AHC_TARGET_MODE 235static void ahc_queue_lstate_event(struct ahc_softc *ahc, 236 struct ahc_tmode_lstate *lstate, 237 u_int initiator_id, 238 u_int event_type, 239 u_int event_arg); 240static void ahc_update_scsiid(struct ahc_softc *ahc, 241 u_int targid_mask); 242static int ahc_handle_target_cmd(struct ahc_softc *ahc, 243 struct target_cmd *cmd); 244#endif 245/************************* Sequencer Execution Control ************************/ 246/* 247 * Restart the sequencer program from address zero 248 */ 249void 250ahc_restart(struct ahc_softc *ahc) 251{ 252 253 ahc_pause(ahc); 254 255 /* No more pending messages. */ 256 ahc_clear_msg_state(ahc); 257 258 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 259 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 260 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 261 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 262 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 263 ahc_outb(ahc, SAVED_LUN, 0xFF); 264 265 /* 266 * Ensure that the sequencer's idea of TQINPOS 267 * matches our own. The sequencer increments TQINPOS 268 * only after it sees a DMA complete and a reset could 269 * occur before the increment leaving the kernel to believe 270 * the command arrived but the sequencer to not. 271 */ 272 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 273 274 /* Always allow reselection */ 275 ahc_outb(ahc, SCSISEQ, 276 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 277 if ((ahc->features & AHC_CMD_CHAN) != 0) { 278 /* Ensure that no DMA operations are in progress */ 279 ahc_outb(ahc, CCSCBCNT, 0); 280 ahc_outb(ahc, CCSGCTL, 0); 281 ahc_outb(ahc, CCSCBCTL, 0); 282 } 283 /* 284 * If we were in the process of DMA'ing SCB data into 285 * an SCB, replace that SCB on the free list. This prevents 286 * an SCB leak. 287 */ 288 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 289 ahc_add_curscb_to_free_list(ahc); 290 ahc_outb(ahc, SEQ_FLAGS2, 291 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 292 } 293 ahc_outb(ahc, MWI_RESIDUAL, 0); 294 ahc_outb(ahc, SEQCTL, ahc->seqctl); 295 ahc_outb(ahc, SEQADDR0, 0); 296 ahc_outb(ahc, SEQADDR1, 0); 297 ahc_unpause(ahc); 298} 299 300/************************* Input/Output Queues ********************************/ 301void 302ahc_run_qoutfifo(struct ahc_softc *ahc) 303{ 304 struct scb *scb; 305 u_int scb_index; 306 307 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 308 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 309 310 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 311 if ((ahc->qoutfifonext & 0x03) == 0x03) { 312 u_int modnext; 313 314 /* 315 * Clear 32bits of QOUTFIFO at a time 316 * so that we don't clobber an incoming 317 * byte DMA to the array on architectures 318 * that only support 32bit load and store 319 * operations. 320 */ 321 modnext = ahc->qoutfifonext & ~0x3; 322 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 323 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 324 ahc->shared_data_dmamap, 325 /*offset*/modnext, /*len*/4, 326 BUS_DMASYNC_PREREAD); 327 } 328 ahc->qoutfifonext++; 329 330 scb = ahc_lookup_scb(ahc, scb_index); 331 if (scb == NULL) { 332 printf("%s: WARNING no command for scb %d " 333 "(cmdcmplt)\nQOUTPOS = %d\n", 334 ahc_name(ahc), scb_index, 335 (ahc->qoutfifonext - 1) & 0xFF); 336 continue; 337 } 338 339 /* 340 * Save off the residual 341 * if there is one. 342 */ 343 ahc_update_residual(ahc, scb); 344 ahc_done(ahc, scb); 345 } 346} 347 348void 349ahc_run_untagged_queues(struct ahc_softc *ahc) 350{ 351 int i; 352 353 for (i = 0; i < 16; i++) 354 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 355} 356 357void 358ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 359{ 360 struct scb *scb; 361 362 if (ahc->untagged_queue_lock != 0) 363 return; 364 365 if ((scb = TAILQ_FIRST(queue)) != NULL 366 && (scb->flags & SCB_ACTIVE) == 0) { 367 scb->flags |= SCB_ACTIVE; 368 ahc_queue_scb(ahc, scb); 369 } 370} 371 372/************************* Interrupt Handling *********************************/ 373void 374ahc_handle_brkadrint(struct ahc_softc *ahc) 375{ 376 /* 377 * We upset the sequencer :-( 378 * Lookup the error message 379 */ 380 int i; 381 int error; 382 383 error = ahc_inb(ahc, ERROR); 384 for (i = 0; error != 1 && i < num_errors; i++) 385 error >>= 1; 386 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 387 ahc_name(ahc), ahc_hard_errors[i].errmesg, 388 ahc_inb(ahc, SEQADDR0) | 389 (ahc_inb(ahc, SEQADDR1) << 8)); 390 391 ahc_dump_card_state(ahc); 392 393 /* Tell everyone that this HBA is no longer available */ 394 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 395 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 396 CAM_NO_HBA); 397 398 /* Disable all interrupt sources by resetting the controller */ 399 ahc_shutdown(ahc); 400} 401 402void 403ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 404{ 405 struct scb *scb; 406 struct ahc_devinfo devinfo; 407 408 ahc_fetch_devinfo(ahc, &devinfo); 409 410 /* 411 * Clear the upper byte that holds SEQINT status 412 * codes and clear the SEQINT bit. We will unpause 413 * the sequencer, if appropriate, after servicing 414 * the request. 415 */ 416 ahc_outb(ahc, CLRINT, CLRSEQINT); 417 switch (intstat & SEQINT_MASK) { 418 case BAD_STATUS: 419 { 420 u_int scb_index; 421 struct hardware_scb *hscb; 422 423 /* 424 * Set the default return value to 0 (don't 425 * send sense). The sense code will change 426 * this if needed. 427 */ 428 ahc_outb(ahc, RETURN_1, 0); 429 430 /* 431 * The sequencer will notify us when a command 432 * has an error that would be of interest to 433 * the kernel. This allows us to leave the sequencer 434 * running in the common case of command completes 435 * without error. The sequencer will already have 436 * dma'd the SCB back up to us, so we can reference 437 * the in kernel copy directly. 438 */ 439 scb_index = ahc_inb(ahc, SCB_TAG); 440 scb = ahc_lookup_scb(ahc, scb_index); 441 if (scb == NULL) { 442 ahc_print_devinfo(ahc, &devinfo); 443 printf("ahc_intr - referenced scb " 444 "not valid during seqint 0x%x scb(%d)\n", 445 intstat, scb_index); 446 ahc_dump_card_state(ahc); 447 panic("for safety"); 448 goto unpause; 449 } 450 451 hscb = scb->hscb; 452 453 /* Don't want to clobber the original sense code */ 454 if ((scb->flags & SCB_SENSE) != 0) { 455 /* 456 * Clear the SCB_SENSE Flag and have 457 * the sequencer do a normal command 458 * complete. 459 */ 460 scb->flags &= ~SCB_SENSE; 461 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 462 break; 463 } 464 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 465 /* Freeze the queue until the client sees the error. */ 466 ahc_freeze_devq(ahc, scb); 467 ahc_freeze_scb(scb); 468 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 469 switch (hscb->shared_data.status.scsi_status) { 470 case SCSI_STATUS_OK: 471 printf("%s: Interrupted for staus of 0???\n", 472 ahc_name(ahc)); 473 break; 474 case SCSI_STATUS_CMD_TERMINATED: 475 case SCSI_STATUS_CHECK_COND: 476 { 477 struct ahc_dma_seg *sg; 478 struct scsi_sense *sc; 479 struct ahc_initiator_tinfo *targ_info; 480 struct ahc_tmode_tstate *tstate; 481 struct ahc_transinfo *tinfo; 482#ifdef AHC_DEBUG 483 if (ahc_debug & AHC_SHOW_SENSE) { 484 ahc_print_path(ahc, scb); 485 printf("SCB %d: requests Check Status\n", 486 scb->hscb->tag); 487 } 488#endif 489 490 if (ahc_perform_autosense(scb) == 0) 491 break; 492 493 targ_info = ahc_fetch_transinfo(ahc, 494 devinfo.channel, 495 devinfo.our_scsiid, 496 devinfo.target, 497 &tstate); 498 tinfo = &targ_info->curr; 499 sg = scb->sg_list; 500 sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 501 /* 502 * Save off the residual if there is one. 503 */ 504 ahc_update_residual(ahc, scb); 505#ifdef AHC_DEBUG 506 if (ahc_debug & AHC_SHOW_SENSE) { 507 ahc_print_path(ahc, scb); 508 printf("Sending Sense\n"); 509 } 510#endif 511 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 512 sg->len = ahc_get_sense_bufsize(ahc, scb); 513 sg->len |= AHC_DMA_LAST_SEG; 514 515 /* Fixup byte order */ 516 sg->addr = ahc_htole32(sg->addr); 517 sg->len = ahc_htole32(sg->len); 518 519 sc->opcode = REQUEST_SENSE; 520 sc->byte2 = 0; 521 if (tinfo->protocol_version <= SCSI_REV_2 522 && SCB_GET_LUN(scb) < 8) 523 sc->byte2 = SCB_GET_LUN(scb) << 5; 524 sc->unused[0] = 0; 525 sc->unused[1] = 0; 526 sc->length = sg->len; 527 sc->control = 0; 528 529 /* 530 * We can't allow the target to disconnect. 531 * This will be an untagged transaction and 532 * having the target disconnect will make this 533 * transaction indestinguishable from outstanding 534 * tagged transactions. 535 */ 536 hscb->control = 0; 537 538 /* 539 * This request sense could be because the 540 * the device lost power or in some other 541 * way has lost our transfer negotiations. 542 * Renegotiate if appropriate. Unit attention 543 * errors will be reported before any data 544 * phases occur. 545 */ 546 if (ahc_get_residual(scb) 547 == ahc_get_transfer_length(scb)) { 548 ahc_update_neg_request(ahc, &devinfo, 549 tstate, targ_info, 550 AHC_NEG_IF_NON_ASYNC); 551 } 552 if (tstate->auto_negotiate & devinfo.target_mask) { 553 hscb->control |= MK_MESSAGE; 554 scb->flags &= ~SCB_NEGOTIATE; 555 scb->flags |= SCB_AUTO_NEGOTIATE; 556 } 557 hscb->cdb_len = sizeof(*sc); 558 hscb->dataptr = sg->addr; 559 hscb->datacnt = sg->len; 560 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 561 hscb->sgptr = ahc_htole32(hscb->sgptr); 562 scb->sg_count = 1; 563 scb->flags |= SCB_SENSE; 564 ahc_qinfifo_requeue_tail(ahc, scb); 565 ahc_outb(ahc, RETURN_1, SEND_SENSE); 566 /* 567 * Ensure we have enough time to actually 568 * retrieve the sense. 569 */ 570 ahc_scb_timer_reset(scb, 5 * 1000000); 571 break; 572 } 573 default: 574 break; 575 } 576 break; 577 } 578 case NO_MATCH: 579 { 580 /* Ensure we don't leave the selection hardware on */ 581 ahc_outb(ahc, SCSISEQ, 582 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 583 584 printf("%s:%c:%d: no active SCB for reconnecting " 585 "target - issuing BUS DEVICE RESET\n", 586 ahc_name(ahc), devinfo.channel, devinfo.target); 587 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 588 "ARG_1 == 0x%x ACCUM = 0x%x\n", 589 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 590 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 591 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 592 "SINDEX == 0x%x\n", 593 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 594 ahc_index_busy_tcl(ahc, 595 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 596 ahc_inb(ahc, SAVED_LUN))), 597 ahc_inb(ahc, SINDEX)); 598 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 599 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 600 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 601 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 602 ahc_inb(ahc, SCB_CONTROL)); 603 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 604 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 605 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 606 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 607 ahc_dump_card_state(ahc); 608 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 609 ahc->msgout_len = 1; 610 ahc->msgout_index = 0; 611 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 612 ahc_outb(ahc, MSG_OUT, HOST_MSG); 613 ahc_assert_atn(ahc); 614 break; 615 } 616 case SEND_REJECT: 617 { 618 u_int rejbyte = ahc_inb(ahc, ACCUM); 619 printf("%s:%c:%d: Warning - unknown message received from " 620 "target (0x%x). Rejecting\n", 621 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 622 break; 623 } 624 case PROTO_VIOLATION: 625 { 626 ahc_handle_proto_violation(ahc); 627 break; 628 } 629 case IGN_WIDE_RES: 630 ahc_handle_ign_wide_residue(ahc, &devinfo); 631 break; 632 case PDATA_REINIT: 633 ahc_reinitialize_dataptrs(ahc); 634 break; 635 case BAD_PHASE: 636 { 637 u_int lastphase; 638 639 lastphase = ahc_inb(ahc, LASTPHASE); 640 printf("%s:%c:%d: unknown scsi bus phase %x, " 641 "lastphase = 0x%x. Attempting to continue\n", 642 ahc_name(ahc), devinfo.channel, devinfo.target, 643 lastphase, ahc_inb(ahc, SCSISIGI)); 644 break; 645 } 646 case MISSED_BUSFREE: 647 { 648 u_int lastphase; 649 650 lastphase = ahc_inb(ahc, LASTPHASE); 651 printf("%s:%c:%d: Missed busfree. " 652 "Lastphase = 0x%x, Curphase = 0x%x\n", 653 ahc_name(ahc), devinfo.channel, devinfo.target, 654 lastphase, ahc_inb(ahc, SCSISIGI)); 655 ahc_restart(ahc); 656 return; 657 } 658 case HOST_MSG_LOOP: 659 { 660 /* 661 * The sequencer has encountered a message phase 662 * that requires host assistance for completion. 663 * While handling the message phase(s), we will be 664 * notified by the sequencer after each byte is 665 * transfered so we can track bus phase changes. 666 * 667 * If this is the first time we've seen a HOST_MSG_LOOP 668 * interrupt, initialize the state of the host message 669 * loop. 670 */ 671 if (ahc->msg_type == MSG_TYPE_NONE) { 672 struct scb *scb; 673 u_int scb_index; 674 u_int bus_phase; 675 676 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 677 if (bus_phase != P_MESGIN 678 && bus_phase != P_MESGOUT) { 679 printf("ahc_intr: HOST_MSG_LOOP bad " 680 "phase 0x%x\n", 681 bus_phase); 682 /* 683 * Probably transitioned to bus free before 684 * we got here. Just punt the message. 685 */ 686 ahc_clear_intstat(ahc); 687 ahc_restart(ahc); 688 return; 689 } 690 691 scb_index = ahc_inb(ahc, SCB_TAG); 692 scb = ahc_lookup_scb(ahc, scb_index); 693 if (devinfo.role == ROLE_INITIATOR) { 694 if (scb == NULL) 695 panic("HOST_MSG_LOOP with " 696 "invalid SCB %x\n", scb_index); 697 698 if (bus_phase == P_MESGOUT) 699 ahc_setup_initiator_msgout(ahc, 700 &devinfo, 701 scb); 702 else { 703 ahc->msg_type = 704 MSG_TYPE_INITIATOR_MSGIN; 705 ahc->msgin_index = 0; 706 } 707 } 708#if AHC_TARGET_MODE 709 else { 710 if (bus_phase == P_MESGOUT) { 711 ahc->msg_type = 712 MSG_TYPE_TARGET_MSGOUT; 713 ahc->msgin_index = 0; 714 } 715 else 716 ahc_setup_target_msgin(ahc, 717 &devinfo, 718 scb); 719 } 720#endif 721 } 722 723 ahc_handle_message_phase(ahc); 724 break; 725 } 726 case PERR_DETECTED: 727 { 728 /* 729 * If we've cleared the parity error interrupt 730 * but the sequencer still believes that SCSIPERR 731 * is true, it must be that the parity error is 732 * for the currently presented byte on the bus, 733 * and we are not in a phase (data-in) where we will 734 * eventually ack this byte. Ack the byte and 735 * throw it away in the hope that the target will 736 * take us to message out to deliver the appropriate 737 * error message. 738 */ 739 if ((intstat & SCSIINT) == 0 740 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 741 742 if ((ahc->features & AHC_DT) == 0) { 743 u_int curphase; 744 745 /* 746 * The hardware will only let you ack bytes 747 * if the expected phase in SCSISIGO matches 748 * the current phase. Make sure this is 749 * currently the case. 750 */ 751 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 752 ahc_outb(ahc, LASTPHASE, curphase); 753 ahc_outb(ahc, SCSISIGO, curphase); 754 } 755 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 756 int wait; 757 758 /* 759 * In a data phase. Faster to bitbucket 760 * the data than to individually ack each 761 * byte. This is also the only strategy 762 * that will work with AUTOACK enabled. 763 */ 764 ahc_outb(ahc, SXFRCTL1, 765 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 766 wait = 5000; 767 while (--wait != 0) { 768 if ((ahc_inb(ahc, SCSISIGI) 769 & (CDI|MSGI)) != 0) 770 break; 771 ahc_delay(100); 772 } 773 ahc_outb(ahc, SXFRCTL1, 774 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 775 if (wait == 0) { 776 struct scb *scb; 777 u_int scb_index; 778 779 ahc_print_devinfo(ahc, &devinfo); 780 printf("Unable to clear parity error. " 781 "Resetting bus.\n"); 782 scb_index = ahc_inb(ahc, SCB_TAG); 783 scb = ahc_lookup_scb(ahc, scb_index); 784 if (scb != NULL) 785 ahc_set_transaction_status(scb, 786 CAM_UNCOR_PARITY); 787 ahc_reset_channel(ahc, devinfo.channel, 788 /*init reset*/TRUE); 789 } 790 } else { 791 ahc_inb(ahc, SCSIDATL); 792 } 793 } 794 break; 795 } 796 case DATA_OVERRUN: 797 { 798 /* 799 * When the sequencer detects an overrun, it 800 * places the controller in "BITBUCKET" mode 801 * and allows the target to complete its transfer. 802 * Unfortunately, none of the counters get updated 803 * when the controller is in this mode, so we have 804 * no way of knowing how large the overrun was. 805 */ 806 u_int scbindex = ahc_inb(ahc, SCB_TAG); 807 u_int lastphase = ahc_inb(ahc, LASTPHASE); 808 u_int i; 809 810 scb = ahc_lookup_scb(ahc, scbindex); 811 for (i = 0; i < num_phases; i++) { 812 if (lastphase == ahc_phase_table[i].phase) 813 break; 814 } 815 ahc_print_path(ahc, scb); 816 printf("data overrun detected %s." 817 " Tag == 0x%x.\n", 818 ahc_phase_table[i].phasemsg, 819 scb->hscb->tag); 820 ahc_print_path(ahc, scb); 821 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 822 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 823 ahc_get_transfer_length(scb), scb->sg_count); 824 if (scb->sg_count > 0) { 825 for (i = 0; i < scb->sg_count; i++) { 826 827 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 828 i, 829 (ahc_le32toh(scb->sg_list[i].len) >> 24 830 & SG_HIGH_ADDR_BITS), 831 ahc_le32toh(scb->sg_list[i].addr), 832 ahc_le32toh(scb->sg_list[i].len) 833 & AHC_SG_LEN_MASK); 834 } 835 } 836 /* 837 * Set this and it will take effect when the 838 * target does a command complete. 839 */ 840 ahc_freeze_devq(ahc, scb); 841 if ((scb->flags & SCB_SENSE) == 0) { 842 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); 843 } else { 844 scb->flags &= ~SCB_SENSE; 845 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 846 } 847 ahc_freeze_scb(scb); 848 849 if ((ahc->features & AHC_ULTRA2) != 0) { 850 /* 851 * Clear the channel in case we return 852 * to data phase later. 853 */ 854 ahc_outb(ahc, SXFRCTL0, 855 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 856 ahc_outb(ahc, SXFRCTL0, 857 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 858 } 859 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 860 u_int dscommand1; 861 862 /* Ensure HHADDR is 0 for future DMA operations. */ 863 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 864 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 865 ahc_outb(ahc, HADDR, 0); 866 ahc_outb(ahc, DSCOMMAND1, dscommand1); 867 } 868 break; 869 } 870 case MKMSG_FAILED: 871 { 872 u_int scbindex; 873 874 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 875 ahc_name(ahc), devinfo.channel, devinfo.target, 876 devinfo.lun); 877 scbindex = ahc_inb(ahc, SCB_TAG); 878 scb = ahc_lookup_scb(ahc, scbindex); 879 if (scb != NULL 880 && (scb->flags & SCB_RECOVERY_SCB) != 0) 881 /* 882 * Ensure that we didn't put a second instance of this 883 * SCB into the QINFIFO. 884 */ 885 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 886 SCB_GET_CHANNEL(ahc, scb), 887 SCB_GET_LUN(scb), scb->hscb->tag, 888 ROLE_INITIATOR, /*status*/0, 889 SEARCH_REMOVE); 890 break; 891 } 892 case NO_FREE_SCB: 893 { 894 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 895 ahc_dump_card_state(ahc); 896 panic("for safety"); 897 break; 898 } 899 case SCB_MISMATCH: 900 { 901 u_int scbptr; 902 903 scbptr = ahc_inb(ahc, SCBPTR); 904 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 905 scbptr, ahc_inb(ahc, ARG_1), 906 ahc->scb_data->hscbs[scbptr].tag); 907 ahc_dump_card_state(ahc); 908 panic("for saftey"); 909 break; 910 } 911 case OUT_OF_RANGE: 912 { 913 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 914 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 915 "ARG_1 == 0x%x ACCUM = 0x%x\n", 916 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 917 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 918 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 919 "SINDEX == 0x%x\n, A == 0x%x\n", 920 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 921 ahc_index_busy_tcl(ahc, 922 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 923 ahc_inb(ahc, SAVED_LUN))), 924 ahc_inb(ahc, SINDEX), 925 ahc_inb(ahc, ACCUM)); 926 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 927 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 928 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 929 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 930 ahc_inb(ahc, SCB_CONTROL)); 931 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 932 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 933 ahc_dump_card_state(ahc); 934 panic("for safety"); 935 break; 936 } 937 default: 938 printf("ahc_intr: seqint, " 939 "intstat == 0x%x, scsisigi = 0x%x\n", 940 intstat, ahc_inb(ahc, SCSISIGI)); 941 break; 942 } 943unpause: 944 /* 945 * The sequencer is paused immediately on 946 * a SEQINT, so we should restart it when 947 * we're done. 948 */ 949 ahc_unpause(ahc); 950} 951 952void 953ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 954{ 955 u_int scb_index; 956 u_int status0; 957 u_int status; 958 struct scb *scb; 959 char cur_channel; 960 char intr_channel; 961 962 if ((ahc->features & AHC_TWIN) != 0 963 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 964 cur_channel = 'B'; 965 else 966 cur_channel = 'A'; 967 intr_channel = cur_channel; 968 969 if ((ahc->features & AHC_ULTRA2) != 0) 970 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 971 else 972 status0 = 0; 973 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 974 if (status == 0 && status0 == 0) { 975 if ((ahc->features & AHC_TWIN) != 0) { 976 /* Try the other channel */ 977 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 978 status = ahc_inb(ahc, SSTAT1) 979 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 980 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 981 } 982 if (status == 0) { 983 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 984 ahc_outb(ahc, CLRINT, CLRSCSIINT); 985 ahc_unpause(ahc); 986 return; 987 } 988 } 989 990 /* Make sure the sequencer is in a safe location. */ 991 ahc_clear_critical_section(ahc); 992 993 scb_index = ahc_inb(ahc, SCB_TAG); 994 scb = ahc_lookup_scb(ahc, scb_index); 995 if (scb != NULL 996 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 997 scb = NULL; 998 999 if ((ahc->features & AHC_ULTRA2) != 0 1000 && (status0 & IOERR) != 0) { 1001 int now_lvd; 1002 1003 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1004 printf("%s: Transceiver State Has Changed to %s mode\n", 1005 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1006 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1007 /* 1008 * When transitioning to SE mode, the reset line 1009 * glitches, triggering an arbitration bug in some 1010 * Ultra2 controllers. This bug is cleared when we 1011 * assert the reset line. Since a reset glitch has 1012 * already occurred with this transition and a 1013 * transceiver state change is handled just like 1014 * a bus reset anyway, asserting the reset line 1015 * ourselves is safe. 1016 */ 1017 ahc_reset_channel(ahc, intr_channel, 1018 /*Initiate Reset*/now_lvd == 0); 1019 } else if ((status & SCSIRSTI) != 0) { 1020 printf("%s: Someone reset channel %c\n", 1021 ahc_name(ahc), intr_channel); 1022 if (intr_channel != cur_channel) 1023 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1024 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1025 } else if ((status & SCSIPERR) != 0) { 1026 /* 1027 * Determine the bus phase and queue an appropriate message. 1028 * SCSIPERR is latched true as soon as a parity error 1029 * occurs. If the sequencer acked the transfer that 1030 * caused the parity error and the currently presented 1031 * transfer on the bus has correct parity, SCSIPERR will 1032 * be cleared by CLRSCSIPERR. Use this to determine if 1033 * we should look at the last phase the sequencer recorded, 1034 * or the current phase presented on the bus. 1035 */ 1036 struct ahc_devinfo devinfo; 1037 u_int mesg_out; 1038 u_int curphase; 1039 u_int errorphase; 1040 u_int lastphase; 1041 u_int scsirate; 1042 u_int i; 1043 u_int sstat2; 1044 int silent; 1045 1046 lastphase = ahc_inb(ahc, LASTPHASE); 1047 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1048 sstat2 = ahc_inb(ahc, SSTAT2); 1049 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1050 /* 1051 * For all phases save DATA, the sequencer won't 1052 * automatically ack a byte that has a parity error 1053 * in it. So the only way that the current phase 1054 * could be 'data-in' is if the parity error is for 1055 * an already acked byte in the data phase. During 1056 * synchronous data-in transfers, we may actually 1057 * ack bytes before latching the current phase in 1058 * LASTPHASE, leading to the discrepancy between 1059 * curphase and lastphase. 1060 */ 1061 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1062 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1063 errorphase = curphase; 1064 else 1065 errorphase = lastphase; 1066 1067 for (i = 0; i < num_phases; i++) { 1068 if (errorphase == ahc_phase_table[i].phase) 1069 break; 1070 } 1071 mesg_out = ahc_phase_table[i].mesg_out; 1072 silent = FALSE; 1073 if (scb != NULL) { 1074 if (SCB_IS_SILENT(scb)) 1075 silent = TRUE; 1076 else 1077 ahc_print_path(ahc, scb); 1078 scb->flags |= SCB_TRANSMISSION_ERROR; 1079 } else 1080 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1081 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1082 scsirate = ahc_inb(ahc, SCSIRATE); 1083 if (silent == FALSE) { 1084 printf("parity error detected %s. " 1085 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1086 ahc_phase_table[i].phasemsg, 1087 ahc_inw(ahc, SEQADDR0), 1088 scsirate); 1089 if ((ahc->features & AHC_DT) != 0) { 1090 if ((sstat2 & CRCVALERR) != 0) 1091 printf("\tCRC Value Mismatch\n"); 1092 if ((sstat2 & CRCENDERR) != 0) 1093 printf("\tNo terminal CRC packet " 1094 "recevied\n"); 1095 if ((sstat2 & CRCREQERR) != 0) 1096 printf("\tIllegal CRC packet " 1097 "request\n"); 1098 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1099 printf("\tUnexpected %sDT Data Phase\n", 1100 (scsirate & SINGLE_EDGE) 1101 ? "" : "non-"); 1102 } 1103 } 1104 1105 if ((ahc->features & AHC_DT) != 0 1106 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1107 /* 1108 * This error applies regardless of 1109 * data direction, so ignore the value 1110 * in the phase table. 1111 */ 1112 mesg_out = MSG_INITIATOR_DET_ERR; 1113 } 1114 1115 /* 1116 * We've set the hardware to assert ATN if we 1117 * get a parity error on "in" phases, so all we 1118 * need to do is stuff the message buffer with 1119 * the appropriate message. "In" phases have set 1120 * mesg_out to something other than MSG_NOP. 1121 */ 1122 if (mesg_out != MSG_NOOP) { 1123 if (ahc->msg_type != MSG_TYPE_NONE) 1124 ahc->send_msg_perror = TRUE; 1125 else 1126 ahc_outb(ahc, MSG_OUT, mesg_out); 1127 } 1128 /* 1129 * Force a renegotiation with this target just in 1130 * case we are out of sync for some external reason 1131 * unknown (or unreported) by the target. 1132 */ 1133 ahc_fetch_devinfo(ahc, &devinfo); 1134 ahc_force_renegotiation(ahc, &devinfo); 1135 1136 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1137 ahc_unpause(ahc); 1138 } else if ((status & SELTO) != 0) { 1139 u_int scbptr; 1140 1141 /* Stop the selection */ 1142 ahc_outb(ahc, SCSISEQ, 0); 1143 1144 /* No more pending messages */ 1145 ahc_clear_msg_state(ahc); 1146 1147 /* Clear interrupt state */ 1148 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1149 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1150 1151 /* 1152 * Although the driver does not care about the 1153 * 'Selection in Progress' status bit, the busy 1154 * LED does. SELINGO is only cleared by a sucessfull 1155 * selection, so we must manually clear it to insure 1156 * the LED turns off just incase no future successful 1157 * selections occur (e.g. no devices on the bus). 1158 */ 1159 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1160 1161 scbptr = ahc_inb(ahc, WAITING_SCBH); 1162 ahc_outb(ahc, SCBPTR, scbptr); 1163 scb_index = ahc_inb(ahc, SCB_TAG); 1164 1165 scb = ahc_lookup_scb(ahc, scb_index); 1166 if (scb == NULL) { 1167 printf("%s: ahc_intr - referenced scb not " 1168 "valid during SELTO scb(%d, %d)\n", 1169 ahc_name(ahc), scbptr, scb_index); 1170 ahc_dump_card_state(ahc); 1171 } else { 1172 struct ahc_devinfo devinfo; 1173#ifdef AHC_DEBUG 1174 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1175 ahc_print_path(ahc, scb); 1176 printf("Saw Selection Timeout for SCB 0x%x\n", 1177 scb_index); 1178 } 1179#endif 1180 /* 1181 * Force a renegotiation with this target just in 1182 * case the cable was pulled and will later be 1183 * re-attached. The target may forget its negotiation 1184 * settings with us should it attempt to reselect 1185 * during the interruption. The target will not issue 1186 * a unit attention in this case, so we must always 1187 * renegotiate. 1188 */ 1189 ahc_scb_devinfo(ahc, &devinfo, scb); 1190 ahc_force_renegotiation(ahc, &devinfo); 1191 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1192 ahc_freeze_devq(ahc, scb); 1193 } 1194 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1195 ahc_restart(ahc); 1196 } else if ((status & BUSFREE) != 0 1197 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1198 struct ahc_devinfo devinfo; 1199 u_int lastphase; 1200 u_int saved_scsiid; 1201 u_int saved_lun; 1202 u_int target; 1203 u_int initiator_role_id; 1204 char channel; 1205 int printerror; 1206 1207 /* 1208 * Clear our selection hardware as soon as possible. 1209 * We may have an entry in the waiting Q for this target, 1210 * that is affected by this busfree and we don't want to 1211 * go about selecting the target while we handle the event. 1212 */ 1213 ahc_outb(ahc, SCSISEQ, 1214 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1215 1216 /* 1217 * Disable busfree interrupts and clear the busfree 1218 * interrupt status. We do this here so that several 1219 * bus transactions occur prior to clearing the SCSIINT 1220 * latch. It can take a bit for the clearing to take effect. 1221 */ 1222 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1223 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1224 1225 /* 1226 * Look at what phase we were last in. 1227 * If its message out, chances are pretty good 1228 * that the busfree was in response to one of 1229 * our abort requests. 1230 */ 1231 lastphase = ahc_inb(ahc, LASTPHASE); 1232 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1233 saved_lun = ahc_inb(ahc, SAVED_LUN); 1234 target = SCSIID_TARGET(ahc, saved_scsiid); 1235 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1236 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1237 ahc_compile_devinfo(&devinfo, initiator_role_id, 1238 target, saved_lun, channel, ROLE_INITIATOR); 1239 printerror = 1; 1240 1241 if (lastphase == P_MESGOUT) { 1242 u_int tag; 1243 1244 tag = SCB_LIST_NULL; 1245 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1246 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1247 if (ahc->msgout_buf[ahc->msgout_index - 1] 1248 == MSG_ABORT_TAG) 1249 tag = scb->hscb->tag; 1250 ahc_print_path(ahc, scb); 1251 printf("SCB %d - Abort%s Completed.\n", 1252 scb->hscb->tag, tag == SCB_LIST_NULL ? 1253 "" : " Tag"); 1254 ahc_abort_scbs(ahc, target, channel, 1255 saved_lun, tag, 1256 ROLE_INITIATOR, 1257 CAM_REQ_ABORTED); 1258 printerror = 0; 1259 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1260 MSG_BUS_DEV_RESET, TRUE)) { 1261#ifdef __FreeBSD__ 1262 /* 1263 * Don't mark the user's request for this BDR 1264 * as completing with CAM_BDR_SENT. CAM3 1265 * specifies CAM_REQ_CMP. 1266 */ 1267 if (scb != NULL 1268 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1269 && ahc_match_scb(ahc, scb, target, channel, 1270 CAM_LUN_WILDCARD, 1271 SCB_LIST_NULL, 1272 ROLE_INITIATOR)) { 1273 ahc_set_transaction_status(scb, CAM_REQ_CMP); 1274 } 1275#endif 1276 ahc_compile_devinfo(&devinfo, 1277 initiator_role_id, 1278 target, 1279 CAM_LUN_WILDCARD, 1280 channel, 1281 ROLE_INITIATOR); 1282 ahc_handle_devreset(ahc, &devinfo, 1283 CAM_BDR_SENT, 1284 "Bus Device Reset", 1285 /*verbose_level*/0); 1286 printerror = 0; 1287 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1288 MSG_EXT_PPR, FALSE)) { 1289 struct ahc_initiator_tinfo *tinfo; 1290 struct ahc_tmode_tstate *tstate; 1291 1292 /* 1293 * PPR Rejected. Try non-ppr negotiation 1294 * and retry command. 1295 */ 1296 tinfo = ahc_fetch_transinfo(ahc, 1297 devinfo.channel, 1298 devinfo.our_scsiid, 1299 devinfo.target, 1300 &tstate); 1301 tinfo->curr.transport_version = 2; 1302 tinfo->goal.transport_version = 2; 1303 tinfo->goal.ppr_options = 0; 1304 ahc_qinfifo_requeue_tail(ahc, scb); 1305 printerror = 0; 1306 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1307 MSG_EXT_WDTR, FALSE) 1308 || ahc_sent_msg(ahc, AHCMSG_EXT, 1309 MSG_EXT_SDTR, FALSE)) { 1310 /* 1311 * Negotiation Rejected. Go-async and 1312 * retry command. 1313 */ 1314 ahc_set_width(ahc, &devinfo, 1315 MSG_EXT_WDTR_BUS_8_BIT, 1316 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1317 /*paused*/TRUE); 1318 ahc_set_syncrate(ahc, &devinfo, 1319 /*syncrate*/NULL, 1320 /*period*/0, /*offset*/0, 1321 /*ppr_options*/0, 1322 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1323 /*paused*/TRUE); 1324 ahc_qinfifo_requeue_tail(ahc, scb); 1325 printerror = 0; 1326 } 1327 } 1328 if (printerror != 0) { 1329 u_int i; 1330 1331 if (scb != NULL) { 1332 u_int tag; 1333 1334 if ((scb->hscb->control & TAG_ENB) != 0) 1335 tag = scb->hscb->tag; 1336 else 1337 tag = SCB_LIST_NULL; 1338 ahc_print_path(ahc, scb); 1339 ahc_abort_scbs(ahc, target, channel, 1340 SCB_GET_LUN(scb), tag, 1341 ROLE_INITIATOR, 1342 CAM_UNEXP_BUSFREE); 1343 } else { 1344 /* 1345 * We had not fully identified this connection, 1346 * so we cannot abort anything. 1347 */ 1348 printf("%s: ", ahc_name(ahc)); 1349 } 1350 for (i = 0; i < num_phases; i++) { 1351 if (lastphase == ahc_phase_table[i].phase) 1352 break; 1353 } 1354 if (lastphase != P_BUSFREE) { 1355 /* 1356 * Renegotiate with this device at the 1357 * next oportunity just in case this busfree 1358 * is due to a negotiation mismatch with the 1359 * device. 1360 */ 1361 ahc_force_renegotiation(ahc, &devinfo); 1362 } 1363 printf("Unexpected busfree %s\n" 1364 "SEQADDR == 0x%x\n", 1365 ahc_phase_table[i].phasemsg, 1366 ahc_inb(ahc, SEQADDR0) 1367 | (ahc_inb(ahc, SEQADDR1) << 8)); 1368 } 1369 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1370 ahc_restart(ahc); 1371 } else { 1372 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1373 ahc_name(ahc), status); 1374 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1375 } 1376} 1377 1378/* 1379 * Force renegotiation to occur the next time we initiate 1380 * a command to the current device. 1381 */ 1382static void 1383ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1384{ 1385 struct ahc_initiator_tinfo *targ_info; 1386 struct ahc_tmode_tstate *tstate; 1387 1388 targ_info = ahc_fetch_transinfo(ahc, 1389 devinfo->channel, 1390 devinfo->our_scsiid, 1391 devinfo->target, 1392 &tstate); 1393 ahc_update_neg_request(ahc, devinfo, tstate, 1394 targ_info, AHC_NEG_IF_NON_ASYNC); 1395} 1396 1397#define AHC_MAX_STEPS 2000 1398void 1399ahc_clear_critical_section(struct ahc_softc *ahc) 1400{ 1401 int stepping; 1402 int steps; 1403 u_int simode0; 1404 u_int simode1; 1405 1406 if (ahc->num_critical_sections == 0) 1407 return; 1408 1409 stepping = FALSE; 1410 steps = 0; 1411 simode0 = 0; 1412 simode1 = 0; 1413 for (;;) { 1414 struct cs *cs; 1415 u_int seqaddr; 1416 u_int i; 1417 1418 seqaddr = ahc_inb(ahc, SEQADDR0) 1419 | (ahc_inb(ahc, SEQADDR1) << 8); 1420 1421 /* 1422 * Seqaddr represents the next instruction to execute, 1423 * so we are really executing the instruction just 1424 * before it. 1425 */ 1426 if (seqaddr != 0) 1427 seqaddr -= 1; 1428 cs = ahc->critical_sections; 1429 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1430 1431 if (cs->begin < seqaddr && cs->end >= seqaddr) 1432 break; 1433 } 1434 1435 if (i == ahc->num_critical_sections) 1436 break; 1437 1438 if (steps > AHC_MAX_STEPS) { 1439 printf("%s: Infinite loop in critical section\n", 1440 ahc_name(ahc)); 1441 ahc_dump_card_state(ahc); 1442 panic("critical section loop"); 1443 } 1444 1445 steps++; 1446 if (stepping == FALSE) { 1447 1448 /* 1449 * Disable all interrupt sources so that the 1450 * sequencer will not be stuck by a pausing 1451 * interrupt condition while we attempt to 1452 * leave a critical section. 1453 */ 1454 simode0 = ahc_inb(ahc, SIMODE0); 1455 ahc_outb(ahc, SIMODE0, 0); 1456 simode1 = ahc_inb(ahc, SIMODE1); 1457 if ((ahc->features & AHC_DT) != 0) 1458 /* 1459 * On DT class controllers, we 1460 * use the enhanced busfree logic. 1461 * Unfortunately we cannot re-enable 1462 * busfree detection within the 1463 * current connection, so we must 1464 * leave it on while single stepping. 1465 */ 1466 ahc_outb(ahc, SIMODE1, ENBUSFREE); 1467 else 1468 ahc_outb(ahc, SIMODE1, 0); 1469 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1470 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP); 1471 stepping = TRUE; 1472 } 1473 if ((ahc->features & AHC_DT) != 0) { 1474 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1475 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1476 } 1477 ahc_outb(ahc, HCNTRL, ahc->unpause); 1478 while (!ahc_is_paused(ahc)) 1479 ahc_delay(200); 1480 } 1481 if (stepping) { 1482 ahc_outb(ahc, SIMODE0, simode0); 1483 ahc_outb(ahc, SIMODE1, simode1); 1484 ahc_outb(ahc, SEQCTL, ahc->seqctl); 1485 } 1486} 1487 1488/* 1489 * Clear any pending interrupt status. 1490 */ 1491void 1492ahc_clear_intstat(struct ahc_softc *ahc) 1493{ 1494 /* Clear any interrupt conditions this may have caused */ 1495 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1496 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1497 CLRREQINIT); 1498 ahc_flush_device_writes(ahc); 1499 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1500 ahc_flush_device_writes(ahc); 1501 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1502 ahc_flush_device_writes(ahc); 1503} 1504 1505/**************************** Debugging Routines ******************************/ 1506#ifdef AHC_DEBUG 1507uint32_t ahc_debug = AHC_DEBUG_OPTS; 1508#endif 1509 1510void 1511ahc_print_scb(struct scb *scb) 1512{ 1513 int i; 1514 1515 struct hardware_scb *hscb = scb->hscb; 1516 1517 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1518 (void *)scb, 1519 hscb->control, 1520 hscb->scsiid, 1521 hscb->lun, 1522 hscb->cdb_len); 1523 printf("Shared Data: "); 1524 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 1525 printf("%#02x", hscb->shared_data.cdb[i]); 1526 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1527 ahc_le32toh(hscb->dataptr), 1528 ahc_le32toh(hscb->datacnt), 1529 ahc_le32toh(hscb->sgptr), 1530 hscb->tag); 1531 if (scb->sg_count > 0) { 1532 for (i = 0; i < scb->sg_count; i++) { 1533 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 1534 i, 1535 (ahc_le32toh(scb->sg_list[i].len) >> 24 1536 & SG_HIGH_ADDR_BITS), 1537 ahc_le32toh(scb->sg_list[i].addr), 1538 ahc_le32toh(scb->sg_list[i].len)); 1539 } 1540 } 1541} 1542 1543/************************* Transfer Negotiation *******************************/ 1544/* 1545 * Allocate per target mode instance (ID we respond to as a target) 1546 * transfer negotiation data structures. 1547 */ 1548static struct ahc_tmode_tstate * 1549ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1550{ 1551 struct ahc_tmode_tstate *master_tstate; 1552 struct ahc_tmode_tstate *tstate; 1553 int i; 1554 1555 master_tstate = ahc->enabled_targets[ahc->our_id]; 1556 if (channel == 'B') { 1557 scsi_id += 8; 1558 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1559 } 1560 if (ahc->enabled_targets[scsi_id] != NULL 1561 && ahc->enabled_targets[scsi_id] != master_tstate) 1562 panic("%s: ahc_alloc_tstate - Target already allocated", 1563 ahc_name(ahc)); 1564 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate), 1565 M_DEVBUF, M_NOWAIT); 1566 if (tstate == NULL) 1567 return (NULL); 1568 1569 /* 1570 * If we have allocated a master tstate, copy user settings from 1571 * the master tstate (taken from SRAM or the EEPROM) for this 1572 * channel, but reset our current and goal settings to async/narrow 1573 * until an initiator talks to us. 1574 */ 1575 if (master_tstate != NULL) { 1576 memcpy(tstate, master_tstate, sizeof(*tstate)); 1577 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1578 tstate->ultraenb = 0; 1579 for (i = 0; i < AHC_NUM_TARGETS; i++) { 1580 memset(&tstate->transinfo[i].curr, 0, 1581 sizeof(tstate->transinfo[i].curr)); 1582 memset(&tstate->transinfo[i].goal, 0, 1583 sizeof(tstate->transinfo[i].goal)); 1584 } 1585 } else 1586 memset(tstate, 0, sizeof(*tstate)); 1587 ahc->enabled_targets[scsi_id] = tstate; 1588 return (tstate); 1589} 1590 1591#ifdef AHC_TARGET_MODE 1592/* 1593 * Free per target mode instance (ID we respond to as a target) 1594 * transfer negotiation data structures. 1595 */ 1596static void 1597ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1598{ 1599 struct ahc_tmode_tstate *tstate; 1600 1601 /* 1602 * Don't clean up our "master" tstate. 1603 * It has our default user settings. 1604 */ 1605 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1606 || (channel == 'A' && scsi_id == ahc->our_id)) 1607 && force == FALSE) 1608 return; 1609 1610 if (channel == 'B') 1611 scsi_id += 8; 1612 tstate = ahc->enabled_targets[scsi_id]; 1613 if (tstate != NULL) 1614 free(tstate, M_DEVBUF); 1615 ahc->enabled_targets[scsi_id] = NULL; 1616} 1617#endif 1618 1619/* 1620 * Called when we have an active connection to a target on the bus, 1621 * this function finds the nearest syncrate to the input period limited 1622 * by the capabilities of the bus connectivity of and sync settings for 1623 * the target. 1624 */ 1625struct ahc_syncrate * 1626ahc_devlimited_syncrate(struct ahc_softc *ahc, 1627 struct ahc_initiator_tinfo *tinfo, 1628 u_int *period, u_int *ppr_options, role_t role) 1629{ 1630 struct ahc_transinfo *transinfo; 1631 u_int maxsync; 1632 1633 if ((ahc->features & AHC_ULTRA2) != 0) { 1634 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1635 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1636 maxsync = AHC_SYNCRATE_DT; 1637 } else { 1638 maxsync = AHC_SYNCRATE_ULTRA; 1639 /* Can't do DT on an SE bus */ 1640 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1641 } 1642 } else if ((ahc->features & AHC_ULTRA) != 0) { 1643 maxsync = AHC_SYNCRATE_ULTRA; 1644 } else { 1645 maxsync = AHC_SYNCRATE_FAST; 1646 } 1647 /* 1648 * Never allow a value higher than our current goal 1649 * period otherwise we may allow a target initiated 1650 * negotiation to go above the limit as set by the 1651 * user. In the case of an initiator initiated 1652 * sync negotiation, we limit based on the user 1653 * setting. This allows the system to still accept 1654 * incoming negotiations even if target initiated 1655 * negotiation is not performed. 1656 */ 1657 if (role == ROLE_TARGET) 1658 transinfo = &tinfo->user; 1659 else 1660 transinfo = &tinfo->goal; 1661 *ppr_options &= transinfo->ppr_options; 1662 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 1663 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2); 1664 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1665 } 1666 if (transinfo->period == 0) { 1667 *period = 0; 1668 *ppr_options = 0; 1669 return (NULL); 1670 } 1671 *period = MAX(*period, transinfo->period); 1672 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1673} 1674 1675/* 1676 * Look up the valid period to SCSIRATE conversion in our table. 1677 * Return the period and offset that should be sent to the target 1678 * if this was the beginning of an SDTR. 1679 */ 1680struct ahc_syncrate * 1681ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1682 u_int *ppr_options, u_int maxsync) 1683{ 1684 struct ahc_syncrate *syncrate; 1685 1686 if ((ahc->features & AHC_DT) == 0) 1687 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1688 1689 /* Skip all DT only entries if DT is not available */ 1690 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1691 && maxsync < AHC_SYNCRATE_ULTRA2) 1692 maxsync = AHC_SYNCRATE_ULTRA2; 1693 1694 for (syncrate = &ahc_syncrates[maxsync]; 1695 syncrate->rate != NULL; 1696 syncrate++) { 1697 1698 /* 1699 * The Ultra2 table doesn't go as low 1700 * as for the Fast/Ultra cards. 1701 */ 1702 if ((ahc->features & AHC_ULTRA2) != 0 1703 && (syncrate->sxfr_u2 == 0)) 1704 break; 1705 1706 if (*period <= syncrate->period) { 1707 /* 1708 * When responding to a target that requests 1709 * sync, the requested rate may fall between 1710 * two rates that we can output, but still be 1711 * a rate that we can receive. Because of this, 1712 * we want to respond to the target with 1713 * the same rate that it sent to us even 1714 * if the period we use to send data to it 1715 * is lower. Only lower the response period 1716 * if we must. 1717 */ 1718 if (syncrate == &ahc_syncrates[maxsync]) 1719 *period = syncrate->period; 1720 1721 /* 1722 * At some speeds, we only support 1723 * ST transfers. 1724 */ 1725 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1726 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1727 break; 1728 } 1729 } 1730 1731 if ((*period == 0) 1732 || (syncrate->rate == NULL) 1733 || ((ahc->features & AHC_ULTRA2) != 0 1734 && (syncrate->sxfr_u2 == 0))) { 1735 /* Use asynchronous transfers. */ 1736 *period = 0; 1737 syncrate = NULL; 1738 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1739 } 1740 return (syncrate); 1741} 1742 1743/* 1744 * Convert from an entry in our syncrate table to the SCSI equivalent 1745 * sync "period" factor. 1746 */ 1747u_int 1748ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1749{ 1750 struct ahc_syncrate *syncrate; 1751 1752 if ((ahc->features & AHC_ULTRA2) != 0) 1753 scsirate &= SXFR_ULTRA2; 1754 else 1755 scsirate &= SXFR; 1756 1757 syncrate = &ahc_syncrates[maxsync]; 1758 while (syncrate->rate != NULL) { 1759 1760 if ((ahc->features & AHC_ULTRA2) != 0) { 1761 if (syncrate->sxfr_u2 == 0) 1762 break; 1763 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1764 return (syncrate->period); 1765 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1766 return (syncrate->period); 1767 } 1768 syncrate++; 1769 } 1770 return (0); /* async */ 1771} 1772 1773/* 1774 * Truncate the given synchronous offset to a value the 1775 * current adapter type and syncrate are capable of. 1776 */ 1777void 1778ahc_validate_offset(struct ahc_softc *ahc, 1779 struct ahc_initiator_tinfo *tinfo, 1780 struct ahc_syncrate *syncrate, 1781 u_int *offset, int wide, role_t role) 1782{ 1783 u_int maxoffset; 1784 1785 /* Limit offset to what we can do */ 1786 if (syncrate == NULL) { 1787 maxoffset = 0; 1788 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1789 maxoffset = MAX_OFFSET_ULTRA2; 1790 } else { 1791 if (wide) 1792 maxoffset = MAX_OFFSET_16BIT; 1793 else 1794 maxoffset = MAX_OFFSET_8BIT; 1795 } 1796 *offset = MIN(*offset, maxoffset); 1797 if (tinfo != NULL) { 1798 if (role == ROLE_TARGET) 1799 *offset = MIN(*offset, tinfo->user.offset); 1800 else 1801 *offset = MIN(*offset, tinfo->goal.offset); 1802 } 1803} 1804 1805/* 1806 * Truncate the given transfer width parameter to a value the 1807 * current adapter type is capable of. 1808 */ 1809void 1810ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1811 u_int *bus_width, role_t role) 1812{ 1813 switch (*bus_width) { 1814 default: 1815 if (ahc->features & AHC_WIDE) { 1816 /* Respond Wide */ 1817 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1818 break; 1819 } 1820 /* FALLTHROUGH */ 1821 case MSG_EXT_WDTR_BUS_8_BIT: 1822 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1823 break; 1824 } 1825 if (tinfo != NULL) { 1826 if (role == ROLE_TARGET) 1827 *bus_width = MIN(tinfo->user.width, *bus_width); 1828 else 1829 *bus_width = MIN(tinfo->goal.width, *bus_width); 1830 } 1831} 1832 1833/* 1834 * Update the bitmask of targets for which the controller should 1835 * negotiate with at the next convenient oportunity. This currently 1836 * means the next time we send the initial identify messages for 1837 * a new transaction. 1838 */ 1839int 1840ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1841 struct ahc_tmode_tstate *tstate, 1842 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 1843{ 1844 u_int auto_negotiate_orig; 1845 1846 auto_negotiate_orig = tstate->auto_negotiate; 1847 if (neg_type == AHC_NEG_ALWAYS) { 1848 /* 1849 * Force our "current" settings to be 1850 * unknown so that unless a bus reset 1851 * occurs the need to renegotiate is 1852 * recorded persistently. 1853 */ 1854 if ((ahc->features & AHC_WIDE) != 0) 1855 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 1856 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 1857 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 1858 } 1859 if (tinfo->curr.period != tinfo->goal.period 1860 || tinfo->curr.width != tinfo->goal.width 1861 || tinfo->curr.offset != tinfo->goal.offset 1862 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 1863 || (neg_type == AHC_NEG_IF_NON_ASYNC 1864 && (tinfo->goal.offset != 0 1865 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1866 || tinfo->goal.ppr_options != 0))) 1867 tstate->auto_negotiate |= devinfo->target_mask; 1868 else 1869 tstate->auto_negotiate &= ~devinfo->target_mask; 1870 1871 return (auto_negotiate_orig != tstate->auto_negotiate); 1872} 1873 1874/* 1875 * Update the user/goal/curr tables of synchronous negotiation 1876 * parameters as well as, in the case of a current or active update, 1877 * any data structures on the host controller. In the case of an 1878 * active update, the specified target is currently talking to us on 1879 * the bus, so the transfer parameter update must take effect 1880 * immediately. 1881 */ 1882void 1883ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1884 struct ahc_syncrate *syncrate, u_int period, 1885 u_int offset, u_int ppr_options, u_int type, int paused) 1886{ 1887 struct ahc_initiator_tinfo *tinfo; 1888 struct ahc_tmode_tstate *tstate; 1889 u_int old_period; 1890 u_int old_offset; 1891 u_int old_ppr; 1892 int active; 1893 int update_needed; 1894 1895 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1896 update_needed = 0; 1897 1898 if (syncrate == NULL) { 1899 period = 0; 1900 offset = 0; 1901 } 1902 1903 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1904 devinfo->target, &tstate); 1905 1906 if ((type & AHC_TRANS_USER) != 0) { 1907 tinfo->user.period = period; 1908 tinfo->user.offset = offset; 1909 tinfo->user.ppr_options = ppr_options; 1910 } 1911 1912 if ((type & AHC_TRANS_GOAL) != 0) { 1913 tinfo->goal.period = period; 1914 tinfo->goal.offset = offset; 1915 tinfo->goal.ppr_options = ppr_options; 1916 } 1917 1918 old_period = tinfo->curr.period; 1919 old_offset = tinfo->curr.offset; 1920 old_ppr = tinfo->curr.ppr_options; 1921 1922 if ((type & AHC_TRANS_CUR) != 0 1923 && (old_period != period 1924 || old_offset != offset 1925 || old_ppr != ppr_options)) { 1926 u_int scsirate; 1927 1928 update_needed++; 1929 scsirate = tinfo->scsirate; 1930 if ((ahc->features & AHC_ULTRA2) != 0) { 1931 1932 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1933 if (syncrate != NULL) { 1934 scsirate |= syncrate->sxfr_u2; 1935 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 1936 scsirate |= ENABLE_CRC; 1937 else 1938 scsirate |= SINGLE_EDGE; 1939 } 1940 } else { 1941 1942 scsirate &= ~(SXFR|SOFS); 1943 /* 1944 * Ensure Ultra mode is set properly for 1945 * this target. 1946 */ 1947 tstate->ultraenb &= ~devinfo->target_mask; 1948 if (syncrate != NULL) { 1949 if (syncrate->sxfr & ULTRA_SXFR) { 1950 tstate->ultraenb |= 1951 devinfo->target_mask; 1952 } 1953 scsirate |= syncrate->sxfr & SXFR; 1954 scsirate |= offset & SOFS; 1955 } 1956 if (active) { 1957 u_int sxfrctl0; 1958 1959 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1960 sxfrctl0 &= ~FAST20; 1961 if (tstate->ultraenb & devinfo->target_mask) 1962 sxfrctl0 |= FAST20; 1963 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1964 } 1965 } 1966 if (active) { 1967 ahc_outb(ahc, SCSIRATE, scsirate); 1968 if ((ahc->features & AHC_ULTRA2) != 0) 1969 ahc_outb(ahc, SCSIOFFSET, offset); 1970 } 1971 1972 tinfo->scsirate = scsirate; 1973 tinfo->curr.period = period; 1974 tinfo->curr.offset = offset; 1975 tinfo->curr.ppr_options = ppr_options; 1976 1977 ahc_send_async(ahc, devinfo->channel, devinfo->target, 1978 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 1979 if (bootverbose) { 1980 if (offset != 0) { 1981 printf("%s: target %d synchronous at %sMHz%s, " 1982 "offset = 0x%x\n", ahc_name(ahc), 1983 devinfo->target, syncrate->rate, 1984 (ppr_options & MSG_EXT_PPR_DT_REQ) 1985 ? " DT" : "", offset); 1986 } else { 1987 printf("%s: target %d using " 1988 "asynchronous transfers\n", 1989 ahc_name(ahc), devinfo->target); 1990 } 1991 } 1992 } 1993 1994 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 1995 tinfo, AHC_NEG_TO_GOAL); 1996 1997 if (update_needed) 1998 ahc_update_pending_scbs(ahc); 1999} 2000 2001/* 2002 * Update the user/goal/curr tables of wide negotiation 2003 * parameters as well as, in the case of a current or active update, 2004 * any data structures on the host controller. In the case of an 2005 * active update, the specified target is currently talking to us on 2006 * the bus, so the transfer parameter update must take effect 2007 * immediately. 2008 */ 2009void 2010ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2011 u_int width, u_int type, int paused) 2012{ 2013 struct ahc_initiator_tinfo *tinfo; 2014 struct ahc_tmode_tstate *tstate; 2015 u_int oldwidth; 2016 int active; 2017 int update_needed; 2018 2019 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2020 update_needed = 0; 2021 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2022 devinfo->target, &tstate); 2023 2024 if ((type & AHC_TRANS_USER) != 0) 2025 tinfo->user.width = width; 2026 2027 if ((type & AHC_TRANS_GOAL) != 0) 2028 tinfo->goal.width = width; 2029 2030 oldwidth = tinfo->curr.width; 2031 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2032 u_int scsirate; 2033 2034 update_needed++; 2035 scsirate = tinfo->scsirate; 2036 scsirate &= ~WIDEXFER; 2037 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2038 scsirate |= WIDEXFER; 2039 2040 tinfo->scsirate = scsirate; 2041 2042 if (active) 2043 ahc_outb(ahc, SCSIRATE, scsirate); 2044 2045 tinfo->curr.width = width; 2046 2047 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2048 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2049 if (bootverbose) { 2050 printf("%s: target %d using %dbit transfers\n", 2051 ahc_name(ahc), devinfo->target, 2052 8 * (0x01 << width)); 2053 } 2054 } 2055 2056 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2057 tinfo, AHC_NEG_TO_GOAL); 2058 if (update_needed) 2059 ahc_update_pending_scbs(ahc); 2060} 2061 2062/* 2063 * Update the current state of tagged queuing for a given target. 2064 */ 2065void 2066ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2067 ahc_queue_alg alg) 2068{ 2069 ahc_platform_set_tags(ahc, devinfo, alg); 2070 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2071 devinfo->lun, AC_TRANSFER_NEG, &alg); 2072} 2073 2074/* 2075 * When the transfer settings for a connection change, update any 2076 * in-transit SCBs to contain the new data so the hardware will 2077 * be set correctly during future (re)selections. 2078 */ 2079static void 2080ahc_update_pending_scbs(struct ahc_softc *ahc) 2081{ 2082 struct scb *pending_scb; 2083 int pending_scb_count; 2084 int i; 2085 int paused; 2086 u_int saved_scbptr; 2087 2088 /* 2089 * Traverse the pending SCB list and ensure that all of the 2090 * SCBs there have the proper settings. 2091 */ 2092 pending_scb_count = 0; 2093 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2094 struct ahc_devinfo devinfo; 2095 struct hardware_scb *pending_hscb; 2096 struct ahc_initiator_tinfo *tinfo; 2097 struct ahc_tmode_tstate *tstate; 2098 2099 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2100 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2101 devinfo.our_scsiid, 2102 devinfo.target, &tstate); 2103 pending_hscb = pending_scb->hscb; 2104 pending_hscb->control &= ~ULTRAENB; 2105 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2106 pending_hscb->control |= ULTRAENB; 2107 pending_hscb->scsirate = tinfo->scsirate; 2108 pending_hscb->scsioffset = tinfo->curr.offset; 2109 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2110 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2111 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2112 pending_hscb->control &= ~MK_MESSAGE; 2113 } 2114 ahc_sync_scb(ahc, pending_scb, 2115 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2116 pending_scb_count++; 2117 } 2118 2119 if (pending_scb_count == 0) 2120 return; 2121 2122 if (ahc_is_paused(ahc)) { 2123 paused = 1; 2124 } else { 2125 paused = 0; 2126 ahc_pause(ahc); 2127 } 2128 2129 saved_scbptr = ahc_inb(ahc, SCBPTR); 2130 /* Ensure that the hscbs down on the card match the new information */ 2131 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2132 struct hardware_scb *pending_hscb; 2133 u_int control; 2134 u_int scb_tag; 2135 2136 ahc_outb(ahc, SCBPTR, i); 2137 scb_tag = ahc_inb(ahc, SCB_TAG); 2138 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2139 if (pending_scb == NULL) 2140 continue; 2141 2142 pending_hscb = pending_scb->hscb; 2143 control = ahc_inb(ahc, SCB_CONTROL); 2144 control &= ~(ULTRAENB|MK_MESSAGE); 2145 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2146 ahc_outb(ahc, SCB_CONTROL, control); 2147 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2148 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2149 } 2150 ahc_outb(ahc, SCBPTR, saved_scbptr); 2151 2152 if (paused == 0) 2153 ahc_unpause(ahc); 2154} 2155 2156/**************************** Pathing Information *****************************/ 2157static void 2158ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2159{ 2160 u_int saved_scsiid; 2161 role_t role; 2162 int our_id; 2163 2164 if (ahc_inb(ahc, SSTAT0) & TARGET) 2165 role = ROLE_TARGET; 2166 else 2167 role = ROLE_INITIATOR; 2168 2169 if (role == ROLE_TARGET 2170 && (ahc->features & AHC_MULTI_TID) != 0 2171 && (ahc_inb(ahc, SEQ_FLAGS) 2172 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2173 /* We were selected, so pull our id from TARGIDIN */ 2174 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2175 } else if ((ahc->features & AHC_ULTRA2) != 0) 2176 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2177 else 2178 our_id = ahc_inb(ahc, SCSIID) & OID; 2179 2180 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2181 ahc_compile_devinfo(devinfo, 2182 our_id, 2183 SCSIID_TARGET(ahc, saved_scsiid), 2184 ahc_inb(ahc, SAVED_LUN), 2185 SCSIID_CHANNEL(ahc, saved_scsiid), 2186 role); 2187} 2188 2189struct ahc_phase_table_entry* 2190ahc_lookup_phase_entry(int phase) 2191{ 2192 struct ahc_phase_table_entry *entry; 2193 struct ahc_phase_table_entry *last_entry; 2194 2195 /* 2196 * num_phases doesn't include the default entry which 2197 * will be returned if the phase doesn't match. 2198 */ 2199 last_entry = &ahc_phase_table[num_phases]; 2200 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2201 if (phase == entry->phase) 2202 break; 2203 } 2204 return (entry); 2205} 2206 2207void 2208ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2209 u_int lun, char channel, role_t role) 2210{ 2211 devinfo->our_scsiid = our_id; 2212 devinfo->target = target; 2213 devinfo->lun = lun; 2214 devinfo->target_offset = target; 2215 devinfo->channel = channel; 2216 devinfo->role = role; 2217 if (channel == 'B') 2218 devinfo->target_offset += 8; 2219 devinfo->target_mask = (0x01 << devinfo->target_offset); 2220} 2221 2222void 2223ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2224{ 2225 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2226 devinfo->target, devinfo->lun); 2227} 2228 2229static void 2230ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2231 struct scb *scb) 2232{ 2233 role_t role; 2234 int our_id; 2235 2236 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2237 role = ROLE_INITIATOR; 2238 if ((scb->flags & SCB_TARGET_SCB) != 0) 2239 role = ROLE_TARGET; 2240 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2241 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2242} 2243 2244 2245/************************ Message Phase Processing ****************************/ 2246static void 2247ahc_assert_atn(struct ahc_softc *ahc) 2248{ 2249 u_int scsisigo; 2250 2251 scsisigo = ATNO; 2252 if ((ahc->features & AHC_DT) == 0) 2253 scsisigo |= ahc_inb(ahc, SCSISIGI); 2254 ahc_outb(ahc, SCSISIGO, scsisigo); 2255} 2256 2257/* 2258 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2259 * or enters the initial message out phase, we are interrupted. Fill our 2260 * outgoing message buffer with the appropriate message and beging handing 2261 * the message phase(s) manually. 2262 */ 2263static void 2264ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2265 struct scb *scb) 2266{ 2267 /* 2268 * To facilitate adding multiple messages together, 2269 * each routine should increment the index and len 2270 * variables instead of setting them explicitly. 2271 */ 2272 ahc->msgout_index = 0; 2273 ahc->msgout_len = 0; 2274 2275 if ((scb->flags & SCB_DEVICE_RESET) == 0 2276 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2277 u_int identify_msg; 2278 2279 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2280 if ((scb->hscb->control & DISCENB) != 0) 2281 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2282 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2283 ahc->msgout_len++; 2284 2285 if ((scb->hscb->control & TAG_ENB) != 0) { 2286 ahc->msgout_buf[ahc->msgout_index++] = 2287 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2288 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2289 ahc->msgout_len += 2; 2290 } 2291 } 2292 2293 if (scb->flags & SCB_DEVICE_RESET) { 2294 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2295 ahc->msgout_len++; 2296 ahc_print_path(ahc, scb); 2297 printf("Bus Device Reset Message Sent\n"); 2298 /* 2299 * Clear our selection hardware in advance of 2300 * the busfree. We may have an entry in the waiting 2301 * Q for this target, and we don't want to go about 2302 * selecting while we handle the busfree and blow it 2303 * away. 2304 */ 2305 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2306 } else if ((scb->flags & SCB_ABORT) != 0) { 2307 if ((scb->hscb->control & TAG_ENB) != 0) 2308 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2309 else 2310 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2311 ahc->msgout_len++; 2312 ahc_print_path(ahc, scb); 2313 printf("Abort%s Message Sent\n", 2314 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2315 /* 2316 * Clear our selection hardware in advance of 2317 * the busfree. We may have an entry in the waiting 2318 * Q for this target, and we don't want to go about 2319 * selecting while we handle the busfree and blow it 2320 * away. 2321 */ 2322 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2323 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2324 ahc_build_transfer_msg(ahc, devinfo); 2325 } else { 2326 printf("ahc_intr: AWAITING_MSG for an SCB that " 2327 "does not have a waiting message\n"); 2328 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2329 devinfo->target_mask); 2330 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2331 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2332 ahc_inb(ahc, MSG_OUT), scb->flags); 2333 } 2334 2335 /* 2336 * Clear the MK_MESSAGE flag from the SCB so we aren't 2337 * asked to send this message again. 2338 */ 2339 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2340 scb->hscb->control &= ~MK_MESSAGE; 2341 ahc->msgout_index = 0; 2342 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2343} 2344 2345/* 2346 * Build an appropriate transfer negotiation message for the 2347 * currently active target. 2348 */ 2349static void 2350ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2351{ 2352 /* 2353 * We need to initiate transfer negotiations. 2354 * If our current and goal settings are identical, 2355 * we want to renegotiate due to a check condition. 2356 */ 2357 struct ahc_initiator_tinfo *tinfo; 2358 struct ahc_tmode_tstate *tstate; 2359 struct ahc_syncrate *rate; 2360 int dowide; 2361 int dosync; 2362 int doppr; 2363 u_int period; 2364 u_int ppr_options; 2365 u_int offset; 2366 2367 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2368 devinfo->target, &tstate); 2369 /* 2370 * Filter our period based on the current connection. 2371 * If we can't perform DT transfers on this segment (not in LVD 2372 * mode for instance), then our decision to issue a PPR message 2373 * may change. 2374 */ 2375 period = tinfo->goal.period; 2376 ppr_options = tinfo->goal.ppr_options; 2377 /* Target initiated PPR is not allowed in the SCSI spec */ 2378 if (devinfo->role == ROLE_TARGET) 2379 ppr_options = 0; 2380 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2381 &ppr_options, devinfo->role); 2382 dowide = tinfo->curr.width != tinfo->goal.width; 2383 dosync = tinfo->curr.period != period; 2384 /* 2385 * Only use PPR if we have options that need it, even if the device 2386 * claims to support it. There might be an expander in the way 2387 * that doesn't. 2388 */ 2389 doppr = ppr_options != 0; 2390 2391 if (!dowide && !dosync && !doppr) { 2392 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2393 dosync = tinfo->goal.offset != 0; 2394 } 2395 2396 if (!dowide && !dosync && !doppr) { 2397 /* 2398 * Force async with a WDTR message if we have a wide bus, 2399 * or just issue an SDTR with a 0 offset. 2400 */ 2401 if ((ahc->features & AHC_WIDE) != 0) 2402 dowide = 1; 2403 else 2404 dosync = 1; 2405 2406 if (bootverbose) { 2407 ahc_print_devinfo(ahc, devinfo); 2408 printf("Ensuring async\n"); 2409 } 2410 } 2411 2412 /* Target initiated PPR is not allowed in the SCSI spec */ 2413 if (devinfo->role == ROLE_TARGET) 2414 doppr = 0; 2415 2416 /* 2417 * Both the PPR message and SDTR message require the 2418 * goal syncrate to be limited to what the target device 2419 * is capable of handling (based on whether an LVD->SE 2420 * expander is on the bus), so combine these two cases. 2421 * Regardless, guarantee that if we are using WDTR and SDTR 2422 * messages that WDTR comes first. 2423 */ 2424 if (doppr || (dosync && !dowide)) { 2425 2426 offset = tinfo->goal.offset; 2427 ahc_validate_offset(ahc, tinfo, rate, &offset, 2428 doppr ? tinfo->goal.width 2429 : tinfo->curr.width, 2430 devinfo->role); 2431 if (doppr) { 2432 ahc_construct_ppr(ahc, devinfo, period, offset, 2433 tinfo->goal.width, ppr_options); 2434 } else { 2435 ahc_construct_sdtr(ahc, devinfo, period, offset); 2436 } 2437 } else { 2438 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2439 } 2440} 2441 2442/* 2443 * Build a synchronous negotiation message in our message 2444 * buffer based on the input parameters. 2445 */ 2446static void 2447ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2448 u_int period, u_int offset) 2449{ 2450 if (offset == 0) 2451 period = AHC_ASYNC_XFER_PERIOD; 2452 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2453 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 2454 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 2455 ahc->msgout_buf[ahc->msgout_index++] = period; 2456 ahc->msgout_buf[ahc->msgout_index++] = offset; 2457 ahc->msgout_len += 5; 2458 if (bootverbose) { 2459 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2460 ahc_name(ahc), devinfo->channel, devinfo->target, 2461 devinfo->lun, period, offset); 2462 } 2463} 2464 2465/* 2466 * Build a wide negotiation message in our message 2467 * buffer based on the input parameters. 2468 */ 2469static void 2470ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2471 u_int bus_width) 2472{ 2473 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2474 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 2475 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 2476 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2477 ahc->msgout_len += 4; 2478 if (bootverbose) { 2479 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2480 ahc_name(ahc), devinfo->channel, devinfo->target, 2481 devinfo->lun, bus_width); 2482 } 2483} 2484 2485/* 2486 * Build a parallel protocol request message in our message 2487 * buffer based on the input parameters. 2488 */ 2489static void 2490ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2491 u_int period, u_int offset, u_int bus_width, 2492 u_int ppr_options) 2493{ 2494 if (offset == 0) 2495 period = AHC_ASYNC_XFER_PERIOD; 2496 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2497 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; 2498 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; 2499 ahc->msgout_buf[ahc->msgout_index++] = period; 2500 ahc->msgout_buf[ahc->msgout_index++] = 0; 2501 ahc->msgout_buf[ahc->msgout_index++] = offset; 2502 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2503 ahc->msgout_buf[ahc->msgout_index++] = ppr_options; 2504 ahc->msgout_len += 8; 2505 if (bootverbose) { 2506 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2507 "offset %x, ppr_options %x\n", ahc_name(ahc), 2508 devinfo->channel, devinfo->target, devinfo->lun, 2509 bus_width, period, offset, ppr_options); 2510 } 2511} 2512 2513/* 2514 * Clear any active message state. 2515 */ 2516static void 2517ahc_clear_msg_state(struct ahc_softc *ahc) 2518{ 2519 ahc->msgout_len = 0; 2520 ahc->msgin_index = 0; 2521 ahc->msg_type = MSG_TYPE_NONE; 2522 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2523 /* 2524 * The target didn't care to respond to our 2525 * message request, so clear ATN. 2526 */ 2527 ahc_outb(ahc, CLRSINT1, CLRATNO); 2528 } 2529 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2530 ahc_outb(ahc, SEQ_FLAGS2, 2531 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 2532} 2533 2534static void 2535ahc_handle_proto_violation(struct ahc_softc *ahc) 2536{ 2537 struct ahc_devinfo devinfo; 2538 struct scb *scb; 2539 u_int scbid; 2540 u_int seq_flags; 2541 u_int curphase; 2542 u_int lastphase; 2543 int found; 2544 2545 ahc_fetch_devinfo(ahc, &devinfo); 2546 scbid = ahc_inb(ahc, SCB_TAG); 2547 scb = ahc_lookup_scb(ahc, scbid); 2548 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 2549 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2550 lastphase = ahc_inb(ahc, LASTPHASE); 2551 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2552 2553 /* 2554 * The reconnecting target either did not send an 2555 * identify message, or did, but we didn't find an SCB 2556 * to match. 2557 */ 2558 ahc_print_devinfo(ahc, &devinfo); 2559 printf("Target did not send an IDENTIFY message. " 2560 "LASTPHASE = 0x%x.\n", lastphase); 2561 scb = NULL; 2562 } else if (scb == NULL) { 2563 /* 2564 * We don't seem to have an SCB active for this 2565 * transaction. Print an error and reset the bus. 2566 */ 2567 ahc_print_devinfo(ahc, &devinfo); 2568 printf("No SCB found during protocol violation\n"); 2569 goto proto_violation_reset; 2570 } else { 2571 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2572 if ((seq_flags & NO_CDB_SENT) != 0) { 2573 ahc_print_path(ahc, scb); 2574 printf("No or incomplete CDB sent to device.\n"); 2575 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 2576 /* 2577 * The target never bothered to provide status to 2578 * us prior to completing the command. Since we don't 2579 * know the disposition of this command, we must attempt 2580 * to abort it. Assert ATN and prepare to send an abort 2581 * message. 2582 */ 2583 ahc_print_path(ahc, scb); 2584 printf("Completed command without status.\n"); 2585 } else { 2586 ahc_print_path(ahc, scb); 2587 printf("Unknown protocol violation.\n"); 2588 ahc_dump_card_state(ahc); 2589 } 2590 } 2591 if ((lastphase & ~P_DATAIN_DT) == 0 2592 || lastphase == P_COMMAND) { 2593proto_violation_reset: 2594 /* 2595 * Target either went directly to data/command 2596 * phase or didn't respond to our ATN. 2597 * The only safe thing to do is to blow 2598 * it away with a bus reset. 2599 */ 2600 found = ahc_reset_channel(ahc, 'A', TRUE); 2601 printf("%s: Issued Channel %c Bus Reset. " 2602 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 2603 } else { 2604 /* 2605 * Leave the selection hardware off in case 2606 * this abort attempt will affect yet to 2607 * be sent commands. 2608 */ 2609 ahc_outb(ahc, SCSISEQ, 2610 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 2611 ahc_assert_atn(ahc); 2612 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2613 if (scb == NULL) { 2614 ahc_print_devinfo(ahc, &devinfo); 2615 ahc->msgout_buf[0] = MSG_ABORT_TASK; 2616 ahc->msgout_len = 1; 2617 ahc->msgout_index = 0; 2618 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2619 } else { 2620 ahc_print_path(ahc, scb); 2621 scb->flags |= SCB_ABORT; 2622 } 2623 printf("Protocol violation %s. Attempting to abort.\n", 2624 ahc_lookup_phase_entry(curphase)->phasemsg); 2625 } 2626} 2627 2628/* 2629 * Manual message loop handler. 2630 */ 2631static void 2632ahc_handle_message_phase(struct ahc_softc *ahc) 2633{ 2634 struct ahc_devinfo devinfo; 2635 u_int bus_phase; 2636 int end_session; 2637 2638 ahc_fetch_devinfo(ahc, &devinfo); 2639 end_session = FALSE; 2640 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2641 2642reswitch: 2643 switch (ahc->msg_type) { 2644 case MSG_TYPE_INITIATOR_MSGOUT: 2645 { 2646 int lastbyte; 2647 int phasemis; 2648 int msgdone; 2649 2650 if (ahc->msgout_len == 0) 2651 panic("HOST_MSG_LOOP interrupt with no active message"); 2652 2653#ifdef AHC_DEBUG 2654 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2655 ahc_print_devinfo(ahc, &devinfo); 2656 printf("INITIATOR_MSG_OUT"); 2657 } 2658#endif 2659 phasemis = bus_phase != P_MESGOUT; 2660 if (phasemis) { 2661#ifdef AHC_DEBUG 2662 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2663 printf(" PHASEMIS %s\n", 2664 ahc_lookup_phase_entry(bus_phase) 2665 ->phasemsg); 2666 } 2667#endif 2668 if (bus_phase == P_MESGIN) { 2669 /* 2670 * Change gears and see if 2671 * this messages is of interest to 2672 * us or should be passed back to 2673 * the sequencer. 2674 */ 2675 ahc_outb(ahc, CLRSINT1, CLRATNO); 2676 ahc->send_msg_perror = FALSE; 2677 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2678 ahc->msgin_index = 0; 2679 goto reswitch; 2680 } 2681 end_session = TRUE; 2682 break; 2683 } 2684 2685 if (ahc->send_msg_perror) { 2686 ahc_outb(ahc, CLRSINT1, CLRATNO); 2687 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2688#ifdef AHC_DEBUG 2689 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2690 printf(" byte 0x%x\n", ahc->send_msg_perror); 2691#endif 2692 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2693 break; 2694 } 2695 2696 msgdone = ahc->msgout_index == ahc->msgout_len; 2697 if (msgdone) { 2698 /* 2699 * The target has requested a retry. 2700 * Re-assert ATN, reset our message index to 2701 * 0, and try again. 2702 */ 2703 ahc->msgout_index = 0; 2704 ahc_assert_atn(ahc); 2705 } 2706 2707 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2708 if (lastbyte) { 2709 /* Last byte is signified by dropping ATN */ 2710 ahc_outb(ahc, CLRSINT1, CLRATNO); 2711 } 2712 2713 /* 2714 * Clear our interrupt status and present 2715 * the next byte on the bus. 2716 */ 2717 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2718#ifdef AHC_DEBUG 2719 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2720 printf(" byte 0x%x\n", 2721 ahc->msgout_buf[ahc->msgout_index]); 2722#endif 2723 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2724 break; 2725 } 2726 case MSG_TYPE_INITIATOR_MSGIN: 2727 { 2728 int phasemis; 2729 int message_done; 2730 2731#ifdef AHC_DEBUG 2732 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2733 ahc_print_devinfo(ahc, &devinfo); 2734 printf("INITIATOR_MSG_IN"); 2735 } 2736#endif 2737 phasemis = bus_phase != P_MESGIN; 2738 if (phasemis) { 2739#ifdef AHC_DEBUG 2740 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2741 printf(" PHASEMIS %s\n", 2742 ahc_lookup_phase_entry(bus_phase) 2743 ->phasemsg); 2744 } 2745#endif 2746 ahc->msgin_index = 0; 2747 if (bus_phase == P_MESGOUT 2748 && (ahc->send_msg_perror == TRUE 2749 || (ahc->msgout_len != 0 2750 && ahc->msgout_index == 0))) { 2751 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2752 goto reswitch; 2753 } 2754 end_session = TRUE; 2755 break; 2756 } 2757 2758 /* Pull the byte in without acking it */ 2759 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2760#ifdef AHC_DEBUG 2761 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2762 printf(" byte 0x%x\n", 2763 ahc->msgin_buf[ahc->msgin_index]); 2764#endif 2765 2766 message_done = ahc_parse_msg(ahc, &devinfo); 2767 2768 if (message_done) { 2769 /* 2770 * Clear our incoming message buffer in case there 2771 * is another message following this one. 2772 */ 2773 ahc->msgin_index = 0; 2774 2775 /* 2776 * If this message illicited a response, 2777 * assert ATN so the target takes us to the 2778 * message out phase. 2779 */ 2780 if (ahc->msgout_len != 0) { 2781#ifdef AHC_DEBUG 2782 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2783 ahc_print_devinfo(ahc, &devinfo); 2784 printf("Asserting ATN for response\n"); 2785 } 2786#endif 2787 ahc_assert_atn(ahc); 2788 } 2789 } else 2790 ahc->msgin_index++; 2791 2792 if (message_done == MSGLOOP_TERMINATED) { 2793 end_session = TRUE; 2794 } else { 2795 /* Ack the byte */ 2796 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2797 ahc_inb(ahc, SCSIDATL); 2798 } 2799 break; 2800 } 2801 case MSG_TYPE_TARGET_MSGIN: 2802 { 2803 int msgdone; 2804 int msgout_request; 2805 2806 if (ahc->msgout_len == 0) 2807 panic("Target MSGIN with no active message"); 2808 2809 /* 2810 * If we interrupted a mesgout session, the initiator 2811 * will not know this until our first REQ. So, we 2812 * only honor mesgout requests after we've sent our 2813 * first byte. 2814 */ 2815 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2816 && ahc->msgout_index > 0) 2817 msgout_request = TRUE; 2818 else 2819 msgout_request = FALSE; 2820 2821 if (msgout_request) { 2822 2823 /* 2824 * Change gears and see if 2825 * this messages is of interest to 2826 * us or should be passed back to 2827 * the sequencer. 2828 */ 2829 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2830 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2831 ahc->msgin_index = 0; 2832 /* Dummy read to REQ for first byte */ 2833 ahc_inb(ahc, SCSIDATL); 2834 ahc_outb(ahc, SXFRCTL0, 2835 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2836 break; 2837 } 2838 2839 msgdone = ahc->msgout_index == ahc->msgout_len; 2840 if (msgdone) { 2841 ahc_outb(ahc, SXFRCTL0, 2842 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2843 end_session = TRUE; 2844 break; 2845 } 2846 2847 /* 2848 * Present the next byte on the bus. 2849 */ 2850 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2851 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2852 break; 2853 } 2854 case MSG_TYPE_TARGET_MSGOUT: 2855 { 2856 int lastbyte; 2857 int msgdone; 2858 2859 /* 2860 * The initiator signals that this is 2861 * the last byte by dropping ATN. 2862 */ 2863 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2864 2865 /* 2866 * Read the latched byte, but turn off SPIOEN first 2867 * so that we don't inadvertently cause a REQ for the 2868 * next byte. 2869 */ 2870 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2871 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2872 msgdone = ahc_parse_msg(ahc, &devinfo); 2873 if (msgdone == MSGLOOP_TERMINATED) { 2874 /* 2875 * The message is *really* done in that it caused 2876 * us to go to bus free. The sequencer has already 2877 * been reset at this point, so pull the ejection 2878 * handle. 2879 */ 2880 return; 2881 } 2882 2883 ahc->msgin_index++; 2884 2885 /* 2886 * XXX Read spec about initiator dropping ATN too soon 2887 * and use msgdone to detect it. 2888 */ 2889 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2890 ahc->msgin_index = 0; 2891 2892 /* 2893 * If this message illicited a response, transition 2894 * to the Message in phase and send it. 2895 */ 2896 if (ahc->msgout_len != 0) { 2897 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2898 ahc_outb(ahc, SXFRCTL0, 2899 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2900 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2901 ahc->msgin_index = 0; 2902 break; 2903 } 2904 } 2905 2906 if (lastbyte) 2907 end_session = TRUE; 2908 else { 2909 /* Ask for the next byte. */ 2910 ahc_outb(ahc, SXFRCTL0, 2911 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2912 } 2913 2914 break; 2915 } 2916 default: 2917 panic("Unknown REQINIT message type"); 2918 } 2919 2920 if (end_session) { 2921 ahc_clear_msg_state(ahc); 2922 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2923 } else 2924 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2925} 2926 2927/* 2928 * See if we sent a particular extended message to the target. 2929 * If "full" is true, return true only if the target saw the full 2930 * message. If "full" is false, return true if the target saw at 2931 * least the first byte of the message. 2932 */ 2933static int 2934ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 2935{ 2936 int found; 2937 u_int index; 2938 2939 found = FALSE; 2940 index = 0; 2941 2942 while (index < ahc->msgout_len) { 2943 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2944 u_int end_index; 2945 2946 end_index = index + 1 + ahc->msgout_buf[index + 1]; 2947 if (ahc->msgout_buf[index+2] == msgval 2948 && type == AHCMSG_EXT) { 2949 2950 if (full) { 2951 if (ahc->msgout_index > end_index) 2952 found = TRUE; 2953 } else if (ahc->msgout_index > index) 2954 found = TRUE; 2955 } 2956 index = end_index; 2957 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 2958 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2959 2960 /* Skip tag type and tag id or residue param*/ 2961 index += 2; 2962 } else { 2963 /* Single byte message */ 2964 if (type == AHCMSG_1B 2965 && ahc->msgout_buf[index] == msgval 2966 && ahc->msgout_index > index) 2967 found = TRUE; 2968 index++; 2969 } 2970 2971 if (found) 2972 break; 2973 } 2974 return (found); 2975} 2976 2977/* 2978 * Wait for a complete incoming message, parse it, and respond accordingly. 2979 */ 2980static int 2981ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2982{ 2983 struct ahc_initiator_tinfo *tinfo; 2984 struct ahc_tmode_tstate *tstate; 2985 int reject; 2986 int done; 2987 int response; 2988 u_int targ_scsirate; 2989 2990 done = MSGLOOP_IN_PROG; 2991 response = FALSE; 2992 reject = FALSE; 2993 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2994 devinfo->target, &tstate); 2995 targ_scsirate = tinfo->scsirate; 2996 2997 /* 2998 * Parse as much of the message as is available, 2999 * rejecting it if we don't support it. When 3000 * the entire message is available and has been 3001 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3002 * that we have parsed an entire message. 3003 * 3004 * In the case of extended messages, we accept the length 3005 * byte outright and perform more checking once we know the 3006 * extended message type. 3007 */ 3008 switch (ahc->msgin_buf[0]) { 3009 case MSG_DISCONNECT: 3010 case MSG_SAVEDATAPOINTER: 3011 case MSG_CMDCOMPLETE: 3012 case MSG_RESTOREPOINTERS: 3013 case MSG_IGN_WIDE_RESIDUE: 3014 /* 3015 * End our message loop as these are messages 3016 * the sequencer handles on its own. 3017 */ 3018 done = MSGLOOP_TERMINATED; 3019 break; 3020 case MSG_MESSAGE_REJECT: 3021 response = ahc_handle_msg_reject(ahc, devinfo); 3022 /* FALLTHROUGH */ 3023 case MSG_NOOP: 3024 done = MSGLOOP_MSGCOMPLETE; 3025 break; 3026 case MSG_EXTENDED: 3027 { 3028 /* Wait for enough of the message to begin validation */ 3029 if (ahc->msgin_index < 2) 3030 break; 3031 switch (ahc->msgin_buf[2]) { 3032 case MSG_EXT_SDTR: 3033 { 3034 struct ahc_syncrate *syncrate; 3035 u_int period; 3036 u_int ppr_options; 3037 u_int offset; 3038 u_int saved_offset; 3039 3040 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3041 reject = TRUE; 3042 break; 3043 } 3044 3045 /* 3046 * Wait until we have both args before validating 3047 * and acting on this message. 3048 * 3049 * Add one to MSG_EXT_SDTR_LEN to account for 3050 * the extended message preamble. 3051 */ 3052 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3053 break; 3054 3055 period = ahc->msgin_buf[3]; 3056 ppr_options = 0; 3057 saved_offset = offset = ahc->msgin_buf[4]; 3058 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3059 &ppr_options, 3060 devinfo->role); 3061 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3062 targ_scsirate & WIDEXFER, 3063 devinfo->role); 3064 if (bootverbose) { 3065 printf("(%s:%c:%d:%d): Received " 3066 "SDTR period %x, offset %x\n\t" 3067 "Filtered to period %x, offset %x\n", 3068 ahc_name(ahc), devinfo->channel, 3069 devinfo->target, devinfo->lun, 3070 ahc->msgin_buf[3], saved_offset, 3071 period, offset); 3072 } 3073 ahc_set_syncrate(ahc, devinfo, 3074 syncrate, period, 3075 offset, ppr_options, 3076 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3077 /*paused*/TRUE); 3078 3079 /* 3080 * See if we initiated Sync Negotiation 3081 * and didn't have to fall down to async 3082 * transfers. 3083 */ 3084 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3085 /* We started it */ 3086 if (saved_offset != offset) { 3087 /* Went too low - force async */ 3088 reject = TRUE; 3089 } 3090 } else { 3091 /* 3092 * Send our own SDTR in reply 3093 */ 3094 if (bootverbose 3095 && devinfo->role == ROLE_INITIATOR) { 3096 printf("(%s:%c:%d:%d): Target " 3097 "Initiated SDTR\n", 3098 ahc_name(ahc), devinfo->channel, 3099 devinfo->target, devinfo->lun); 3100 } 3101 ahc->msgout_index = 0; 3102 ahc->msgout_len = 0; 3103 ahc_construct_sdtr(ahc, devinfo, 3104 period, offset); 3105 ahc->msgout_index = 0; 3106 response = TRUE; 3107 } 3108 done = MSGLOOP_MSGCOMPLETE; 3109 break; 3110 } 3111 case MSG_EXT_WDTR: 3112 { 3113 u_int bus_width; 3114 u_int saved_width; 3115 u_int sending_reply; 3116 3117 sending_reply = FALSE; 3118 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3119 reject = TRUE; 3120 break; 3121 } 3122 3123 /* 3124 * Wait until we have our arg before validating 3125 * and acting on this message. 3126 * 3127 * Add one to MSG_EXT_WDTR_LEN to account for 3128 * the extended message preamble. 3129 */ 3130 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3131 break; 3132 3133 bus_width = ahc->msgin_buf[3]; 3134 saved_width = bus_width; 3135 ahc_validate_width(ahc, tinfo, &bus_width, 3136 devinfo->role); 3137 if (bootverbose) { 3138 printf("(%s:%c:%d:%d): Received WDTR " 3139 "%x filtered to %x\n", 3140 ahc_name(ahc), devinfo->channel, 3141 devinfo->target, devinfo->lun, 3142 saved_width, bus_width); 3143 } 3144 3145 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3146 /* 3147 * Don't send a WDTR back to the 3148 * target, since we asked first. 3149 * If the width went higher than our 3150 * request, reject it. 3151 */ 3152 if (saved_width > bus_width) { 3153 reject = TRUE; 3154 printf("(%s:%c:%d:%d): requested %dBit " 3155 "transfers. Rejecting...\n", 3156 ahc_name(ahc), devinfo->channel, 3157 devinfo->target, devinfo->lun, 3158 8 * (0x01 << bus_width)); 3159 bus_width = 0; 3160 } 3161 } else { 3162 /* 3163 * Send our own WDTR in reply 3164 */ 3165 if (bootverbose 3166 && devinfo->role == ROLE_INITIATOR) { 3167 printf("(%s:%c:%d:%d): Target " 3168 "Initiated WDTR\n", 3169 ahc_name(ahc), devinfo->channel, 3170 devinfo->target, devinfo->lun); 3171 } 3172 ahc->msgout_index = 0; 3173 ahc->msgout_len = 0; 3174 ahc_construct_wdtr(ahc, devinfo, bus_width); 3175 ahc->msgout_index = 0; 3176 response = TRUE; 3177 sending_reply = TRUE; 3178 } 3179 ahc_set_width(ahc, devinfo, bus_width, 3180 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3181 /*paused*/TRUE); 3182 /* After a wide message, we are async */ 3183 ahc_set_syncrate(ahc, devinfo, 3184 /*syncrate*/NULL, /*period*/0, 3185 /*offset*/0, /*ppr_options*/0, 3186 AHC_TRANS_ACTIVE, /*paused*/TRUE); 3187 if (sending_reply == FALSE && reject == FALSE) { 3188 3189 if (tinfo->goal.offset) { 3190 ahc->msgout_index = 0; 3191 ahc->msgout_len = 0; 3192 ahc_build_transfer_msg(ahc, devinfo); 3193 ahc->msgout_index = 0; 3194 response = TRUE; 3195 } 3196 } 3197 done = MSGLOOP_MSGCOMPLETE; 3198 break; 3199 } 3200 case MSG_EXT_PPR: 3201 { 3202 struct ahc_syncrate *syncrate; 3203 u_int period; 3204 u_int offset; 3205 u_int bus_width; 3206 u_int ppr_options; 3207 u_int saved_width; 3208 u_int saved_offset; 3209 u_int saved_ppr_options; 3210 3211 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3212 reject = TRUE; 3213 break; 3214 } 3215 3216 /* 3217 * Wait until we have all args before validating 3218 * and acting on this message. 3219 * 3220 * Add one to MSG_EXT_PPR_LEN to account for 3221 * the extended message preamble. 3222 */ 3223 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3224 break; 3225 3226 period = ahc->msgin_buf[3]; 3227 offset = ahc->msgin_buf[5]; 3228 bus_width = ahc->msgin_buf[6]; 3229 saved_width = bus_width; 3230 ppr_options = ahc->msgin_buf[7]; 3231 /* 3232 * According to the spec, a DT only 3233 * period factor with no DT option 3234 * set implies async. 3235 */ 3236 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3237 && period == 9) 3238 offset = 0; 3239 saved_ppr_options = ppr_options; 3240 saved_offset = offset; 3241 3242 /* 3243 * Mask out any options we don't support 3244 * on any controller. Transfer options are 3245 * only available if we are negotiating wide. 3246 */ 3247 ppr_options &= MSG_EXT_PPR_DT_REQ; 3248 if (bus_width == 0) 3249 ppr_options = 0; 3250 3251 ahc_validate_width(ahc, tinfo, &bus_width, 3252 devinfo->role); 3253 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3254 &ppr_options, 3255 devinfo->role); 3256 ahc_validate_offset(ahc, tinfo, syncrate, 3257 &offset, bus_width, 3258 devinfo->role); 3259 3260 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3261 /* 3262 * If we are unable to do any of the 3263 * requested options (we went too low), 3264 * then we'll have to reject the message. 3265 */ 3266 if (saved_width > bus_width 3267 || saved_offset != offset 3268 || saved_ppr_options != ppr_options) { 3269 reject = TRUE; 3270 period = 0; 3271 offset = 0; 3272 bus_width = 0; 3273 ppr_options = 0; 3274 syncrate = NULL; 3275 } 3276 } else { 3277 if (devinfo->role != ROLE_TARGET) 3278 printf("(%s:%c:%d:%d): Target " 3279 "Initiated PPR\n", 3280 ahc_name(ahc), devinfo->channel, 3281 devinfo->target, devinfo->lun); 3282 else 3283 printf("(%s:%c:%d:%d): Initiator " 3284 "Initiated PPR\n", 3285 ahc_name(ahc), devinfo->channel, 3286 devinfo->target, devinfo->lun); 3287 ahc->msgout_index = 0; 3288 ahc->msgout_len = 0; 3289 ahc_construct_ppr(ahc, devinfo, period, offset, 3290 bus_width, ppr_options); 3291 ahc->msgout_index = 0; 3292 response = TRUE; 3293 } 3294 if (bootverbose) { 3295 printf("(%s:%c:%d:%d): Received PPR width %x, " 3296 "period %x, offset %x,options %x\n" 3297 "\tFiltered to width %x, period %x, " 3298 "offset %x, options %x\n", 3299 ahc_name(ahc), devinfo->channel, 3300 devinfo->target, devinfo->lun, 3301 saved_width, ahc->msgin_buf[3], 3302 saved_offset, saved_ppr_options, 3303 bus_width, period, offset, ppr_options); 3304 } 3305 ahc_set_width(ahc, devinfo, bus_width, 3306 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3307 /*paused*/TRUE); 3308 ahc_set_syncrate(ahc, devinfo, 3309 syncrate, period, 3310 offset, ppr_options, 3311 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3312 /*paused*/TRUE); 3313 done = MSGLOOP_MSGCOMPLETE; 3314 break; 3315 } 3316 default: 3317 /* Unknown extended message. Reject it. */ 3318 reject = TRUE; 3319 break; 3320 } 3321 break; 3322 } 3323#ifdef AHC_TARGET_MODE 3324 case MSG_BUS_DEV_RESET: 3325 ahc_handle_devreset(ahc, devinfo, 3326 CAM_BDR_SENT, 3327 "Bus Device Reset Received", 3328 /*verbose_level*/0); 3329 ahc_restart(ahc); 3330 done = MSGLOOP_TERMINATED; 3331 break; 3332 case MSG_ABORT_TAG: 3333 case MSG_ABORT: 3334 case MSG_CLEAR_QUEUE: 3335 { 3336 int tag; 3337 3338 /* Target mode messages */ 3339 if (devinfo->role != ROLE_TARGET) { 3340 reject = TRUE; 3341 break; 3342 } 3343 tag = SCB_LIST_NULL; 3344 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3345 tag = ahc_inb(ahc, INITIATOR_TAG); 3346 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3347 devinfo->lun, tag, ROLE_TARGET, 3348 CAM_REQ_ABORTED); 3349 3350 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3351 if (tstate != NULL) { 3352 struct ahc_tmode_lstate* lstate; 3353 3354 lstate = tstate->enabled_luns[devinfo->lun]; 3355 if (lstate != NULL) { 3356 ahc_queue_lstate_event(ahc, lstate, 3357 devinfo->our_scsiid, 3358 ahc->msgin_buf[0], 3359 /*arg*/tag); 3360 ahc_send_lstate_events(ahc, lstate); 3361 } 3362 } 3363 ahc_restart(ahc); 3364 done = MSGLOOP_TERMINATED; 3365 break; 3366 } 3367#endif 3368 case MSG_TERM_IO_PROC: 3369 default: 3370 reject = TRUE; 3371 break; 3372 } 3373 3374 if (reject) { 3375 /* 3376 * Setup to reject the message. 3377 */ 3378 ahc->msgout_index = 0; 3379 ahc->msgout_len = 1; 3380 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3381 done = MSGLOOP_MSGCOMPLETE; 3382 response = TRUE; 3383 } 3384 3385 if (done != MSGLOOP_IN_PROG && !response) 3386 /* Clear the outgoing message buffer */ 3387 ahc->msgout_len = 0; 3388 3389 return (done); 3390} 3391 3392/* 3393 * Process a message reject message. 3394 */ 3395static int 3396ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3397{ 3398 /* 3399 * What we care about here is if we had an 3400 * outstanding SDTR or WDTR message for this 3401 * target. If we did, this is a signal that 3402 * the target is refusing negotiation. 3403 */ 3404 struct scb *scb; 3405 struct ahc_initiator_tinfo *tinfo; 3406 struct ahc_tmode_tstate *tstate; 3407 u_int scb_index; 3408 u_int last_msg; 3409 int response = 0; 3410 3411 scb_index = ahc_inb(ahc, SCB_TAG); 3412 scb = ahc_lookup_scb(ahc, scb_index); 3413 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3414 devinfo->our_scsiid, 3415 devinfo->target, &tstate); 3416 /* Might be necessary */ 3417 last_msg = ahc_inb(ahc, LAST_MSG); 3418 3419 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3420 /* 3421 * Target does not support the PPR message. 3422 * Attempt to negotiate SPI-2 style. 3423 */ 3424 if (bootverbose) { 3425 printf("(%s:%c:%d:%d): PPR Rejected. " 3426 "Trying WDTR/SDTR\n", 3427 ahc_name(ahc), devinfo->channel, 3428 devinfo->target, devinfo->lun); 3429 } 3430 tinfo->goal.ppr_options = 0; 3431 tinfo->curr.transport_version = 2; 3432 tinfo->goal.transport_version = 2; 3433 ahc->msgout_index = 0; 3434 ahc->msgout_len = 0; 3435 ahc_build_transfer_msg(ahc, devinfo); 3436 ahc->msgout_index = 0; 3437 response = 1; 3438 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3439 3440 /* note 8bit xfers */ 3441 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3442 "8bit transfers\n", ahc_name(ahc), 3443 devinfo->channel, devinfo->target, devinfo->lun); 3444 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3445 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3446 /*paused*/TRUE); 3447 /* 3448 * No need to clear the sync rate. If the target 3449 * did not accept the command, our syncrate is 3450 * unaffected. If the target started the negotiation, 3451 * but rejected our response, we already cleared the 3452 * sync rate before sending our WDTR. 3453 */ 3454 if (tinfo->goal.offset != tinfo->curr.offset) { 3455 3456 /* Start the sync negotiation */ 3457 ahc->msgout_index = 0; 3458 ahc->msgout_len = 0; 3459 ahc_build_transfer_msg(ahc, devinfo); 3460 ahc->msgout_index = 0; 3461 response = 1; 3462 } 3463 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3464 /* note asynch xfers and clear flag */ 3465 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3466 /*offset*/0, /*ppr_options*/0, 3467 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3468 /*paused*/TRUE); 3469 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 3470 "Using asynchronous transfers\n", 3471 ahc_name(ahc), devinfo->channel, 3472 devinfo->target, devinfo->lun); 3473 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 3474 int tag_type; 3475 int mask; 3476 3477 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 3478 3479 if (tag_type == MSG_SIMPLE_TASK) { 3480 printf("(%s:%c:%d:%d): refuses tagged commands. " 3481 "Performing non-tagged I/O\n", ahc_name(ahc), 3482 devinfo->channel, devinfo->target, devinfo->lun); 3483 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE); 3484 mask = ~0x23; 3485 } else { 3486 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 3487 "Performing simple queue tagged I/O only\n", 3488 ahc_name(ahc), devinfo->channel, devinfo->target, 3489 devinfo->lun, tag_type == MSG_ORDERED_TASK 3490 ? "ordered" : "head of queue"); 3491 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC); 3492 mask = ~0x03; 3493 } 3494 3495 /* 3496 * Resend the identify for this CCB as the target 3497 * may believe that the selection is invalid otherwise. 3498 */ 3499 ahc_outb(ahc, SCB_CONTROL, 3500 ahc_inb(ahc, SCB_CONTROL) & mask); 3501 scb->hscb->control &= mask; 3502 ahc_set_transaction_tag(scb, /*enabled*/FALSE, 3503 /*type*/MSG_SIMPLE_TASK); 3504 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3505 ahc_assert_atn(ahc); 3506 3507 /* 3508 * This transaction is now at the head of 3509 * the untagged queue for this target. 3510 */ 3511 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3512 struct scb_tailq *untagged_q; 3513 3514 untagged_q = 3515 &(ahc->untagged_queues[devinfo->target_offset]); 3516 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3517 scb->flags |= SCB_UNTAGGEDQ; 3518 } 3519 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3520 scb->hscb->tag); 3521 3522 /* 3523 * Requeue all tagged commands for this target 3524 * currently in our posession so they can be 3525 * converted to untagged commands. 3526 */ 3527 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3528 SCB_GET_CHANNEL(ahc, scb), 3529 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3530 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3531 SEARCH_COMPLETE); 3532 } else { 3533 /* 3534 * Otherwise, we ignore it. 3535 */ 3536 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3537 ahc_name(ahc), devinfo->channel, devinfo->target, 3538 last_msg); 3539 } 3540 return (response); 3541} 3542 3543/* 3544 * Process an ingnore wide residue message. 3545 */ 3546static void 3547ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3548{ 3549 u_int scb_index; 3550 struct scb *scb; 3551 3552 scb_index = ahc_inb(ahc, SCB_TAG); 3553 scb = ahc_lookup_scb(ahc, scb_index); 3554 /* 3555 * XXX Actually check data direction in the sequencer? 3556 * Perhaps add datadir to some spare bits in the hscb? 3557 */ 3558 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3559 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { 3560 /* 3561 * Ignore the message if we haven't 3562 * seen an appropriate data phase yet. 3563 */ 3564 } else { 3565 /* 3566 * If the residual occurred on the last 3567 * transfer and the transfer request was 3568 * expected to end on an odd count, do 3569 * nothing. Otherwise, subtract a byte 3570 * and update the residual count accordingly. 3571 */ 3572 uint32_t sgptr; 3573 3574 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3575 if ((sgptr & SG_LIST_NULL) != 0 3576 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) { 3577 /* 3578 * If the residual occurred on the last 3579 * transfer and the transfer request was 3580 * expected to end on an odd count, do 3581 * nothing. 3582 */ 3583 } else { 3584 struct ahc_dma_seg *sg; 3585 uint32_t data_cnt; 3586 uint32_t data_addr; 3587 uint32_t sglen; 3588 3589 /* Pull in all of the sgptr */ 3590 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR); 3591 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT); 3592 3593 if ((sgptr & SG_LIST_NULL) != 0) { 3594 /* 3595 * The residual data count is not updated 3596 * for the command run to completion case. 3597 * Explicitly zero the count. 3598 */ 3599 data_cnt &= ~AHC_SG_LEN_MASK; 3600 } 3601 3602 data_addr = ahc_inl(ahc, SHADDR); 3603 3604 data_cnt += 1; 3605 data_addr -= 1; 3606 sgptr &= SG_PTR_MASK; 3607 3608 sg = ahc_sg_bus_to_virt(scb, sgptr); 3609 3610 /* 3611 * The residual sg ptr points to the next S/G 3612 * to load so we must go back one. 3613 */ 3614 sg--; 3615 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 3616 if (sg != scb->sg_list 3617 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 3618 3619 sg--; 3620 sglen = ahc_le32toh(sg->len); 3621 /* 3622 * Preserve High Address and SG_LIST bits 3623 * while setting the count to 1. 3624 */ 3625 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 3626 data_addr = ahc_le32toh(sg->addr) 3627 + (sglen & AHC_SG_LEN_MASK) - 1; 3628 3629 /* 3630 * Increment sg so it points to the 3631 * "next" sg. 3632 */ 3633 sg++; 3634 sgptr = ahc_sg_virt_to_bus(scb, sg); 3635 } 3636 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3637 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3638 /* 3639 * Toggle the "oddness" of the transfer length 3640 * to handle this mid-transfer ignore wide 3641 * residue. This ensures that the oddness is 3642 * correct for subsequent data transfers. 3643 */ 3644 ahc_outb(ahc, SCB_LUN, 3645 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD); 3646 } 3647 } 3648} 3649 3650 3651/* 3652 * Reinitialize the data pointers for the active transfer 3653 * based on its current residual. 3654 */ 3655static void 3656ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 3657{ 3658 struct scb *scb; 3659 struct ahc_dma_seg *sg; 3660 u_int scb_index; 3661 uint32_t sgptr; 3662 uint32_t resid; 3663 uint32_t dataptr; 3664 3665 scb_index = ahc_inb(ahc, SCB_TAG); 3666 scb = ahc_lookup_scb(ahc, scb_index); 3667 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3668 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3669 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 3670 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3671 3672 sgptr &= SG_PTR_MASK; 3673 sg = ahc_sg_bus_to_virt(scb, sgptr); 3674 3675 /* The residual sg_ptr always points to the next sg */ 3676 sg--; 3677 3678 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 3679 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 3680 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 3681 3682 dataptr = ahc_le32toh(sg->addr) 3683 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK) 3684 - resid; 3685 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 3686 u_int dscommand1; 3687 3688 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 3689 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 3690 ahc_outb(ahc, HADDR, 3691 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 3692 ahc_outb(ahc, DSCOMMAND1, dscommand1); 3693 } 3694 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 3695 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 3696 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 3697 ahc_outb(ahc, HADDR, dataptr); 3698 ahc_outb(ahc, HCNT + 2, resid >> 16); 3699 ahc_outb(ahc, HCNT + 1, resid >> 8); 3700 ahc_outb(ahc, HCNT, resid); 3701 if ((ahc->features & AHC_ULTRA2) == 0) { 3702 ahc_outb(ahc, STCNT + 2, resid >> 16); 3703 ahc_outb(ahc, STCNT + 1, resid >> 8); 3704 ahc_outb(ahc, STCNT, resid); 3705 } 3706} 3707 3708/* 3709 * Handle the effects of issuing a bus device reset message. 3710 */ 3711static void 3712ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3713 cam_status status, char *message, int verbose_level) 3714{ 3715#ifdef AHC_TARGET_MODE 3716 struct ahc_tmode_tstate* tstate; 3717 u_int lun; 3718#endif 3719 int found; 3720 3721 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3722 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3723 status); 3724 3725#ifdef AHC_TARGET_MODE 3726 /* 3727 * Send an immediate notify ccb to all target mord peripheral 3728 * drivers affected by this action. 3729 */ 3730 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3731 if (tstate != NULL) { 3732 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3733 struct ahc_tmode_lstate* lstate; 3734 3735 lstate = tstate->enabled_luns[lun]; 3736 if (lstate == NULL) 3737 continue; 3738 3739 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3740 MSG_BUS_DEV_RESET, /*arg*/0); 3741 ahc_send_lstate_events(ahc, lstate); 3742 } 3743 } 3744#endif 3745 3746 /* 3747 * Go back to async/narrow transfers and renegotiate. 3748 */ 3749 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3750 AHC_TRANS_CUR, /*paused*/TRUE); 3751 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3752 /*period*/0, /*offset*/0, /*ppr_options*/0, 3753 AHC_TRANS_CUR, /*paused*/TRUE); 3754 3755 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3756 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); 3757 3758 if (message != NULL 3759 && (verbose_level <= bootverbose)) 3760 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3761 message, devinfo->channel, devinfo->target, found); 3762} 3763 3764#ifdef AHC_TARGET_MODE 3765static void 3766ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3767 struct scb *scb) 3768{ 3769 3770 /* 3771 * To facilitate adding multiple messages together, 3772 * each routine should increment the index and len 3773 * variables instead of setting them explicitly. 3774 */ 3775 ahc->msgout_index = 0; 3776 ahc->msgout_len = 0; 3777 3778 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3779 ahc_build_transfer_msg(ahc, devinfo); 3780 else 3781 panic("ahc_intr: AWAITING target message with no message"); 3782 3783 ahc->msgout_index = 0; 3784 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3785} 3786#endif 3787/**************************** Initialization **********************************/ 3788/* 3789 * Allocate a controller structure for a new device 3790 * and perform initial initializion. 3791 */ 3792struct ahc_softc * 3793ahc_alloc(void *platform_arg, char *name) 3794{ 3795 struct ahc_softc *ahc; 3796 int i; 3797 3798#ifndef __FreeBSD__ 3799 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT); 3800 if (!ahc) { 3801 printf("aic7xxx: cannot malloc softc!\n"); 3802 free(name, M_DEVBUF); 3803 return NULL; 3804 } 3805#else 3806 ahc = device_get_softc((device_t)platform_arg); 3807#endif 3808 memset(ahc, 0, sizeof(*ahc)); 3809 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 3810 M_DEVBUF, M_NOWAIT); 3811 if (ahc->seep_config == NULL) { 3812#ifndef __FreeBSD__ 3813 free(ahc, M_DEVBUF); 3814#endif 3815 free(name, M_DEVBUF); 3816 return (NULL); 3817 } 3818 LIST_INIT(&ahc->pending_scbs); 3819 /* We don't know our unit number until the OSM sets it */ 3820 ahc->name = name; 3821 ahc->unit = -1; 3822 ahc->description = NULL; 3823 ahc->channel = 'A'; 3824 ahc->channel_b = 'B'; 3825 ahc->chip = AHC_NONE; 3826 ahc->features = AHC_FENONE; 3827 ahc->bugs = AHC_BUGNONE; 3828 ahc->flags = AHC_FNONE; 3829 /* 3830 * Default to all error reporting enabled with the 3831 * sequencer operating at its fastest speed. 3832 * The bus attach code may modify this. 3833 */ 3834 ahc->seqctl = FASTMODE; 3835 3836 for (i = 0; i < AHC_NUM_TARGETS; i++) 3837 TAILQ_INIT(&ahc->untagged_queues[i]); 3838 if (ahc_platform_alloc(ahc, platform_arg) != 0) { 3839 ahc_free(ahc); 3840 ahc = NULL; 3841 } 3842 return (ahc); 3843} 3844 3845int 3846ahc_softc_init(struct ahc_softc *ahc) 3847{ 3848 3849 /* The IRQMS bit is only valid on VL and EISA chips */ 3850 if ((ahc->chip & AHC_PCI) == 0) 3851 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 3852 else 3853 ahc->unpause = 0; 3854 ahc->pause = ahc->unpause | PAUSE; 3855 /* XXX The shared scb data stuff should be deprecated */ 3856 if (ahc->scb_data == NULL) { 3857 ahc->scb_data = malloc(sizeof(*ahc->scb_data), 3858 M_DEVBUF, M_NOWAIT); 3859 if (ahc->scb_data == NULL) 3860 return (ENOMEM); 3861 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); 3862 } 3863 3864 return (0); 3865} 3866 3867void 3868ahc_softc_insert(struct ahc_softc *ahc) 3869{ 3870 struct ahc_softc *list_ahc; 3871 3872#if AHC_PCI_CONFIG > 0 3873 /* 3874 * Second Function PCI devices need to inherit some 3875 * settings from function 0. 3876 */ 3877 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI 3878 && (ahc->features & AHC_MULTI_FUNC) != 0) { 3879 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3880 ahc_dev_softc_t list_pci; 3881 ahc_dev_softc_t pci; 3882 3883 list_pci = list_ahc->dev_softc; 3884 pci = ahc->dev_softc; 3885 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci) 3886 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) { 3887 struct ahc_softc *master; 3888 struct ahc_softc *slave; 3889 3890 if (ahc_get_pci_function(list_pci) == 0) { 3891 master = list_ahc; 3892 slave = ahc; 3893 } else { 3894 master = ahc; 3895 slave = list_ahc; 3896 } 3897 slave->flags &= ~AHC_BIOS_ENABLED; 3898 slave->flags |= 3899 master->flags & AHC_BIOS_ENABLED; 3900 slave->flags &= ~AHC_PRIMARY_CHANNEL; 3901 slave->flags |= 3902 master->flags & AHC_PRIMARY_CHANNEL; 3903 break; 3904 } 3905 } 3906 } 3907#endif 3908 3909 /* 3910 * Insertion sort into our list of softcs. 3911 */ 3912 list_ahc = TAILQ_FIRST(&ahc_tailq); 3913 while (list_ahc != NULL 3914 && ahc_softc_comp(ahc, list_ahc) <= 0) 3915 list_ahc = TAILQ_NEXT(list_ahc, links); 3916 if (list_ahc != NULL) 3917 TAILQ_INSERT_BEFORE(list_ahc, ahc, links); 3918 else 3919 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); 3920 ahc->init_level++; 3921} 3922 3923/* 3924 * Verify that the passed in softc pointer is for a 3925 * controller that is still configured. 3926 */ 3927struct ahc_softc * 3928ahc_find_softc(struct ahc_softc *ahc) 3929{ 3930 struct ahc_softc *list_ahc; 3931 3932 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3933 if (list_ahc == ahc) 3934 return (ahc); 3935 } 3936 return (NULL); 3937} 3938 3939void 3940ahc_set_unit(struct ahc_softc *ahc, int unit) 3941{ 3942 ahc->unit = unit; 3943} 3944 3945void 3946ahc_set_name(struct ahc_softc *ahc, char *name) 3947{ 3948 if (ahc->name != NULL) 3949 free(ahc->name, M_DEVBUF); 3950 ahc->name = name; 3951} 3952 3953void 3954ahc_free(struct ahc_softc *ahc) 3955{ 3956 int i; 3957 3958 switch (ahc->init_level) { 3959 default: 3960 case 5: 3961 ahc_shutdown(ahc); 3962 TAILQ_REMOVE(&ahc_tailq, ahc, links); 3963 /* FALLTHROUGH */ 3964 case 4: 3965 ahc_dmamap_unload(ahc, ahc->shared_data_dmat, 3966 ahc->shared_data_dmamap); 3967 /* FALLTHROUGH */ 3968 case 3: 3969 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo, 3970 ahc->shared_data_dmamap); 3971 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat, 3972 ahc->shared_data_dmamap); 3973 /* FALLTHROUGH */ 3974 case 2: 3975 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat); 3976 case 1: 3977#ifndef __linux__ 3978 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat); 3979#endif 3980 break; 3981 case 0: 3982 break; 3983 } 3984 3985#ifndef __linux__ 3986 ahc_dma_tag_destroy(ahc, ahc->parent_dmat); 3987#endif 3988 ahc_platform_free(ahc); 3989 ahc_fini_scbdata(ahc); 3990 for (i = 0; i < AHC_NUM_TARGETS; i++) { 3991 struct ahc_tmode_tstate *tstate; 3992 3993 tstate = ahc->enabled_targets[i]; 3994 if (tstate != NULL) { 3995#if AHC_TARGET_MODE 3996 int j; 3997 3998 for (j = 0; j < AHC_NUM_LUNS; j++) { 3999 struct ahc_tmode_lstate *lstate; 4000 4001 lstate = tstate->enabled_luns[j]; 4002 if (lstate != NULL) { 4003 xpt_free_path(lstate->path); 4004 free(lstate, M_DEVBUF); 4005 } 4006 } 4007#endif 4008 free(tstate, M_DEVBUF); 4009 } 4010 } 4011#if AHC_TARGET_MODE 4012 if (ahc->black_hole != NULL) { 4013 xpt_free_path(ahc->black_hole->path); 4014 free(ahc->black_hole, M_DEVBUF); 4015 } 4016#endif 4017 if (ahc->name != NULL) 4018 free(ahc->name, M_DEVBUF); 4019 if (ahc->seep_config != NULL) 4020 free(ahc->seep_config, M_DEVBUF); 4021#ifndef __FreeBSD__ 4022 free(ahc, M_DEVBUF); 4023#endif 4024 return; 4025} 4026 4027void 4028ahc_shutdown(void *arg) 4029{ 4030 struct ahc_softc *ahc; 4031 int i; 4032 4033 ahc = (struct ahc_softc *)arg; 4034 4035 /* This will reset most registers to 0, but not all */ 4036 ahc_reset(ahc); 4037 ahc_outb(ahc, SCSISEQ, 0); 4038 ahc_outb(ahc, SXFRCTL0, 0); 4039 ahc_outb(ahc, DSPCISTATUS, 0); 4040 4041 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 4042 ahc_outb(ahc, i, 0); 4043} 4044 4045/* 4046 * Reset the controller and record some information about it 4047 * that is only available just after a reset. 4048 */ 4049int 4050ahc_reset(struct ahc_softc *ahc) 4051{ 4052 u_int sblkctl; 4053 u_int sxfrctl1_a, sxfrctl1_b; 4054 int error; 4055 int wait; 4056 4057 /* 4058 * Preserve the value of the SXFRCTL1 register for all channels. 4059 * It contains settings that affect termination and we don't want 4060 * to disturb the integrity of the bus. 4061 */ 4062 ahc_pause(ahc); 4063 if ((ahc_inb(ahc, HCNTRL) & CHIPRST) != 0) { 4064 /* 4065 * The chip has not been initialized since 4066 * PCI/EISA/VLB bus reset. Don't trust 4067 * "left over BIOS data". 4068 */ 4069 ahc->flags |= AHC_NO_BIOS_INIT; 4070 } 4071 sxfrctl1_b = 0; 4072 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4073 u_int sblkctl; 4074 4075 /* 4076 * Save channel B's settings in case this chip 4077 * is setup for TWIN channel operation. 4078 */ 4079 sblkctl = ahc_inb(ahc, SBLKCTL); 4080 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4081 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4082 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4083 } 4084 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4085 4086 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4087 4088 /* 4089 * Ensure that the reset has finished. We delay 1000us 4090 * prior to reading the register to make sure the chip 4091 * has sufficiently completed its reset to handle register 4092 * accesses. 4093 */ 4094 wait = 1000; 4095 do { 4096 ahc_delay(1000); 4097 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4098 4099 if (wait == 0) { 4100 printf("%s: WARNING - Failed chip reset! " 4101 "Trying to initialize anyway.\n", ahc_name(ahc)); 4102 } 4103 ahc_outb(ahc, HCNTRL, ahc->pause); 4104 4105 /* Determine channel configuration */ 4106 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4107 /* No Twin Channel PCI cards */ 4108 if ((ahc->chip & AHC_PCI) != 0) 4109 sblkctl &= ~SELBUSB; 4110 switch (sblkctl) { 4111 case 0: 4112 /* Single Narrow Channel */ 4113 break; 4114 case 2: 4115 /* Wide Channel */ 4116 ahc->features |= AHC_WIDE; 4117 break; 4118 case 8: 4119 /* Twin Channel */ 4120 ahc->features |= AHC_TWIN; 4121 break; 4122 default: 4123 printf(" Unsupported adapter type. Ignoring\n"); 4124 return(-1); 4125 } 4126 4127 /* 4128 * Reload sxfrctl1. 4129 * 4130 * We must always initialize STPWEN to 1 before we 4131 * restore the saved values. STPWEN is initialized 4132 * to a tri-state condition which can only be cleared 4133 * by turning it on. 4134 */ 4135 if ((ahc->features & AHC_TWIN) != 0) { 4136 u_int sblkctl; 4137 4138 sblkctl = ahc_inb(ahc, SBLKCTL); 4139 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4140 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4141 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4142 } 4143 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4144 4145 error = 0; 4146 if (ahc->init_level > 0) 4147 /* 4148 * If a recovery action has forced a chip reset, 4149 * re-initialize the chip to our liking. 4150 */ 4151 error = ahc->bus_chip_init(ahc); 4152#ifdef AHC_DUMP_SEQ 4153 else 4154 ahc_dumpseq(ahc); 4155#endif 4156 4157 return (error); 4158} 4159 4160/* 4161 * Determine the number of SCBs available on the controller 4162 */ 4163int 4164ahc_probe_scbs(struct ahc_softc *ahc) { 4165 int i; 4166 4167 for (i = 0; i < AHC_SCB_MAX; i++) { 4168 4169 ahc_outb(ahc, SCBPTR, i); 4170 ahc_outb(ahc, SCB_BASE, i); 4171 if (ahc_inb(ahc, SCB_BASE) != i) 4172 break; 4173 ahc_outb(ahc, SCBPTR, 0); 4174 if (ahc_inb(ahc, SCB_BASE) != 0) 4175 break; 4176 } 4177 return (i); 4178} 4179 4180static void 4181ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4182{ 4183 bus_addr_t *baddr; 4184 4185 baddr = (bus_addr_t *)arg; 4186 *baddr = segs->ds_addr; 4187} 4188 4189static void 4190ahc_build_free_scb_list(struct ahc_softc *ahc) 4191{ 4192 int scbsize; 4193 int i; 4194 4195 scbsize = 32; 4196 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4197 scbsize = 64; 4198 4199 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4200 int j; 4201 4202 ahc_outb(ahc, SCBPTR, i); 4203 4204 /* 4205 * Touch all SCB bytes to avoid parity errors 4206 * should one of our debugging routines read 4207 * an otherwise uninitiatlized byte. 4208 */ 4209 for (j = 0; j < scbsize; j++) 4210 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4211 4212 /* Clear the control byte. */ 4213 ahc_outb(ahc, SCB_CONTROL, 0); 4214 4215 /* Set the next pointer */ 4216 if ((ahc->flags & AHC_PAGESCBS) != 0) 4217 ahc_outb(ahc, SCB_NEXT, i+1); 4218 else 4219 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4220 4221 /* Make the tag number, SCSIID, and lun invalid */ 4222 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4223 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4224 ahc_outb(ahc, SCB_LUN, 0xFF); 4225 } 4226 4227 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4228 /* SCB 0 heads the free list. */ 4229 ahc_outb(ahc, FREE_SCBH, 0); 4230 } else { 4231 /* No free list. */ 4232 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4233 } 4234 4235 /* Make sure that the last SCB terminates the free list */ 4236 ahc_outb(ahc, SCBPTR, i-1); 4237 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4238} 4239 4240static int 4241ahc_init_scbdata(struct ahc_softc *ahc) 4242{ 4243 struct scb_data *scb_data; 4244 4245 scb_data = ahc->scb_data; 4246 SLIST_INIT(&scb_data->free_scbs); 4247 SLIST_INIT(&scb_data->sg_maps); 4248 4249 /* Allocate SCB resources */ 4250 scb_data->scbarray = 4251 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, 4252 M_DEVBUF, M_NOWAIT); 4253 if (scb_data->scbarray == NULL) 4254 return (ENOMEM); 4255 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC); 4256 4257 /* Determine the number of hardware SCBs and initialize them */ 4258 4259 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4260 if (ahc->scb_data->maxhscbs == 0) { 4261 printf("%s: No SCB space found\n", ahc_name(ahc)); 4262 return (ENXIO); 4263 } 4264 4265 /* 4266 * Create our DMA tags. These tags define the kinds of device 4267 * accessible memory allocations and memory mappings we will 4268 * need to perform during normal operation. 4269 * 4270 * Unless we need to further restrict the allocation, we rely 4271 * on the restrictions of the parent dmat, hence the common 4272 * use of MAXADDR and MAXSIZE. 4273 */ 4274 4275 /* DMA tag for our hardware scb structures */ 4276 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4277 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4278 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4279 /*highaddr*/BUS_SPACE_MAXADDR, 4280 /*filter*/NULL, /*filterarg*/NULL, 4281 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4282 /*nsegments*/1, 4283 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4284 /*flags*/0, &scb_data->hscb_dmat) != 0) { 4285 goto error_exit; 4286 } 4287 4288 scb_data->init_level++; 4289 4290 /* Allocation for our hscbs */ 4291 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat, 4292 (void **)&scb_data->hscbs, 4293 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) { 4294 goto error_exit; 4295 } 4296 4297 scb_data->init_level++; 4298 4299 /* And permanently map them */ 4300 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap, 4301 scb_data->hscbs, 4302 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4303 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0); 4304 4305 scb_data->init_level++; 4306 4307 /* DMA tag for our sense buffers */ 4308 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4309 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4310 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4311 /*highaddr*/BUS_SPACE_MAXADDR, 4312 /*filter*/NULL, /*filterarg*/NULL, 4313 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4314 /*nsegments*/1, 4315 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4316 /*flags*/0, &scb_data->sense_dmat) != 0) { 4317 goto error_exit; 4318 } 4319 4320 scb_data->init_level++; 4321 4322 /* Allocate them */ 4323 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat, 4324 (void **)&scb_data->sense, 4325 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) { 4326 goto error_exit; 4327 } 4328 4329 scb_data->init_level++; 4330 4331 /* And permanently map them */ 4332 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap, 4333 scb_data->sense, 4334 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4335 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0); 4336 4337 scb_data->init_level++; 4338 4339 /* DMA tag for our S/G structures. We allocate in page sized chunks */ 4340 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8, 4341 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4342 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4343 /*highaddr*/BUS_SPACE_MAXADDR, 4344 /*filter*/NULL, /*filterarg*/NULL, 4345 PAGE_SIZE, /*nsegments*/1, 4346 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4347 /*flags*/0, &scb_data->sg_dmat) != 0) { 4348 goto error_exit; 4349 } 4350 4351 scb_data->init_level++; 4352 4353 /* Perform initial CCB allocation */ 4354 memset(scb_data->hscbs, 0, 4355 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4356 ahc_alloc_scbs(ahc); 4357 4358 if (scb_data->numscbs == 0) { 4359 printf("%s: ahc_init_scbdata - " 4360 "Unable to allocate initial scbs\n", 4361 ahc_name(ahc)); 4362 goto error_exit; 4363 } 4364 4365 /* 4366 * Reserve the next queued SCB. 4367 */ 4368 ahc->next_queued_scb = ahc_get_scb(ahc); 4369 4370 /* 4371 * Note that we were successfull 4372 */ 4373 return (0); 4374 4375error_exit: 4376 4377 return (ENOMEM); 4378} 4379 4380static void 4381ahc_fini_scbdata(struct ahc_softc *ahc) 4382{ 4383 struct scb_data *scb_data; 4384 4385 scb_data = ahc->scb_data; 4386 if (scb_data == NULL) 4387 return; 4388 4389 switch (scb_data->init_level) { 4390 default: 4391 case 7: 4392 { 4393 struct sg_map_node *sg_map; 4394 4395 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4396 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4397 ahc_dmamap_unload(ahc, scb_data->sg_dmat, 4398 sg_map->sg_dmamap); 4399 ahc_dmamem_free(ahc, scb_data->sg_dmat, 4400 sg_map->sg_vaddr, 4401 sg_map->sg_dmamap); 4402 free(sg_map, M_DEVBUF); 4403 } 4404 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat); 4405 } 4406 case 6: 4407 ahc_dmamap_unload(ahc, scb_data->sense_dmat, 4408 scb_data->sense_dmamap); 4409 case 5: 4410 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense, 4411 scb_data->sense_dmamap); 4412 ahc_dmamap_destroy(ahc, scb_data->sense_dmat, 4413 scb_data->sense_dmamap); 4414 case 4: 4415 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat); 4416 case 3: 4417 ahc_dmamap_unload(ahc, scb_data->hscb_dmat, 4418 scb_data->hscb_dmamap); 4419 case 2: 4420 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs, 4421 scb_data->hscb_dmamap); 4422 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat, 4423 scb_data->hscb_dmamap); 4424 case 1: 4425 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat); 4426 break; 4427 case 0: 4428 break; 4429 } 4430 if (scb_data->scbarray != NULL) 4431 free(scb_data->scbarray, M_DEVBUF); 4432} 4433 4434void 4435ahc_alloc_scbs(struct ahc_softc *ahc) 4436{ 4437 struct scb_data *scb_data; 4438 struct scb *next_scb; 4439 struct sg_map_node *sg_map; 4440 bus_addr_t physaddr; 4441 struct ahc_dma_seg *segs; 4442 int newcount; 4443 int i; 4444 4445 scb_data = ahc->scb_data; 4446 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4447 /* Can't allocate any more */ 4448 return; 4449 4450 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4451 4452 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4453 4454 if (sg_map == NULL) 4455 return; 4456 4457 /* Allocate S/G space for the next batch of SCBS */ 4458 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat, 4459 (void **)&sg_map->sg_vaddr, 4460 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { 4461 free(sg_map, M_DEVBUF); 4462 return; 4463 } 4464 4465 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4466 4467 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap, 4468 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb, 4469 &sg_map->sg_physaddr, /*flags*/0); 4470 4471 segs = sg_map->sg_vaddr; 4472 physaddr = sg_map->sg_physaddr; 4473 4474 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4475 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4476 for (i = 0; i < newcount; i++) { 4477 struct scb_platform_data *pdata; 4478#ifndef __linux__ 4479 int error; 4480#endif 4481 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 4482 M_DEVBUF, M_NOWAIT); 4483 if (pdata == NULL) 4484 break; 4485 next_scb->platform_data = pdata; 4486 next_scb->sg_map = sg_map; 4487 next_scb->sg_list = segs; 4488 /* 4489 * The sequencer always starts with the second entry. 4490 * The first entry is embedded in the scb. 4491 */ 4492 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4493 next_scb->ahc_softc = ahc; 4494 next_scb->flags = SCB_FREE; 4495#ifndef __linux__ 4496 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0, 4497 &next_scb->dmamap); 4498 if (error != 0) 4499 break; 4500#endif 4501 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4502 next_scb->hscb->tag = ahc->scb_data->numscbs; 4503 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4504 next_scb, links.sle); 4505 segs += AHC_NSEG; 4506 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4507 next_scb++; 4508 ahc->scb_data->numscbs++; 4509 } 4510} 4511 4512void 4513ahc_controller_info(struct ahc_softc *ahc, char *buf) 4514{ 4515 int len; 4516 4517 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4518 buf += len; 4519 if ((ahc->features & AHC_TWIN) != 0) 4520 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " 4521 "B SCSI Id=%d, primary %c, ", 4522 ahc->our_id, ahc->our_id_b, 4523 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4524 else { 4525 const char *speed; 4526 const char *type; 4527 4528 speed = ""; 4529 if ((ahc->features & AHC_ULTRA) != 0) { 4530 speed = "Ultra "; 4531 } else if ((ahc->features & AHC_DT) != 0) { 4532 speed = "Ultra160 "; 4533 } else if ((ahc->features & AHC_ULTRA2) != 0) { 4534 speed = "Ultra2 "; 4535 } 4536 if ((ahc->features & AHC_WIDE) != 0) { 4537 type = "Wide"; 4538 } else { 4539 type = "Single"; 4540 } 4541 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ", 4542 speed, type, ahc->channel, ahc->our_id); 4543 } 4544 buf += len; 4545 4546 if ((ahc->flags & AHC_PAGESCBS) != 0) 4547 sprintf(buf, "%d/%d SCBs", 4548 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 4549 else 4550 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); 4551} 4552 4553int 4554ahc_chip_init(struct ahc_softc *ahc) 4555{ 4556 int term; 4557 int error; 4558 u_int i; 4559 u_int scsi_conf; 4560 u_int scsiseq_template; 4561 uint32_t physaddr; 4562 4563 ahc_outb(ahc, SEQ_FLAGS, 0); 4564 ahc_outb(ahc, SEQ_FLAGS2, 0); 4565 4566 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4567 if (ahc->features & AHC_TWIN) { 4568 4569 /* 4570 * Setup Channel B first. 4571 */ 4572 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4573 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4574 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4575 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4576 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4577 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4578 if ((ahc->features & AHC_ULTRA2) != 0) 4579 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4580 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4581 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4582 4583 /* Select Channel A */ 4584 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4585 } 4586 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4587 if ((ahc->features & AHC_ULTRA2) != 0) 4588 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4589 else 4590 ahc_outb(ahc, SCSIID, ahc->our_id); 4591 scsi_conf = ahc_inb(ahc, SCSICONF); 4592 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4593 |term|ahc->seltime 4594 |ENSTIMER|ACTNEGEN); 4595 if ((ahc->features & AHC_ULTRA2) != 0) 4596 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4597 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4598 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4599 4600 /* There are no untagged SCBs active yet. */ 4601 for (i = 0; i < 16; i++) { 4602 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4603 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4604 int lun; 4605 4606 /* 4607 * The SCB based BTT allows an entry per 4608 * target and lun pair. 4609 */ 4610 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4611 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4612 } 4613 } 4614 4615 /* All of our queues are empty */ 4616 for (i = 0; i < 256; i++) 4617 ahc->qoutfifo[i] = SCB_LIST_NULL; 4618 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 4619 4620 for (i = 0; i < 256; i++) 4621 ahc->qinfifo[i] = SCB_LIST_NULL; 4622 4623 if ((ahc->features & AHC_MULTI_TID) != 0) { 4624 ahc_outb(ahc, TARGID, 0); 4625 ahc_outb(ahc, TARGID + 1, 0); 4626 } 4627 4628 /* 4629 * Tell the sequencer where it can find our arrays in memory. 4630 */ 4631 physaddr = ahc->scb_data->hscb_busaddr; 4632 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4633 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4634 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4635 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4636 4637 physaddr = ahc->shared_data_busaddr; 4638 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4639 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4640 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4641 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4642 4643 /* 4644 * Initialize the group code to command length table. 4645 * This overrides the values in TARG_SCSIRATE, so only 4646 * setup the table after we have processed that information. 4647 */ 4648 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4649 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4650 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4651 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4652 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4653 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4654 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4655 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4656 4657 if ((ahc->features & AHC_HS_MAILBOX) != 0) 4658 ahc_outb(ahc, HS_MAILBOX, 0); 4659 4660 /* Tell the sequencer of our initial queue positions */ 4661 if ((ahc->features & AHC_TARGETMODE) != 0) { 4662 ahc->tqinfifonext = 1; 4663 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4664 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4665 } 4666 ahc->qinfifonext = 0; 4667 ahc->qoutfifonext = 0; 4668 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4669 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4670 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4671 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext); 4672 ahc_outb(ahc, SDSCB_QOFF, 0); 4673 } else { 4674 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4675 ahc_outb(ahc, QINPOS, ahc->qinfifonext); 4676 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext); 4677 } 4678 4679 /* We don't have any waiting selections */ 4680 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4681 4682 /* Our disconnection list is empty too */ 4683 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4684 4685 /* Message out buffer starts empty */ 4686 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4687 4688 /* 4689 * Setup the allowed SCSI Sequences based on operational mode. 4690 * If we are a target, we'll enalbe select in operations once 4691 * we've had a lun enabled. 4692 */ 4693 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4694 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4695 scsiseq_template |= ENRSELI; 4696 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4697 4698 /* Initialize our list of free SCBs. */ 4699 ahc_build_free_scb_list(ahc); 4700 4701 /* 4702 * Tell the sequencer which SCB will be the next one it receives. 4703 */ 4704 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4705 4706 /* 4707 * Load the Sequencer program and Enable the adapter 4708 * in "fast" mode. 4709 */ 4710 if (bootverbose) 4711 printf("%s: Downloading Sequencer Program...", 4712 ahc_name(ahc)); 4713 4714 error = ahc_loadseq(ahc); 4715 if (error != 0) 4716 return (error); 4717 4718 if ((ahc->features & AHC_ULTRA2) != 0) { 4719 int wait; 4720 4721 /* 4722 * Wait for up to 500ms for our transceivers 4723 * to settle. If the adapter does not have 4724 * a cable attached, the transceivers may 4725 * never settle, so don't complain if we 4726 * fail here. 4727 */ 4728 ahc_pause(ahc); 4729 for (wait = 5000; 4730 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4731 wait--) 4732 ahc_delay(100); 4733 ahc_unpause(ahc); 4734 } 4735 4736 return (0); 4737} 4738 4739/* 4740 * Start the board, ready for normal operation 4741 */ 4742int 4743ahc_init(struct ahc_softc *ahc) 4744{ 4745 int max_targ; 4746 u_int i; 4747 u_int scsi_conf; 4748 u_int ultraenb; 4749 u_int discenable; 4750 u_int tagenable; 4751 size_t driver_data_size; 4752 4753#ifdef AHC_DEBUG 4754 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 4755 ahc->flags |= AHC_SEQUENCER_DEBUG; 4756#endif 4757 4758#ifdef AHC_PRINT_SRAM 4759 printf("Scratch Ram:"); 4760 for (i = 0x20; i < 0x5f; i++) { 4761 if (((i % 8) == 0) && (i != 0)) { 4762 printf ("\n "); 4763 } 4764 printf (" 0x%x", ahc_inb(ahc, i)); 4765 } 4766 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4767 for (i = 0x70; i < 0x7f; i++) { 4768 if (((i % 8) == 0) && (i != 0)) { 4769 printf ("\n "); 4770 } 4771 printf (" 0x%x", ahc_inb(ahc, i)); 4772 } 4773 } 4774 printf ("\n"); 4775 /* 4776 * Reading uninitialized scratch ram may 4777 * generate parity errors. 4778 */ 4779 ahc_outb(ahc, CLRINT, CLRPARERR); 4780 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 4781#endif 4782 max_targ = 15; 4783 4784 /* 4785 * Assume we have a board at this stage and it has been reset. 4786 */ 4787 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4788 ahc->our_id = ahc->our_id_b = 7; 4789 4790 /* 4791 * Default to allowing initiator operations. 4792 */ 4793 ahc->flags |= AHC_INITIATORROLE; 4794 4795 /* 4796 * Only allow target mode features if this unit has them enabled. 4797 */ 4798 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4799 ahc->features &= ~AHC_TARGETMODE; 4800 4801#ifndef __linux__ 4802 /* DMA tag for mapping buffers into device visible space. */ 4803 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4804 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4805 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING 4806 ? (bus_addr_t)0x7FFFFFFFFFULL 4807 : BUS_SPACE_MAXADDR_32BIT, 4808 /*highaddr*/BUS_SPACE_MAXADDR, 4809 /*filter*/NULL, /*filterarg*/NULL, 4810 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE, 4811 /*nsegments*/AHC_NSEG, 4812 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 4813 /*flags*/BUS_DMA_ALLOCNOW, 4814 &ahc->buffer_dmat) != 0) { 4815 return (ENOMEM); 4816 } 4817#endif 4818 4819 ahc->init_level++; 4820 4821 /* 4822 * DMA tag for our command fifos and other data in system memory 4823 * the card's sequencer must be able to access. For initiator 4824 * roles, we need to allocate space for the qinfifo and qoutfifo. 4825 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4826 * When providing for the target mode role, we must additionally 4827 * provide space for the incoming target command fifo and an extra 4828 * byte to deal with a dma bug in some chip versions. 4829 */ 4830 driver_data_size = 2 * 256 * sizeof(uint8_t); 4831 if ((ahc->features & AHC_TARGETMODE) != 0) 4832 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4833 + /*DMA WideOdd Bug Buffer*/1; 4834 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4835 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4836 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4837 /*highaddr*/BUS_SPACE_MAXADDR, 4838 /*filter*/NULL, /*filterarg*/NULL, 4839 driver_data_size, 4840 /*nsegments*/1, 4841 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4842 /*flags*/0, &ahc->shared_data_dmat) != 0) { 4843 return (ENOMEM); 4844 } 4845 4846 ahc->init_level++; 4847 4848 /* Allocation of driver data */ 4849 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat, 4850 (void **)&ahc->qoutfifo, 4851 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) { 4852 return (ENOMEM); 4853 } 4854 4855 ahc->init_level++; 4856 4857 /* And permanently map it in */ 4858 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, 4859 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb, 4860 &ahc->shared_data_busaddr, /*flags*/0); 4861 4862 if ((ahc->features & AHC_TARGETMODE) != 0) { 4863 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4864 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4865 ahc->dma_bug_buf = ahc->shared_data_busaddr 4866 + driver_data_size - 1; 4867 /* All target command blocks start out invalid. */ 4868 for (i = 0; i < AHC_TMODE_CMDS; i++) 4869 ahc->targetcmds[i].cmd_valid = 0; 4870 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 4871 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4872 } 4873 ahc->qinfifo = &ahc->qoutfifo[256]; 4874 4875 ahc->init_level++; 4876 4877 /* Allocate SCB data now that buffer_dmat is initialized */ 4878 if (ahc->scb_data->maxhscbs == 0) 4879 if (ahc_init_scbdata(ahc) != 0) 4880 return (ENOMEM); 4881 4882 /* 4883 * Allocate a tstate to house information for our 4884 * initiator presence on the bus as well as the user 4885 * data for any target mode initiator. 4886 */ 4887 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4888 printf("%s: unable to allocate ahc_tmode_tstate. " 4889 "Failing attach\n", ahc_name(ahc)); 4890 return (ENOMEM); 4891 } 4892 4893 if ((ahc->features & AHC_TWIN) != 0) { 4894 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4895 printf("%s: unable to allocate ahc_tmode_tstate. " 4896 "Failing attach\n", ahc_name(ahc)); 4897 return (ENOMEM); 4898 } 4899 } 4900 4901 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 4902 ahc->flags |= AHC_PAGESCBS; 4903 } else { 4904 ahc->flags &= ~AHC_PAGESCBS; 4905 } 4906 4907#ifdef AHC_DEBUG 4908 if (ahc_debug & AHC_SHOW_MISC) { 4909 printf("%s: hardware scb %u bytes; kernel scb %u bytes; " 4910 "ahc_dma %u bytes\n", 4911 ahc_name(ahc), 4912 (u_int)sizeof(struct hardware_scb), 4913 (u_int)sizeof(struct scb), 4914 (u_int)sizeof(struct ahc_dma_seg)); 4915 } 4916#endif /* AHC_DEBUG */ 4917 4918 /* 4919 * Look at the information that board initialization or 4920 * the board bios has left us. 4921 */ 4922 if (ahc->features & AHC_TWIN) { 4923 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4924 if ((scsi_conf & RESET_SCSI) != 0 4925 && (ahc->flags & AHC_INITIATORROLE) != 0) 4926 ahc->flags |= AHC_RESET_BUS_B; 4927 } 4928 4929 scsi_conf = ahc_inb(ahc, SCSICONF); 4930 if ((scsi_conf & RESET_SCSI) != 0 4931 && (ahc->flags & AHC_INITIATORROLE) != 0) 4932 ahc->flags |= AHC_RESET_BUS_A; 4933 4934 ultraenb = 0; 4935 tagenable = ALL_TARGETS_MASK; 4936 4937 /* Grab the disconnection disable table and invert it for our needs */ 4938 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 4939 printf("%s: Host Adapter Bios disabled. Using default SCSI " 4940 "device parameters\n", ahc_name(ahc)); 4941 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 4942 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 4943 discenable = ALL_TARGETS_MASK; 4944 if ((ahc->features & AHC_ULTRA) != 0) 4945 ultraenb = ALL_TARGETS_MASK; 4946 } else { 4947 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 4948 | ahc_inb(ahc, DISC_DSB)); 4949 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 4950 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 4951 | ahc_inb(ahc, ULTRA_ENB); 4952 } 4953 4954 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 4955 max_targ = 7; 4956 4957 for (i = 0; i <= max_targ; i++) { 4958 struct ahc_initiator_tinfo *tinfo; 4959 struct ahc_tmode_tstate *tstate; 4960 u_int our_id; 4961 u_int target_id; 4962 char channel; 4963 4964 channel = 'A'; 4965 our_id = ahc->our_id; 4966 target_id = i; 4967 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 4968 channel = 'B'; 4969 our_id = ahc->our_id_b; 4970 target_id = i % 8; 4971 } 4972 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 4973 target_id, &tstate); 4974 /* Default to async narrow across the board */ 4975 memset(tinfo, 0, sizeof(*tinfo)); 4976 if (ahc->flags & AHC_USEDEFAULTS) { 4977 if ((ahc->features & AHC_WIDE) != 0) 4978 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4979 4980 /* 4981 * These will be truncated when we determine the 4982 * connection type we have with the target. 4983 */ 4984 tinfo->user.period = ahc_syncrates->period; 4985 tinfo->user.offset = MAX_OFFSET; 4986 } else { 4987 u_int scsirate; 4988 uint16_t mask; 4989 4990 /* Take the settings leftover in scratch RAM. */ 4991 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 4992 mask = (0x01 << i); 4993 if ((ahc->features & AHC_ULTRA2) != 0) { 4994 u_int offset; 4995 u_int maxsync; 4996 4997 if ((scsirate & SOFS) == 0x0F) { 4998 /* 4999 * Haven't negotiated yet, 5000 * so the format is different. 5001 */ 5002 scsirate = (scsirate & SXFR) >> 4 5003 | (ultraenb & mask) 5004 ? 0x08 : 0x0 5005 | (scsirate & WIDEXFER); 5006 offset = MAX_OFFSET_ULTRA2; 5007 } else 5008 offset = ahc_inb(ahc, TARG_OFFSET + i); 5009 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 5010 /* Set to the lowest sync rate, 5MHz */ 5011 scsirate |= 0x1c; 5012 maxsync = AHC_SYNCRATE_ULTRA2; 5013 if ((ahc->features & AHC_DT) != 0) 5014 maxsync = AHC_SYNCRATE_DT; 5015 tinfo->user.period = 5016 ahc_find_period(ahc, scsirate, maxsync); 5017 if (offset == 0) 5018 tinfo->user.period = 0; 5019 else 5020 tinfo->user.offset = MAX_OFFSET; 5021 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 5022 && (ahc->features & AHC_DT) != 0) 5023 tinfo->user.ppr_options = 5024 MSG_EXT_PPR_DT_REQ; 5025 } else if ((scsirate & SOFS) != 0) { 5026 if ((scsirate & SXFR) == 0x40 5027 && (ultraenb & mask) != 0) { 5028 /* Treat 10MHz as a non-ultra speed */ 5029 scsirate &= ~SXFR; 5030 ultraenb &= ~mask; 5031 } 5032 tinfo->user.period = 5033 ahc_find_period(ahc, scsirate, 5034 (ultraenb & mask) 5035 ? AHC_SYNCRATE_ULTRA 5036 : AHC_SYNCRATE_FAST); 5037 if (tinfo->user.period != 0) 5038 tinfo->user.offset = MAX_OFFSET; 5039 } 5040 if (tinfo->user.period == 0) 5041 tinfo->user.offset = 0; 5042 if ((scsirate & WIDEXFER) != 0 5043 && (ahc->features & AHC_WIDE) != 0) 5044 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 5045 tinfo->user.protocol_version = 4; 5046 if ((ahc->features & AHC_DT) != 0) 5047 tinfo->user.transport_version = 3; 5048 else 5049 tinfo->user.transport_version = 2; 5050 tinfo->goal.protocol_version = 2; 5051 tinfo->goal.transport_version = 2; 5052 tinfo->curr.protocol_version = 2; 5053 tinfo->curr.transport_version = 2; 5054 } 5055 tstate->ultraenb = 0; 5056 } 5057 ahc->user_discenable = discenable; 5058 ahc->user_tagenable = tagenable; 5059 5060 return (ahc->bus_chip_init(ahc)); 5061} 5062 5063void 5064ahc_intr_enable(struct ahc_softc *ahc, int enable) 5065{ 5066 u_int hcntrl; 5067 5068 hcntrl = ahc_inb(ahc, HCNTRL); 5069 hcntrl &= ~INTEN; 5070 ahc->pause &= ~INTEN; 5071 ahc->unpause &= ~INTEN; 5072 if (enable) { 5073 hcntrl |= INTEN; 5074 ahc->pause |= INTEN; 5075 ahc->unpause |= INTEN; 5076 } 5077 ahc_outb(ahc, HCNTRL, hcntrl); 5078} 5079 5080/* 5081 * Ensure that the card is paused in a location 5082 * outside of all critical sections and that all 5083 * pending work is completed prior to returning. 5084 * This routine should only be called from outside 5085 * an interrupt context. 5086 */ 5087void 5088ahc_pause_and_flushwork(struct ahc_softc *ahc) 5089{ 5090 int intstat; 5091 int maxloops; 5092 int paused; 5093 5094 maxloops = 1000; 5095 ahc->flags |= AHC_ALL_INTERRUPTS; 5096 paused = FALSE; 5097 do { 5098 if (paused) 5099 ahc_unpause(ahc); 5100 ahc_intr(ahc); 5101 ahc_pause(ahc); 5102 paused = TRUE; 5103 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO); 5104 ahc_clear_critical_section(ahc); 5105 intstat = ahc_inb(ahc, INTSTAT); 5106 } while (--maxloops 5107 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0) 5108 && ((intstat & INT_PEND) != 0 5109 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0)); 5110 if (maxloops == 0) { 5111 printf("Infinite interrupt loop, INTSTAT = %x", 5112 ahc_inb(ahc, INTSTAT)); 5113 } 5114 ahc_platform_flushwork(ahc); 5115 ahc->flags &= ~AHC_ALL_INTERRUPTS; 5116} 5117 5118int 5119ahc_suspend(struct ahc_softc *ahc) 5120{ 5121 5122 ahc_pause_and_flushwork(ahc); 5123 5124 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 5125 ahc_unpause(ahc); 5126 return (EBUSY); 5127 } 5128 5129#if AHC_TARGET_MODE 5130 /* 5131 * XXX What about ATIOs that have not yet been serviced? 5132 * Perhaps we should just refuse to be suspended if we 5133 * are acting in a target role. 5134 */ 5135 if (ahc->pending_device != NULL) { 5136 ahc_unpause(ahc); 5137 return (EBUSY); 5138 } 5139#endif 5140 ahc_shutdown(ahc); 5141 return (0); 5142} 5143 5144int 5145ahc_resume(struct ahc_softc *ahc) 5146{ 5147 5148 ahc_reset(ahc); 5149 return (0); 5150} 5151 5152/************************** Busy Target Table *********************************/ 5153/* 5154 * Return the untagged transaction id for a given target/channel lun. 5155 * Optionally, clear the entry. 5156 */ 5157u_int 5158ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5159{ 5160 u_int scbid; 5161 u_int target_offset; 5162 5163 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5164 u_int saved_scbptr; 5165 5166 saved_scbptr = ahc_inb(ahc, SCBPTR); 5167 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5168 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5169 ahc_outb(ahc, SCBPTR, saved_scbptr); 5170 } else { 5171 target_offset = TCL_TARGET_OFFSET(tcl); 5172 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5173 } 5174 5175 return (scbid); 5176} 5177 5178void 5179ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5180{ 5181 u_int target_offset; 5182 5183 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5184 u_int saved_scbptr; 5185 5186 saved_scbptr = ahc_inb(ahc, SCBPTR); 5187 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5188 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5189 ahc_outb(ahc, SCBPTR, saved_scbptr); 5190 } else { 5191 target_offset = TCL_TARGET_OFFSET(tcl); 5192 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5193 } 5194} 5195 5196void 5197ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5198{ 5199 u_int target_offset; 5200 5201 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5202 u_int saved_scbptr; 5203 5204 saved_scbptr = ahc_inb(ahc, SCBPTR); 5205 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5206 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5207 ahc_outb(ahc, SCBPTR, saved_scbptr); 5208 } else { 5209 target_offset = TCL_TARGET_OFFSET(tcl); 5210 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5211 } 5212} 5213 5214/************************** SCB and SCB queue management **********************/ 5215int 5216ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5217 char channel, int lun, u_int tag, role_t role) 5218{ 5219 int targ = SCB_GET_TARGET(ahc, scb); 5220 char chan = SCB_GET_CHANNEL(ahc, scb); 5221 int slun = SCB_GET_LUN(scb); 5222 int match; 5223 5224 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5225 if (match != 0) 5226 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5227 if (match != 0) 5228 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5229 if (match != 0) { 5230#if AHC_TARGET_MODE 5231 int group; 5232 5233 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5234 if (role == ROLE_INITIATOR) { 5235 match = (group != XPT_FC_GROUP_TMODE) 5236 && ((tag == scb->hscb->tag) 5237 || (tag == SCB_LIST_NULL)); 5238 } else if (role == ROLE_TARGET) { 5239 match = (group == XPT_FC_GROUP_TMODE) 5240 && ((tag == scb->io_ctx->csio.tag_id) 5241 || (tag == SCB_LIST_NULL)); 5242 } 5243#else /* !AHC_TARGET_MODE */ 5244 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5245#endif /* AHC_TARGET_MODE */ 5246 } 5247 5248 return match; 5249} 5250 5251void 5252ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5253{ 5254 int target; 5255 char channel; 5256 int lun; 5257 5258 target = SCB_GET_TARGET(ahc, scb); 5259 lun = SCB_GET_LUN(scb); 5260 channel = SCB_GET_CHANNEL(ahc, scb); 5261 5262 ahc_search_qinfifo(ahc, target, channel, lun, 5263 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5264 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5265 5266 ahc_platform_freeze_devq(ahc, scb); 5267} 5268 5269void 5270ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5271{ 5272 struct scb *prev_scb; 5273 5274 prev_scb = NULL; 5275 if (ahc_qinfifo_count(ahc) != 0) { 5276 u_int prev_tag; 5277 uint8_t prev_pos; 5278 5279 prev_pos = ahc->qinfifonext - 1; 5280 prev_tag = ahc->qinfifo[prev_pos]; 5281 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5282 } 5283 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5284 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5285 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5286 } else { 5287 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5288 } 5289} 5290 5291static void 5292ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5293 struct scb *scb) 5294{ 5295 if (prev_scb == NULL) { 5296 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5297 } else { 5298 prev_scb->hscb->next = scb->hscb->tag; 5299 ahc_sync_scb(ahc, prev_scb, 5300 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5301 } 5302 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 5303 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5304 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5305} 5306 5307static int 5308ahc_qinfifo_count(struct ahc_softc *ahc) 5309{ 5310 uint8_t qinpos; 5311 uint8_t diff; 5312 5313 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5314 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5315 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5316 } else 5317 qinpos = ahc_inb(ahc, QINPOS); 5318 diff = ahc->qinfifonext - qinpos; 5319 return (diff); 5320} 5321 5322int 5323ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5324 int lun, u_int tag, role_t role, uint32_t status, 5325 ahc_search_action action) 5326{ 5327 struct scb *scb; 5328 struct scb *prev_scb; 5329 uint8_t qinstart; 5330 uint8_t qinpos; 5331 uint8_t qintail; 5332 uint8_t next; 5333 uint8_t prev; 5334 uint8_t curscbptr; 5335 int found; 5336 int have_qregs; 5337 5338 qintail = ahc->qinfifonext; 5339 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5340 if (have_qregs) { 5341 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5342 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5343 } else 5344 qinstart = ahc_inb(ahc, QINPOS); 5345 qinpos = qinstart; 5346 found = 0; 5347 prev_scb = NULL; 5348 5349 if (action == SEARCH_COMPLETE) { 5350 /* 5351 * Don't attempt to run any queued untagged transactions 5352 * until we are done with the abort process. 5353 */ 5354 ahc_freeze_untagged_queues(ahc); 5355 } 5356 5357 /* 5358 * Start with an empty queue. Entries that are not chosen 5359 * for removal will be re-added to the queue as we go. 5360 */ 5361 ahc->qinfifonext = qinpos; 5362 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5363 5364 while (qinpos != qintail) { 5365 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5366 if (scb == NULL) { 5367 printf("qinpos = %d, SCB index = %d\n", 5368 qinpos, ahc->qinfifo[qinpos]); 5369 panic("Loop 1\n"); 5370 } 5371 5372 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5373 /* 5374 * We found an scb that needs to be acted on. 5375 */ 5376 found++; 5377 switch (action) { 5378 case SEARCH_COMPLETE: 5379 { 5380 cam_status ostat; 5381 cam_status cstat; 5382 5383 ostat = ahc_get_transaction_status(scb); 5384 if (ostat == CAM_REQ_INPROG) 5385 ahc_set_transaction_status(scb, status); 5386 cstat = ahc_get_transaction_status(scb); 5387 if (cstat != CAM_REQ_CMP) 5388 ahc_freeze_scb(scb); 5389 if ((scb->flags & SCB_ACTIVE) == 0) 5390 printf("Inactive SCB in qinfifo\n"); 5391 ahc_done(ahc, scb); 5392 5393 /* FALLTHROUGH */ 5394 } 5395 case SEARCH_REMOVE: 5396 break; 5397 case SEARCH_COUNT: 5398 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5399 prev_scb = scb; 5400 break; 5401 } 5402 } else { 5403 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5404 prev_scb = scb; 5405 } 5406 qinpos++; 5407 } 5408 5409 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5410 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5411 } else { 5412 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5413 } 5414 5415 if (action != SEARCH_COUNT 5416 && (found != 0) 5417 && (qinstart != ahc->qinfifonext)) { 5418 /* 5419 * The sequencer may be in the process of dmaing 5420 * down the SCB at the beginning of the queue. 5421 * This could be problematic if either the first, 5422 * or the second SCB is removed from the queue 5423 * (the first SCB includes a pointer to the "next" 5424 * SCB to dma). If we have removed any entries, swap 5425 * the first element in the queue with the next HSCB 5426 * so the sequencer will notice that NEXT_QUEUED_SCB 5427 * has changed during its dma attempt and will retry 5428 * the DMA. 5429 */ 5430 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5431 5432 if (scb == NULL) { 5433 printf("found = %d, qinstart = %d, qinfifionext = %d\n", 5434 found, qinstart, ahc->qinfifonext); 5435 panic("First/Second Qinfifo fixup\n"); 5436 } 5437 /* 5438 * ahc_swap_with_next_hscb forces our next pointer to 5439 * point to the reserved SCB for future commands. Save 5440 * and restore our original next pointer to maintain 5441 * queue integrity. 5442 */ 5443 next = scb->hscb->next; 5444 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5445 ahc_swap_with_next_hscb(ahc, scb); 5446 scb->hscb->next = next; 5447 ahc->qinfifo[qinstart] = scb->hscb->tag; 5448 5449 /* Tell the card about the new head of the qinfifo. */ 5450 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5451 5452 /* Fixup the tail "next" pointer. */ 5453 qintail = ahc->qinfifonext - 1; 5454 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5455 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5456 } 5457 5458 /* 5459 * Search waiting for selection list. 5460 */ 5461 curscbptr = ahc_inb(ahc, SCBPTR); 5462 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5463 prev = SCB_LIST_NULL; 5464 5465 while (next != SCB_LIST_NULL) { 5466 uint8_t scb_index; 5467 5468 ahc_outb(ahc, SCBPTR, next); 5469 scb_index = ahc_inb(ahc, SCB_TAG); 5470 if (scb_index >= ahc->scb_data->numscbs) { 5471 printf("Waiting List inconsistency. " 5472 "SCB index == %d, yet numscbs == %d.", 5473 scb_index, ahc->scb_data->numscbs); 5474 ahc_dump_card_state(ahc); 5475 panic("for safety"); 5476 } 5477 scb = ahc_lookup_scb(ahc, scb_index); 5478 if (scb == NULL) { 5479 printf("scb_index = %d, next = %d\n", 5480 scb_index, next); 5481 panic("Waiting List traversal\n"); 5482 } 5483 if (ahc_match_scb(ahc, scb, target, channel, 5484 lun, SCB_LIST_NULL, role)) { 5485 /* 5486 * We found an scb that needs to be acted on. 5487 */ 5488 found++; 5489 switch (action) { 5490 case SEARCH_COMPLETE: 5491 { 5492 cam_status ostat; 5493 cam_status cstat; 5494 5495 ostat = ahc_get_transaction_status(scb); 5496 if (ostat == CAM_REQ_INPROG) 5497 ahc_set_transaction_status(scb, 5498 status); 5499 cstat = ahc_get_transaction_status(scb); 5500 if (cstat != CAM_REQ_CMP) 5501 ahc_freeze_scb(scb); 5502 if ((scb->flags & SCB_ACTIVE) == 0) 5503 printf("Inactive SCB in Waiting List\n"); 5504 ahc_done(ahc, scb); 5505 /* FALLTHROUGH */ 5506 } 5507 case SEARCH_REMOVE: 5508 next = ahc_rem_wscb(ahc, next, prev); 5509 break; 5510 case SEARCH_COUNT: 5511 prev = next; 5512 next = ahc_inb(ahc, SCB_NEXT); 5513 break; 5514 } 5515 } else { 5516 5517 prev = next; 5518 next = ahc_inb(ahc, SCB_NEXT); 5519 } 5520 } 5521 ahc_outb(ahc, SCBPTR, curscbptr); 5522 5523 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target, 5524 channel, lun, status, action); 5525 5526 if (action == SEARCH_COMPLETE) 5527 ahc_release_untagged_queues(ahc); 5528 return (found); 5529} 5530 5531int 5532ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx, 5533 int target, char channel, int lun, uint32_t status, 5534 ahc_search_action action) 5535{ 5536 struct scb *scb; 5537 int maxtarget; 5538 int found; 5539 int i; 5540 5541 if (action == SEARCH_COMPLETE) { 5542 /* 5543 * Don't attempt to run any queued untagged transactions 5544 * until we are done with the abort process. 5545 */ 5546 ahc_freeze_untagged_queues(ahc); 5547 } 5548 5549 found = 0; 5550 i = 0; 5551 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5552 5553 maxtarget = 16; 5554 if (target != CAM_TARGET_WILDCARD) { 5555 5556 i = target; 5557 if (channel == 'B') 5558 i += 8; 5559 maxtarget = i + 1; 5560 } 5561 } else { 5562 maxtarget = 0; 5563 } 5564 5565 for (; i < maxtarget; i++) { 5566 struct scb_tailq *untagged_q; 5567 struct scb *next_scb; 5568 5569 untagged_q = &(ahc->untagged_queues[i]); 5570 next_scb = TAILQ_FIRST(untagged_q); 5571 while (next_scb != NULL) { 5572 5573 scb = next_scb; 5574 next_scb = TAILQ_NEXT(scb, links.tqe); 5575 5576 /* 5577 * The head of the list may be the currently 5578 * active untagged command for a device. 5579 * We're only searching for commands that 5580 * have not been started. A transaction 5581 * marked active but still in the qinfifo 5582 * is removed by the qinfifo scanning code 5583 * above. 5584 */ 5585 if ((scb->flags & SCB_ACTIVE) != 0) 5586 continue; 5587 5588 if (ahc_match_scb(ahc, scb, target, channel, lun, 5589 SCB_LIST_NULL, ROLE_INITIATOR) == 0 5590 || (ctx != NULL && ctx != scb->io_ctx)) 5591 continue; 5592 5593 /* 5594 * We found an scb that needs to be acted on. 5595 */ 5596 found++; 5597 switch (action) { 5598 case SEARCH_COMPLETE: 5599 { 5600 cam_status ostat; 5601 cam_status cstat; 5602 5603 ostat = ahc_get_transaction_status(scb); 5604 if (ostat == CAM_REQ_INPROG) 5605 ahc_set_transaction_status(scb, status); 5606 cstat = ahc_get_transaction_status(scb); 5607 if (cstat != CAM_REQ_CMP) 5608 ahc_freeze_scb(scb); 5609 if ((scb->flags & SCB_ACTIVE) == 0) 5610 printf("Inactive SCB in untaggedQ\n"); 5611 ahc_done(ahc, scb); 5612 break; 5613 } 5614 case SEARCH_REMOVE: 5615 scb->flags &= ~SCB_UNTAGGEDQ; 5616 TAILQ_REMOVE(untagged_q, scb, links.tqe); 5617 break; 5618 case SEARCH_COUNT: 5619 break; 5620 } 5621 } 5622 } 5623 5624 if (action == SEARCH_COMPLETE) 5625 ahc_release_untagged_queues(ahc); 5626 return (found); 5627} 5628 5629int 5630ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5631 int lun, u_int tag, int stop_on_first, int remove, 5632 int save_state) 5633{ 5634 struct scb *scbp; 5635 u_int next; 5636 u_int prev; 5637 u_int count; 5638 u_int active_scb; 5639 5640 count = 0; 5641 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5642 prev = SCB_LIST_NULL; 5643 5644 if (save_state) { 5645 /* restore this when we're done */ 5646 active_scb = ahc_inb(ahc, SCBPTR); 5647 } else 5648 /* Silence compiler */ 5649 active_scb = SCB_LIST_NULL; 5650 5651 while (next != SCB_LIST_NULL) { 5652 u_int scb_index; 5653 5654 ahc_outb(ahc, SCBPTR, next); 5655 scb_index = ahc_inb(ahc, SCB_TAG); 5656 if (scb_index >= ahc->scb_data->numscbs) { 5657 printf("Disconnected List inconsistency. " 5658 "SCB index == %d, yet numscbs == %d.", 5659 scb_index, ahc->scb_data->numscbs); 5660 ahc_dump_card_state(ahc); 5661 panic("for safety"); 5662 } 5663 5664 if (next == prev) { 5665 panic("Disconnected List Loop. " 5666 "cur SCBPTR == %x, prev SCBPTR == %x.", 5667 next, prev); 5668 } 5669 scbp = ahc_lookup_scb(ahc, scb_index); 5670 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5671 tag, ROLE_INITIATOR)) { 5672 count++; 5673 if (remove) { 5674 next = 5675 ahc_rem_scb_from_disc_list(ahc, prev, next); 5676 } else { 5677 prev = next; 5678 next = ahc_inb(ahc, SCB_NEXT); 5679 } 5680 if (stop_on_first) 5681 break; 5682 } else { 5683 prev = next; 5684 next = ahc_inb(ahc, SCB_NEXT); 5685 } 5686 } 5687 if (save_state) 5688 ahc_outb(ahc, SCBPTR, active_scb); 5689 return (count); 5690} 5691 5692/* 5693 * Remove an SCB from the on chip list of disconnected transactions. 5694 * This is empty/unused if we are not performing SCB paging. 5695 */ 5696static u_int 5697ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5698{ 5699 u_int next; 5700 5701 ahc_outb(ahc, SCBPTR, scbptr); 5702 next = ahc_inb(ahc, SCB_NEXT); 5703 5704 ahc_outb(ahc, SCB_CONTROL, 0); 5705 5706 ahc_add_curscb_to_free_list(ahc); 5707 5708 if (prev != SCB_LIST_NULL) { 5709 ahc_outb(ahc, SCBPTR, prev); 5710 ahc_outb(ahc, SCB_NEXT, next); 5711 } else 5712 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5713 5714 return (next); 5715} 5716 5717/* 5718 * Add the SCB as selected by SCBPTR onto the on chip list of 5719 * free hardware SCBs. This list is empty/unused if we are not 5720 * performing SCB paging. 5721 */ 5722static void 5723ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5724{ 5725 /* 5726 * Invalidate the tag so that our abort 5727 * routines don't think it's active. 5728 */ 5729 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5730 5731 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5732 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5733 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5734 } 5735} 5736 5737/* 5738 * Manipulate the waiting for selection list and return the 5739 * scb that follows the one that we remove. 5740 */ 5741static u_int 5742ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5743{ 5744 u_int curscb, next; 5745 5746 /* 5747 * Select the SCB we want to abort and 5748 * pull the next pointer out of it. 5749 */ 5750 curscb = ahc_inb(ahc, SCBPTR); 5751 ahc_outb(ahc, SCBPTR, scbpos); 5752 next = ahc_inb(ahc, SCB_NEXT); 5753 5754 /* Clear the necessary fields */ 5755 ahc_outb(ahc, SCB_CONTROL, 0); 5756 5757 ahc_add_curscb_to_free_list(ahc); 5758 5759 /* update the waiting list */ 5760 if (prev == SCB_LIST_NULL) { 5761 /* First in the list */ 5762 ahc_outb(ahc, WAITING_SCBH, next); 5763 5764 /* 5765 * Ensure we aren't attempting to perform 5766 * selection for this entry. 5767 */ 5768 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5769 } else { 5770 /* 5771 * Select the scb that pointed to us 5772 * and update its next pointer. 5773 */ 5774 ahc_outb(ahc, SCBPTR, prev); 5775 ahc_outb(ahc, SCB_NEXT, next); 5776 } 5777 5778 /* 5779 * Point us back at the original scb position. 5780 */ 5781 ahc_outb(ahc, SCBPTR, curscb); 5782 return next; 5783} 5784 5785/******************************** Error Handling ******************************/ 5786/* 5787 * Abort all SCBs that match the given description (target/channel/lun/tag), 5788 * setting their status to the passed in status if the status has not already 5789 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5790 * is paused before it is called. 5791 */ 5792int 5793ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5794 int lun, u_int tag, role_t role, uint32_t status) 5795{ 5796 struct scb *scbp; 5797 struct scb *scbp_next; 5798 u_int active_scb; 5799 int i, j; 5800 int maxtarget; 5801 int minlun; 5802 int maxlun; 5803 5804 int found; 5805 5806 /* 5807 * Don't attempt to run any queued untagged transactions 5808 * until we are done with the abort process. 5809 */ 5810 ahc_freeze_untagged_queues(ahc); 5811 5812 /* restore this when we're done */ 5813 active_scb = ahc_inb(ahc, SCBPTR); 5814 5815 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5816 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5817 5818 /* 5819 * Clean out the busy target table for any untagged commands. 5820 */ 5821 i = 0; 5822 maxtarget = 16; 5823 if (target != CAM_TARGET_WILDCARD) { 5824 i = target; 5825 if (channel == 'B') 5826 i += 8; 5827 maxtarget = i + 1; 5828 } 5829 5830 if (lun == CAM_LUN_WILDCARD) { 5831 5832 /* 5833 * Unless we are using an SCB based 5834 * busy targets table, there is only 5835 * one table entry for all luns of 5836 * a target. 5837 */ 5838 minlun = 0; 5839 maxlun = 1; 5840 if ((ahc->flags & AHC_SCB_BTT) != 0) 5841 maxlun = AHC_NUM_LUNS; 5842 } else { 5843 minlun = lun; 5844 maxlun = lun + 1; 5845 } 5846 5847 if (role != ROLE_TARGET) { 5848 for (;i < maxtarget; i++) { 5849 for (j = minlun;j < maxlun; j++) { 5850 u_int scbid; 5851 u_int tcl; 5852 5853 tcl = BUILD_TCL(i << 4, j); 5854 scbid = ahc_index_busy_tcl(ahc, tcl); 5855 scbp = ahc_lookup_scb(ahc, scbid); 5856 if (scbp == NULL 5857 || ahc_match_scb(ahc, scbp, target, channel, 5858 lun, tag, role) == 0) 5859 continue; 5860 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5861 } 5862 } 5863 5864 /* 5865 * Go through the disconnected list and remove any entries we 5866 * have queued for completion, 0'ing their control byte too. 5867 * We save the active SCB and restore it ourselves, so there 5868 * is no reason for this search to restore it too. 5869 */ 5870 ahc_search_disc_list(ahc, target, channel, lun, tag, 5871 /*stop_on_first*/FALSE, /*remove*/TRUE, 5872 /*save_state*/FALSE); 5873 } 5874 5875 /* 5876 * Go through the hardware SCB array looking for commands that 5877 * were active but not on any list. In some cases, these remnants 5878 * might not still have mappings in the scbindex array (e.g. unexpected 5879 * bus free with the same scb queued for an abort). Don't hold this 5880 * against them. 5881 */ 5882 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5883 u_int scbid; 5884 5885 ahc_outb(ahc, SCBPTR, i); 5886 scbid = ahc_inb(ahc, SCB_TAG); 5887 scbp = ahc_lookup_scb(ahc, scbid); 5888 if ((scbp == NULL && scbid != SCB_LIST_NULL) 5889 || (scbp != NULL 5890 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 5891 ahc_add_curscb_to_free_list(ahc); 5892 } 5893 5894 /* 5895 * Go through the pending CCB list and look for 5896 * commands for this target that are still active. 5897 * These are other tagged commands that were 5898 * disconnected when the reset occurred. 5899 */ 5900 scbp_next = LIST_FIRST(&ahc->pending_scbs); 5901 while (scbp_next != NULL) { 5902 scbp = scbp_next; 5903 scbp_next = LIST_NEXT(scbp, pending_links); 5904 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 5905 cam_status ostat; 5906 5907 ostat = ahc_get_transaction_status(scbp); 5908 if (ostat == CAM_REQ_INPROG) 5909 ahc_set_transaction_status(scbp, status); 5910 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) 5911 ahc_freeze_scb(scbp); 5912 if ((scbp->flags & SCB_ACTIVE) == 0) 5913 printf("Inactive SCB on pending list\n"); 5914 ahc_done(ahc, scbp); 5915 found++; 5916 } 5917 } 5918 ahc_outb(ahc, SCBPTR, active_scb); 5919 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 5920 ahc_release_untagged_queues(ahc); 5921 return found; 5922} 5923 5924static void 5925ahc_reset_current_bus(struct ahc_softc *ahc) 5926{ 5927 uint8_t scsiseq; 5928 5929 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5930 scsiseq = ahc_inb(ahc, SCSISEQ); 5931 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5932 ahc_flush_device_writes(ahc); 5933 ahc_delay(AHC_BUSRESET_DELAY); 5934 /* Turn off the bus reset */ 5935 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5936 5937 ahc_clear_intstat(ahc); 5938 5939 /* Re-enable reset interrupts */ 5940 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5941} 5942 5943int 5944ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5945{ 5946 struct ahc_devinfo devinfo; 5947 u_int initiator, target, max_scsiid; 5948 u_int sblkctl; 5949 u_int scsiseq; 5950 u_int simode1; 5951 int found; 5952 int restart_needed; 5953 char cur_channel; 5954 5955 ahc->pending_device = NULL; 5956 5957 ahc_compile_devinfo(&devinfo, 5958 CAM_TARGET_WILDCARD, 5959 CAM_TARGET_WILDCARD, 5960 CAM_LUN_WILDCARD, 5961 channel, ROLE_UNKNOWN); 5962 ahc_pause(ahc); 5963 5964 /* Make sure the sequencer is in a safe location. */ 5965 ahc_clear_critical_section(ahc); 5966 5967 /* 5968 * Run our command complete fifos to ensure that we perform 5969 * completion processing on any commands that 'completed' 5970 * before the reset occurred. 5971 */ 5972 ahc_run_qoutfifo(ahc); 5973#if AHC_TARGET_MODE 5974 /* 5975 * XXX - In Twin mode, the tqinfifo may have commands 5976 * for an unaffected channel in it. However, if 5977 * we have run out of ATIO resources to drain that 5978 * queue, we may not get them all out here. Further, 5979 * the blocked transactions for the reset channel 5980 * should just be killed off, irrespecitve of whether 5981 * we are blocked on ATIO resources. Write a routine 5982 * to compact the tqinfifo appropriately. 5983 */ 5984 if ((ahc->flags & AHC_TARGETROLE) != 0) { 5985 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 5986 } 5987#endif 5988 5989 /* 5990 * Reset the bus if we are initiating this reset 5991 */ 5992 sblkctl = ahc_inb(ahc, SBLKCTL); 5993 cur_channel = 'A'; 5994 if ((ahc->features & AHC_TWIN) != 0 5995 && ((sblkctl & SELBUSB) != 0)) 5996 cur_channel = 'B'; 5997 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 5998 if (cur_channel != channel) { 5999 /* Case 1: Command for another bus is active 6000 * Stealthily reset the other bus without 6001 * upsetting the current bus. 6002 */ 6003 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 6004 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 6005#if AHC_TARGET_MODE 6006 /* 6007 * Bus resets clear ENSELI, so we cannot 6008 * defer re-enabling bus reset interrupts 6009 * if we are in target mode. 6010 */ 6011 if ((ahc->flags & AHC_TARGETROLE) != 0) 6012 simode1 |= ENSCSIRST; 6013#endif 6014 ahc_outb(ahc, SIMODE1, simode1); 6015 if (initiate_reset) 6016 ahc_reset_current_bus(ahc); 6017 ahc_clear_intstat(ahc); 6018 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6019 ahc_outb(ahc, SBLKCTL, sblkctl); 6020 restart_needed = FALSE; 6021 } else { 6022 /* Case 2: A command from this bus is active or we're idle */ 6023 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 6024#if AHC_TARGET_MODE 6025 /* 6026 * Bus resets clear ENSELI, so we cannot 6027 * defer re-enabling bus reset interrupts 6028 * if we are in target mode. 6029 */ 6030 if ((ahc->flags & AHC_TARGETROLE) != 0) 6031 simode1 |= ENSCSIRST; 6032#endif 6033 ahc_outb(ahc, SIMODE1, simode1); 6034 if (initiate_reset) 6035 ahc_reset_current_bus(ahc); 6036 ahc_clear_intstat(ahc); 6037 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6038 restart_needed = TRUE; 6039 } 6040 6041 /* 6042 * Clean up all the state information for the 6043 * pending transactions on this bus. 6044 */ 6045 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 6046 CAM_LUN_WILDCARD, SCB_LIST_NULL, 6047 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 6048 6049 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 6050 6051#ifdef AHC_TARGET_MODE 6052 /* 6053 * Send an immediate notify ccb to all target more peripheral 6054 * drivers affected by this action. 6055 */ 6056 for (target = 0; target <= max_scsiid; target++) { 6057 struct ahc_tmode_tstate* tstate; 6058 u_int lun; 6059 6060 tstate = ahc->enabled_targets[target]; 6061 if (tstate == NULL) 6062 continue; 6063 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 6064 struct ahc_tmode_lstate* lstate; 6065 6066 lstate = tstate->enabled_luns[lun]; 6067 if (lstate == NULL) 6068 continue; 6069 6070 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 6071 EVENT_TYPE_BUS_RESET, /*arg*/0); 6072 ahc_send_lstate_events(ahc, lstate); 6073 } 6074 } 6075#endif 6076 /* Notify the XPT that a bus reset occurred */ 6077 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD, 6078 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 6079 6080 /* 6081 * Revert to async/narrow transfers until we renegotiate. 6082 */ 6083 for (target = 0; target <= max_scsiid; target++) { 6084 6085 if (ahc->enabled_targets[target] == NULL) 6086 continue; 6087 for (initiator = 0; initiator <= max_scsiid; initiator++) { 6088 struct ahc_devinfo devinfo; 6089 6090 ahc_compile_devinfo(&devinfo, target, initiator, 6091 CAM_LUN_WILDCARD, 6092 channel, ROLE_UNKNOWN); 6093 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6094 AHC_TRANS_CUR, /*paused*/TRUE); 6095 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 6096 /*period*/0, /*offset*/0, 6097 /*ppr_options*/0, AHC_TRANS_CUR, 6098 /*paused*/TRUE); 6099 } 6100 } 6101 6102 if (restart_needed) 6103 ahc_restart(ahc); 6104 else 6105 ahc_unpause(ahc); 6106 return found; 6107} 6108 6109 6110/***************************** Residual Processing ****************************/ 6111/* 6112 * Calculate the residual for a just completed SCB. 6113 */ 6114void 6115ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6116{ 6117 struct hardware_scb *hscb; 6118 struct status_pkt *spkt; 6119 uint32_t sgptr; 6120 uint32_t resid_sgptr; 6121 uint32_t resid; 6122 6123 /* 6124 * 5 cases. 6125 * 1) No residual. 6126 * SG_RESID_VALID clear in sgptr. 6127 * 2) Transferless command 6128 * 3) Never performed any transfers. 6129 * sgptr has SG_FULL_RESID set. 6130 * 4) No residual but target did not 6131 * save data pointers after the 6132 * last transfer, so sgptr was 6133 * never updated. 6134 * 5) We have a partial residual. 6135 * Use residual_sgptr to determine 6136 * where we are. 6137 */ 6138 6139 hscb = scb->hscb; 6140 sgptr = ahc_le32toh(hscb->sgptr); 6141 if ((sgptr & SG_RESID_VALID) == 0) 6142 /* Case 1 */ 6143 return; 6144 sgptr &= ~SG_RESID_VALID; 6145 6146 if ((sgptr & SG_LIST_NULL) != 0) 6147 /* Case 2 */ 6148 return; 6149 6150 spkt = &hscb->shared_data.status; 6151 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr); 6152 if ((sgptr & SG_FULL_RESID) != 0) { 6153 /* Case 3 */ 6154 resid = ahc_get_transfer_length(scb); 6155 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 6156 /* Case 4 */ 6157 return; 6158 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 6159 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 6160 } else { 6161 struct ahc_dma_seg *sg; 6162 6163 /* 6164 * Remainder of the SG where the transfer 6165 * stopped. 6166 */ 6167 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6168 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6169 6170 /* The residual sg_ptr always points to the next sg */ 6171 sg--; 6172 6173 /* 6174 * Add up the contents of all residual 6175 * SG segments that are after the SG where 6176 * the transfer stopped. 6177 */ 6178 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6179 sg++; 6180 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 6181 } 6182 } 6183 if ((scb->flags & SCB_SENSE) == 0) 6184 ahc_set_residual(scb, resid); 6185 else 6186 ahc_set_sense_residual(scb, resid); 6187 6188#ifdef AHC_DEBUG 6189 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6190 ahc_print_path(ahc, scb); 6191 printf("Handled %sResidual of %d bytes\n", 6192 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6193 } 6194#endif 6195} 6196 6197/******************************* Target Mode **********************************/ 6198#ifdef AHC_TARGET_MODE 6199/* 6200 * Add a target mode event to this lun's queue 6201 */ 6202static void 6203ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6204 u_int initiator_id, u_int event_type, u_int event_arg) 6205{ 6206 struct ahc_tmode_event *event; 6207 int pending; 6208 6209 xpt_freeze_devq(lstate->path, /*count*/1); 6210 if (lstate->event_w_idx >= lstate->event_r_idx) 6211 pending = lstate->event_w_idx - lstate->event_r_idx; 6212 else 6213 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6214 - (lstate->event_r_idx - lstate->event_w_idx); 6215 6216 if (event_type == EVENT_TYPE_BUS_RESET 6217 || event_type == MSG_BUS_DEV_RESET) { 6218 /* 6219 * Any earlier events are irrelevant, so reset our buffer. 6220 * This has the effect of allowing us to deal with reset 6221 * floods (an external device holding down the reset line) 6222 * without losing the event that is really interesting. 6223 */ 6224 lstate->event_r_idx = 0; 6225 lstate->event_w_idx = 0; 6226 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6227 } 6228 6229 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6230 xpt_print_path(lstate->path); 6231 printf("immediate event %x:%x lost\n", 6232 lstate->event_buffer[lstate->event_r_idx].event_type, 6233 lstate->event_buffer[lstate->event_r_idx].event_arg); 6234 lstate->event_r_idx++; 6235 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6236 lstate->event_r_idx = 0; 6237 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6238 } 6239 6240 event = &lstate->event_buffer[lstate->event_w_idx]; 6241 event->initiator_id = initiator_id; 6242 event->event_type = event_type; 6243 event->event_arg = event_arg; 6244 lstate->event_w_idx++; 6245 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6246 lstate->event_w_idx = 0; 6247} 6248 6249/* 6250 * Send any target mode events queued up waiting 6251 * for immediate notify resources. 6252 */ 6253void 6254ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6255{ 6256 struct ccb_hdr *ccbh; 6257 struct ccb_immed_notify *inot; 6258 6259 while (lstate->event_r_idx != lstate->event_w_idx 6260 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6261 struct ahc_tmode_event *event; 6262 6263 event = &lstate->event_buffer[lstate->event_r_idx]; 6264 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6265 inot = (struct ccb_immed_notify *)ccbh; 6266 switch (event->event_type) { 6267 case EVENT_TYPE_BUS_RESET: 6268 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6269 break; 6270 default: 6271 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6272 inot->message_args[0] = event->event_type; 6273 inot->message_args[1] = event->event_arg; 6274 break; 6275 } 6276 inot->initiator_id = event->initiator_id; 6277 inot->sense_len = 0; 6278 xpt_done((union ccb *)inot); 6279 lstate->event_r_idx++; 6280 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6281 lstate->event_r_idx = 0; 6282 } 6283} 6284#endif 6285 6286/******************** Sequencer Program Patching/Download *********************/ 6287 6288#ifdef AHC_DUMP_SEQ 6289void 6290ahc_dumpseq(struct ahc_softc* ahc) 6291{ 6292 int i; 6293 6294 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6295 ahc_outb(ahc, SEQADDR0, 0); 6296 ahc_outb(ahc, SEQADDR1, 0); 6297 for (i = 0; i < ahc->instruction_ram_size; i++) { 6298 uint8_t ins_bytes[4]; 6299 6300 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6301 printf("0x%08x\n", ins_bytes[0] << 24 6302 | ins_bytes[1] << 16 6303 | ins_bytes[2] << 8 6304 | ins_bytes[3]); 6305 } 6306} 6307#endif 6308 6309static int 6310ahc_loadseq(struct ahc_softc *ahc) 6311{ 6312 struct cs cs_table[num_critical_sections]; 6313 u_int begin_set[num_critical_sections]; 6314 u_int end_set[num_critical_sections]; 6315 struct patch *cur_patch; 6316 u_int cs_count; 6317 u_int cur_cs; 6318 u_int i; 6319 u_int skip_addr; 6320 u_int sg_prefetch_cnt; 6321 int downloaded; 6322 uint8_t download_consts[7]; 6323 6324 /* 6325 * Start out with 0 critical sections 6326 * that apply to this firmware load. 6327 */ 6328 cs_count = 0; 6329 cur_cs = 0; 6330 memset(begin_set, 0, sizeof(begin_set)); 6331 memset(end_set, 0, sizeof(end_set)); 6332 6333 /* Setup downloadable constant table */ 6334 download_consts[QOUTFIFO_OFFSET] = 0; 6335 if (ahc->targetcmds != NULL) 6336 download_consts[QOUTFIFO_OFFSET] += 32; 6337 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6338 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6339 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6340 sg_prefetch_cnt = ahc->pci_cachesize; 6341 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6342 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6343 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6344 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6345 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6346 6347 cur_patch = patches; 6348 downloaded = 0; 6349 skip_addr = 0; 6350 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6351 ahc_outb(ahc, SEQADDR0, 0); 6352 ahc_outb(ahc, SEQADDR1, 0); 6353 6354 for (i = 0; i < sizeof(seqprog)/4; i++) { 6355 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6356 /* 6357 * Don't download this instruction as it 6358 * is in a patch that was removed. 6359 */ 6360 continue; 6361 } 6362 6363 if (downloaded == ahc->instruction_ram_size) { 6364 /* 6365 * We're about to exceed the instruction 6366 * storage capacity for this chip. Fail 6367 * the load. 6368 */ 6369 printf("\n%s: Program too large for instruction memory " 6370 "size of %d!\n", ahc_name(ahc), 6371 ahc->instruction_ram_size); 6372 return (ENOMEM); 6373 } 6374 6375 /* 6376 * Move through the CS table until we find a CS 6377 * that might apply to this instruction. 6378 */ 6379 for (; cur_cs < num_critical_sections; cur_cs++) { 6380 if (critical_sections[cur_cs].end <= i) { 6381 if (begin_set[cs_count] == TRUE 6382 && end_set[cs_count] == FALSE) { 6383 cs_table[cs_count].end = downloaded; 6384 end_set[cs_count] = TRUE; 6385 cs_count++; 6386 } 6387 continue; 6388 } 6389 if (critical_sections[cur_cs].begin <= i 6390 && begin_set[cs_count] == FALSE) { 6391 cs_table[cs_count].begin = downloaded; 6392 begin_set[cs_count] = TRUE; 6393 } 6394 break; 6395 } 6396 ahc_download_instr(ahc, i, download_consts); 6397 downloaded++; 6398 } 6399 6400 ahc->num_critical_sections = cs_count; 6401 if (cs_count != 0) { 6402 6403 cs_count *= sizeof(struct cs); 6404 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 6405 if (ahc->critical_sections == NULL) 6406 panic("ahc_loadseq: Could not malloc"); 6407 memcpy(ahc->critical_sections, cs_table, cs_count); 6408 } 6409 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6410 ahc_restart(ahc); 6411 6412 if (bootverbose) { 6413 printf(" %d instructions downloaded\n", downloaded); 6414 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6415 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6416 } 6417 return (0); 6418} 6419 6420static int 6421ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 6422 u_int start_instr, u_int *skip_addr) 6423{ 6424 struct patch *cur_patch; 6425 struct patch *last_patch; 6426 u_int num_patches; 6427 6428 num_patches = sizeof(patches)/sizeof(struct patch); 6429 last_patch = &patches[num_patches]; 6430 cur_patch = *start_patch; 6431 6432 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6433 6434 if (cur_patch->patch_func(ahc) == 0) { 6435 6436 /* Start rejecting code */ 6437 *skip_addr = start_instr + cur_patch->skip_instr; 6438 cur_patch += cur_patch->skip_patch; 6439 } else { 6440 /* Accepted this patch. Advance to the next 6441 * one and wait for our intruction pointer to 6442 * hit this point. 6443 */ 6444 cur_patch++; 6445 } 6446 } 6447 6448 *start_patch = cur_patch; 6449 if (start_instr < *skip_addr) 6450 /* Still skipping */ 6451 return (0); 6452 6453 return (1); 6454} 6455 6456static void 6457ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6458{ 6459 union ins_formats instr; 6460 struct ins_format1 *fmt1_ins; 6461 struct ins_format3 *fmt3_ins; 6462 u_int opcode; 6463 6464 /* 6465 * The firmware is always compiled into a little endian format. 6466 */ 6467 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6468 6469 fmt1_ins = &instr.format1; 6470 fmt3_ins = NULL; 6471 6472 /* Pull the opcode */ 6473 opcode = instr.format1.opcode; 6474 switch (opcode) { 6475 case AIC_OP_JMP: 6476 case AIC_OP_JC: 6477 case AIC_OP_JNC: 6478 case AIC_OP_CALL: 6479 case AIC_OP_JNE: 6480 case AIC_OP_JNZ: 6481 case AIC_OP_JE: 6482 case AIC_OP_JZ: 6483 { 6484 struct patch *cur_patch; 6485 int address_offset; 6486 u_int address; 6487 u_int skip_addr; 6488 u_int i; 6489 6490 fmt3_ins = &instr.format3; 6491 address_offset = 0; 6492 address = fmt3_ins->address; 6493 cur_patch = patches; 6494 skip_addr = 0; 6495 6496 for (i = 0; i < address;) { 6497 6498 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6499 6500 if (skip_addr > i) { 6501 int end_addr; 6502 6503 end_addr = MIN(address, skip_addr); 6504 address_offset += end_addr - i; 6505 i = skip_addr; 6506 } else { 6507 i++; 6508 } 6509 } 6510 address -= address_offset; 6511 fmt3_ins->address = address; 6512 /* FALLTHROUGH */ 6513 } 6514 case AIC_OP_OR: 6515 case AIC_OP_AND: 6516 case AIC_OP_XOR: 6517 case AIC_OP_ADD: 6518 case AIC_OP_ADC: 6519 case AIC_OP_BMOV: 6520 if (fmt1_ins->parity != 0) { 6521 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6522 } 6523 fmt1_ins->parity = 0; 6524 if ((ahc->features & AHC_CMD_CHAN) == 0 6525 && opcode == AIC_OP_BMOV) { 6526 /* 6527 * Block move was added at the same time 6528 * as the command channel. Verify that 6529 * this is only a move of a single element 6530 * and convert the BMOV to a MOV 6531 * (AND with an immediate of FF). 6532 */ 6533 if (fmt1_ins->immediate != 1) 6534 panic("%s: BMOV not supported\n", 6535 ahc_name(ahc)); 6536 fmt1_ins->opcode = AIC_OP_AND; 6537 fmt1_ins->immediate = 0xff; 6538 } 6539 /* FALLTHROUGH */ 6540 case AIC_OP_ROL: 6541 if ((ahc->features & AHC_ULTRA2) != 0) { 6542 int i, count; 6543 6544 /* Calculate odd parity for the instruction */ 6545 for (i = 0, count = 0; i < 31; i++) { 6546 uint32_t mask; 6547 6548 mask = 0x01 << i; 6549 if ((instr.integer & mask) != 0) 6550 count++; 6551 } 6552 if ((count & 0x01) == 0) 6553 instr.format1.parity = 1; 6554 } else { 6555 /* Compress the instruction for older sequencers */ 6556 if (fmt3_ins != NULL) { 6557 instr.integer = 6558 fmt3_ins->immediate 6559 | (fmt3_ins->source << 8) 6560 | (fmt3_ins->address << 16) 6561 | (fmt3_ins->opcode << 25); 6562 } else { 6563 instr.integer = 6564 fmt1_ins->immediate 6565 | (fmt1_ins->source << 8) 6566 | (fmt1_ins->destination << 16) 6567 | (fmt1_ins->ret << 24) 6568 | (fmt1_ins->opcode << 25); 6569 } 6570 } 6571 /* The sequencer is a little endian cpu */ 6572 instr.integer = ahc_htole32(instr.integer); 6573 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6574 break; 6575 default: 6576 panic("Unknown opcode encountered in seq program"); 6577 break; 6578 } 6579} 6580 6581int 6582ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 6583 const char *name, u_int address, u_int value, 6584 u_int *cur_column, u_int wrap_point) 6585{ 6586 int printed; 6587 u_int printed_mask; 6588 6589 if (cur_column != NULL && *cur_column >= wrap_point) { 6590 printf("\n"); 6591 *cur_column = 0; 6592 } 6593 printed = printf("%s[0x%x]", name, value); 6594 if (table == NULL) { 6595 printed += printf(" "); 6596 *cur_column += printed; 6597 return (printed); 6598 } 6599 printed_mask = 0; 6600 while (printed_mask != 0xFF) { 6601 int entry; 6602 6603 for (entry = 0; entry < num_entries; entry++) { 6604 if (((value & table[entry].mask) 6605 != table[entry].value) 6606 || ((printed_mask & table[entry].mask) 6607 == table[entry].mask)) 6608 continue; 6609 6610 printed += printf("%s%s", 6611 printed_mask == 0 ? ":(" : "|", 6612 table[entry].name); 6613 printed_mask |= table[entry].mask; 6614 6615 break; 6616 } 6617 if (entry >= num_entries) 6618 break; 6619 } 6620 if (printed_mask != 0) 6621 printed += printf(") "); 6622 else 6623 printed += printf(" "); 6624 if (cur_column != NULL) 6625 *cur_column += printed; 6626 return (printed); 6627} 6628 6629void 6630ahc_dump_card_state(struct ahc_softc *ahc) 6631{ 6632 struct scb *scb; 6633 struct scb_tailq *untagged_q; 6634 u_int cur_col; 6635 int paused; 6636 int target; 6637 int maxtarget; 6638 int i; 6639 uint8_t last_phase; 6640 uint8_t qinpos; 6641 uint8_t qintail; 6642 uint8_t qoutpos; 6643 uint8_t scb_index; 6644 uint8_t saved_scbptr; 6645 6646 if (ahc_is_paused(ahc)) { 6647 paused = 1; 6648 } else { 6649 paused = 0; 6650 ahc_pause(ahc); 6651 } 6652 6653 saved_scbptr = ahc_inb(ahc, SCBPTR); 6654 last_phase = ahc_inb(ahc, LASTPHASE); 6655 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 6656 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6657 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6658 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6659 if (paused) 6660 printf("Card was paused\n"); 6661 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 6662 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 6663 ahc_inb(ahc, ARG_2)); 6664 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 6665 ahc_inb(ahc, SCBPTR)); 6666 cur_col = 0; 6667 if ((ahc->features & AHC_DT) != 0) 6668 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 6669 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 6670 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 6671 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 6672 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 6673 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 6674 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 6675 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 6676 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 6677 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 6678 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 6679 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 6680 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 6681 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 6682 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 6683 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 6684 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 6685 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 6686 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 6687 if (cur_col != 0) 6688 printf("\n"); 6689 printf("STACK:"); 6690 for (i = 0; i < STACK_SIZE; i++) 6691 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 6692 printf("\nSCB count = %d\n", ahc->scb_data->numscbs); 6693 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6694 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6695 /* QINFIFO */ 6696 printf("QINFIFO entries: "); 6697 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6698 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6699 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6700 } else 6701 qinpos = ahc_inb(ahc, QINPOS); 6702 qintail = ahc->qinfifonext; 6703 while (qinpos != qintail) { 6704 printf("%d ", ahc->qinfifo[qinpos]); 6705 qinpos++; 6706 } 6707 printf("\n"); 6708 6709 printf("Waiting Queue entries: "); 6710 scb_index = ahc_inb(ahc, WAITING_SCBH); 6711 i = 0; 6712 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6713 ahc_outb(ahc, SCBPTR, scb_index); 6714 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6715 scb_index = ahc_inb(ahc, SCB_NEXT); 6716 } 6717 printf("\n"); 6718 6719 printf("Disconnected Queue entries: "); 6720 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6721 i = 0; 6722 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6723 ahc_outb(ahc, SCBPTR, scb_index); 6724 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6725 scb_index = ahc_inb(ahc, SCB_NEXT); 6726 } 6727 printf("\n"); 6728 6729 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 6730 printf("QOUTFIFO entries: "); 6731 qoutpos = ahc->qoutfifonext; 6732 i = 0; 6733 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6734 printf("%d ", ahc->qoutfifo[qoutpos]); 6735 qoutpos++; 6736 } 6737 printf("\n"); 6738 6739 printf("Sequencer Free SCB List: "); 6740 scb_index = ahc_inb(ahc, FREE_SCBH); 6741 i = 0; 6742 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6743 ahc_outb(ahc, SCBPTR, scb_index); 6744 printf("%d ", scb_index); 6745 scb_index = ahc_inb(ahc, SCB_NEXT); 6746 } 6747 printf("\n"); 6748 6749 printf("Sequencer SCB Info: "); 6750 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6751 ahc_outb(ahc, SCBPTR, i); 6752 cur_col = printf("\n%3d ", i); 6753 6754 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 6755 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 6756 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 6757 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6758 } 6759 printf("\n"); 6760 6761 printf("Pending list: "); 6762 i = 0; 6763 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6764 if (i++ > 256) 6765 break; 6766 cur_col = printf("\n%3d ", scb->hscb->tag); 6767 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 6768 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 6769 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 6770 if ((ahc->flags & AHC_PAGESCBS) == 0) { 6771 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 6772 printf("("); 6773 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 6774 &cur_col, 60); 6775 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6776 printf(")"); 6777 } 6778 } 6779 printf("\n"); 6780 6781 printf("Kernel Free SCB list: "); 6782 i = 0; 6783 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6784 if (i++ > 256) 6785 break; 6786 printf("%d ", scb->hscb->tag); 6787 } 6788 printf("\n"); 6789 6790 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6791 for (target = 0; target <= maxtarget; target++) { 6792 untagged_q = &ahc->untagged_queues[target]; 6793 if (TAILQ_FIRST(untagged_q) == NULL) 6794 continue; 6795 printf("Untagged Q(%d): ", target); 6796 i = 0; 6797 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6798 if (i++ > 256) 6799 break; 6800 printf("%d ", scb->hscb->tag); 6801 } 6802 printf("\n"); 6803 } 6804 6805 ahc_platform_dump_card_state(ahc); 6806 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 6807 ahc_outb(ahc, SCBPTR, saved_scbptr); 6808 if (paused == 0) 6809 ahc_unpause(ahc); 6810} 6811 6812/************************* Target Mode ****************************************/ 6813#ifdef AHC_TARGET_MODE 6814cam_status 6815ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 6816 struct ahc_tmode_tstate **tstate, 6817 struct ahc_tmode_lstate **lstate, 6818 int notfound_failure) 6819{ 6820 6821 if ((ahc->features & AHC_TARGETMODE) == 0) 6822 return (CAM_REQ_INVALID); 6823 6824 /* 6825 * Handle the 'black hole' device that sucks up 6826 * requests to unattached luns on enabled targets. 6827 */ 6828 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 6829 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 6830 *tstate = NULL; 6831 *lstate = ahc->black_hole; 6832 } else { 6833 u_int max_id; 6834 6835 max_id = (ahc->features & AHC_WIDE) ? 15 : 7; 6836 if (ccb->ccb_h.target_id > max_id) 6837 return (CAM_TID_INVALID); 6838 6839 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 6840 return (CAM_LUN_INVALID); 6841 6842 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 6843 *lstate = NULL; 6844 if (*tstate != NULL) 6845 *lstate = 6846 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 6847 } 6848 6849 if (notfound_failure != 0 && *lstate == NULL) 6850 return (CAM_PATH_INVALID); 6851 6852 return (CAM_REQ_CMP); 6853} 6854 6855void 6856ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 6857{ 6858 struct ahc_tmode_tstate *tstate; 6859 struct ahc_tmode_lstate *lstate; 6860 struct ccb_en_lun *cel; 6861 cam_status status; 6862 u_long s; 6863 u_int target; 6864 u_int lun; 6865 u_int target_mask; 6866 u_int our_id; 6867 int error; 6868 char channel; 6869 6870 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 6871 /*notfound_failure*/FALSE); 6872 6873 if (status != CAM_REQ_CMP) { 6874 ccb->ccb_h.status = status; 6875 return; 6876 } 6877 6878 if (cam_sim_bus(sim) == 0) 6879 our_id = ahc->our_id; 6880 else 6881 our_id = ahc->our_id_b; 6882 6883 if (ccb->ccb_h.target_id != our_id) { 6884 /* 6885 * our_id represents our initiator ID, or 6886 * the ID of the first target to have an 6887 * enabled lun in target mode. There are 6888 * two cases that may preclude enabling a 6889 * target id other than our_id. 6890 * 6891 * o our_id is for an active initiator role. 6892 * Since the hardware does not support 6893 * reselections to the initiator role at 6894 * anything other than our_id, and our_id 6895 * is used by the hardware to indicate the 6896 * ID to use for both select-out and 6897 * reselect-out operations, the only target 6898 * ID we can support in this mode is our_id. 6899 * 6900 * o The MULTARGID feature is not available and 6901 * a previous target mode ID has been enabled. 6902 */ 6903 if ((ahc->features & AHC_MULTIROLE) != 0) { 6904 6905 if ((ahc->features & AHC_MULTI_TID) != 0 6906 && (ahc->flags & AHC_INITIATORROLE) != 0) { 6907 /* 6908 * Only allow additional targets if 6909 * the initiator role is disabled. 6910 * The hardware cannot handle a re-select-in 6911 * on the initiator id during a re-select-out 6912 * on a different target id. 6913 */ 6914 status = CAM_TID_INVALID; 6915 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 6916 || ahc->enabled_luns > 0) { 6917 /* 6918 * Only allow our target id to change 6919 * if the initiator role is not configured 6920 * and there are no enabled luns which 6921 * are attached to the currently registered 6922 * scsi id. 6923 */ 6924 status = CAM_TID_INVALID; 6925 } 6926 } else if ((ahc->features & AHC_MULTI_TID) == 0 6927 && ahc->enabled_luns > 0) { 6928 6929 status = CAM_TID_INVALID; 6930 } 6931 } 6932 6933 if (status != CAM_REQ_CMP) { 6934 ccb->ccb_h.status = status; 6935 return; 6936 } 6937 6938 /* 6939 * We now have an id that is valid. 6940 * If we aren't in target mode, switch modes. 6941 */ 6942 if ((ahc->flags & AHC_TARGETROLE) == 0 6943 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 6944 u_long s; 6945 ahc_flag saved_flags; 6946 6947 printf("Configuring Target Mode\n"); 6948 ahc_lock(ahc, &s); 6949 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 6950 ccb->ccb_h.status = CAM_BUSY; 6951 ahc_unlock(ahc, &s); 6952 return; 6953 } 6954 saved_flags = ahc->flags; 6955 ahc->flags |= AHC_TARGETROLE; 6956 if ((ahc->features & AHC_MULTIROLE) == 0) 6957 ahc->flags &= ~AHC_INITIATORROLE; 6958 ahc_pause(ahc); 6959 error = ahc_loadseq(ahc); 6960 if (error != 0) { 6961 /* 6962 * Restore original configuration and notify 6963 * the caller that we cannot support target mode. 6964 * Since the adapter started out in this 6965 * configuration, the firmware load will succeed, 6966 * so there is no point in checking ahc_loadseq's 6967 * return value. 6968 */ 6969 ahc->flags = saved_flags; 6970 (void)ahc_loadseq(ahc); 6971 ahc_unpause(ahc); 6972 ahc_unlock(ahc, &s); 6973 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 6974 return; 6975 } 6976 ahc_unlock(ahc, &s); 6977 } 6978 cel = &ccb->cel; 6979 target = ccb->ccb_h.target_id; 6980 lun = ccb->ccb_h.target_lun; 6981 channel = SIM_CHANNEL(ahc, sim); 6982 target_mask = 0x01 << target; 6983 if (channel == 'B') 6984 target_mask <<= 8; 6985 6986 if (cel->enable != 0) { 6987 u_int scsiseq; 6988 6989 /* Are we already enabled?? */ 6990 if (lstate != NULL) { 6991 xpt_print_path(ccb->ccb_h.path); 6992 printf("Lun already enabled\n"); 6993 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 6994 return; 6995 } 6996 6997 if (cel->grp6_len != 0 6998 || cel->grp7_len != 0) { 6999 /* 7000 * Don't (yet?) support vendor 7001 * specific commands. 7002 */ 7003 ccb->ccb_h.status = CAM_REQ_INVALID; 7004 printf("Non-zero Group Codes\n"); 7005 return; 7006 } 7007 7008 /* 7009 * Seems to be okay. 7010 * Setup our data structures. 7011 */ 7012 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 7013 tstate = ahc_alloc_tstate(ahc, target, channel); 7014 if (tstate == NULL) { 7015 xpt_print_path(ccb->ccb_h.path); 7016 printf("Couldn't allocate tstate\n"); 7017 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7018 return; 7019 } 7020 } 7021 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 7022 if (lstate == NULL) { 7023 xpt_print_path(ccb->ccb_h.path); 7024 printf("Couldn't allocate lstate\n"); 7025 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7026 return; 7027 } 7028 memset(lstate, 0, sizeof(*lstate)); 7029 status = xpt_create_path(&lstate->path, /*periph*/NULL, 7030 xpt_path_path_id(ccb->ccb_h.path), 7031 xpt_path_target_id(ccb->ccb_h.path), 7032 xpt_path_lun_id(ccb->ccb_h.path)); 7033 if (status != CAM_REQ_CMP) { 7034 free(lstate, M_DEVBUF); 7035 xpt_print_path(ccb->ccb_h.path); 7036 printf("Couldn't allocate path\n"); 7037 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7038 return; 7039 } 7040 SLIST_INIT(&lstate->accept_tios); 7041 SLIST_INIT(&lstate->immed_notifies); 7042 ahc_lock(ahc, &s); 7043 ahc_pause(ahc); 7044 if (target != CAM_TARGET_WILDCARD) { 7045 tstate->enabled_luns[lun] = lstate; 7046 ahc->enabled_luns++; 7047 7048 if ((ahc->features & AHC_MULTI_TID) != 0) { 7049 u_int targid_mask; 7050 7051 targid_mask = ahc_inb(ahc, TARGID) 7052 | (ahc_inb(ahc, TARGID + 1) << 8); 7053 7054 targid_mask |= target_mask; 7055 ahc_outb(ahc, TARGID, targid_mask); 7056 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 7057 7058 ahc_update_scsiid(ahc, targid_mask); 7059 } else { 7060 u_int our_id; 7061 char channel; 7062 7063 channel = SIM_CHANNEL(ahc, sim); 7064 our_id = SIM_SCSI_ID(ahc, sim); 7065 7066 /* 7067 * This can only happen if selections 7068 * are not enabled 7069 */ 7070 if (target != our_id) { 7071 u_int sblkctl; 7072 char cur_channel; 7073 int swap; 7074 7075 sblkctl = ahc_inb(ahc, SBLKCTL); 7076 cur_channel = (sblkctl & SELBUSB) 7077 ? 'B' : 'A'; 7078 if ((ahc->features & AHC_TWIN) == 0) 7079 cur_channel = 'A'; 7080 swap = cur_channel != channel; 7081 if (channel == 'A') 7082 ahc->our_id = target; 7083 else 7084 ahc->our_id_b = target; 7085 7086 if (swap) 7087 ahc_outb(ahc, SBLKCTL, 7088 sblkctl ^ SELBUSB); 7089 7090 ahc_outb(ahc, SCSIID, target); 7091 7092 if (swap) 7093 ahc_outb(ahc, SBLKCTL, sblkctl); 7094 } 7095 } 7096 } else 7097 ahc->black_hole = lstate; 7098 /* Allow select-in operations */ 7099 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 7100 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7101 scsiseq |= ENSELI; 7102 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7103 scsiseq = ahc_inb(ahc, SCSISEQ); 7104 scsiseq |= ENSELI; 7105 ahc_outb(ahc, SCSISEQ, scsiseq); 7106 } 7107 ahc_unpause(ahc); 7108 ahc_unlock(ahc, &s); 7109 ccb->ccb_h.status = CAM_REQ_CMP; 7110 xpt_print_path(ccb->ccb_h.path); 7111 printf("Lun now enabled for target mode\n"); 7112 } else { 7113 struct scb *scb; 7114 int i, empty; 7115 7116 if (lstate == NULL) { 7117 ccb->ccb_h.status = CAM_LUN_INVALID; 7118 return; 7119 } 7120 7121 ahc_lock(ahc, &s); 7122 7123 ccb->ccb_h.status = CAM_REQ_CMP; 7124 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7125 struct ccb_hdr *ccbh; 7126 7127 ccbh = &scb->io_ctx->ccb_h; 7128 if (ccbh->func_code == XPT_CONT_TARGET_IO 7129 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 7130 printf("CTIO pending\n"); 7131 ccb->ccb_h.status = CAM_REQ_INVALID; 7132 ahc_unlock(ahc, &s); 7133 return; 7134 } 7135 } 7136 7137 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 7138 printf("ATIOs pending\n"); 7139 ccb->ccb_h.status = CAM_REQ_INVALID; 7140 } 7141 7142 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 7143 printf("INOTs pending\n"); 7144 ccb->ccb_h.status = CAM_REQ_INVALID; 7145 } 7146 7147 if (ccb->ccb_h.status != CAM_REQ_CMP) { 7148 ahc_unlock(ahc, &s); 7149 return; 7150 } 7151 7152 xpt_print_path(ccb->ccb_h.path); 7153 printf("Target mode disabled\n"); 7154 xpt_free_path(lstate->path); 7155 free(lstate, M_DEVBUF); 7156 7157 ahc_pause(ahc); 7158 /* Can we clean up the target too? */ 7159 if (target != CAM_TARGET_WILDCARD) { 7160 tstate->enabled_luns[lun] = NULL; 7161 ahc->enabled_luns--; 7162 for (empty = 1, i = 0; i < 8; i++) 7163 if (tstate->enabled_luns[i] != NULL) { 7164 empty = 0; 7165 break; 7166 } 7167 7168 if (empty) { 7169 ahc_free_tstate(ahc, target, channel, 7170 /*force*/FALSE); 7171 if (ahc->features & AHC_MULTI_TID) { 7172 u_int targid_mask; 7173 7174 targid_mask = ahc_inb(ahc, TARGID) 7175 | (ahc_inb(ahc, TARGID + 1) 7176 << 8); 7177 7178 targid_mask &= ~target_mask; 7179 ahc_outb(ahc, TARGID, targid_mask); 7180 ahc_outb(ahc, TARGID+1, 7181 (targid_mask >> 8)); 7182 ahc_update_scsiid(ahc, targid_mask); 7183 } 7184 } 7185 } else { 7186 7187 ahc->black_hole = NULL; 7188 7189 /* 7190 * We can't allow selections without 7191 * our black hole device. 7192 */ 7193 empty = TRUE; 7194 } 7195 if (ahc->enabled_luns == 0) { 7196 /* Disallow select-in */ 7197 u_int scsiseq; 7198 7199 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7200 scsiseq &= ~ENSELI; 7201 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7202 scsiseq = ahc_inb(ahc, SCSISEQ); 7203 scsiseq &= ~ENSELI; 7204 ahc_outb(ahc, SCSISEQ, scsiseq); 7205 7206 if ((ahc->features & AHC_MULTIROLE) == 0) { 7207 printf("Configuring Initiator Mode\n"); 7208 ahc->flags &= ~AHC_TARGETROLE; 7209 ahc->flags |= AHC_INITIATORROLE; 7210 ahc_pause(ahc); 7211 /* 7212 * Returning to a configuration that 7213 * fit previously will always succeed. 7214 */ 7215 (void)ahc_loadseq(ahc); 7216 } 7217 } 7218 ahc_unpause(ahc); 7219 ahc_unlock(ahc, &s); 7220 } 7221} 7222 7223static void 7224ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7225{ 7226 u_int scsiid_mask; 7227 u_int scsiid; 7228 7229 if ((ahc->features & AHC_MULTI_TID) == 0) 7230 panic("ahc_update_scsiid called on non-multitid unit\n"); 7231 7232 /* 7233 * Since we will rely on the TARGID mask 7234 * for selection enables, ensure that OID 7235 * in SCSIID is not set to some other ID 7236 * that we don't want to allow selections on. 7237 */ 7238 if ((ahc->features & AHC_ULTRA2) != 0) 7239 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7240 else 7241 scsiid = ahc_inb(ahc, SCSIID); 7242 scsiid_mask = 0x1 << (scsiid & OID); 7243 if ((targid_mask & scsiid_mask) == 0) { 7244 u_int our_id; 7245 7246 /* ffs counts from 1 */ 7247 our_id = ffs(targid_mask); 7248 if (our_id == 0) 7249 our_id = ahc->our_id; 7250 else 7251 our_id--; 7252 scsiid &= TID; 7253 scsiid |= our_id; 7254 } 7255 if ((ahc->features & AHC_ULTRA2) != 0) 7256 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7257 else 7258 ahc_outb(ahc, SCSIID, scsiid); 7259} 7260 7261void 7262ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7263{ 7264 struct target_cmd *cmd; 7265 7266 /* 7267 * If the card supports auto-access pause, 7268 * we can access the card directly regardless 7269 * of whether it is paused or not. 7270 */ 7271 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7272 paused = TRUE; 7273 7274 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7275 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7276 7277 /* 7278 * Only advance through the queue if we 7279 * have the resources to process the command. 7280 */ 7281 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7282 break; 7283 7284 cmd->cmd_valid = 0; 7285 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 7286 ahc->shared_data_dmamap, 7287 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7288 sizeof(struct target_cmd), 7289 BUS_DMASYNC_PREREAD); 7290 ahc->tqinfifonext++; 7291 7292 /* 7293 * Lazily update our position in the target mode incoming 7294 * command queue as seen by the sequencer. 7295 */ 7296 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7297 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7298 u_int hs_mailbox; 7299 7300 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7301 hs_mailbox &= ~HOST_TQINPOS; 7302 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7303 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7304 } else { 7305 if (!paused) 7306 ahc_pause(ahc); 7307 ahc_outb(ahc, KERNEL_TQINPOS, 7308 ahc->tqinfifonext & HOST_TQINPOS); 7309 if (!paused) 7310 ahc_unpause(ahc); 7311 } 7312 } 7313 } 7314} 7315 7316static int 7317ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7318{ 7319 struct ahc_tmode_tstate *tstate; 7320 struct ahc_tmode_lstate *lstate; 7321 struct ccb_accept_tio *atio; 7322 uint8_t *byte; 7323 int initiator; 7324 int target; 7325 int lun; 7326 7327 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7328 target = SCSIID_OUR_ID(cmd->scsiid); 7329 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7330 7331 byte = cmd->bytes; 7332 tstate = ahc->enabled_targets[target]; 7333 lstate = NULL; 7334 if (tstate != NULL) 7335 lstate = tstate->enabled_luns[lun]; 7336 7337 /* 7338 * Commands for disabled luns go to the black hole driver. 7339 */ 7340 if (lstate == NULL) 7341 lstate = ahc->black_hole; 7342 7343 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7344 if (atio == NULL) { 7345 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7346 /* 7347 * Wait for more ATIOs from the peripheral driver for this lun. 7348 */ 7349 if (bootverbose) 7350 printf("%s: ATIOs exhausted\n", ahc_name(ahc)); 7351 return (1); 7352 } else 7353 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7354#if 0 7355 printf("Incoming command from %d for %d:%d%s\n", 7356 initiator, target, lun, 7357 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7358#endif 7359 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7360 7361 if (lstate == ahc->black_hole) { 7362 /* Fill in the wildcards */ 7363 atio->ccb_h.target_id = target; 7364 atio->ccb_h.target_lun = lun; 7365 } 7366 7367 /* 7368 * Package it up and send it off to 7369 * whomever has this lun enabled. 7370 */ 7371 atio->sense_len = 0; 7372 atio->init_id = initiator; 7373 if (byte[0] != 0xFF) { 7374 /* Tag was included */ 7375 atio->tag_action = *byte++; 7376 atio->tag_id = *byte++; 7377 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 7378 } else { 7379 atio->ccb_h.flags = 0; 7380 } 7381 byte++; 7382 7383 /* Okay. Now determine the cdb size based on the command code */ 7384 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7385 case 0: 7386 atio->cdb_len = 6; 7387 break; 7388 case 1: 7389 case 2: 7390 atio->cdb_len = 10; 7391 break; 7392 case 4: 7393 atio->cdb_len = 16; 7394 break; 7395 case 5: 7396 atio->cdb_len = 12; 7397 break; 7398 case 3: 7399 default: 7400 /* Only copy the opcode. */ 7401 atio->cdb_len = 1; 7402 printf("Reserved or VU command code type encountered\n"); 7403 break; 7404 } 7405 7406 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7407 7408 atio->ccb_h.status |= CAM_CDB_RECVD; 7409 7410 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7411 /* 7412 * We weren't allowed to disconnect. 7413 * We're hanging on the bus until a 7414 * continue target I/O comes in response 7415 * to this accept tio. 7416 */ 7417#if 0 7418 printf("Received Immediate Command %d:%d:%d - %p\n", 7419 initiator, target, lun, ahc->pending_device); 7420#endif 7421 ahc->pending_device = lstate; 7422 ahc_freeze_ccb((union ccb *)atio); 7423 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7424 } 7425 xpt_done((union ccb*)atio); 7426 return (0); 7427} 7428 7429#endif 7430