aic7xxx.c revision 114621
1/* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#128 $ 41 * 42 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx.c 114621 2003-05-03 23:55:38Z gibbs $ 43 */ 44 45#ifdef __linux__ 46#include "aic7xxx_osm.h" 47#include "aic7xxx_inline.h" 48#include "aicasm/aicasm_insformat.h" 49#else 50#include <dev/aic7xxx/aic7xxx_osm.h> 51#include <dev/aic7xxx/aic7xxx_inline.h> 52#include <dev/aic7xxx/aicasm/aicasm_insformat.h> 53#endif 54 55/****************************** Softc Data ************************************/ 56struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); 57 58/***************************** Lookup Tables **********************************/ 59char *ahc_chip_names[] = 60{ 61 "NONE", 62 "aic7770", 63 "aic7850", 64 "aic7855", 65 "aic7859", 66 "aic7860", 67 "aic7870", 68 "aic7880", 69 "aic7895", 70 "aic7895C", 71 "aic7890/91", 72 "aic7896/97", 73 "aic7892", 74 "aic7899" 75}; 76static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names); 77 78/* 79 * Hardware error codes. 80 */ 81struct ahc_hard_error_entry { 82 uint8_t errno; 83 char *errmesg; 84}; 85 86static struct ahc_hard_error_entry ahc_hard_errors[] = { 87 { ILLHADDR, "Illegal Host Access" }, 88 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 89 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 90 { SQPARERR, "Sequencer Parity Error" }, 91 { DPARERR, "Data-path Parity Error" }, 92 { MPARERR, "Scratch or SCB Memory Parity Error" }, 93 { PCIERRSTAT, "PCI Error detected" }, 94 { CIOPARERR, "CIOBUS Parity Error" }, 95}; 96static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors); 97 98static struct ahc_phase_table_entry ahc_phase_table[] = 99{ 100 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 101 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 102 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 103 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 104 { P_COMMAND, MSG_NOOP, "in Command phase" }, 105 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 106 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 107 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 108 { P_BUSFREE, MSG_NOOP, "while idle" }, 109 { 0, MSG_NOOP, "in unknown phase" } 110}; 111 112/* 113 * In most cases we only wish to itterate over real phases, so 114 * exclude the last element from the count. 115 */ 116static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1; 117 118/* 119 * Valid SCSIRATE values. (p. 3-17) 120 * Provides a mapping of tranfer periods in ns to the proper value to 121 * stick in the scsixfer reg. 122 */ 123static struct ahc_syncrate ahc_syncrates[] = 124{ 125 /* ultra2 fast/ultra period rate */ 126 { 0x42, 0x000, 9, "80.0" }, 127 { 0x03, 0x000, 10, "40.0" }, 128 { 0x04, 0x000, 11, "33.0" }, 129 { 0x05, 0x100, 12, "20.0" }, 130 { 0x06, 0x110, 15, "16.0" }, 131 { 0x07, 0x120, 18, "13.4" }, 132 { 0x08, 0x000, 25, "10.0" }, 133 { 0x19, 0x010, 31, "8.0" }, 134 { 0x1a, 0x020, 37, "6.67" }, 135 { 0x1b, 0x030, 43, "5.7" }, 136 { 0x1c, 0x040, 50, "5.0" }, 137 { 0x00, 0x050, 56, "4.4" }, 138 { 0x00, 0x060, 62, "4.0" }, 139 { 0x00, 0x070, 68, "3.6" }, 140 { 0x00, 0x000, 0, NULL } 141}; 142 143/* Our Sequencer Program */ 144#include "aic7xxx_seq.h" 145 146/**************************** Function Declarations ***************************/ 147static void ahc_force_renegotiation(struct ahc_softc *ahc, 148 struct ahc_devinfo *devinfo); 149static struct ahc_tmode_tstate* 150 ahc_alloc_tstate(struct ahc_softc *ahc, 151 u_int scsi_id, char channel); 152#ifdef AHC_TARGET_MODE 153static void ahc_free_tstate(struct ahc_softc *ahc, 154 u_int scsi_id, char channel, int force); 155#endif 156static struct ahc_syncrate* 157 ahc_devlimited_syncrate(struct ahc_softc *ahc, 158 struct ahc_initiator_tinfo *, 159 u_int *period, 160 u_int *ppr_options, 161 role_t role); 162static void ahc_update_pending_scbs(struct ahc_softc *ahc); 163static void ahc_fetch_devinfo(struct ahc_softc *ahc, 164 struct ahc_devinfo *devinfo); 165static void ahc_scb_devinfo(struct ahc_softc *ahc, 166 struct ahc_devinfo *devinfo, 167 struct scb *scb); 168static void ahc_assert_atn(struct ahc_softc *ahc); 169static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 170 struct ahc_devinfo *devinfo, 171 struct scb *scb); 172static void ahc_build_transfer_msg(struct ahc_softc *ahc, 173 struct ahc_devinfo *devinfo); 174static void ahc_construct_sdtr(struct ahc_softc *ahc, 175 struct ahc_devinfo *devinfo, 176 u_int period, u_int offset); 177static void ahc_construct_wdtr(struct ahc_softc *ahc, 178 struct ahc_devinfo *devinfo, 179 u_int bus_width); 180static void ahc_construct_ppr(struct ahc_softc *ahc, 181 struct ahc_devinfo *devinfo, 182 u_int period, u_int offset, 183 u_int bus_width, u_int ppr_options); 184static void ahc_clear_msg_state(struct ahc_softc *ahc); 185static void ahc_handle_proto_violation(struct ahc_softc *ahc); 186static void ahc_handle_message_phase(struct ahc_softc *ahc); 187typedef enum { 188 AHCMSG_1B, 189 AHCMSG_2B, 190 AHCMSG_EXT 191} ahc_msgtype; 192static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 193 u_int msgval, int full); 194static int ahc_parse_msg(struct ahc_softc *ahc, 195 struct ahc_devinfo *devinfo); 196static int ahc_handle_msg_reject(struct ahc_softc *ahc, 197 struct ahc_devinfo *devinfo); 198static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 199 struct ahc_devinfo *devinfo); 200static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 201static void ahc_handle_devreset(struct ahc_softc *ahc, 202 struct ahc_devinfo *devinfo, 203 cam_status status, char *message, 204 int verbose_level); 205#if AHC_TARGET_MODE 206static void ahc_setup_target_msgin(struct ahc_softc *ahc, 207 struct ahc_devinfo *devinfo, 208 struct scb *scb); 209#endif 210 211static bus_dmamap_callback_t ahc_dmamap_cb; 212static void ahc_build_free_scb_list(struct ahc_softc *ahc); 213static int ahc_init_scbdata(struct ahc_softc *ahc); 214static void ahc_fini_scbdata(struct ahc_softc *ahc); 215static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 216 struct scb *prev_scb, 217 struct scb *scb); 218static int ahc_qinfifo_count(struct ahc_softc *ahc); 219static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 220 u_int prev, u_int scbptr); 221static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 222static u_int ahc_rem_wscb(struct ahc_softc *ahc, 223 u_int scbpos, u_int prev); 224static void ahc_reset_current_bus(struct ahc_softc *ahc); 225#ifdef AHC_DUMP_SEQ 226static void ahc_dumpseq(struct ahc_softc *ahc); 227#endif 228static int ahc_loadseq(struct ahc_softc *ahc); 229static int ahc_check_patch(struct ahc_softc *ahc, 230 struct patch **start_patch, 231 u_int start_instr, u_int *skip_addr); 232static void ahc_download_instr(struct ahc_softc *ahc, 233 u_int instrptr, uint8_t *dconsts); 234#ifdef AHC_TARGET_MODE 235static void ahc_queue_lstate_event(struct ahc_softc *ahc, 236 struct ahc_tmode_lstate *lstate, 237 u_int initiator_id, 238 u_int event_type, 239 u_int event_arg); 240static void ahc_update_scsiid(struct ahc_softc *ahc, 241 u_int targid_mask); 242static int ahc_handle_target_cmd(struct ahc_softc *ahc, 243 struct target_cmd *cmd); 244#endif 245/************************* Sequencer Execution Control ************************/ 246/* 247 * Restart the sequencer program from address zero 248 */ 249void 250ahc_restart(struct ahc_softc *ahc) 251{ 252 253 ahc_pause(ahc); 254 255 /* No more pending messages. */ 256 ahc_clear_msg_state(ahc); 257 258 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 259 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 260 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 261 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 262 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 263 ahc_outb(ahc, SAVED_LUN, 0xFF); 264 265 /* 266 * Ensure that the sequencer's idea of TQINPOS 267 * matches our own. The sequencer increments TQINPOS 268 * only after it sees a DMA complete and a reset could 269 * occur before the increment leaving the kernel to believe 270 * the command arrived but the sequencer to not. 271 */ 272 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 273 274 /* Always allow reselection */ 275 ahc_outb(ahc, SCSISEQ, 276 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 277 if ((ahc->features & AHC_CMD_CHAN) != 0) { 278 /* Ensure that no DMA operations are in progress */ 279 ahc_outb(ahc, CCSCBCNT, 0); 280 ahc_outb(ahc, CCSGCTL, 0); 281 ahc_outb(ahc, CCSCBCTL, 0); 282 } 283 /* 284 * If we were in the process of DMA'ing SCB data into 285 * an SCB, replace that SCB on the free list. This prevents 286 * an SCB leak. 287 */ 288 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 289 ahc_add_curscb_to_free_list(ahc); 290 ahc_outb(ahc, SEQ_FLAGS2, 291 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 292 } 293 ahc_outb(ahc, MWI_RESIDUAL, 0); 294 ahc_outb(ahc, SEQCTL, FASTMODE); 295 ahc_outb(ahc, SEQADDR0, 0); 296 ahc_outb(ahc, SEQADDR1, 0); 297 ahc_unpause(ahc); 298} 299 300/************************* Input/Output Queues ********************************/ 301void 302ahc_run_qoutfifo(struct ahc_softc *ahc) 303{ 304 struct scb *scb; 305 u_int scb_index; 306 307 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 308 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 309 310 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 311 if ((ahc->qoutfifonext & 0x03) == 0x03) { 312 u_int modnext; 313 314 /* 315 * Clear 32bits of QOUTFIFO at a time 316 * so that we don't clobber an incoming 317 * byte DMA to the array on architectures 318 * that only support 32bit load and store 319 * operations. 320 */ 321 modnext = ahc->qoutfifonext & ~0x3; 322 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 323 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 324 ahc->shared_data_dmamap, 325 /*offset*/modnext, /*len*/4, 326 BUS_DMASYNC_PREREAD); 327 } 328 ahc->qoutfifonext++; 329 330 scb = ahc_lookup_scb(ahc, scb_index); 331 if (scb == NULL) { 332 printf("%s: WARNING no command for scb %d " 333 "(cmdcmplt)\nQOUTPOS = %d\n", 334 ahc_name(ahc), scb_index, 335 (ahc->qoutfifonext - 1) & 0xFF); 336 continue; 337 } 338 339 /* 340 * Save off the residual 341 * if there is one. 342 */ 343 ahc_update_residual(ahc, scb); 344 ahc_done(ahc, scb); 345 } 346} 347 348void 349ahc_run_untagged_queues(struct ahc_softc *ahc) 350{ 351 int i; 352 353 for (i = 0; i < 16; i++) 354 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 355} 356 357void 358ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 359{ 360 struct scb *scb; 361 362 if (ahc->untagged_queue_lock != 0) 363 return; 364 365 if ((scb = TAILQ_FIRST(queue)) != NULL 366 && (scb->flags & SCB_ACTIVE) == 0) { 367 scb->flags |= SCB_ACTIVE; 368 ahc_queue_scb(ahc, scb); 369 } 370} 371 372/************************* Interrupt Handling *********************************/ 373void 374ahc_handle_brkadrint(struct ahc_softc *ahc) 375{ 376 /* 377 * We upset the sequencer :-( 378 * Lookup the error message 379 */ 380 int i; 381 int error; 382 383 error = ahc_inb(ahc, ERROR); 384 for (i = 0; error != 1 && i < num_errors; i++) 385 error >>= 1; 386 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 387 ahc_name(ahc), ahc_hard_errors[i].errmesg, 388 ahc_inb(ahc, SEQADDR0) | 389 (ahc_inb(ahc, SEQADDR1) << 8)); 390 391 ahc_dump_card_state(ahc); 392 393 /* Tell everyone that this HBA is no longer available */ 394 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 395 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 396 CAM_NO_HBA); 397 398 /* Disable all interrupt sources by resetting the controller */ 399 ahc_shutdown(ahc); 400} 401 402void 403ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 404{ 405 struct scb *scb; 406 struct ahc_devinfo devinfo; 407 408 ahc_fetch_devinfo(ahc, &devinfo); 409 410 /* 411 * Clear the upper byte that holds SEQINT status 412 * codes and clear the SEQINT bit. We will unpause 413 * the sequencer, if appropriate, after servicing 414 * the request. 415 */ 416 ahc_outb(ahc, CLRINT, CLRSEQINT); 417 switch (intstat & SEQINT_MASK) { 418 case BAD_STATUS: 419 { 420 u_int scb_index; 421 struct hardware_scb *hscb; 422 423 /* 424 * Set the default return value to 0 (don't 425 * send sense). The sense code will change 426 * this if needed. 427 */ 428 ahc_outb(ahc, RETURN_1, 0); 429 430 /* 431 * The sequencer will notify us when a command 432 * has an error that would be of interest to 433 * the kernel. This allows us to leave the sequencer 434 * running in the common case of command completes 435 * without error. The sequencer will already have 436 * dma'd the SCB back up to us, so we can reference 437 * the in kernel copy directly. 438 */ 439 scb_index = ahc_inb(ahc, SCB_TAG); 440 scb = ahc_lookup_scb(ahc, scb_index); 441 if (scb == NULL) { 442 ahc_print_devinfo(ahc, &devinfo); 443 printf("ahc_intr - referenced scb " 444 "not valid during seqint 0x%x scb(%d)\n", 445 intstat, scb_index); 446 ahc_dump_card_state(ahc); 447 panic("for safety"); 448 goto unpause; 449 } 450 451 hscb = scb->hscb; 452 453 /* Don't want to clobber the original sense code */ 454 if ((scb->flags & SCB_SENSE) != 0) { 455 /* 456 * Clear the SCB_SENSE Flag and have 457 * the sequencer do a normal command 458 * complete. 459 */ 460 scb->flags &= ~SCB_SENSE; 461 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 462 break; 463 } 464 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 465 /* Freeze the queue until the client sees the error. */ 466 ahc_freeze_devq(ahc, scb); 467 ahc_freeze_scb(scb); 468 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 469 switch (hscb->shared_data.status.scsi_status) { 470 case SCSI_STATUS_OK: 471 printf("%s: Interrupted for staus of 0???\n", 472 ahc_name(ahc)); 473 break; 474 case SCSI_STATUS_CMD_TERMINATED: 475 case SCSI_STATUS_CHECK_COND: 476 { 477 struct ahc_dma_seg *sg; 478 struct scsi_sense *sc; 479 struct ahc_initiator_tinfo *targ_info; 480 struct ahc_tmode_tstate *tstate; 481 struct ahc_transinfo *tinfo; 482#ifdef AHC_DEBUG 483 if (ahc_debug & AHC_SHOW_SENSE) { 484 ahc_print_path(ahc, scb); 485 printf("SCB %d: requests Check Status\n", 486 scb->hscb->tag); 487 } 488#endif 489 490 if (ahc_perform_autosense(scb) == 0) 491 break; 492 493 targ_info = ahc_fetch_transinfo(ahc, 494 devinfo.channel, 495 devinfo.our_scsiid, 496 devinfo.target, 497 &tstate); 498 tinfo = &targ_info->curr; 499 sg = scb->sg_list; 500 sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 501 /* 502 * Save off the residual if there is one. 503 */ 504 ahc_update_residual(ahc, scb); 505#ifdef AHC_DEBUG 506 if (ahc_debug & AHC_SHOW_SENSE) { 507 ahc_print_path(ahc, scb); 508 printf("Sending Sense\n"); 509 } 510#endif 511 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 512 sg->len = ahc_get_sense_bufsize(ahc, scb); 513 sg->len |= AHC_DMA_LAST_SEG; 514 515 /* Fixup byte order */ 516 sg->addr = ahc_htole32(sg->addr); 517 sg->len = ahc_htole32(sg->len); 518 519 sc->opcode = REQUEST_SENSE; 520 sc->byte2 = 0; 521 if (tinfo->protocol_version <= SCSI_REV_2 522 && SCB_GET_LUN(scb) < 8) 523 sc->byte2 = SCB_GET_LUN(scb) << 5; 524 sc->unused[0] = 0; 525 sc->unused[1] = 0; 526 sc->length = sg->len; 527 sc->control = 0; 528 529 /* 530 * We can't allow the target to disconnect. 531 * This will be an untagged transaction and 532 * having the target disconnect will make this 533 * transaction indestinguishable from outstanding 534 * tagged transactions. 535 */ 536 hscb->control = 0; 537 538 /* 539 * This request sense could be because the 540 * the device lost power or in some other 541 * way has lost our transfer negotiations. 542 * Renegotiate if appropriate. Unit attention 543 * errors will be reported before any data 544 * phases occur. 545 */ 546 if (ahc_get_residual(scb) 547 == ahc_get_transfer_length(scb)) { 548 ahc_update_neg_request(ahc, &devinfo, 549 tstate, targ_info, 550 AHC_NEG_IF_NON_ASYNC); 551 } 552 if (tstate->auto_negotiate & devinfo.target_mask) { 553 hscb->control |= MK_MESSAGE; 554 scb->flags &= ~SCB_NEGOTIATE; 555 scb->flags |= SCB_AUTO_NEGOTIATE; 556 } 557 hscb->cdb_len = sizeof(*sc); 558 hscb->dataptr = sg->addr; 559 hscb->datacnt = sg->len; 560 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 561 hscb->sgptr = ahc_htole32(hscb->sgptr); 562 scb->sg_count = 1; 563 scb->flags |= SCB_SENSE; 564 ahc_qinfifo_requeue_tail(ahc, scb); 565 ahc_outb(ahc, RETURN_1, SEND_SENSE); 566 /* 567 * Ensure we have enough time to actually 568 * retrieve the sense. 569 */ 570 ahc_scb_timer_reset(scb, 5 * 1000000); 571 break; 572 } 573 default: 574 break; 575 } 576 break; 577 } 578 case NO_MATCH: 579 { 580 /* Ensure we don't leave the selection hardware on */ 581 ahc_outb(ahc, SCSISEQ, 582 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 583 584 printf("%s:%c:%d: no active SCB for reconnecting " 585 "target - issuing BUS DEVICE RESET\n", 586 ahc_name(ahc), devinfo.channel, devinfo.target); 587 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 588 "ARG_1 == 0x%x ACCUM = 0x%x\n", 589 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 590 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 591 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 592 "SINDEX == 0x%x\n", 593 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 594 ahc_index_busy_tcl(ahc, 595 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 596 ahc_inb(ahc, SAVED_LUN))), 597 ahc_inb(ahc, SINDEX)); 598 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 599 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 600 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 601 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 602 ahc_inb(ahc, SCB_CONTROL)); 603 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 604 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 605 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 606 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 607 ahc_dump_card_state(ahc); 608 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 609 ahc->msgout_len = 1; 610 ahc->msgout_index = 0; 611 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 612 ahc_outb(ahc, MSG_OUT, HOST_MSG); 613 ahc_assert_atn(ahc); 614 break; 615 } 616 case SEND_REJECT: 617 { 618 u_int rejbyte = ahc_inb(ahc, ACCUM); 619 printf("%s:%c:%d: Warning - unknown message received from " 620 "target (0x%x). Rejecting\n", 621 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 622 break; 623 } 624 case PROTO_VIOLATION: 625 { 626 ahc_handle_proto_violation(ahc); 627 break; 628 } 629 case IGN_WIDE_RES: 630 ahc_handle_ign_wide_residue(ahc, &devinfo); 631 break; 632 case PDATA_REINIT: 633 ahc_reinitialize_dataptrs(ahc); 634 break; 635 case BAD_PHASE: 636 { 637 u_int lastphase; 638 639 lastphase = ahc_inb(ahc, LASTPHASE); 640 printf("%s:%c:%d: unknown scsi bus phase %x, " 641 "lastphase = 0x%x. Attempting to continue\n", 642 ahc_name(ahc), devinfo.channel, devinfo.target, 643 lastphase, ahc_inb(ahc, SCSISIGI)); 644 break; 645 } 646 case MISSED_BUSFREE: 647 { 648 u_int lastphase; 649 650 lastphase = ahc_inb(ahc, LASTPHASE); 651 printf("%s:%c:%d: Missed busfree. " 652 "Lastphase = 0x%x, Curphase = 0x%x\n", 653 ahc_name(ahc), devinfo.channel, devinfo.target, 654 lastphase, ahc_inb(ahc, SCSISIGI)); 655 ahc_restart(ahc); 656 return; 657 } 658 case HOST_MSG_LOOP: 659 { 660 /* 661 * The sequencer has encountered a message phase 662 * that requires host assistance for completion. 663 * While handling the message phase(s), we will be 664 * notified by the sequencer after each byte is 665 * transfered so we can track bus phase changes. 666 * 667 * If this is the first time we've seen a HOST_MSG_LOOP 668 * interrupt, initialize the state of the host message 669 * loop. 670 */ 671 if (ahc->msg_type == MSG_TYPE_NONE) { 672 struct scb *scb; 673 u_int scb_index; 674 u_int bus_phase; 675 676 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 677 if (bus_phase != P_MESGIN 678 && bus_phase != P_MESGOUT) { 679 printf("ahc_intr: HOST_MSG_LOOP bad " 680 "phase 0x%x\n", 681 bus_phase); 682 /* 683 * Probably transitioned to bus free before 684 * we got here. Just punt the message. 685 */ 686 ahc_clear_intstat(ahc); 687 ahc_restart(ahc); 688 return; 689 } 690 691 scb_index = ahc_inb(ahc, SCB_TAG); 692 scb = ahc_lookup_scb(ahc, scb_index); 693 if (devinfo.role == ROLE_INITIATOR) { 694 if (scb == NULL) 695 panic("HOST_MSG_LOOP with " 696 "invalid SCB %x\n", scb_index); 697 698 if (bus_phase == P_MESGOUT) 699 ahc_setup_initiator_msgout(ahc, 700 &devinfo, 701 scb); 702 else { 703 ahc->msg_type = 704 MSG_TYPE_INITIATOR_MSGIN; 705 ahc->msgin_index = 0; 706 } 707 } 708#if AHC_TARGET_MODE 709 else { 710 if (bus_phase == P_MESGOUT) { 711 ahc->msg_type = 712 MSG_TYPE_TARGET_MSGOUT; 713 ahc->msgin_index = 0; 714 } 715 else 716 ahc_setup_target_msgin(ahc, 717 &devinfo, 718 scb); 719 } 720#endif 721 } 722 723 ahc_handle_message_phase(ahc); 724 break; 725 } 726 case PERR_DETECTED: 727 { 728 /* 729 * If we've cleared the parity error interrupt 730 * but the sequencer still believes that SCSIPERR 731 * is true, it must be that the parity error is 732 * for the currently presented byte on the bus, 733 * and we are not in a phase (data-in) where we will 734 * eventually ack this byte. Ack the byte and 735 * throw it away in the hope that the target will 736 * take us to message out to deliver the appropriate 737 * error message. 738 */ 739 if ((intstat & SCSIINT) == 0 740 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 741 742 if ((ahc->features & AHC_DT) == 0) { 743 u_int curphase; 744 745 /* 746 * The hardware will only let you ack bytes 747 * if the expected phase in SCSISIGO matches 748 * the current phase. Make sure this is 749 * currently the case. 750 */ 751 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 752 ahc_outb(ahc, LASTPHASE, curphase); 753 ahc_outb(ahc, SCSISIGO, curphase); 754 } 755 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 756 int wait; 757 758 /* 759 * In a data phase. Faster to bitbucket 760 * the data than to individually ack each 761 * byte. This is also the only strategy 762 * that will work with AUTOACK enabled. 763 */ 764 ahc_outb(ahc, SXFRCTL1, 765 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 766 wait = 5000; 767 while (--wait != 0) { 768 if ((ahc_inb(ahc, SCSISIGI) 769 & (CDI|MSGI)) != 0) 770 break; 771 ahc_delay(100); 772 } 773 ahc_outb(ahc, SXFRCTL1, 774 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 775 if (wait == 0) { 776 struct scb *scb; 777 u_int scb_index; 778 779 ahc_print_devinfo(ahc, &devinfo); 780 printf("Unable to clear parity error. " 781 "Resetting bus.\n"); 782 scb_index = ahc_inb(ahc, SCB_TAG); 783 scb = ahc_lookup_scb(ahc, scb_index); 784 if (scb != NULL) 785 ahc_set_transaction_status(scb, 786 CAM_UNCOR_PARITY); 787 ahc_reset_channel(ahc, devinfo.channel, 788 /*init reset*/TRUE); 789 } 790 } else { 791 ahc_inb(ahc, SCSIDATL); 792 } 793 } 794 break; 795 } 796 case DATA_OVERRUN: 797 { 798 /* 799 * When the sequencer detects an overrun, it 800 * places the controller in "BITBUCKET" mode 801 * and allows the target to complete its transfer. 802 * Unfortunately, none of the counters get updated 803 * when the controller is in this mode, so we have 804 * no way of knowing how large the overrun was. 805 */ 806 u_int scbindex = ahc_inb(ahc, SCB_TAG); 807 u_int lastphase = ahc_inb(ahc, LASTPHASE); 808 u_int i; 809 810 scb = ahc_lookup_scb(ahc, scbindex); 811 for (i = 0; i < num_phases; i++) { 812 if (lastphase == ahc_phase_table[i].phase) 813 break; 814 } 815 ahc_print_path(ahc, scb); 816 printf("data overrun detected %s." 817 " Tag == 0x%x.\n", 818 ahc_phase_table[i].phasemsg, 819 scb->hscb->tag); 820 ahc_print_path(ahc, scb); 821 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 822 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 823 ahc_get_transfer_length(scb), scb->sg_count); 824 if (scb->sg_count > 0) { 825 for (i = 0; i < scb->sg_count; i++) { 826 827 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 828 i, 829 (ahc_le32toh(scb->sg_list[i].len) >> 24 830 & SG_HIGH_ADDR_BITS), 831 ahc_le32toh(scb->sg_list[i].addr), 832 ahc_le32toh(scb->sg_list[i].len) 833 & AHC_SG_LEN_MASK); 834 } 835 } 836 /* 837 * Set this and it will take effect when the 838 * target does a command complete. 839 */ 840 ahc_freeze_devq(ahc, scb); 841 if ((scb->flags & SCB_SENSE) == 0) { 842 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); 843 } else { 844 scb->flags &= ~SCB_SENSE; 845 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 846 } 847 ahc_freeze_scb(scb); 848 849 if ((ahc->features & AHC_ULTRA2) != 0) { 850 /* 851 * Clear the channel in case we return 852 * to data phase later. 853 */ 854 ahc_outb(ahc, SXFRCTL0, 855 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 856 ahc_outb(ahc, SXFRCTL0, 857 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 858 } 859 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 860 u_int dscommand1; 861 862 /* Ensure HHADDR is 0 for future DMA operations. */ 863 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 864 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 865 ahc_outb(ahc, HADDR, 0); 866 ahc_outb(ahc, DSCOMMAND1, dscommand1); 867 } 868 break; 869 } 870 case MKMSG_FAILED: 871 { 872 u_int scbindex; 873 874 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 875 ahc_name(ahc), devinfo.channel, devinfo.target, 876 devinfo.lun); 877 scbindex = ahc_inb(ahc, SCB_TAG); 878 scb = ahc_lookup_scb(ahc, scbindex); 879 if (scb != NULL 880 && (scb->flags & SCB_RECOVERY_SCB) != 0) 881 /* 882 * Ensure that we didn't put a second instance of this 883 * SCB into the QINFIFO. 884 */ 885 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 886 SCB_GET_CHANNEL(ahc, scb), 887 SCB_GET_LUN(scb), scb->hscb->tag, 888 ROLE_INITIATOR, /*status*/0, 889 SEARCH_REMOVE); 890 break; 891 } 892 case NO_FREE_SCB: 893 { 894 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 895 ahc_dump_card_state(ahc); 896 panic("for safety"); 897 break; 898 } 899 case SCB_MISMATCH: 900 { 901 u_int scbptr; 902 903 scbptr = ahc_inb(ahc, SCBPTR); 904 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 905 scbptr, ahc_inb(ahc, ARG_1), 906 ahc->scb_data->hscbs[scbptr].tag); 907 ahc_dump_card_state(ahc); 908 panic("for saftey"); 909 break; 910 } 911 case OUT_OF_RANGE: 912 { 913 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 914 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 915 "ARG_1 == 0x%x ACCUM = 0x%x\n", 916 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 917 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 918 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 919 "SINDEX == 0x%x\n, A == 0x%x\n", 920 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 921 ahc_index_busy_tcl(ahc, 922 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 923 ahc_inb(ahc, SAVED_LUN))), 924 ahc_inb(ahc, SINDEX), 925 ahc_inb(ahc, ACCUM)); 926 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 927 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 928 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 929 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 930 ahc_inb(ahc, SCB_CONTROL)); 931 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 932 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 933 ahc_dump_card_state(ahc); 934 panic("for safety"); 935 break; 936 } 937 default: 938 printf("ahc_intr: seqint, " 939 "intstat == 0x%x, scsisigi = 0x%x\n", 940 intstat, ahc_inb(ahc, SCSISIGI)); 941 break; 942 } 943unpause: 944 /* 945 * The sequencer is paused immediately on 946 * a SEQINT, so we should restart it when 947 * we're done. 948 */ 949 ahc_unpause(ahc); 950} 951 952void 953ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 954{ 955 u_int scb_index; 956 u_int status0; 957 u_int status; 958 struct scb *scb; 959 char cur_channel; 960 char intr_channel; 961 962 if ((ahc->features & AHC_TWIN) != 0 963 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 964 cur_channel = 'B'; 965 else 966 cur_channel = 'A'; 967 intr_channel = cur_channel; 968 969 if ((ahc->features & AHC_ULTRA2) != 0) 970 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 971 else 972 status0 = 0; 973 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 974 if (status == 0 && status0 == 0) { 975 if ((ahc->features & AHC_TWIN) != 0) { 976 /* Try the other channel */ 977 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 978 status = ahc_inb(ahc, SSTAT1) 979 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 980 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 981 } 982 if (status == 0) { 983 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 984 ahc_outb(ahc, CLRINT, CLRSCSIINT); 985 ahc_unpause(ahc); 986 return; 987 } 988 } 989 990 /* Make sure the sequencer is in a safe location. */ 991 ahc_clear_critical_section(ahc); 992 993 scb_index = ahc_inb(ahc, SCB_TAG); 994 scb = ahc_lookup_scb(ahc, scb_index); 995 if (scb != NULL 996 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 997 scb = NULL; 998 999 if ((ahc->features & AHC_ULTRA2) != 0 1000 && (status0 & IOERR) != 0) { 1001 int now_lvd; 1002 1003 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1004 printf("%s: Transceiver State Has Changed to %s mode\n", 1005 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1006 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1007 /* 1008 * When transitioning to SE mode, the reset line 1009 * glitches, triggering an arbitration bug in some 1010 * Ultra2 controllers. This bug is cleared when we 1011 * assert the reset line. Since a reset glitch has 1012 * already occurred with this transition and a 1013 * transceiver state change is handled just like 1014 * a bus reset anyway, asserting the reset line 1015 * ourselves is safe. 1016 */ 1017 ahc_reset_channel(ahc, intr_channel, 1018 /*Initiate Reset*/now_lvd == 0); 1019 } else if ((status & SCSIRSTI) != 0) { 1020 printf("%s: Someone reset channel %c\n", 1021 ahc_name(ahc), intr_channel); 1022 if (intr_channel != cur_channel) 1023 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1024 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1025 } else if ((status & SCSIPERR) != 0) { 1026 /* 1027 * Determine the bus phase and queue an appropriate message. 1028 * SCSIPERR is latched true as soon as a parity error 1029 * occurs. If the sequencer acked the transfer that 1030 * caused the parity error and the currently presented 1031 * transfer on the bus has correct parity, SCSIPERR will 1032 * be cleared by CLRSCSIPERR. Use this to determine if 1033 * we should look at the last phase the sequencer recorded, 1034 * or the current phase presented on the bus. 1035 */ 1036 struct ahc_devinfo devinfo; 1037 u_int mesg_out; 1038 u_int curphase; 1039 u_int errorphase; 1040 u_int lastphase; 1041 u_int scsirate; 1042 u_int i; 1043 u_int sstat2; 1044 int silent; 1045 1046 lastphase = ahc_inb(ahc, LASTPHASE); 1047 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1048 sstat2 = ahc_inb(ahc, SSTAT2); 1049 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1050 /* 1051 * For all phases save DATA, the sequencer won't 1052 * automatically ack a byte that has a parity error 1053 * in it. So the only way that the current phase 1054 * could be 'data-in' is if the parity error is for 1055 * an already acked byte in the data phase. During 1056 * synchronous data-in transfers, we may actually 1057 * ack bytes before latching the current phase in 1058 * LASTPHASE, leading to the discrepancy between 1059 * curphase and lastphase. 1060 */ 1061 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1062 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1063 errorphase = curphase; 1064 else 1065 errorphase = lastphase; 1066 1067 for (i = 0; i < num_phases; i++) { 1068 if (errorphase == ahc_phase_table[i].phase) 1069 break; 1070 } 1071 mesg_out = ahc_phase_table[i].mesg_out; 1072 silent = FALSE; 1073 if (scb != NULL) { 1074 if (SCB_IS_SILENT(scb)) 1075 silent = TRUE; 1076 else 1077 ahc_print_path(ahc, scb); 1078 scb->flags |= SCB_TRANSMISSION_ERROR; 1079 } else 1080 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1081 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1082 scsirate = ahc_inb(ahc, SCSIRATE); 1083 if (silent == FALSE) { 1084 printf("parity error detected %s. " 1085 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1086 ahc_phase_table[i].phasemsg, 1087 ahc_inw(ahc, SEQADDR0), 1088 scsirate); 1089 if ((ahc->features & AHC_DT) != 0) { 1090 if ((sstat2 & CRCVALERR) != 0) 1091 printf("\tCRC Value Mismatch\n"); 1092 if ((sstat2 & CRCENDERR) != 0) 1093 printf("\tNo terminal CRC packet " 1094 "recevied\n"); 1095 if ((sstat2 & CRCREQERR) != 0) 1096 printf("\tIllegal CRC packet " 1097 "request\n"); 1098 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1099 printf("\tUnexpected %sDT Data Phase\n", 1100 (scsirate & SINGLE_EDGE) 1101 ? "" : "non-"); 1102 } 1103 } 1104 1105 if ((ahc->features & AHC_DT) != 0 1106 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1107 /* 1108 * This error applies regardless of 1109 * data direction, so ignore the value 1110 * in the phase table. 1111 */ 1112 mesg_out = MSG_INITIATOR_DET_ERR; 1113 } 1114 1115 /* 1116 * We've set the hardware to assert ATN if we 1117 * get a parity error on "in" phases, so all we 1118 * need to do is stuff the message buffer with 1119 * the appropriate message. "In" phases have set 1120 * mesg_out to something other than MSG_NOP. 1121 */ 1122 if (mesg_out != MSG_NOOP) { 1123 if (ahc->msg_type != MSG_TYPE_NONE) 1124 ahc->send_msg_perror = TRUE; 1125 else 1126 ahc_outb(ahc, MSG_OUT, mesg_out); 1127 } 1128 /* 1129 * Force a renegotiation with this target just in 1130 * case we are out of sync for some external reason 1131 * unknown (or unreported) by the target. 1132 */ 1133 ahc_fetch_devinfo(ahc, &devinfo); 1134 ahc_force_renegotiation(ahc, &devinfo); 1135 1136 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1137 ahc_unpause(ahc); 1138 } else if ((status & SELTO) != 0) { 1139 u_int scbptr; 1140 1141 /* Stop the selection */ 1142 ahc_outb(ahc, SCSISEQ, 0); 1143 1144 /* No more pending messages */ 1145 ahc_clear_msg_state(ahc); 1146 1147 /* Clear interrupt state */ 1148 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1149 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1150 1151 /* 1152 * Although the driver does not care about the 1153 * 'Selection in Progress' status bit, the busy 1154 * LED does. SELINGO is only cleared by a sucessfull 1155 * selection, so we must manually clear it to insure 1156 * the LED turns off just incase no future successful 1157 * selections occur (e.g. no devices on the bus). 1158 */ 1159 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1160 1161 scbptr = ahc_inb(ahc, WAITING_SCBH); 1162 ahc_outb(ahc, SCBPTR, scbptr); 1163 scb_index = ahc_inb(ahc, SCB_TAG); 1164 1165 scb = ahc_lookup_scb(ahc, scb_index); 1166 if (scb == NULL) { 1167 printf("%s: ahc_intr - referenced scb not " 1168 "valid during SELTO scb(%d, %d)\n", 1169 ahc_name(ahc), scbptr, scb_index); 1170 ahc_dump_card_state(ahc); 1171 } else { 1172 struct ahc_devinfo devinfo; 1173#ifdef AHC_DEBUG 1174 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1175 ahc_print_path(ahc, scb); 1176 printf("Saw Selection Timeout for SCB 0x%x\n", 1177 scb_index); 1178 } 1179#endif 1180 /* 1181 * Force a renegotiation with this target just in 1182 * case the cable was pulled and will later be 1183 * re-attached. The target may forget its negotiation 1184 * settings with us should it attempt to reselect 1185 * during the interruption. The target will not issue 1186 * a unit attention in this case, so we must always 1187 * renegotiate. 1188 */ 1189 ahc_scb_devinfo(ahc, &devinfo, scb); 1190 ahc_force_renegotiation(ahc, &devinfo); 1191 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1192 ahc_freeze_devq(ahc, scb); 1193 } 1194 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1195 ahc_restart(ahc); 1196 } else if ((status & BUSFREE) != 0 1197 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1198 struct ahc_devinfo devinfo; 1199 u_int lastphase; 1200 u_int saved_scsiid; 1201 u_int saved_lun; 1202 u_int target; 1203 u_int initiator_role_id; 1204 char channel; 1205 int printerror; 1206 1207 /* 1208 * Clear our selection hardware as soon as possible. 1209 * We may have an entry in the waiting Q for this target, 1210 * that is affected by this busfree and we don't want to 1211 * go about selecting the target while we handle the event. 1212 */ 1213 ahc_outb(ahc, SCSISEQ, 1214 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1215 1216 /* 1217 * Disable busfree interrupts and clear the busfree 1218 * interrupt status. We do this here so that several 1219 * bus transactions occur prior to clearing the SCSIINT 1220 * latch. It can take a bit for the clearing to take effect. 1221 */ 1222 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1223 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1224 1225 /* 1226 * Look at what phase we were last in. 1227 * If its message out, chances are pretty good 1228 * that the busfree was in response to one of 1229 * our abort requests. 1230 */ 1231 lastphase = ahc_inb(ahc, LASTPHASE); 1232 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1233 saved_lun = ahc_inb(ahc, SAVED_LUN); 1234 target = SCSIID_TARGET(ahc, saved_scsiid); 1235 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1236 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1237 ahc_compile_devinfo(&devinfo, initiator_role_id, 1238 target, saved_lun, channel, ROLE_INITIATOR); 1239 printerror = 1; 1240 1241 if (lastphase == P_MESGOUT) { 1242 u_int tag; 1243 1244 tag = SCB_LIST_NULL; 1245 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1246 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1247 if (ahc->msgout_buf[ahc->msgout_index - 1] 1248 == MSG_ABORT_TAG) 1249 tag = scb->hscb->tag; 1250 ahc_print_path(ahc, scb); 1251 printf("SCB %d - Abort%s Completed.\n", 1252 scb->hscb->tag, tag == SCB_LIST_NULL ? 1253 "" : " Tag"); 1254 ahc_abort_scbs(ahc, target, channel, 1255 saved_lun, tag, 1256 ROLE_INITIATOR, 1257 CAM_REQ_ABORTED); 1258 printerror = 0; 1259 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1260 MSG_BUS_DEV_RESET, TRUE)) { 1261#ifdef __FreeBSD__ 1262 /* 1263 * Don't mark the user's request for this BDR 1264 * as completing with CAM_BDR_SENT. CAM3 1265 * specifies CAM_REQ_CMP. 1266 */ 1267 if (scb != NULL 1268 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1269 && ahc_match_scb(ahc, scb, target, channel, 1270 CAM_LUN_WILDCARD, 1271 SCB_LIST_NULL, 1272 ROLE_INITIATOR)) { 1273 ahc_set_transaction_status(scb, CAM_REQ_CMP); 1274 } 1275#endif 1276 ahc_compile_devinfo(&devinfo, 1277 initiator_role_id, 1278 target, 1279 CAM_LUN_WILDCARD, 1280 channel, 1281 ROLE_INITIATOR); 1282 ahc_handle_devreset(ahc, &devinfo, 1283 CAM_BDR_SENT, 1284 "Bus Device Reset", 1285 /*verbose_level*/0); 1286 printerror = 0; 1287 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1288 MSG_EXT_PPR, FALSE)) { 1289 struct ahc_initiator_tinfo *tinfo; 1290 struct ahc_tmode_tstate *tstate; 1291 1292 /* 1293 * PPR Rejected. Try non-ppr negotiation 1294 * and retry command. 1295 */ 1296 tinfo = ahc_fetch_transinfo(ahc, 1297 devinfo.channel, 1298 devinfo.our_scsiid, 1299 devinfo.target, 1300 &tstate); 1301 tinfo->curr.transport_version = 2; 1302 tinfo->goal.transport_version = 2; 1303 tinfo->goal.ppr_options = 0; 1304 ahc_qinfifo_requeue_tail(ahc, scb); 1305 printerror = 0; 1306 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1307 MSG_EXT_WDTR, FALSE) 1308 || ahc_sent_msg(ahc, AHCMSG_EXT, 1309 MSG_EXT_SDTR, FALSE)) { 1310 /* 1311 * Negotiation Rejected. Go-async and 1312 * retry command. 1313 */ 1314 ahc_set_width(ahc, &devinfo, 1315 MSG_EXT_WDTR_BUS_8_BIT, 1316 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1317 /*paused*/TRUE); 1318 ahc_set_syncrate(ahc, &devinfo, 1319 /*syncrate*/NULL, 1320 /*period*/0, /*offset*/0, 1321 /*ppr_options*/0, 1322 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1323 /*paused*/TRUE); 1324 ahc_qinfifo_requeue_tail(ahc, scb); 1325 printerror = 0; 1326 } 1327 } 1328 if (printerror != 0) { 1329 u_int i; 1330 1331 if (scb != NULL) { 1332 u_int tag; 1333 1334 if ((scb->hscb->control & TAG_ENB) != 0) 1335 tag = scb->hscb->tag; 1336 else 1337 tag = SCB_LIST_NULL; 1338 ahc_print_path(ahc, scb); 1339 ahc_abort_scbs(ahc, target, channel, 1340 SCB_GET_LUN(scb), tag, 1341 ROLE_INITIATOR, 1342 CAM_UNEXP_BUSFREE); 1343 } else { 1344 /* 1345 * We had not fully identified this connection, 1346 * so we cannot abort anything. 1347 */ 1348 printf("%s: ", ahc_name(ahc)); 1349 } 1350 for (i = 0; i < num_phases; i++) { 1351 if (lastphase == ahc_phase_table[i].phase) 1352 break; 1353 } 1354 if (lastphase != P_BUSFREE) { 1355 /* 1356 * Renegotiate with this device at the 1357 * next oportunity just in case this busfree 1358 * is due to a negotiation mismatch with the 1359 * device. 1360 */ 1361 ahc_force_renegotiation(ahc, &devinfo); 1362 } 1363 printf("Unexpected busfree %s\n" 1364 "SEQADDR == 0x%x\n", 1365 ahc_phase_table[i].phasemsg, 1366 ahc_inb(ahc, SEQADDR0) 1367 | (ahc_inb(ahc, SEQADDR1) << 8)); 1368 } 1369 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1370 ahc_restart(ahc); 1371 } else { 1372 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1373 ahc_name(ahc), status); 1374 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1375 } 1376} 1377 1378/* 1379 * Force renegotiation to occur the next time we initiate 1380 * a command to the current device. 1381 */ 1382static void 1383ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1384{ 1385 struct ahc_initiator_tinfo *targ_info; 1386 struct ahc_tmode_tstate *tstate; 1387 1388 targ_info = ahc_fetch_transinfo(ahc, 1389 devinfo->channel, 1390 devinfo->our_scsiid, 1391 devinfo->target, 1392 &tstate); 1393 ahc_update_neg_request(ahc, devinfo, tstate, 1394 targ_info, AHC_NEG_IF_NON_ASYNC); 1395} 1396 1397#define AHC_MAX_STEPS 2000 1398void 1399ahc_clear_critical_section(struct ahc_softc *ahc) 1400{ 1401 int stepping; 1402 int steps; 1403 u_int simode0; 1404 u_int simode1; 1405 1406 if (ahc->num_critical_sections == 0) 1407 return; 1408 1409 stepping = FALSE; 1410 steps = 0; 1411 simode0 = 0; 1412 simode1 = 0; 1413 for (;;) { 1414 struct cs *cs; 1415 u_int seqaddr; 1416 u_int i; 1417 1418 seqaddr = ahc_inb(ahc, SEQADDR0) 1419 | (ahc_inb(ahc, SEQADDR1) << 8); 1420 1421 /* 1422 * Seqaddr represents the next instruction to execute, 1423 * so we are really executing the instruction just 1424 * before it. 1425 */ 1426 if (seqaddr != 0) 1427 seqaddr -= 1; 1428 cs = ahc->critical_sections; 1429 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1430 1431 if (cs->begin < seqaddr && cs->end >= seqaddr) 1432 break; 1433 } 1434 1435 if (i == ahc->num_critical_sections) 1436 break; 1437 1438 if (steps > AHC_MAX_STEPS) { 1439 printf("%s: Infinite loop in critical section\n", 1440 ahc_name(ahc)); 1441 ahc_dump_card_state(ahc); 1442 panic("critical section loop"); 1443 } 1444 1445 steps++; 1446 if (stepping == FALSE) { 1447 1448 /* 1449 * Disable all interrupt sources so that the 1450 * sequencer will not be stuck by a pausing 1451 * interrupt condition while we attempt to 1452 * leave a critical section. 1453 */ 1454 simode0 = ahc_inb(ahc, SIMODE0); 1455 ahc_outb(ahc, SIMODE0, 0); 1456 simode1 = ahc_inb(ahc, SIMODE1); 1457 if ((ahc->features & AHC_DT) != 0) 1458 /* 1459 * On DT class controllers, we 1460 * use the enhanced busfree logic. 1461 * Unfortunately we cannot re-enable 1462 * busfree detection within the 1463 * current connection, so we must 1464 * leave it on while single stepping. 1465 */ 1466 ahc_outb(ahc, SIMODE1, ENBUSFREE); 1467 else 1468 ahc_outb(ahc, SIMODE1, 0); 1469 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1470 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) | STEP); 1471 stepping = TRUE; 1472 } 1473 if ((ahc->features & AHC_DT) != 0) { 1474 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1475 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1476 } 1477 ahc_outb(ahc, HCNTRL, ahc->unpause); 1478 while (!ahc_is_paused(ahc)) 1479 ahc_delay(200); 1480 } 1481 if (stepping) { 1482 ahc_outb(ahc, SIMODE0, simode0); 1483 ahc_outb(ahc, SIMODE1, simode1); 1484 ahc_outb(ahc, SEQCTL, ahc_inb(ahc, SEQCTL) & ~STEP); 1485 } 1486} 1487 1488/* 1489 * Clear any pending interrupt status. 1490 */ 1491void 1492ahc_clear_intstat(struct ahc_softc *ahc) 1493{ 1494 /* Clear any interrupt conditions this may have caused */ 1495 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1496 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1497 CLRREQINIT); 1498 ahc_flush_device_writes(ahc); 1499 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1500 ahc_flush_device_writes(ahc); 1501 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1502 ahc_flush_device_writes(ahc); 1503} 1504 1505/**************************** Debugging Routines ******************************/ 1506#ifdef AHC_DEBUG 1507uint32_t ahc_debug = AHC_DEBUG_OPTS; 1508#endif 1509 1510void 1511ahc_print_scb(struct scb *scb) 1512{ 1513 int i; 1514 1515 struct hardware_scb *hscb = scb->hscb; 1516 1517 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1518 (void *)scb, 1519 hscb->control, 1520 hscb->scsiid, 1521 hscb->lun, 1522 hscb->cdb_len); 1523 printf("Shared Data: "); 1524 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 1525 printf("%#02x", hscb->shared_data.cdb[i]); 1526 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1527 ahc_le32toh(hscb->dataptr), 1528 ahc_le32toh(hscb->datacnt), 1529 ahc_le32toh(hscb->sgptr), 1530 hscb->tag); 1531 if (scb->sg_count > 0) { 1532 for (i = 0; i < scb->sg_count; i++) { 1533 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 1534 i, 1535 (ahc_le32toh(scb->sg_list[i].len) >> 24 1536 & SG_HIGH_ADDR_BITS), 1537 ahc_le32toh(scb->sg_list[i].addr), 1538 ahc_le32toh(scb->sg_list[i].len)); 1539 } 1540 } 1541} 1542 1543/************************* Transfer Negotiation *******************************/ 1544/* 1545 * Allocate per target mode instance (ID we respond to as a target) 1546 * transfer negotiation data structures. 1547 */ 1548static struct ahc_tmode_tstate * 1549ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1550{ 1551 struct ahc_tmode_tstate *master_tstate; 1552 struct ahc_tmode_tstate *tstate; 1553 int i; 1554 1555 master_tstate = ahc->enabled_targets[ahc->our_id]; 1556 if (channel == 'B') { 1557 scsi_id += 8; 1558 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1559 } 1560 if (ahc->enabled_targets[scsi_id] != NULL 1561 && ahc->enabled_targets[scsi_id] != master_tstate) 1562 panic("%s: ahc_alloc_tstate - Target already allocated", 1563 ahc_name(ahc)); 1564 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate), 1565 M_DEVBUF, M_NOWAIT); 1566 if (tstate == NULL) 1567 return (NULL); 1568 1569 /* 1570 * If we have allocated a master tstate, copy user settings from 1571 * the master tstate (taken from SRAM or the EEPROM) for this 1572 * channel, but reset our current and goal settings to async/narrow 1573 * until an initiator talks to us. 1574 */ 1575 if (master_tstate != NULL) { 1576 memcpy(tstate, master_tstate, sizeof(*tstate)); 1577 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1578 tstate->ultraenb = 0; 1579 for (i = 0; i < AHC_NUM_TARGETS; i++) { 1580 memset(&tstate->transinfo[i].curr, 0, 1581 sizeof(tstate->transinfo[i].curr)); 1582 memset(&tstate->transinfo[i].goal, 0, 1583 sizeof(tstate->transinfo[i].goal)); 1584 } 1585 } else 1586 memset(tstate, 0, sizeof(*tstate)); 1587 ahc->enabled_targets[scsi_id] = tstate; 1588 return (tstate); 1589} 1590 1591#ifdef AHC_TARGET_MODE 1592/* 1593 * Free per target mode instance (ID we respond to as a target) 1594 * transfer negotiation data structures. 1595 */ 1596static void 1597ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1598{ 1599 struct ahc_tmode_tstate *tstate; 1600 1601 /* 1602 * Don't clean up our "master" tstate. 1603 * It has our default user settings. 1604 */ 1605 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1606 || (channel == 'A' && scsi_id == ahc->our_id)) 1607 && force == FALSE) 1608 return; 1609 1610 if (channel == 'B') 1611 scsi_id += 8; 1612 tstate = ahc->enabled_targets[scsi_id]; 1613 if (tstate != NULL) 1614 free(tstate, M_DEVBUF); 1615 ahc->enabled_targets[scsi_id] = NULL; 1616} 1617#endif 1618 1619/* 1620 * Called when we have an active connection to a target on the bus, 1621 * this function finds the nearest syncrate to the input period limited 1622 * by the capabilities of the bus connectivity of and sync settings for 1623 * the target. 1624 */ 1625struct ahc_syncrate * 1626ahc_devlimited_syncrate(struct ahc_softc *ahc, 1627 struct ahc_initiator_tinfo *tinfo, 1628 u_int *period, u_int *ppr_options, role_t role) 1629{ 1630 struct ahc_transinfo *transinfo; 1631 u_int maxsync; 1632 1633 if ((ahc->features & AHC_ULTRA2) != 0) { 1634 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1635 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1636 maxsync = AHC_SYNCRATE_DT; 1637 } else { 1638 maxsync = AHC_SYNCRATE_ULTRA; 1639 /* Can't do DT on an SE bus */ 1640 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1641 } 1642 } else if ((ahc->features & AHC_ULTRA) != 0) { 1643 maxsync = AHC_SYNCRATE_ULTRA; 1644 } else { 1645 maxsync = AHC_SYNCRATE_FAST; 1646 } 1647 /* 1648 * Never allow a value higher than our current goal 1649 * period otherwise we may allow a target initiated 1650 * negotiation to go above the limit as set by the 1651 * user. In the case of an initiator initiated 1652 * sync negotiation, we limit based on the user 1653 * setting. This allows the system to still accept 1654 * incoming negotiations even if target initiated 1655 * negotiation is not performed. 1656 */ 1657 if (role == ROLE_TARGET) 1658 transinfo = &tinfo->user; 1659 else 1660 transinfo = &tinfo->goal; 1661 *ppr_options &= transinfo->ppr_options; 1662 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 1663 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2); 1664 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1665 } 1666 if (transinfo->period == 0) { 1667 *period = 0; 1668 *ppr_options = 0; 1669 return (NULL); 1670 } 1671 *period = MAX(*period, transinfo->period); 1672 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1673} 1674 1675/* 1676 * Look up the valid period to SCSIRATE conversion in our table. 1677 * Return the period and offset that should be sent to the target 1678 * if this was the beginning of an SDTR. 1679 */ 1680struct ahc_syncrate * 1681ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1682 u_int *ppr_options, u_int maxsync) 1683{ 1684 struct ahc_syncrate *syncrate; 1685 1686 if ((ahc->features & AHC_DT) == 0) 1687 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1688 1689 /* Skip all DT only entries if DT is not available */ 1690 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1691 && maxsync < AHC_SYNCRATE_ULTRA2) 1692 maxsync = AHC_SYNCRATE_ULTRA2; 1693 1694 for (syncrate = &ahc_syncrates[maxsync]; 1695 syncrate->rate != NULL; 1696 syncrate++) { 1697 1698 /* 1699 * The Ultra2 table doesn't go as low 1700 * as for the Fast/Ultra cards. 1701 */ 1702 if ((ahc->features & AHC_ULTRA2) != 0 1703 && (syncrate->sxfr_u2 == 0)) 1704 break; 1705 1706 if (*period <= syncrate->period) { 1707 /* 1708 * When responding to a target that requests 1709 * sync, the requested rate may fall between 1710 * two rates that we can output, but still be 1711 * a rate that we can receive. Because of this, 1712 * we want to respond to the target with 1713 * the same rate that it sent to us even 1714 * if the period we use to send data to it 1715 * is lower. Only lower the response period 1716 * if we must. 1717 */ 1718 if (syncrate == &ahc_syncrates[maxsync]) 1719 *period = syncrate->period; 1720 1721 /* 1722 * At some speeds, we only support 1723 * ST transfers. 1724 */ 1725 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1726 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1727 break; 1728 } 1729 } 1730 1731 if ((*period == 0) 1732 || (syncrate->rate == NULL) 1733 || ((ahc->features & AHC_ULTRA2) != 0 1734 && (syncrate->sxfr_u2 == 0))) { 1735 /* Use asynchronous transfers. */ 1736 *period = 0; 1737 syncrate = NULL; 1738 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1739 } 1740 return (syncrate); 1741} 1742 1743/* 1744 * Convert from an entry in our syncrate table to the SCSI equivalent 1745 * sync "period" factor. 1746 */ 1747u_int 1748ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1749{ 1750 struct ahc_syncrate *syncrate; 1751 1752 if ((ahc->features & AHC_ULTRA2) != 0) 1753 scsirate &= SXFR_ULTRA2; 1754 else 1755 scsirate &= SXFR; 1756 1757 syncrate = &ahc_syncrates[maxsync]; 1758 while (syncrate->rate != NULL) { 1759 1760 if ((ahc->features & AHC_ULTRA2) != 0) { 1761 if (syncrate->sxfr_u2 == 0) 1762 break; 1763 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1764 return (syncrate->period); 1765 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1766 return (syncrate->period); 1767 } 1768 syncrate++; 1769 } 1770 return (0); /* async */ 1771} 1772 1773/* 1774 * Truncate the given synchronous offset to a value the 1775 * current adapter type and syncrate are capable of. 1776 */ 1777void 1778ahc_validate_offset(struct ahc_softc *ahc, 1779 struct ahc_initiator_tinfo *tinfo, 1780 struct ahc_syncrate *syncrate, 1781 u_int *offset, int wide, role_t role) 1782{ 1783 u_int maxoffset; 1784 1785 /* Limit offset to what we can do */ 1786 if (syncrate == NULL) { 1787 maxoffset = 0; 1788 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1789 maxoffset = MAX_OFFSET_ULTRA2; 1790 } else { 1791 if (wide) 1792 maxoffset = MAX_OFFSET_16BIT; 1793 else 1794 maxoffset = MAX_OFFSET_8BIT; 1795 } 1796 *offset = MIN(*offset, maxoffset); 1797 if (tinfo != NULL) { 1798 if (role == ROLE_TARGET) 1799 *offset = MIN(*offset, tinfo->user.offset); 1800 else 1801 *offset = MIN(*offset, tinfo->goal.offset); 1802 } 1803} 1804 1805/* 1806 * Truncate the given transfer width parameter to a value the 1807 * current adapter type is capable of. 1808 */ 1809void 1810ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1811 u_int *bus_width, role_t role) 1812{ 1813 switch (*bus_width) { 1814 default: 1815 if (ahc->features & AHC_WIDE) { 1816 /* Respond Wide */ 1817 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1818 break; 1819 } 1820 /* FALLTHROUGH */ 1821 case MSG_EXT_WDTR_BUS_8_BIT: 1822 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1823 break; 1824 } 1825 if (tinfo != NULL) { 1826 if (role == ROLE_TARGET) 1827 *bus_width = MIN(tinfo->user.width, *bus_width); 1828 else 1829 *bus_width = MIN(tinfo->goal.width, *bus_width); 1830 } 1831} 1832 1833/* 1834 * Update the bitmask of targets for which the controller should 1835 * negotiate with at the next convenient oportunity. This currently 1836 * means the next time we send the initial identify messages for 1837 * a new transaction. 1838 */ 1839int 1840ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1841 struct ahc_tmode_tstate *tstate, 1842 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 1843{ 1844 u_int auto_negotiate_orig; 1845 1846 auto_negotiate_orig = tstate->auto_negotiate; 1847 if (neg_type == AHC_NEG_ALWAYS) { 1848 /* 1849 * Force our "current" settings to be 1850 * unknown so that unless a bus reset 1851 * occurs the need to renegotiate is 1852 * recorded persistently. 1853 */ 1854 if ((ahc->features & AHC_WIDE) != 0) 1855 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 1856 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 1857 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 1858 } 1859 if (tinfo->curr.period != tinfo->goal.period 1860 || tinfo->curr.width != tinfo->goal.width 1861 || tinfo->curr.offset != tinfo->goal.offset 1862 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 1863 || (neg_type == AHC_NEG_IF_NON_ASYNC 1864 && (tinfo->goal.offset != 0 1865 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1866 || tinfo->goal.ppr_options != 0))) 1867 tstate->auto_negotiate |= devinfo->target_mask; 1868 else 1869 tstate->auto_negotiate &= ~devinfo->target_mask; 1870 1871 return (auto_negotiate_orig != tstate->auto_negotiate); 1872} 1873 1874/* 1875 * Update the user/goal/curr tables of synchronous negotiation 1876 * parameters as well as, in the case of a current or active update, 1877 * any data structures on the host controller. In the case of an 1878 * active update, the specified target is currently talking to us on 1879 * the bus, so the transfer parameter update must take effect 1880 * immediately. 1881 */ 1882void 1883ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1884 struct ahc_syncrate *syncrate, u_int period, 1885 u_int offset, u_int ppr_options, u_int type, int paused) 1886{ 1887 struct ahc_initiator_tinfo *tinfo; 1888 struct ahc_tmode_tstate *tstate; 1889 u_int old_period; 1890 u_int old_offset; 1891 u_int old_ppr; 1892 int active; 1893 int update_needed; 1894 1895 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1896 update_needed = 0; 1897 1898 if (syncrate == NULL) { 1899 period = 0; 1900 offset = 0; 1901 } 1902 1903 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1904 devinfo->target, &tstate); 1905 1906 if ((type & AHC_TRANS_USER) != 0) { 1907 tinfo->user.period = period; 1908 tinfo->user.offset = offset; 1909 tinfo->user.ppr_options = ppr_options; 1910 } 1911 1912 if ((type & AHC_TRANS_GOAL) != 0) { 1913 tinfo->goal.period = period; 1914 tinfo->goal.offset = offset; 1915 tinfo->goal.ppr_options = ppr_options; 1916 } 1917 1918 old_period = tinfo->curr.period; 1919 old_offset = tinfo->curr.offset; 1920 old_ppr = tinfo->curr.ppr_options; 1921 1922 if ((type & AHC_TRANS_CUR) != 0 1923 && (old_period != period 1924 || old_offset != offset 1925 || old_ppr != ppr_options)) { 1926 u_int scsirate; 1927 1928 update_needed++; 1929 scsirate = tinfo->scsirate; 1930 if ((ahc->features & AHC_ULTRA2) != 0) { 1931 1932 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1933 if (syncrate != NULL) { 1934 scsirate |= syncrate->sxfr_u2; 1935 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 1936 scsirate |= ENABLE_CRC; 1937 else 1938 scsirate |= SINGLE_EDGE; 1939 } 1940 } else { 1941 1942 scsirate &= ~(SXFR|SOFS); 1943 /* 1944 * Ensure Ultra mode is set properly for 1945 * this target. 1946 */ 1947 tstate->ultraenb &= ~devinfo->target_mask; 1948 if (syncrate != NULL) { 1949 if (syncrate->sxfr & ULTRA_SXFR) { 1950 tstate->ultraenb |= 1951 devinfo->target_mask; 1952 } 1953 scsirate |= syncrate->sxfr & SXFR; 1954 scsirate |= offset & SOFS; 1955 } 1956 if (active) { 1957 u_int sxfrctl0; 1958 1959 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1960 sxfrctl0 &= ~FAST20; 1961 if (tstate->ultraenb & devinfo->target_mask) 1962 sxfrctl0 |= FAST20; 1963 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1964 } 1965 } 1966 if (active) { 1967 ahc_outb(ahc, SCSIRATE, scsirate); 1968 if ((ahc->features & AHC_ULTRA2) != 0) 1969 ahc_outb(ahc, SCSIOFFSET, offset); 1970 } 1971 1972 tinfo->scsirate = scsirate; 1973 tinfo->curr.period = period; 1974 tinfo->curr.offset = offset; 1975 tinfo->curr.ppr_options = ppr_options; 1976 1977 ahc_send_async(ahc, devinfo->channel, devinfo->target, 1978 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 1979 if (bootverbose) { 1980 if (offset != 0) { 1981 printf("%s: target %d synchronous at %sMHz%s, " 1982 "offset = 0x%x\n", ahc_name(ahc), 1983 devinfo->target, syncrate->rate, 1984 (ppr_options & MSG_EXT_PPR_DT_REQ) 1985 ? " DT" : "", offset); 1986 } else { 1987 printf("%s: target %d using " 1988 "asynchronous transfers\n", 1989 ahc_name(ahc), devinfo->target); 1990 } 1991 } 1992 } 1993 1994 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 1995 tinfo, AHC_NEG_TO_GOAL); 1996 1997 if (update_needed) 1998 ahc_update_pending_scbs(ahc); 1999} 2000 2001/* 2002 * Update the user/goal/curr tables of wide negotiation 2003 * parameters as well as, in the case of a current or active update, 2004 * any data structures on the host controller. In the case of an 2005 * active update, the specified target is currently talking to us on 2006 * the bus, so the transfer parameter update must take effect 2007 * immediately. 2008 */ 2009void 2010ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2011 u_int width, u_int type, int paused) 2012{ 2013 struct ahc_initiator_tinfo *tinfo; 2014 struct ahc_tmode_tstate *tstate; 2015 u_int oldwidth; 2016 int active; 2017 int update_needed; 2018 2019 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2020 update_needed = 0; 2021 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2022 devinfo->target, &tstate); 2023 2024 if ((type & AHC_TRANS_USER) != 0) 2025 tinfo->user.width = width; 2026 2027 if ((type & AHC_TRANS_GOAL) != 0) 2028 tinfo->goal.width = width; 2029 2030 oldwidth = tinfo->curr.width; 2031 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2032 u_int scsirate; 2033 2034 update_needed++; 2035 scsirate = tinfo->scsirate; 2036 scsirate &= ~WIDEXFER; 2037 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2038 scsirate |= WIDEXFER; 2039 2040 tinfo->scsirate = scsirate; 2041 2042 if (active) 2043 ahc_outb(ahc, SCSIRATE, scsirate); 2044 2045 tinfo->curr.width = width; 2046 2047 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2048 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2049 if (bootverbose) { 2050 printf("%s: target %d using %dbit transfers\n", 2051 ahc_name(ahc), devinfo->target, 2052 8 * (0x01 << width)); 2053 } 2054 } 2055 2056 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2057 tinfo, AHC_NEG_TO_GOAL); 2058 if (update_needed) 2059 ahc_update_pending_scbs(ahc); 2060} 2061 2062/* 2063 * Update the current state of tagged queuing for a given target. 2064 */ 2065void 2066ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2067 ahc_queue_alg alg) 2068{ 2069 ahc_platform_set_tags(ahc, devinfo, alg); 2070 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2071 devinfo->lun, AC_TRANSFER_NEG, &alg); 2072} 2073 2074/* 2075 * When the transfer settings for a connection change, update any 2076 * in-transit SCBs to contain the new data so the hardware will 2077 * be set correctly during future (re)selections. 2078 */ 2079static void 2080ahc_update_pending_scbs(struct ahc_softc *ahc) 2081{ 2082 struct scb *pending_scb; 2083 int pending_scb_count; 2084 int i; 2085 int paused; 2086 u_int saved_scbptr; 2087 2088 /* 2089 * Traverse the pending SCB list and ensure that all of the 2090 * SCBs there have the proper settings. 2091 */ 2092 pending_scb_count = 0; 2093 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2094 struct ahc_devinfo devinfo; 2095 struct hardware_scb *pending_hscb; 2096 struct ahc_initiator_tinfo *tinfo; 2097 struct ahc_tmode_tstate *tstate; 2098 2099 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2100 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2101 devinfo.our_scsiid, 2102 devinfo.target, &tstate); 2103 pending_hscb = pending_scb->hscb; 2104 pending_hscb->control &= ~ULTRAENB; 2105 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2106 pending_hscb->control |= ULTRAENB; 2107 pending_hscb->scsirate = tinfo->scsirate; 2108 pending_hscb->scsioffset = tinfo->curr.offset; 2109 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2110 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2111 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2112 pending_hscb->control &= ~MK_MESSAGE; 2113 } 2114 ahc_sync_scb(ahc, pending_scb, 2115 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2116 pending_scb_count++; 2117 } 2118 2119 if (pending_scb_count == 0) 2120 return; 2121 2122 if (ahc_is_paused(ahc)) { 2123 paused = 1; 2124 } else { 2125 paused = 0; 2126 ahc_pause(ahc); 2127 } 2128 2129 saved_scbptr = ahc_inb(ahc, SCBPTR); 2130 /* Ensure that the hscbs down on the card match the new information */ 2131 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2132 struct hardware_scb *pending_hscb; 2133 u_int control; 2134 u_int scb_tag; 2135 2136 ahc_outb(ahc, SCBPTR, i); 2137 scb_tag = ahc_inb(ahc, SCB_TAG); 2138 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2139 if (pending_scb == NULL) 2140 continue; 2141 2142 pending_hscb = pending_scb->hscb; 2143 control = ahc_inb(ahc, SCB_CONTROL); 2144 control &= ~(ULTRAENB|MK_MESSAGE); 2145 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2146 ahc_outb(ahc, SCB_CONTROL, control); 2147 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2148 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2149 } 2150 ahc_outb(ahc, SCBPTR, saved_scbptr); 2151 2152 if (paused == 0) 2153 ahc_unpause(ahc); 2154} 2155 2156/**************************** Pathing Information *****************************/ 2157static void 2158ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2159{ 2160 u_int saved_scsiid; 2161 role_t role; 2162 int our_id; 2163 2164 if (ahc_inb(ahc, SSTAT0) & TARGET) 2165 role = ROLE_TARGET; 2166 else 2167 role = ROLE_INITIATOR; 2168 2169 if (role == ROLE_TARGET 2170 && (ahc->features & AHC_MULTI_TID) != 0 2171 && (ahc_inb(ahc, SEQ_FLAGS) 2172 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2173 /* We were selected, so pull our id from TARGIDIN */ 2174 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2175 } else if ((ahc->features & AHC_ULTRA2) != 0) 2176 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2177 else 2178 our_id = ahc_inb(ahc, SCSIID) & OID; 2179 2180 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2181 ahc_compile_devinfo(devinfo, 2182 our_id, 2183 SCSIID_TARGET(ahc, saved_scsiid), 2184 ahc_inb(ahc, SAVED_LUN), 2185 SCSIID_CHANNEL(ahc, saved_scsiid), 2186 role); 2187} 2188 2189struct ahc_phase_table_entry* 2190ahc_lookup_phase_entry(int phase) 2191{ 2192 struct ahc_phase_table_entry *entry; 2193 struct ahc_phase_table_entry *last_entry; 2194 2195 /* 2196 * num_phases doesn't include the default entry which 2197 * will be returned if the phase doesn't match. 2198 */ 2199 last_entry = &ahc_phase_table[num_phases]; 2200 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2201 if (phase == entry->phase) 2202 break; 2203 } 2204 return (entry); 2205} 2206 2207void 2208ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2209 u_int lun, char channel, role_t role) 2210{ 2211 devinfo->our_scsiid = our_id; 2212 devinfo->target = target; 2213 devinfo->lun = lun; 2214 devinfo->target_offset = target; 2215 devinfo->channel = channel; 2216 devinfo->role = role; 2217 if (channel == 'B') 2218 devinfo->target_offset += 8; 2219 devinfo->target_mask = (0x01 << devinfo->target_offset); 2220} 2221 2222void 2223ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2224{ 2225 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2226 devinfo->target, devinfo->lun); 2227} 2228 2229static void 2230ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2231 struct scb *scb) 2232{ 2233 role_t role; 2234 int our_id; 2235 2236 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2237 role = ROLE_INITIATOR; 2238 if ((scb->flags & SCB_TARGET_SCB) != 0) 2239 role = ROLE_TARGET; 2240 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2241 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2242} 2243 2244 2245/************************ Message Phase Processing ****************************/ 2246static void 2247ahc_assert_atn(struct ahc_softc *ahc) 2248{ 2249 u_int scsisigo; 2250 2251 scsisigo = ATNO; 2252 if ((ahc->features & AHC_DT) == 0) 2253 scsisigo |= ahc_inb(ahc, SCSISIGI); 2254 ahc_outb(ahc, SCSISIGO, scsisigo); 2255} 2256 2257/* 2258 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2259 * or enters the initial message out phase, we are interrupted. Fill our 2260 * outgoing message buffer with the appropriate message and beging handing 2261 * the message phase(s) manually. 2262 */ 2263static void 2264ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2265 struct scb *scb) 2266{ 2267 /* 2268 * To facilitate adding multiple messages together, 2269 * each routine should increment the index and len 2270 * variables instead of setting them explicitly. 2271 */ 2272 ahc->msgout_index = 0; 2273 ahc->msgout_len = 0; 2274 2275 if ((scb->flags & SCB_DEVICE_RESET) == 0 2276 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2277 u_int identify_msg; 2278 2279 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2280 if ((scb->hscb->control & DISCENB) != 0) 2281 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2282 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2283 ahc->msgout_len++; 2284 2285 if ((scb->hscb->control & TAG_ENB) != 0) { 2286 ahc->msgout_buf[ahc->msgout_index++] = 2287 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2288 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2289 ahc->msgout_len += 2; 2290 } 2291 } 2292 2293 if (scb->flags & SCB_DEVICE_RESET) { 2294 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2295 ahc->msgout_len++; 2296 ahc_print_path(ahc, scb); 2297 printf("Bus Device Reset Message Sent\n"); 2298 /* 2299 * Clear our selection hardware in advance of 2300 * the busfree. We may have an entry in the waiting 2301 * Q for this target, and we don't want to go about 2302 * selecting while we handle the busfree and blow it 2303 * away. 2304 */ 2305 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2306 } else if ((scb->flags & SCB_ABORT) != 0) { 2307 if ((scb->hscb->control & TAG_ENB) != 0) 2308 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2309 else 2310 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2311 ahc->msgout_len++; 2312 ahc_print_path(ahc, scb); 2313 printf("Abort%s Message Sent\n", 2314 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2315 /* 2316 * Clear our selection hardware in advance of 2317 * the busfree. We may have an entry in the waiting 2318 * Q for this target, and we don't want to go about 2319 * selecting while we handle the busfree and blow it 2320 * away. 2321 */ 2322 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2323 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2324 ahc_build_transfer_msg(ahc, devinfo); 2325 } else { 2326 printf("ahc_intr: AWAITING_MSG for an SCB that " 2327 "does not have a waiting message\n"); 2328 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2329 devinfo->target_mask); 2330 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2331 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2332 ahc_inb(ahc, MSG_OUT), scb->flags); 2333 } 2334 2335 /* 2336 * Clear the MK_MESSAGE flag from the SCB so we aren't 2337 * asked to send this message again. 2338 */ 2339 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2340 scb->hscb->control &= ~MK_MESSAGE; 2341 ahc->msgout_index = 0; 2342 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2343} 2344 2345/* 2346 * Build an appropriate transfer negotiation message for the 2347 * currently active target. 2348 */ 2349static void 2350ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2351{ 2352 /* 2353 * We need to initiate transfer negotiations. 2354 * If our current and goal settings are identical, 2355 * we want to renegotiate due to a check condition. 2356 */ 2357 struct ahc_initiator_tinfo *tinfo; 2358 struct ahc_tmode_tstate *tstate; 2359 struct ahc_syncrate *rate; 2360 int dowide; 2361 int dosync; 2362 int doppr; 2363 u_int period; 2364 u_int ppr_options; 2365 u_int offset; 2366 2367 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2368 devinfo->target, &tstate); 2369 /* 2370 * Filter our period based on the current connection. 2371 * If we can't perform DT transfers on this segment (not in LVD 2372 * mode for instance), then our decision to issue a PPR message 2373 * may change. 2374 */ 2375 period = tinfo->goal.period; 2376 ppr_options = tinfo->goal.ppr_options; 2377 /* Target initiated PPR is not allowed in the SCSI spec */ 2378 if (devinfo->role == ROLE_TARGET) 2379 ppr_options = 0; 2380 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2381 &ppr_options, devinfo->role); 2382 dowide = tinfo->curr.width != tinfo->goal.width; 2383 dosync = tinfo->curr.period != period; 2384 /* 2385 * Only use PPR if we have options that need it, even if the device 2386 * claims to support it. There might be an expander in the way 2387 * that doesn't. 2388 */ 2389 doppr = ppr_options != 0; 2390 2391 if (!dowide && !dosync && !doppr) { 2392 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2393 dosync = tinfo->goal.offset != 0; 2394 } 2395 2396 if (!dowide && !dosync && !doppr) { 2397 /* 2398 * Force async with a WDTR message if we have a wide bus, 2399 * or just issue an SDTR with a 0 offset. 2400 */ 2401 if ((ahc->features & AHC_WIDE) != 0) 2402 dowide = 1; 2403 else 2404 dosync = 1; 2405 2406 if (bootverbose) { 2407 ahc_print_devinfo(ahc, devinfo); 2408 printf("Ensuring async\n"); 2409 } 2410 } 2411 2412 /* Target initiated PPR is not allowed in the SCSI spec */ 2413 if (devinfo->role == ROLE_TARGET) 2414 doppr = 0; 2415 2416 /* 2417 * Both the PPR message and SDTR message require the 2418 * goal syncrate to be limited to what the target device 2419 * is capable of handling (based on whether an LVD->SE 2420 * expander is on the bus), so combine these two cases. 2421 * Regardless, guarantee that if we are using WDTR and SDTR 2422 * messages that WDTR comes first. 2423 */ 2424 if (doppr || (dosync && !dowide)) { 2425 2426 offset = tinfo->goal.offset; 2427 ahc_validate_offset(ahc, tinfo, rate, &offset, 2428 doppr ? tinfo->goal.width 2429 : tinfo->curr.width, 2430 devinfo->role); 2431 if (doppr) { 2432 ahc_construct_ppr(ahc, devinfo, period, offset, 2433 tinfo->goal.width, ppr_options); 2434 } else { 2435 ahc_construct_sdtr(ahc, devinfo, period, offset); 2436 } 2437 } else { 2438 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2439 } 2440} 2441 2442/* 2443 * Build a synchronous negotiation message in our message 2444 * buffer based on the input parameters. 2445 */ 2446static void 2447ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2448 u_int period, u_int offset) 2449{ 2450 if (offset == 0) 2451 period = AHC_ASYNC_XFER_PERIOD; 2452 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2453 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 2454 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 2455 ahc->msgout_buf[ahc->msgout_index++] = period; 2456 ahc->msgout_buf[ahc->msgout_index++] = offset; 2457 ahc->msgout_len += 5; 2458 if (bootverbose) { 2459 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2460 ahc_name(ahc), devinfo->channel, devinfo->target, 2461 devinfo->lun, period, offset); 2462 } 2463} 2464 2465/* 2466 * Build a wide negotiation message in our message 2467 * buffer based on the input parameters. 2468 */ 2469static void 2470ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2471 u_int bus_width) 2472{ 2473 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2474 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 2475 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 2476 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2477 ahc->msgout_len += 4; 2478 if (bootverbose) { 2479 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2480 ahc_name(ahc), devinfo->channel, devinfo->target, 2481 devinfo->lun, bus_width); 2482 } 2483} 2484 2485/* 2486 * Build a parallel protocol request message in our message 2487 * buffer based on the input parameters. 2488 */ 2489static void 2490ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2491 u_int period, u_int offset, u_int bus_width, 2492 u_int ppr_options) 2493{ 2494 if (offset == 0) 2495 period = AHC_ASYNC_XFER_PERIOD; 2496 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2497 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; 2498 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; 2499 ahc->msgout_buf[ahc->msgout_index++] = period; 2500 ahc->msgout_buf[ahc->msgout_index++] = 0; 2501 ahc->msgout_buf[ahc->msgout_index++] = offset; 2502 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2503 ahc->msgout_buf[ahc->msgout_index++] = ppr_options; 2504 ahc->msgout_len += 8; 2505 if (bootverbose) { 2506 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2507 "offset %x, ppr_options %x\n", ahc_name(ahc), 2508 devinfo->channel, devinfo->target, devinfo->lun, 2509 bus_width, period, offset, ppr_options); 2510 } 2511} 2512 2513/* 2514 * Clear any active message state. 2515 */ 2516static void 2517ahc_clear_msg_state(struct ahc_softc *ahc) 2518{ 2519 ahc->msgout_len = 0; 2520 ahc->msgin_index = 0; 2521 ahc->msg_type = MSG_TYPE_NONE; 2522 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2523 /* 2524 * The target didn't care to respond to our 2525 * message request, so clear ATN. 2526 */ 2527 ahc_outb(ahc, CLRSINT1, CLRATNO); 2528 } 2529 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2530 ahc_outb(ahc, SEQ_FLAGS2, 2531 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 2532} 2533 2534static void 2535ahc_handle_proto_violation(struct ahc_softc *ahc) 2536{ 2537 struct ahc_devinfo devinfo; 2538 struct scb *scb; 2539 u_int scbid; 2540 u_int seq_flags; 2541 u_int curphase; 2542 u_int lastphase; 2543 int found; 2544 2545 ahc_fetch_devinfo(ahc, &devinfo); 2546 scbid = ahc_inb(ahc, SCB_TAG); 2547 scb = ahc_lookup_scb(ahc, scbid); 2548 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 2549 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2550 lastphase = ahc_inb(ahc, LASTPHASE); 2551 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2552 2553 /* 2554 * The reconnecting target either did not send an 2555 * identify message, or did, but we didn't find an SCB 2556 * to match. 2557 */ 2558 ahc_print_devinfo(ahc, &devinfo); 2559 printf("Target did not send an IDENTIFY message. " 2560 "LASTPHASE = 0x%x.\n", lastphase); 2561 scb = NULL; 2562 } else if (scb == NULL) { 2563 /* 2564 * We don't seem to have an SCB active for this 2565 * transaction. Print an error and reset the bus. 2566 */ 2567 ahc_print_devinfo(ahc, &devinfo); 2568 printf("No SCB found during protocol violation\n"); 2569 goto proto_violation_reset; 2570 } else { 2571 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2572 if ((seq_flags & NO_CDB_SENT) != 0) { 2573 ahc_print_path(ahc, scb); 2574 printf("No or incomplete CDB sent to device.\n"); 2575 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 2576 /* 2577 * The target never bothered to provide status to 2578 * us prior to completing the command. Since we don't 2579 * know the disposition of this command, we must attempt 2580 * to abort it. Assert ATN and prepare to send an abort 2581 * message. 2582 */ 2583 ahc_print_path(ahc, scb); 2584 printf("Completed command without status.\n"); 2585 } else { 2586 ahc_print_path(ahc, scb); 2587 printf("Unknown protocol violation.\n"); 2588 ahc_dump_card_state(ahc); 2589 } 2590 } 2591 if ((lastphase & ~P_DATAIN_DT) == 0 2592 || lastphase == P_COMMAND) { 2593proto_violation_reset: 2594 /* 2595 * Target either went directly to data/command 2596 * phase or didn't respond to our ATN. 2597 * The only safe thing to do is to blow 2598 * it away with a bus reset. 2599 */ 2600 found = ahc_reset_channel(ahc, 'A', TRUE); 2601 printf("%s: Issued Channel %c Bus Reset. " 2602 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 2603 } else { 2604 /* 2605 * Leave the selection hardware off in case 2606 * this abort attempt will affect yet to 2607 * be sent commands. 2608 */ 2609 ahc_outb(ahc, SCSISEQ, 2610 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 2611 ahc_assert_atn(ahc); 2612 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2613 if (scb == NULL) { 2614 ahc_print_devinfo(ahc, &devinfo); 2615 ahc->msgout_buf[0] = MSG_ABORT_TASK; 2616 ahc->msgout_len = 1; 2617 ahc->msgout_index = 0; 2618 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2619 } else { 2620 ahc_print_path(ahc, scb); 2621 scb->flags |= SCB_ABORT; 2622 } 2623 printf("Protocol violation %s. Attempting to abort.\n", 2624 ahc_lookup_phase_entry(curphase)->phasemsg); 2625 } 2626} 2627 2628/* 2629 * Manual message loop handler. 2630 */ 2631static void 2632ahc_handle_message_phase(struct ahc_softc *ahc) 2633{ 2634 struct ahc_devinfo devinfo; 2635 u_int bus_phase; 2636 int end_session; 2637 2638 ahc_fetch_devinfo(ahc, &devinfo); 2639 end_session = FALSE; 2640 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2641 2642reswitch: 2643 switch (ahc->msg_type) { 2644 case MSG_TYPE_INITIATOR_MSGOUT: 2645 { 2646 int lastbyte; 2647 int phasemis; 2648 int msgdone; 2649 2650 if (ahc->msgout_len == 0) 2651 panic("HOST_MSG_LOOP interrupt with no active message"); 2652 2653#ifdef AHC_DEBUG 2654 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2655 ahc_print_devinfo(ahc, &devinfo); 2656 printf("INITIATOR_MSG_OUT"); 2657 } 2658#endif 2659 phasemis = bus_phase != P_MESGOUT; 2660 if (phasemis) { 2661#ifdef AHC_DEBUG 2662 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2663 printf(" PHASEMIS %s\n", 2664 ahc_lookup_phase_entry(bus_phase) 2665 ->phasemsg); 2666 } 2667#endif 2668 if (bus_phase == P_MESGIN) { 2669 /* 2670 * Change gears and see if 2671 * this messages is of interest to 2672 * us or should be passed back to 2673 * the sequencer. 2674 */ 2675 ahc_outb(ahc, CLRSINT1, CLRATNO); 2676 ahc->send_msg_perror = FALSE; 2677 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2678 ahc->msgin_index = 0; 2679 goto reswitch; 2680 } 2681 end_session = TRUE; 2682 break; 2683 } 2684 2685 if (ahc->send_msg_perror) { 2686 ahc_outb(ahc, CLRSINT1, CLRATNO); 2687 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2688#ifdef AHC_DEBUG 2689 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2690 printf(" byte 0x%x\n", ahc->send_msg_perror); 2691#endif 2692 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2693 break; 2694 } 2695 2696 msgdone = ahc->msgout_index == ahc->msgout_len; 2697 if (msgdone) { 2698 /* 2699 * The target has requested a retry. 2700 * Re-assert ATN, reset our message index to 2701 * 0, and try again. 2702 */ 2703 ahc->msgout_index = 0; 2704 ahc_assert_atn(ahc); 2705 } 2706 2707 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2708 if (lastbyte) { 2709 /* Last byte is signified by dropping ATN */ 2710 ahc_outb(ahc, CLRSINT1, CLRATNO); 2711 } 2712 2713 /* 2714 * Clear our interrupt status and present 2715 * the next byte on the bus. 2716 */ 2717 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2718#ifdef AHC_DEBUG 2719 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2720 printf(" byte 0x%x\n", 2721 ahc->msgout_buf[ahc->msgout_index]); 2722#endif 2723 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2724 break; 2725 } 2726 case MSG_TYPE_INITIATOR_MSGIN: 2727 { 2728 int phasemis; 2729 int message_done; 2730 2731#ifdef AHC_DEBUG 2732 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2733 ahc_print_devinfo(ahc, &devinfo); 2734 printf("INITIATOR_MSG_IN"); 2735 } 2736#endif 2737 phasemis = bus_phase != P_MESGIN; 2738 if (phasemis) { 2739#ifdef AHC_DEBUG 2740 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2741 printf(" PHASEMIS %s\n", 2742 ahc_lookup_phase_entry(bus_phase) 2743 ->phasemsg); 2744 } 2745#endif 2746 ahc->msgin_index = 0; 2747 if (bus_phase == P_MESGOUT 2748 && (ahc->send_msg_perror == TRUE 2749 || (ahc->msgout_len != 0 2750 && ahc->msgout_index == 0))) { 2751 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2752 goto reswitch; 2753 } 2754 end_session = TRUE; 2755 break; 2756 } 2757 2758 /* Pull the byte in without acking it */ 2759 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2760#ifdef AHC_DEBUG 2761 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2762 printf(" byte 0x%x\n", 2763 ahc->msgin_buf[ahc->msgin_index]); 2764#endif 2765 2766 message_done = ahc_parse_msg(ahc, &devinfo); 2767 2768 if (message_done) { 2769 /* 2770 * Clear our incoming message buffer in case there 2771 * is another message following this one. 2772 */ 2773 ahc->msgin_index = 0; 2774 2775 /* 2776 * If this message illicited a response, 2777 * assert ATN so the target takes us to the 2778 * message out phase. 2779 */ 2780 if (ahc->msgout_len != 0) { 2781#ifdef AHC_DEBUG 2782 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2783 ahc_print_devinfo(ahc, &devinfo); 2784 printf("Asserting ATN for response\n"); 2785 } 2786#endif 2787 ahc_assert_atn(ahc); 2788 } 2789 } else 2790 ahc->msgin_index++; 2791 2792 if (message_done == MSGLOOP_TERMINATED) { 2793 end_session = TRUE; 2794 } else { 2795 /* Ack the byte */ 2796 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2797 ahc_inb(ahc, SCSIDATL); 2798 } 2799 break; 2800 } 2801 case MSG_TYPE_TARGET_MSGIN: 2802 { 2803 int msgdone; 2804 int msgout_request; 2805 2806 if (ahc->msgout_len == 0) 2807 panic("Target MSGIN with no active message"); 2808 2809 /* 2810 * If we interrupted a mesgout session, the initiator 2811 * will not know this until our first REQ. So, we 2812 * only honor mesgout requests after we've sent our 2813 * first byte. 2814 */ 2815 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2816 && ahc->msgout_index > 0) 2817 msgout_request = TRUE; 2818 else 2819 msgout_request = FALSE; 2820 2821 if (msgout_request) { 2822 2823 /* 2824 * Change gears and see if 2825 * this messages is of interest to 2826 * us or should be passed back to 2827 * the sequencer. 2828 */ 2829 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2830 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2831 ahc->msgin_index = 0; 2832 /* Dummy read to REQ for first byte */ 2833 ahc_inb(ahc, SCSIDATL); 2834 ahc_outb(ahc, SXFRCTL0, 2835 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2836 break; 2837 } 2838 2839 msgdone = ahc->msgout_index == ahc->msgout_len; 2840 if (msgdone) { 2841 ahc_outb(ahc, SXFRCTL0, 2842 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2843 end_session = TRUE; 2844 break; 2845 } 2846 2847 /* 2848 * Present the next byte on the bus. 2849 */ 2850 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2851 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2852 break; 2853 } 2854 case MSG_TYPE_TARGET_MSGOUT: 2855 { 2856 int lastbyte; 2857 int msgdone; 2858 2859 /* 2860 * The initiator signals that this is 2861 * the last byte by dropping ATN. 2862 */ 2863 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2864 2865 /* 2866 * Read the latched byte, but turn off SPIOEN first 2867 * so that we don't inadvertently cause a REQ for the 2868 * next byte. 2869 */ 2870 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2871 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2872 msgdone = ahc_parse_msg(ahc, &devinfo); 2873 if (msgdone == MSGLOOP_TERMINATED) { 2874 /* 2875 * The message is *really* done in that it caused 2876 * us to go to bus free. The sequencer has already 2877 * been reset at this point, so pull the ejection 2878 * handle. 2879 */ 2880 return; 2881 } 2882 2883 ahc->msgin_index++; 2884 2885 /* 2886 * XXX Read spec about initiator dropping ATN too soon 2887 * and use msgdone to detect it. 2888 */ 2889 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2890 ahc->msgin_index = 0; 2891 2892 /* 2893 * If this message illicited a response, transition 2894 * to the Message in phase and send it. 2895 */ 2896 if (ahc->msgout_len != 0) { 2897 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2898 ahc_outb(ahc, SXFRCTL0, 2899 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2900 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2901 ahc->msgin_index = 0; 2902 break; 2903 } 2904 } 2905 2906 if (lastbyte) 2907 end_session = TRUE; 2908 else { 2909 /* Ask for the next byte. */ 2910 ahc_outb(ahc, SXFRCTL0, 2911 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2912 } 2913 2914 break; 2915 } 2916 default: 2917 panic("Unknown REQINIT message type"); 2918 } 2919 2920 if (end_session) { 2921 ahc_clear_msg_state(ahc); 2922 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2923 } else 2924 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2925} 2926 2927/* 2928 * See if we sent a particular extended message to the target. 2929 * If "full" is true, return true only if the target saw the full 2930 * message. If "full" is false, return true if the target saw at 2931 * least the first byte of the message. 2932 */ 2933static int 2934ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 2935{ 2936 int found; 2937 u_int index; 2938 2939 found = FALSE; 2940 index = 0; 2941 2942 while (index < ahc->msgout_len) { 2943 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2944 u_int end_index; 2945 2946 end_index = index + 1 + ahc->msgout_buf[index + 1]; 2947 if (ahc->msgout_buf[index+2] == msgval 2948 && type == AHCMSG_EXT) { 2949 2950 if (full) { 2951 if (ahc->msgout_index > end_index) 2952 found = TRUE; 2953 } else if (ahc->msgout_index > index) 2954 found = TRUE; 2955 } 2956 index = end_index; 2957 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 2958 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2959 2960 /* Skip tag type and tag id or residue param*/ 2961 index += 2; 2962 } else { 2963 /* Single byte message */ 2964 if (type == AHCMSG_1B 2965 && ahc->msgout_buf[index] == msgval 2966 && ahc->msgout_index > index) 2967 found = TRUE; 2968 index++; 2969 } 2970 2971 if (found) 2972 break; 2973 } 2974 return (found); 2975} 2976 2977/* 2978 * Wait for a complete incoming message, parse it, and respond accordingly. 2979 */ 2980static int 2981ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2982{ 2983 struct ahc_initiator_tinfo *tinfo; 2984 struct ahc_tmode_tstate *tstate; 2985 int reject; 2986 int done; 2987 int response; 2988 u_int targ_scsirate; 2989 2990 done = MSGLOOP_IN_PROG; 2991 response = FALSE; 2992 reject = FALSE; 2993 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2994 devinfo->target, &tstate); 2995 targ_scsirate = tinfo->scsirate; 2996 2997 /* 2998 * Parse as much of the message as is available, 2999 * rejecting it if we don't support it. When 3000 * the entire message is available and has been 3001 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3002 * that we have parsed an entire message. 3003 * 3004 * In the case of extended messages, we accept the length 3005 * byte outright and perform more checking once we know the 3006 * extended message type. 3007 */ 3008 switch (ahc->msgin_buf[0]) { 3009 case MSG_DISCONNECT: 3010 case MSG_SAVEDATAPOINTER: 3011 case MSG_CMDCOMPLETE: 3012 case MSG_RESTOREPOINTERS: 3013 case MSG_IGN_WIDE_RESIDUE: 3014 /* 3015 * End our message loop as these are messages 3016 * the sequencer handles on its own. 3017 */ 3018 done = MSGLOOP_TERMINATED; 3019 break; 3020 case MSG_MESSAGE_REJECT: 3021 response = ahc_handle_msg_reject(ahc, devinfo); 3022 /* FALLTHROUGH */ 3023 case MSG_NOOP: 3024 done = MSGLOOP_MSGCOMPLETE; 3025 break; 3026 case MSG_EXTENDED: 3027 { 3028 /* Wait for enough of the message to begin validation */ 3029 if (ahc->msgin_index < 2) 3030 break; 3031 switch (ahc->msgin_buf[2]) { 3032 case MSG_EXT_SDTR: 3033 { 3034 struct ahc_syncrate *syncrate; 3035 u_int period; 3036 u_int ppr_options; 3037 u_int offset; 3038 u_int saved_offset; 3039 3040 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3041 reject = TRUE; 3042 break; 3043 } 3044 3045 /* 3046 * Wait until we have both args before validating 3047 * and acting on this message. 3048 * 3049 * Add one to MSG_EXT_SDTR_LEN to account for 3050 * the extended message preamble. 3051 */ 3052 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3053 break; 3054 3055 period = ahc->msgin_buf[3]; 3056 ppr_options = 0; 3057 saved_offset = offset = ahc->msgin_buf[4]; 3058 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3059 &ppr_options, 3060 devinfo->role); 3061 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3062 targ_scsirate & WIDEXFER, 3063 devinfo->role); 3064 if (bootverbose) { 3065 printf("(%s:%c:%d:%d): Received " 3066 "SDTR period %x, offset %x\n\t" 3067 "Filtered to period %x, offset %x\n", 3068 ahc_name(ahc), devinfo->channel, 3069 devinfo->target, devinfo->lun, 3070 ahc->msgin_buf[3], saved_offset, 3071 period, offset); 3072 } 3073 ahc_set_syncrate(ahc, devinfo, 3074 syncrate, period, 3075 offset, ppr_options, 3076 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3077 /*paused*/TRUE); 3078 3079 /* 3080 * See if we initiated Sync Negotiation 3081 * and didn't have to fall down to async 3082 * transfers. 3083 */ 3084 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3085 /* We started it */ 3086 if (saved_offset != offset) { 3087 /* Went too low - force async */ 3088 reject = TRUE; 3089 } 3090 } else { 3091 /* 3092 * Send our own SDTR in reply 3093 */ 3094 if (bootverbose 3095 && devinfo->role == ROLE_INITIATOR) { 3096 printf("(%s:%c:%d:%d): Target " 3097 "Initiated SDTR\n", 3098 ahc_name(ahc), devinfo->channel, 3099 devinfo->target, devinfo->lun); 3100 } 3101 ahc->msgout_index = 0; 3102 ahc->msgout_len = 0; 3103 ahc_construct_sdtr(ahc, devinfo, 3104 period, offset); 3105 ahc->msgout_index = 0; 3106 response = TRUE; 3107 } 3108 done = MSGLOOP_MSGCOMPLETE; 3109 break; 3110 } 3111 case MSG_EXT_WDTR: 3112 { 3113 u_int bus_width; 3114 u_int saved_width; 3115 u_int sending_reply; 3116 3117 sending_reply = FALSE; 3118 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3119 reject = TRUE; 3120 break; 3121 } 3122 3123 /* 3124 * Wait until we have our arg before validating 3125 * and acting on this message. 3126 * 3127 * Add one to MSG_EXT_WDTR_LEN to account for 3128 * the extended message preamble. 3129 */ 3130 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3131 break; 3132 3133 bus_width = ahc->msgin_buf[3]; 3134 saved_width = bus_width; 3135 ahc_validate_width(ahc, tinfo, &bus_width, 3136 devinfo->role); 3137 if (bootverbose) { 3138 printf("(%s:%c:%d:%d): Received WDTR " 3139 "%x filtered to %x\n", 3140 ahc_name(ahc), devinfo->channel, 3141 devinfo->target, devinfo->lun, 3142 saved_width, bus_width); 3143 } 3144 3145 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3146 /* 3147 * Don't send a WDTR back to the 3148 * target, since we asked first. 3149 * If the width went higher than our 3150 * request, reject it. 3151 */ 3152 if (saved_width > bus_width) { 3153 reject = TRUE; 3154 printf("(%s:%c:%d:%d): requested %dBit " 3155 "transfers. Rejecting...\n", 3156 ahc_name(ahc), devinfo->channel, 3157 devinfo->target, devinfo->lun, 3158 8 * (0x01 << bus_width)); 3159 bus_width = 0; 3160 } 3161 } else { 3162 /* 3163 * Send our own WDTR in reply 3164 */ 3165 if (bootverbose 3166 && devinfo->role == ROLE_INITIATOR) { 3167 printf("(%s:%c:%d:%d): Target " 3168 "Initiated WDTR\n", 3169 ahc_name(ahc), devinfo->channel, 3170 devinfo->target, devinfo->lun); 3171 } 3172 ahc->msgout_index = 0; 3173 ahc->msgout_len = 0; 3174 ahc_construct_wdtr(ahc, devinfo, bus_width); 3175 ahc->msgout_index = 0; 3176 response = TRUE; 3177 sending_reply = TRUE; 3178 } 3179 ahc_set_width(ahc, devinfo, bus_width, 3180 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3181 /*paused*/TRUE); 3182 /* After a wide message, we are async */ 3183 ahc_set_syncrate(ahc, devinfo, 3184 /*syncrate*/NULL, /*period*/0, 3185 /*offset*/0, /*ppr_options*/0, 3186 AHC_TRANS_ACTIVE, /*paused*/TRUE); 3187 if (sending_reply == FALSE && reject == FALSE) { 3188 3189 if (tinfo->goal.offset) { 3190 ahc->msgout_index = 0; 3191 ahc->msgout_len = 0; 3192 ahc_build_transfer_msg(ahc, devinfo); 3193 ahc->msgout_index = 0; 3194 response = TRUE; 3195 } 3196 } 3197 done = MSGLOOP_MSGCOMPLETE; 3198 break; 3199 } 3200 case MSG_EXT_PPR: 3201 { 3202 struct ahc_syncrate *syncrate; 3203 u_int period; 3204 u_int offset; 3205 u_int bus_width; 3206 u_int ppr_options; 3207 u_int saved_width; 3208 u_int saved_offset; 3209 u_int saved_ppr_options; 3210 3211 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3212 reject = TRUE; 3213 break; 3214 } 3215 3216 /* 3217 * Wait until we have all args before validating 3218 * and acting on this message. 3219 * 3220 * Add one to MSG_EXT_PPR_LEN to account for 3221 * the extended message preamble. 3222 */ 3223 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3224 break; 3225 3226 period = ahc->msgin_buf[3]; 3227 offset = ahc->msgin_buf[5]; 3228 bus_width = ahc->msgin_buf[6]; 3229 saved_width = bus_width; 3230 ppr_options = ahc->msgin_buf[7]; 3231 /* 3232 * According to the spec, a DT only 3233 * period factor with no DT option 3234 * set implies async. 3235 */ 3236 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3237 && period == 9) 3238 offset = 0; 3239 saved_ppr_options = ppr_options; 3240 saved_offset = offset; 3241 3242 /* 3243 * Mask out any options we don't support 3244 * on any controller. Transfer options are 3245 * only available if we are negotiating wide. 3246 */ 3247 ppr_options &= MSG_EXT_PPR_DT_REQ; 3248 if (bus_width == 0) 3249 ppr_options = 0; 3250 3251 ahc_validate_width(ahc, tinfo, &bus_width, 3252 devinfo->role); 3253 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3254 &ppr_options, 3255 devinfo->role); 3256 ahc_validate_offset(ahc, tinfo, syncrate, 3257 &offset, bus_width, 3258 devinfo->role); 3259 3260 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3261 /* 3262 * If we are unable to do any of the 3263 * requested options (we went too low), 3264 * then we'll have to reject the message. 3265 */ 3266 if (saved_width > bus_width 3267 || saved_offset != offset 3268 || saved_ppr_options != ppr_options) { 3269 reject = TRUE; 3270 period = 0; 3271 offset = 0; 3272 bus_width = 0; 3273 ppr_options = 0; 3274 syncrate = NULL; 3275 } 3276 } else { 3277 if (devinfo->role != ROLE_TARGET) 3278 printf("(%s:%c:%d:%d): Target " 3279 "Initiated PPR\n", 3280 ahc_name(ahc), devinfo->channel, 3281 devinfo->target, devinfo->lun); 3282 else 3283 printf("(%s:%c:%d:%d): Initiator " 3284 "Initiated PPR\n", 3285 ahc_name(ahc), devinfo->channel, 3286 devinfo->target, devinfo->lun); 3287 ahc->msgout_index = 0; 3288 ahc->msgout_len = 0; 3289 ahc_construct_ppr(ahc, devinfo, period, offset, 3290 bus_width, ppr_options); 3291 ahc->msgout_index = 0; 3292 response = TRUE; 3293 } 3294 if (bootverbose) { 3295 printf("(%s:%c:%d:%d): Received PPR width %x, " 3296 "period %x, offset %x,options %x\n" 3297 "\tFiltered to width %x, period %x, " 3298 "offset %x, options %x\n", 3299 ahc_name(ahc), devinfo->channel, 3300 devinfo->target, devinfo->lun, 3301 saved_width, ahc->msgin_buf[3], 3302 saved_offset, saved_ppr_options, 3303 bus_width, period, offset, ppr_options); 3304 } 3305 ahc_set_width(ahc, devinfo, bus_width, 3306 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3307 /*paused*/TRUE); 3308 ahc_set_syncrate(ahc, devinfo, 3309 syncrate, period, 3310 offset, ppr_options, 3311 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3312 /*paused*/TRUE); 3313 done = MSGLOOP_MSGCOMPLETE; 3314 break; 3315 } 3316 default: 3317 /* Unknown extended message. Reject it. */ 3318 reject = TRUE; 3319 break; 3320 } 3321 break; 3322 } 3323#ifdef AHC_TARGET_MODE 3324 case MSG_BUS_DEV_RESET: 3325 ahc_handle_devreset(ahc, devinfo, 3326 CAM_BDR_SENT, 3327 "Bus Device Reset Received", 3328 /*verbose_level*/0); 3329 ahc_restart(ahc); 3330 done = MSGLOOP_TERMINATED; 3331 break; 3332 case MSG_ABORT_TAG: 3333 case MSG_ABORT: 3334 case MSG_CLEAR_QUEUE: 3335 { 3336 int tag; 3337 3338 /* Target mode messages */ 3339 if (devinfo->role != ROLE_TARGET) { 3340 reject = TRUE; 3341 break; 3342 } 3343 tag = SCB_LIST_NULL; 3344 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3345 tag = ahc_inb(ahc, INITIATOR_TAG); 3346 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3347 devinfo->lun, tag, ROLE_TARGET, 3348 CAM_REQ_ABORTED); 3349 3350 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3351 if (tstate != NULL) { 3352 struct ahc_tmode_lstate* lstate; 3353 3354 lstate = tstate->enabled_luns[devinfo->lun]; 3355 if (lstate != NULL) { 3356 ahc_queue_lstate_event(ahc, lstate, 3357 devinfo->our_scsiid, 3358 ahc->msgin_buf[0], 3359 /*arg*/tag); 3360 ahc_send_lstate_events(ahc, lstate); 3361 } 3362 } 3363 ahc_restart(ahc); 3364 done = MSGLOOP_TERMINATED; 3365 break; 3366 } 3367#endif 3368 case MSG_TERM_IO_PROC: 3369 default: 3370 reject = TRUE; 3371 break; 3372 } 3373 3374 if (reject) { 3375 /* 3376 * Setup to reject the message. 3377 */ 3378 ahc->msgout_index = 0; 3379 ahc->msgout_len = 1; 3380 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3381 done = MSGLOOP_MSGCOMPLETE; 3382 response = TRUE; 3383 } 3384 3385 if (done != MSGLOOP_IN_PROG && !response) 3386 /* Clear the outgoing message buffer */ 3387 ahc->msgout_len = 0; 3388 3389 return (done); 3390} 3391 3392/* 3393 * Process a message reject message. 3394 */ 3395static int 3396ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3397{ 3398 /* 3399 * What we care about here is if we had an 3400 * outstanding SDTR or WDTR message for this 3401 * target. If we did, this is a signal that 3402 * the target is refusing negotiation. 3403 */ 3404 struct scb *scb; 3405 struct ahc_initiator_tinfo *tinfo; 3406 struct ahc_tmode_tstate *tstate; 3407 u_int scb_index; 3408 u_int last_msg; 3409 int response = 0; 3410 3411 scb_index = ahc_inb(ahc, SCB_TAG); 3412 scb = ahc_lookup_scb(ahc, scb_index); 3413 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3414 devinfo->our_scsiid, 3415 devinfo->target, &tstate); 3416 /* Might be necessary */ 3417 last_msg = ahc_inb(ahc, LAST_MSG); 3418 3419 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3420 /* 3421 * Target does not support the PPR message. 3422 * Attempt to negotiate SPI-2 style. 3423 */ 3424 if (bootverbose) { 3425 printf("(%s:%c:%d:%d): PPR Rejected. " 3426 "Trying WDTR/SDTR\n", 3427 ahc_name(ahc), devinfo->channel, 3428 devinfo->target, devinfo->lun); 3429 } 3430 tinfo->goal.ppr_options = 0; 3431 tinfo->curr.transport_version = 2; 3432 tinfo->goal.transport_version = 2; 3433 ahc->msgout_index = 0; 3434 ahc->msgout_len = 0; 3435 ahc_build_transfer_msg(ahc, devinfo); 3436 ahc->msgout_index = 0; 3437 response = 1; 3438 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3439 3440 /* note 8bit xfers */ 3441 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3442 "8bit transfers\n", ahc_name(ahc), 3443 devinfo->channel, devinfo->target, devinfo->lun); 3444 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3445 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3446 /*paused*/TRUE); 3447 /* 3448 * No need to clear the sync rate. If the target 3449 * did not accept the command, our syncrate is 3450 * unaffected. If the target started the negotiation, 3451 * but rejected our response, we already cleared the 3452 * sync rate before sending our WDTR. 3453 */ 3454 if (tinfo->goal.offset != tinfo->curr.offset) { 3455 3456 /* Start the sync negotiation */ 3457 ahc->msgout_index = 0; 3458 ahc->msgout_len = 0; 3459 ahc_build_transfer_msg(ahc, devinfo); 3460 ahc->msgout_index = 0; 3461 response = 1; 3462 } 3463 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3464 /* note asynch xfers and clear flag */ 3465 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3466 /*offset*/0, /*ppr_options*/0, 3467 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3468 /*paused*/TRUE); 3469 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 3470 "Using asynchronous transfers\n", 3471 ahc_name(ahc), devinfo->channel, 3472 devinfo->target, devinfo->lun); 3473 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 3474 int tag_type; 3475 int mask; 3476 3477 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 3478 3479 if (tag_type == MSG_SIMPLE_TASK) { 3480 printf("(%s:%c:%d:%d): refuses tagged commands. " 3481 "Performing non-tagged I/O\n", ahc_name(ahc), 3482 devinfo->channel, devinfo->target, devinfo->lun); 3483 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE); 3484 mask = ~0x23; 3485 } else { 3486 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 3487 "Performing simple queue tagged I/O only\n", 3488 ahc_name(ahc), devinfo->channel, devinfo->target, 3489 devinfo->lun, tag_type == MSG_ORDERED_TASK 3490 ? "ordered" : "head of queue"); 3491 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC); 3492 mask = ~0x03; 3493 } 3494 3495 /* 3496 * Resend the identify for this CCB as the target 3497 * may believe that the selection is invalid otherwise. 3498 */ 3499 ahc_outb(ahc, SCB_CONTROL, 3500 ahc_inb(ahc, SCB_CONTROL) & mask); 3501 scb->hscb->control &= mask; 3502 ahc_set_transaction_tag(scb, /*enabled*/FALSE, 3503 /*type*/MSG_SIMPLE_TASK); 3504 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3505 ahc_assert_atn(ahc); 3506 3507 /* 3508 * This transaction is now at the head of 3509 * the untagged queue for this target. 3510 */ 3511 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3512 struct scb_tailq *untagged_q; 3513 3514 untagged_q = 3515 &(ahc->untagged_queues[devinfo->target_offset]); 3516 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3517 scb->flags |= SCB_UNTAGGEDQ; 3518 } 3519 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3520 scb->hscb->tag); 3521 3522 /* 3523 * Requeue all tagged commands for this target 3524 * currently in our posession so they can be 3525 * converted to untagged commands. 3526 */ 3527 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3528 SCB_GET_CHANNEL(ahc, scb), 3529 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3530 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3531 SEARCH_COMPLETE); 3532 } else { 3533 /* 3534 * Otherwise, we ignore it. 3535 */ 3536 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3537 ahc_name(ahc), devinfo->channel, devinfo->target, 3538 last_msg); 3539 } 3540 return (response); 3541} 3542 3543/* 3544 * Process an ingnore wide residue message. 3545 */ 3546static void 3547ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3548{ 3549 u_int scb_index; 3550 struct scb *scb; 3551 3552 scb_index = ahc_inb(ahc, SCB_TAG); 3553 scb = ahc_lookup_scb(ahc, scb_index); 3554 /* 3555 * XXX Actually check data direction in the sequencer? 3556 * Perhaps add datadir to some spare bits in the hscb? 3557 */ 3558 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3559 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { 3560 /* 3561 * Ignore the message if we haven't 3562 * seen an appropriate data phase yet. 3563 */ 3564 } else { 3565 /* 3566 * If the residual occurred on the last 3567 * transfer and the transfer request was 3568 * expected to end on an odd count, do 3569 * nothing. Otherwise, subtract a byte 3570 * and update the residual count accordingly. 3571 */ 3572 uint32_t sgptr; 3573 3574 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3575 if ((sgptr & SG_LIST_NULL) != 0 3576 && ahc_inb(ahc, DATA_COUNT_ODD) == 1) { 3577 /* 3578 * If the residual occurred on the last 3579 * transfer and the transfer request was 3580 * expected to end on an odd count, do 3581 * nothing. 3582 */ 3583 } else { 3584 struct ahc_dma_seg *sg; 3585 uint32_t data_cnt; 3586 uint32_t data_addr; 3587 uint32_t sglen; 3588 3589 /* Pull in the rest of the sgptr */ 3590 sgptr |= (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3591 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3592 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8); 3593 sgptr &= SG_PTR_MASK; 3594 data_cnt = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+3) << 24) 3595 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+2) << 16) 3596 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT+1) << 8) 3597 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT)); 3598 3599 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24) 3600 | (ahc_inb(ahc, SHADDR + 2) << 16) 3601 | (ahc_inb(ahc, SHADDR + 1) << 8) 3602 | (ahc_inb(ahc, SHADDR)); 3603 3604 data_cnt += 1; 3605 data_addr -= 1; 3606 3607 sg = ahc_sg_bus_to_virt(scb, sgptr); 3608 /* 3609 * The residual sg ptr points to the next S/G 3610 * to load so we must go back one. 3611 */ 3612 sg--; 3613 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 3614 if (sg != scb->sg_list 3615 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 3616 3617 sg--; 3618 sglen = ahc_le32toh(sg->len); 3619 /* 3620 * Preserve High Address and SG_LIST bits 3621 * while setting the count to 1. 3622 */ 3623 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 3624 data_addr = ahc_le32toh(sg->addr) 3625 + (sglen & AHC_SG_LEN_MASK) - 1; 3626 3627 /* 3628 * Increment sg so it points to the 3629 * "next" sg. 3630 */ 3631 sg++; 3632 sgptr = ahc_sg_virt_to_bus(scb, sg); 3633 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 3, 3634 sgptr >> 24); 3635 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 2, 3636 sgptr >> 16); 3637 ahc_outb(ahc, SCB_RESIDUAL_SGPTR + 1, 3638 sgptr >> 8); 3639 ahc_outb(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3640 } 3641 3642 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24); 3643 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16); 3644 ahc_outb(ahc, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8); 3645 ahc_outb(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3646 } 3647 } 3648} 3649 3650 3651/* 3652 * Reinitialize the data pointers for the active transfer 3653 * based on its current residual. 3654 */ 3655static void 3656ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 3657{ 3658 struct scb *scb; 3659 struct ahc_dma_seg *sg; 3660 u_int scb_index; 3661 uint32_t sgptr; 3662 uint32_t resid; 3663 uint32_t dataptr; 3664 3665 scb_index = ahc_inb(ahc, SCB_TAG); 3666 scb = ahc_lookup_scb(ahc, scb_index); 3667 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3668 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3669 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 3670 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3671 3672 sgptr &= SG_PTR_MASK; 3673 sg = ahc_sg_bus_to_virt(scb, sgptr); 3674 3675 /* The residual sg_ptr always points to the next sg */ 3676 sg--; 3677 3678 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 3679 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 3680 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 3681 3682 dataptr = ahc_le32toh(sg->addr) 3683 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK) 3684 - resid; 3685 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 3686 u_int dscommand1; 3687 3688 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 3689 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 3690 ahc_outb(ahc, HADDR, 3691 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 3692 ahc_outb(ahc, DSCOMMAND1, dscommand1); 3693 } 3694 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 3695 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 3696 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 3697 ahc_outb(ahc, HADDR, dataptr); 3698 ahc_outb(ahc, HCNT + 2, resid >> 16); 3699 ahc_outb(ahc, HCNT + 1, resid >> 8); 3700 ahc_outb(ahc, HCNT, resid); 3701 if ((ahc->features & AHC_ULTRA2) == 0) { 3702 ahc_outb(ahc, STCNT + 2, resid >> 16); 3703 ahc_outb(ahc, STCNT + 1, resid >> 8); 3704 ahc_outb(ahc, STCNT, resid); 3705 } 3706} 3707 3708/* 3709 * Handle the effects of issuing a bus device reset message. 3710 */ 3711static void 3712ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3713 cam_status status, char *message, int verbose_level) 3714{ 3715#ifdef AHC_TARGET_MODE 3716 struct ahc_tmode_tstate* tstate; 3717 u_int lun; 3718#endif 3719 int found; 3720 3721 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3722 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3723 status); 3724 3725#ifdef AHC_TARGET_MODE 3726 /* 3727 * Send an immediate notify ccb to all target mord peripheral 3728 * drivers affected by this action. 3729 */ 3730 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3731 if (tstate != NULL) { 3732 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3733 struct ahc_tmode_lstate* lstate; 3734 3735 lstate = tstate->enabled_luns[lun]; 3736 if (lstate == NULL) 3737 continue; 3738 3739 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3740 MSG_BUS_DEV_RESET, /*arg*/0); 3741 ahc_send_lstate_events(ahc, lstate); 3742 } 3743 } 3744#endif 3745 3746 /* 3747 * Go back to async/narrow transfers and renegotiate. 3748 */ 3749 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3750 AHC_TRANS_CUR, /*paused*/TRUE); 3751 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3752 /*period*/0, /*offset*/0, /*ppr_options*/0, 3753 AHC_TRANS_CUR, /*paused*/TRUE); 3754 3755 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3756 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); 3757 3758 if (message != NULL 3759 && (verbose_level <= bootverbose)) 3760 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3761 message, devinfo->channel, devinfo->target, found); 3762} 3763 3764#ifdef AHC_TARGET_MODE 3765static void 3766ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3767 struct scb *scb) 3768{ 3769 3770 /* 3771 * To facilitate adding multiple messages together, 3772 * each routine should increment the index and len 3773 * variables instead of setting them explicitly. 3774 */ 3775 ahc->msgout_index = 0; 3776 ahc->msgout_len = 0; 3777 3778 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3779 ahc_build_transfer_msg(ahc, devinfo); 3780 else 3781 panic("ahc_intr: AWAITING target message with no message"); 3782 3783 ahc->msgout_index = 0; 3784 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3785} 3786#endif 3787/**************************** Initialization **********************************/ 3788/* 3789 * Allocate a controller structure for a new device 3790 * and perform initial initializion. 3791 */ 3792struct ahc_softc * 3793ahc_alloc(void *platform_arg, char *name) 3794{ 3795 struct ahc_softc *ahc; 3796 int i; 3797 3798#ifndef __FreeBSD__ 3799 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT); 3800 if (!ahc) { 3801 printf("aic7xxx: cannot malloc softc!\n"); 3802 free(name, M_DEVBUF); 3803 return NULL; 3804 } 3805#else 3806 ahc = device_get_softc((device_t)platform_arg); 3807#endif 3808 memset(ahc, 0, sizeof(*ahc)); 3809 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 3810 M_DEVBUF, M_NOWAIT); 3811 if (ahc->seep_config == NULL) { 3812#ifndef __FreeBSD__ 3813 free(ahc, M_DEVBUF); 3814#endif 3815 free(name, M_DEVBUF); 3816 return (NULL); 3817 } 3818 LIST_INIT(&ahc->pending_scbs); 3819 /* We don't know our unit number until the OSM sets it */ 3820 ahc->name = name; 3821 ahc->unit = -1; 3822 ahc->description = NULL; 3823 ahc->channel = 'A'; 3824 ahc->channel_b = 'B'; 3825 ahc->chip = AHC_NONE; 3826 ahc->features = AHC_FENONE; 3827 ahc->bugs = AHC_BUGNONE; 3828 ahc->flags = AHC_FNONE; 3829 3830 for (i = 0; i < AHC_NUM_TARGETS; i++) 3831 TAILQ_INIT(&ahc->untagged_queues[i]); 3832 if (ahc_platform_alloc(ahc, platform_arg) != 0) { 3833 ahc_free(ahc); 3834 ahc = NULL; 3835 } 3836 return (ahc); 3837} 3838 3839int 3840ahc_softc_init(struct ahc_softc *ahc) 3841{ 3842 3843 /* The IRQMS bit is only valid on VL and EISA chips */ 3844 if ((ahc->chip & AHC_PCI) == 0) 3845 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 3846 else 3847 ahc->unpause = 0; 3848 ahc->pause = ahc->unpause | PAUSE; 3849 /* XXX The shared scb data stuff should be deprecated */ 3850 if (ahc->scb_data == NULL) { 3851 ahc->scb_data = malloc(sizeof(*ahc->scb_data), 3852 M_DEVBUF, M_NOWAIT); 3853 if (ahc->scb_data == NULL) 3854 return (ENOMEM); 3855 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); 3856 } 3857 3858 return (0); 3859} 3860 3861void 3862ahc_softc_insert(struct ahc_softc *ahc) 3863{ 3864 struct ahc_softc *list_ahc; 3865 3866#if AHC_PCI_CONFIG > 0 3867 /* 3868 * Second Function PCI devices need to inherit some 3869 * settings from function 0. 3870 */ 3871 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI 3872 && (ahc->features & AHC_MULTI_FUNC) != 0) { 3873 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3874 ahc_dev_softc_t list_pci; 3875 ahc_dev_softc_t pci; 3876 3877 list_pci = list_ahc->dev_softc; 3878 pci = ahc->dev_softc; 3879 if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci) 3880 && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) { 3881 struct ahc_softc *master; 3882 struct ahc_softc *slave; 3883 3884 if (ahc_get_pci_function(list_pci) == 0) { 3885 master = list_ahc; 3886 slave = ahc; 3887 } else { 3888 master = ahc; 3889 slave = list_ahc; 3890 } 3891 slave->flags &= ~AHC_BIOS_ENABLED; 3892 slave->flags |= 3893 master->flags & AHC_BIOS_ENABLED; 3894 slave->flags &= ~AHC_PRIMARY_CHANNEL; 3895 slave->flags |= 3896 master->flags & AHC_PRIMARY_CHANNEL; 3897 break; 3898 } 3899 } 3900 } 3901#endif 3902 3903 /* 3904 * Insertion sort into our list of softcs. 3905 */ 3906 list_ahc = TAILQ_FIRST(&ahc_tailq); 3907 while (list_ahc != NULL 3908 && ahc_softc_comp(ahc, list_ahc) <= 0) 3909 list_ahc = TAILQ_NEXT(list_ahc, links); 3910 if (list_ahc != NULL) 3911 TAILQ_INSERT_BEFORE(list_ahc, ahc, links); 3912 else 3913 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); 3914 ahc->init_level++; 3915} 3916 3917/* 3918 * Verify that the passed in softc pointer is for a 3919 * controller that is still configured. 3920 */ 3921struct ahc_softc * 3922ahc_find_softc(struct ahc_softc *ahc) 3923{ 3924 struct ahc_softc *list_ahc; 3925 3926 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3927 if (list_ahc == ahc) 3928 return (ahc); 3929 } 3930 return (NULL); 3931} 3932 3933void 3934ahc_set_unit(struct ahc_softc *ahc, int unit) 3935{ 3936 ahc->unit = unit; 3937} 3938 3939void 3940ahc_set_name(struct ahc_softc *ahc, char *name) 3941{ 3942 if (ahc->name != NULL) 3943 free(ahc->name, M_DEVBUF); 3944 ahc->name = name; 3945} 3946 3947void 3948ahc_free(struct ahc_softc *ahc) 3949{ 3950 int i; 3951 3952 switch (ahc->init_level) { 3953 default: 3954 case 5: 3955 ahc_shutdown(ahc); 3956 TAILQ_REMOVE(&ahc_tailq, ahc, links); 3957 /* FALLTHROUGH */ 3958 case 4: 3959 ahc_dmamap_unload(ahc, ahc->shared_data_dmat, 3960 ahc->shared_data_dmamap); 3961 /* FALLTHROUGH */ 3962 case 3: 3963 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo, 3964 ahc->shared_data_dmamap); 3965 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat, 3966 ahc->shared_data_dmamap); 3967 /* FALLTHROUGH */ 3968 case 2: 3969 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat); 3970 case 1: 3971#ifndef __linux__ 3972 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat); 3973#endif 3974 break; 3975 case 0: 3976 break; 3977 } 3978 3979#ifndef __linux__ 3980 ahc_dma_tag_destroy(ahc, ahc->parent_dmat); 3981#endif 3982 ahc_platform_free(ahc); 3983 ahc_fini_scbdata(ahc); 3984 for (i = 0; i < AHC_NUM_TARGETS; i++) { 3985 struct ahc_tmode_tstate *tstate; 3986 3987 tstate = ahc->enabled_targets[i]; 3988 if (tstate != NULL) { 3989#if AHC_TARGET_MODE 3990 int j; 3991 3992 for (j = 0; j < AHC_NUM_LUNS; j++) { 3993 struct ahc_tmode_lstate *lstate; 3994 3995 lstate = tstate->enabled_luns[j]; 3996 if (lstate != NULL) { 3997 xpt_free_path(lstate->path); 3998 free(lstate, M_DEVBUF); 3999 } 4000 } 4001#endif 4002 free(tstate, M_DEVBUF); 4003 } 4004 } 4005#if AHC_TARGET_MODE 4006 if (ahc->black_hole != NULL) { 4007 xpt_free_path(ahc->black_hole->path); 4008 free(ahc->black_hole, M_DEVBUF); 4009 } 4010#endif 4011 if (ahc->name != NULL) 4012 free(ahc->name, M_DEVBUF); 4013 if (ahc->seep_config != NULL) 4014 free(ahc->seep_config, M_DEVBUF); 4015#ifndef __FreeBSD__ 4016 free(ahc, M_DEVBUF); 4017#endif 4018 return; 4019} 4020 4021void 4022ahc_shutdown(void *arg) 4023{ 4024 struct ahc_softc *ahc; 4025 int i; 4026 4027 ahc = (struct ahc_softc *)arg; 4028 4029 /* This will reset most registers to 0, but not all */ 4030 ahc_reset(ahc); 4031 ahc_outb(ahc, SCSISEQ, 0); 4032 ahc_outb(ahc, SXFRCTL0, 0); 4033 ahc_outb(ahc, DSPCISTATUS, 0); 4034 4035 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 4036 ahc_outb(ahc, i, 0); 4037} 4038 4039/* 4040 * Reset the controller and record some information about it 4041 * that is only available just after a reset. 4042 */ 4043int 4044ahc_reset(struct ahc_softc *ahc) 4045{ 4046 u_int sblkctl; 4047 u_int sxfrctl1_a, sxfrctl1_b; 4048 int error; 4049 int wait; 4050 4051 /* 4052 * Preserve the value of the SXFRCTL1 register for all channels. 4053 * It contains settings that affect termination and we don't want 4054 * to disturb the integrity of the bus. 4055 */ 4056 ahc_pause(ahc); 4057 if ((ahc_inb(ahc, HCNTRL) & CHIPRST) != 0) { 4058 /* 4059 * The chip has not been initialized since 4060 * PCI/EISA/VLB bus reset. Don't trust 4061 * "left over BIOS data". 4062 */ 4063 ahc->flags |= AHC_NO_BIOS_INIT; 4064 } 4065 sxfrctl1_b = 0; 4066 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4067 u_int sblkctl; 4068 4069 /* 4070 * Save channel B's settings in case this chip 4071 * is setup for TWIN channel operation. 4072 */ 4073 sblkctl = ahc_inb(ahc, SBLKCTL); 4074 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4075 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4076 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4077 } 4078 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4079 4080 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4081 4082 /* 4083 * Ensure that the reset has finished. We delay 1000us 4084 * prior to reading the register to make sure the chip 4085 * has sufficiently completed its reset to handle register 4086 * accesses. 4087 */ 4088 wait = 1000; 4089 do { 4090 ahc_delay(1000); 4091 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4092 4093 if (wait == 0) { 4094 printf("%s: WARNING - Failed chip reset! " 4095 "Trying to initialize anyway.\n", ahc_name(ahc)); 4096 } 4097 ahc_outb(ahc, HCNTRL, ahc->pause); 4098 4099 /* Determine channel configuration */ 4100 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4101 /* No Twin Channel PCI cards */ 4102 if ((ahc->chip & AHC_PCI) != 0) 4103 sblkctl &= ~SELBUSB; 4104 switch (sblkctl) { 4105 case 0: 4106 /* Single Narrow Channel */ 4107 break; 4108 case 2: 4109 /* Wide Channel */ 4110 ahc->features |= AHC_WIDE; 4111 break; 4112 case 8: 4113 /* Twin Channel */ 4114 ahc->features |= AHC_TWIN; 4115 break; 4116 default: 4117 printf(" Unsupported adapter type. Ignoring\n"); 4118 return(-1); 4119 } 4120 4121 /* 4122 * Reload sxfrctl1. 4123 * 4124 * We must always initialize STPWEN to 1 before we 4125 * restore the saved values. STPWEN is initialized 4126 * to a tri-state condition which can only be cleared 4127 * by turning it on. 4128 */ 4129 if ((ahc->features & AHC_TWIN) != 0) { 4130 u_int sblkctl; 4131 4132 sblkctl = ahc_inb(ahc, SBLKCTL); 4133 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4134 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4135 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4136 } 4137 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4138 4139 error = 0; 4140 if (ahc->init_level > 0) 4141 /* 4142 * If a recovery action has forced a chip reset, 4143 * re-initialize the chip to our liking. 4144 */ 4145 error = ahc->bus_chip_init(ahc); 4146#ifdef AHC_DUMP_SEQ 4147 else 4148 ahc_dumpseq(ahc); 4149#endif 4150 4151 return (error); 4152} 4153 4154/* 4155 * Determine the number of SCBs available on the controller 4156 */ 4157int 4158ahc_probe_scbs(struct ahc_softc *ahc) { 4159 int i; 4160 4161 for (i = 0; i < AHC_SCB_MAX; i++) { 4162 4163 ahc_outb(ahc, SCBPTR, i); 4164 ahc_outb(ahc, SCB_BASE, i); 4165 if (ahc_inb(ahc, SCB_BASE) != i) 4166 break; 4167 ahc_outb(ahc, SCBPTR, 0); 4168 if (ahc_inb(ahc, SCB_BASE) != 0) 4169 break; 4170 } 4171 return (i); 4172} 4173 4174static void 4175ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4176{ 4177 bus_addr_t *baddr; 4178 4179 baddr = (bus_addr_t *)arg; 4180 *baddr = segs->ds_addr; 4181} 4182 4183static void 4184ahc_build_free_scb_list(struct ahc_softc *ahc) 4185{ 4186 int scbsize; 4187 int i; 4188 4189 scbsize = 32; 4190 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4191 scbsize = 64; 4192 4193 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4194 int j; 4195 4196 ahc_outb(ahc, SCBPTR, i); 4197 4198 /* 4199 * Touch all SCB bytes to avoid parity errors 4200 * should one of our debugging routines read 4201 * an otherwise uninitiatlized byte. 4202 */ 4203 for (j = 0; j < scbsize; j++) 4204 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4205 4206 /* Clear the control byte. */ 4207 ahc_outb(ahc, SCB_CONTROL, 0); 4208 4209 /* Set the next pointer */ 4210 if ((ahc->flags & AHC_PAGESCBS) != 0) 4211 ahc_outb(ahc, SCB_NEXT, i+1); 4212 else 4213 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4214 4215 /* Make the tag number, SCSIID, and lun invalid */ 4216 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4217 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4218 ahc_outb(ahc, SCB_LUN, 0xFF); 4219 } 4220 4221 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4222 /* SCB 0 heads the free list. */ 4223 ahc_outb(ahc, FREE_SCBH, 0); 4224 } else { 4225 /* No free list. */ 4226 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4227 } 4228 4229 /* Make sure that the last SCB terminates the free list */ 4230 ahc_outb(ahc, SCBPTR, i-1); 4231 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4232} 4233 4234static int 4235ahc_init_scbdata(struct ahc_softc *ahc) 4236{ 4237 struct scb_data *scb_data; 4238 4239 scb_data = ahc->scb_data; 4240 SLIST_INIT(&scb_data->free_scbs); 4241 SLIST_INIT(&scb_data->sg_maps); 4242 4243 /* Allocate SCB resources */ 4244 scb_data->scbarray = 4245 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, 4246 M_DEVBUF, M_NOWAIT); 4247 if (scb_data->scbarray == NULL) 4248 return (ENOMEM); 4249 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC); 4250 4251 /* Determine the number of hardware SCBs and initialize them */ 4252 4253 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4254 if (ahc->scb_data->maxhscbs == 0) { 4255 printf("%s: No SCB space found\n", ahc_name(ahc)); 4256 return (ENXIO); 4257 } 4258 4259 /* 4260 * Create our DMA tags. These tags define the kinds of device 4261 * accessible memory allocations and memory mappings we will 4262 * need to perform during normal operation. 4263 * 4264 * Unless we need to further restrict the allocation, we rely 4265 * on the restrictions of the parent dmat, hence the common 4266 * use of MAXADDR and MAXSIZE. 4267 */ 4268 4269 /* DMA tag for our hardware scb structures */ 4270 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4271 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4272 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4273 /*highaddr*/BUS_SPACE_MAXADDR, 4274 /*filter*/NULL, /*filterarg*/NULL, 4275 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4276 /*nsegments*/1, 4277 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4278 /*flags*/0, &scb_data->hscb_dmat) != 0) { 4279 goto error_exit; 4280 } 4281 4282 scb_data->init_level++; 4283 4284 /* Allocation for our hscbs */ 4285 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat, 4286 (void **)&scb_data->hscbs, 4287 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) { 4288 goto error_exit; 4289 } 4290 4291 scb_data->init_level++; 4292 4293 /* And permanently map them */ 4294 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap, 4295 scb_data->hscbs, 4296 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4297 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0); 4298 4299 scb_data->init_level++; 4300 4301 /* DMA tag for our sense buffers */ 4302 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4303 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4304 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4305 /*highaddr*/BUS_SPACE_MAXADDR, 4306 /*filter*/NULL, /*filterarg*/NULL, 4307 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4308 /*nsegments*/1, 4309 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4310 /*flags*/0, &scb_data->sense_dmat) != 0) { 4311 goto error_exit; 4312 } 4313 4314 scb_data->init_level++; 4315 4316 /* Allocate them */ 4317 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat, 4318 (void **)&scb_data->sense, 4319 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) { 4320 goto error_exit; 4321 } 4322 4323 scb_data->init_level++; 4324 4325 /* And permanently map them */ 4326 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap, 4327 scb_data->sense, 4328 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4329 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0); 4330 4331 scb_data->init_level++; 4332 4333 /* DMA tag for our S/G structures. We allocate in page sized chunks */ 4334 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8, 4335 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4336 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4337 /*highaddr*/BUS_SPACE_MAXADDR, 4338 /*filter*/NULL, /*filterarg*/NULL, 4339 PAGE_SIZE, /*nsegments*/1, 4340 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4341 /*flags*/0, &scb_data->sg_dmat) != 0) { 4342 goto error_exit; 4343 } 4344 4345 scb_data->init_level++; 4346 4347 /* Perform initial CCB allocation */ 4348 memset(scb_data->hscbs, 0, 4349 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4350 ahc_alloc_scbs(ahc); 4351 4352 if (scb_data->numscbs == 0) { 4353 printf("%s: ahc_init_scbdata - " 4354 "Unable to allocate initial scbs\n", 4355 ahc_name(ahc)); 4356 goto error_exit; 4357 } 4358 4359 /* 4360 * Reserve the next queued SCB. 4361 */ 4362 ahc->next_queued_scb = ahc_get_scb(ahc); 4363 4364 /* 4365 * Note that we were successfull 4366 */ 4367 return (0); 4368 4369error_exit: 4370 4371 return (ENOMEM); 4372} 4373 4374static void 4375ahc_fini_scbdata(struct ahc_softc *ahc) 4376{ 4377 struct scb_data *scb_data; 4378 4379 scb_data = ahc->scb_data; 4380 if (scb_data == NULL) 4381 return; 4382 4383 switch (scb_data->init_level) { 4384 default: 4385 case 7: 4386 { 4387 struct sg_map_node *sg_map; 4388 4389 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4390 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4391 ahc_dmamap_unload(ahc, scb_data->sg_dmat, 4392 sg_map->sg_dmamap); 4393 ahc_dmamem_free(ahc, scb_data->sg_dmat, 4394 sg_map->sg_vaddr, 4395 sg_map->sg_dmamap); 4396 free(sg_map, M_DEVBUF); 4397 } 4398 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat); 4399 } 4400 case 6: 4401 ahc_dmamap_unload(ahc, scb_data->sense_dmat, 4402 scb_data->sense_dmamap); 4403 case 5: 4404 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense, 4405 scb_data->sense_dmamap); 4406 ahc_dmamap_destroy(ahc, scb_data->sense_dmat, 4407 scb_data->sense_dmamap); 4408 case 4: 4409 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat); 4410 case 3: 4411 ahc_dmamap_unload(ahc, scb_data->hscb_dmat, 4412 scb_data->hscb_dmamap); 4413 case 2: 4414 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs, 4415 scb_data->hscb_dmamap); 4416 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat, 4417 scb_data->hscb_dmamap); 4418 case 1: 4419 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat); 4420 break; 4421 case 0: 4422 break; 4423 } 4424 if (scb_data->scbarray != NULL) 4425 free(scb_data->scbarray, M_DEVBUF); 4426} 4427 4428void 4429ahc_alloc_scbs(struct ahc_softc *ahc) 4430{ 4431 struct scb_data *scb_data; 4432 struct scb *next_scb; 4433 struct sg_map_node *sg_map; 4434 bus_addr_t physaddr; 4435 struct ahc_dma_seg *segs; 4436 int newcount; 4437 int i; 4438 4439 scb_data = ahc->scb_data; 4440 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4441 /* Can't allocate any more */ 4442 return; 4443 4444 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4445 4446 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4447 4448 if (sg_map == NULL) 4449 return; 4450 4451 /* Allocate S/G space for the next batch of SCBS */ 4452 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat, 4453 (void **)&sg_map->sg_vaddr, 4454 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { 4455 free(sg_map, M_DEVBUF); 4456 return; 4457 } 4458 4459 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4460 4461 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap, 4462 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb, 4463 &sg_map->sg_physaddr, /*flags*/0); 4464 4465 segs = sg_map->sg_vaddr; 4466 physaddr = sg_map->sg_physaddr; 4467 4468 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4469 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4470 for (i = 0; i < newcount; i++) { 4471 struct scb_platform_data *pdata; 4472#ifndef __linux__ 4473 int error; 4474#endif 4475 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 4476 M_DEVBUF, M_NOWAIT); 4477 if (pdata == NULL) 4478 break; 4479 next_scb->platform_data = pdata; 4480 next_scb->sg_map = sg_map; 4481 next_scb->sg_list = segs; 4482 /* 4483 * The sequencer always starts with the second entry. 4484 * The first entry is embedded in the scb. 4485 */ 4486 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4487 next_scb->ahc_softc = ahc; 4488 next_scb->flags = SCB_FREE; 4489#ifndef __linux__ 4490 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0, 4491 &next_scb->dmamap); 4492 if (error != 0) 4493 break; 4494#endif 4495 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4496 next_scb->hscb->tag = ahc->scb_data->numscbs; 4497 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4498 next_scb, links.sle); 4499 segs += AHC_NSEG; 4500 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4501 next_scb++; 4502 ahc->scb_data->numscbs++; 4503 } 4504} 4505 4506void 4507ahc_controller_info(struct ahc_softc *ahc, char *buf) 4508{ 4509 int len; 4510 4511 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4512 buf += len; 4513 if ((ahc->features & AHC_TWIN) != 0) 4514 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " 4515 "B SCSI Id=%d, primary %c, ", 4516 ahc->our_id, ahc->our_id_b, 4517 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4518 else { 4519 const char *speed; 4520 const char *type; 4521 4522 speed = ""; 4523 if ((ahc->features & AHC_ULTRA) != 0) { 4524 speed = "Ultra "; 4525 } else if ((ahc->features & AHC_DT) != 0) { 4526 speed = "Ultra160 "; 4527 } else if ((ahc->features & AHC_ULTRA2) != 0) { 4528 speed = "Ultra2 "; 4529 } 4530 if ((ahc->features & AHC_WIDE) != 0) { 4531 type = "Wide"; 4532 } else { 4533 type = "Single"; 4534 } 4535 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ", 4536 speed, type, ahc->channel, ahc->our_id); 4537 } 4538 buf += len; 4539 4540 if ((ahc->flags & AHC_PAGESCBS) != 0) 4541 sprintf(buf, "%d/%d SCBs", 4542 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 4543 else 4544 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); 4545} 4546 4547int 4548ahc_chip_init(struct ahc_softc *ahc) 4549{ 4550 int term; 4551 int error; 4552 u_int i; 4553 u_int scsi_conf; 4554 u_int scsiseq_template; 4555 uint32_t physaddr; 4556 4557 ahc_outb(ahc, SEQ_FLAGS, 0); 4558 ahc_outb(ahc, SEQ_FLAGS2, 0); 4559 4560 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4561 if (ahc->features & AHC_TWIN) { 4562 4563 /* 4564 * Setup Channel B first. 4565 */ 4566 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4567 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4568 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4569 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4570 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4571 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4572 if ((ahc->features & AHC_ULTRA2) != 0) 4573 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4574 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4575 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4576 4577 /* Select Channel A */ 4578 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4579 } 4580 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4581 if ((ahc->features & AHC_ULTRA2) != 0) 4582 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4583 else 4584 ahc_outb(ahc, SCSIID, ahc->our_id); 4585 scsi_conf = ahc_inb(ahc, SCSICONF); 4586 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4587 |term|ahc->seltime 4588 |ENSTIMER|ACTNEGEN); 4589 if ((ahc->features & AHC_ULTRA2) != 0) 4590 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4591 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4592 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4593 4594 /* There are no untagged SCBs active yet. */ 4595 for (i = 0; i < 16; i++) { 4596 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4597 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4598 int lun; 4599 4600 /* 4601 * The SCB based BTT allows an entry per 4602 * target and lun pair. 4603 */ 4604 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4605 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4606 } 4607 } 4608 4609 /* All of our queues are empty */ 4610 for (i = 0; i < 256; i++) 4611 ahc->qoutfifo[i] = SCB_LIST_NULL; 4612 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 4613 4614 for (i = 0; i < 256; i++) 4615 ahc->qinfifo[i] = SCB_LIST_NULL; 4616 4617 if ((ahc->features & AHC_MULTI_TID) != 0) { 4618 ahc_outb(ahc, TARGID, 0); 4619 ahc_outb(ahc, TARGID + 1, 0); 4620 } 4621 4622 /* 4623 * Tell the sequencer where it can find our arrays in memory. 4624 */ 4625 physaddr = ahc->scb_data->hscb_busaddr; 4626 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4627 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4628 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4629 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4630 4631 physaddr = ahc->shared_data_busaddr; 4632 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4633 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4634 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4635 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4636 4637 /* 4638 * Initialize the group code to command length table. 4639 * This overrides the values in TARG_SCSIRATE, so only 4640 * setup the table after we have processed that information. 4641 */ 4642 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4643 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4644 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4645 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4646 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4647 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4648 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4649 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4650 4651 if ((ahc->features & AHC_HS_MAILBOX) != 0) 4652 ahc_outb(ahc, HS_MAILBOX, 0); 4653 4654 /* Tell the sequencer of our initial queue positions */ 4655 if ((ahc->features & AHC_TARGETMODE) != 0) { 4656 ahc->tqinfifonext = 1; 4657 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4658 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4659 } 4660 ahc->qinfifonext = 0; 4661 ahc->qoutfifonext = 0; 4662 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4663 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4664 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4665 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext); 4666 ahc_outb(ahc, SDSCB_QOFF, 0); 4667 } else { 4668 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4669 ahc_outb(ahc, QINPOS, ahc->qinfifonext); 4670 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext); 4671 } 4672 4673 /* We don't have any waiting selections */ 4674 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4675 4676 /* Our disconnection list is empty too */ 4677 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4678 4679 /* Message out buffer starts empty */ 4680 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4681 4682 /* 4683 * Setup the allowed SCSI Sequences based on operational mode. 4684 * If we are a target, we'll enalbe select in operations once 4685 * we've had a lun enabled. 4686 */ 4687 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4688 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4689 scsiseq_template |= ENRSELI; 4690 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4691 4692 /* Initialize our list of free SCBs. */ 4693 ahc_build_free_scb_list(ahc); 4694 4695 /* 4696 * Tell the sequencer which SCB will be the next one it receives. 4697 */ 4698 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4699 4700 /* 4701 * Load the Sequencer program and Enable the adapter 4702 * in "fast" mode. 4703 */ 4704 if (bootverbose) 4705 printf("%s: Downloading Sequencer Program...", 4706 ahc_name(ahc)); 4707 4708 error = ahc_loadseq(ahc); 4709 if (error != 0) 4710 return (error); 4711 4712 if ((ahc->features & AHC_ULTRA2) != 0) { 4713 int wait; 4714 4715 /* 4716 * Wait for up to 500ms for our transceivers 4717 * to settle. If the adapter does not have 4718 * a cable attached, the transceivers may 4719 * never settle, so don't complain if we 4720 * fail here. 4721 */ 4722 ahc_pause(ahc); 4723 for (wait = 5000; 4724 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4725 wait--) 4726 ahc_delay(100); 4727 ahc_unpause(ahc); 4728 } 4729 4730 return (0); 4731} 4732 4733/* 4734 * Start the board, ready for normal operation 4735 */ 4736int 4737ahc_init(struct ahc_softc *ahc) 4738{ 4739 int max_targ; 4740 u_int i; 4741 u_int scsi_conf; 4742 u_int ultraenb; 4743 u_int discenable; 4744 u_int tagenable; 4745 size_t driver_data_size; 4746 4747#ifdef AHC_DEBUG 4748 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 4749 ahc->flags |= AHC_SEQUENCER_DEBUG; 4750#endif 4751 4752#ifdef AHC_PRINT_SRAM 4753 printf("Scratch Ram:"); 4754 for (i = 0x20; i < 0x5f; i++) { 4755 if (((i % 8) == 0) && (i != 0)) { 4756 printf ("\n "); 4757 } 4758 printf (" 0x%x", ahc_inb(ahc, i)); 4759 } 4760 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4761 for (i = 0x70; i < 0x7f; i++) { 4762 if (((i % 8) == 0) && (i != 0)) { 4763 printf ("\n "); 4764 } 4765 printf (" 0x%x", ahc_inb(ahc, i)); 4766 } 4767 } 4768 printf ("\n"); 4769 /* 4770 * Reading uninitialized scratch ram may 4771 * generate parity errors. 4772 */ 4773 ahc_outb(ahc, CLRINT, CLRPARERR); 4774 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 4775#endif 4776 max_targ = 15; 4777 4778 /* 4779 * Assume we have a board at this stage and it has been reset. 4780 */ 4781 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4782 ahc->our_id = ahc->our_id_b = 7; 4783 4784 /* 4785 * Default to allowing initiator operations. 4786 */ 4787 ahc->flags |= AHC_INITIATORROLE; 4788 4789 /* 4790 * Only allow target mode features if this unit has them enabled. 4791 */ 4792 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4793 ahc->features &= ~AHC_TARGETMODE; 4794 4795#ifndef __linux__ 4796 /* DMA tag for mapping buffers into device visible space. */ 4797 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4798 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4799 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING 4800 ? (bus_addr_t)0x7FFFFFFFFFULL 4801 : BUS_SPACE_MAXADDR_32BIT, 4802 /*highaddr*/BUS_SPACE_MAXADDR, 4803 /*filter*/NULL, /*filterarg*/NULL, 4804 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE, 4805 /*nsegments*/AHC_NSEG, 4806 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 4807 /*flags*/BUS_DMA_ALLOCNOW, 4808 &ahc->buffer_dmat) != 0) { 4809 return (ENOMEM); 4810 } 4811#endif 4812 4813 ahc->init_level++; 4814 4815 /* 4816 * DMA tag for our command fifos and other data in system memory 4817 * the card's sequencer must be able to access. For initiator 4818 * roles, we need to allocate space for the qinfifo and qoutfifo. 4819 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4820 * When providing for the target mode role, we must additionally 4821 * provide space for the incoming target command fifo and an extra 4822 * byte to deal with a dma bug in some chip versions. 4823 */ 4824 driver_data_size = 2 * 256 * sizeof(uint8_t); 4825 if ((ahc->features & AHC_TARGETMODE) != 0) 4826 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4827 + /*DMA WideOdd Bug Buffer*/1; 4828 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4829 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4830 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4831 /*highaddr*/BUS_SPACE_MAXADDR, 4832 /*filter*/NULL, /*filterarg*/NULL, 4833 driver_data_size, 4834 /*nsegments*/1, 4835 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4836 /*flags*/0, &ahc->shared_data_dmat) != 0) { 4837 return (ENOMEM); 4838 } 4839 4840 ahc->init_level++; 4841 4842 /* Allocation of driver data */ 4843 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat, 4844 (void **)&ahc->qoutfifo, 4845 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) { 4846 return (ENOMEM); 4847 } 4848 4849 ahc->init_level++; 4850 4851 /* And permanently map it in */ 4852 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, 4853 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb, 4854 &ahc->shared_data_busaddr, /*flags*/0); 4855 4856 if ((ahc->features & AHC_TARGETMODE) != 0) { 4857 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4858 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4859 ahc->dma_bug_buf = ahc->shared_data_busaddr 4860 + driver_data_size - 1; 4861 /* All target command blocks start out invalid. */ 4862 for (i = 0; i < AHC_TMODE_CMDS; i++) 4863 ahc->targetcmds[i].cmd_valid = 0; 4864 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 4865 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4866 } 4867 ahc->qinfifo = &ahc->qoutfifo[256]; 4868 4869 ahc->init_level++; 4870 4871 /* Allocate SCB data now that buffer_dmat is initialized */ 4872 if (ahc->scb_data->maxhscbs == 0) 4873 if (ahc_init_scbdata(ahc) != 0) 4874 return (ENOMEM); 4875 4876 /* 4877 * Allocate a tstate to house information for our 4878 * initiator presence on the bus as well as the user 4879 * data for any target mode initiator. 4880 */ 4881 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4882 printf("%s: unable to allocate ahc_tmode_tstate. " 4883 "Failing attach\n", ahc_name(ahc)); 4884 return (ENOMEM); 4885 } 4886 4887 if ((ahc->features & AHC_TWIN) != 0) { 4888 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4889 printf("%s: unable to allocate ahc_tmode_tstate. " 4890 "Failing attach\n", ahc_name(ahc)); 4891 return (ENOMEM); 4892 } 4893 } 4894 4895 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 4896 ahc->flags |= AHC_PAGESCBS; 4897 } else { 4898 ahc->flags &= ~AHC_PAGESCBS; 4899 } 4900 4901#ifdef AHC_DEBUG 4902 if (ahc_debug & AHC_SHOW_MISC) { 4903 printf("%s: hardware scb %u bytes; kernel scb %u bytes; " 4904 "ahc_dma %u bytes\n", 4905 ahc_name(ahc), 4906 (u_int)sizeof(struct hardware_scb), 4907 (u_int)sizeof(struct scb), 4908 (u_int)sizeof(struct ahc_dma_seg)); 4909 } 4910#endif /* AHC_DEBUG */ 4911 4912 /* 4913 * Look at the information that board initialization or 4914 * the board bios has left us. 4915 */ 4916 if (ahc->features & AHC_TWIN) { 4917 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4918 if ((scsi_conf & RESET_SCSI) != 0 4919 && (ahc->flags & AHC_INITIATORROLE) != 0) 4920 ahc->flags |= AHC_RESET_BUS_B; 4921 } 4922 4923 scsi_conf = ahc_inb(ahc, SCSICONF); 4924 if ((scsi_conf & RESET_SCSI) != 0 4925 && (ahc->flags & AHC_INITIATORROLE) != 0) 4926 ahc->flags |= AHC_RESET_BUS_A; 4927 4928 ultraenb = 0; 4929 tagenable = ALL_TARGETS_MASK; 4930 4931 /* Grab the disconnection disable table and invert it for our needs */ 4932 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 4933 printf("%s: Host Adapter Bios disabled. Using default SCSI " 4934 "device parameters\n", ahc_name(ahc)); 4935 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 4936 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 4937 discenable = ALL_TARGETS_MASK; 4938 if ((ahc->features & AHC_ULTRA) != 0) 4939 ultraenb = ALL_TARGETS_MASK; 4940 } else { 4941 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 4942 | ahc_inb(ahc, DISC_DSB)); 4943 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 4944 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 4945 | ahc_inb(ahc, ULTRA_ENB); 4946 } 4947 4948 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 4949 max_targ = 7; 4950 4951 for (i = 0; i <= max_targ; i++) { 4952 struct ahc_initiator_tinfo *tinfo; 4953 struct ahc_tmode_tstate *tstate; 4954 u_int our_id; 4955 u_int target_id; 4956 char channel; 4957 4958 channel = 'A'; 4959 our_id = ahc->our_id; 4960 target_id = i; 4961 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 4962 channel = 'B'; 4963 our_id = ahc->our_id_b; 4964 target_id = i % 8; 4965 } 4966 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 4967 target_id, &tstate); 4968 /* Default to async narrow across the board */ 4969 memset(tinfo, 0, sizeof(*tinfo)); 4970 if (ahc->flags & AHC_USEDEFAULTS) { 4971 if ((ahc->features & AHC_WIDE) != 0) 4972 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4973 4974 /* 4975 * These will be truncated when we determine the 4976 * connection type we have with the target. 4977 */ 4978 tinfo->user.period = ahc_syncrates->period; 4979 tinfo->user.offset = MAX_OFFSET; 4980 } else { 4981 u_int scsirate; 4982 uint16_t mask; 4983 4984 /* Take the settings leftover in scratch RAM. */ 4985 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 4986 mask = (0x01 << i); 4987 if ((ahc->features & AHC_ULTRA2) != 0) { 4988 u_int offset; 4989 u_int maxsync; 4990 4991 if ((scsirate & SOFS) == 0x0F) { 4992 /* 4993 * Haven't negotiated yet, 4994 * so the format is different. 4995 */ 4996 scsirate = (scsirate & SXFR) >> 4 4997 | (ultraenb & mask) 4998 ? 0x08 : 0x0 4999 | (scsirate & WIDEXFER); 5000 offset = MAX_OFFSET_ULTRA2; 5001 } else 5002 offset = ahc_inb(ahc, TARG_OFFSET + i); 5003 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 5004 /* Set to the lowest sync rate, 5MHz */ 5005 scsirate |= 0x1c; 5006 maxsync = AHC_SYNCRATE_ULTRA2; 5007 if ((ahc->features & AHC_DT) != 0) 5008 maxsync = AHC_SYNCRATE_DT; 5009 tinfo->user.period = 5010 ahc_find_period(ahc, scsirate, maxsync); 5011 if (offset == 0) 5012 tinfo->user.period = 0; 5013 else 5014 tinfo->user.offset = MAX_OFFSET; 5015 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 5016 && (ahc->features & AHC_DT) != 0) 5017 tinfo->user.ppr_options = 5018 MSG_EXT_PPR_DT_REQ; 5019 } else if ((scsirate & SOFS) != 0) { 5020 if ((scsirate & SXFR) == 0x40 5021 && (ultraenb & mask) != 0) { 5022 /* Treat 10MHz as a non-ultra speed */ 5023 scsirate &= ~SXFR; 5024 ultraenb &= ~mask; 5025 } 5026 tinfo->user.period = 5027 ahc_find_period(ahc, scsirate, 5028 (ultraenb & mask) 5029 ? AHC_SYNCRATE_ULTRA 5030 : AHC_SYNCRATE_FAST); 5031 if (tinfo->user.period != 0) 5032 tinfo->user.offset = MAX_OFFSET; 5033 } 5034 if (tinfo->user.period == 0) 5035 tinfo->user.offset = 0; 5036 if ((scsirate & WIDEXFER) != 0 5037 && (ahc->features & AHC_WIDE) != 0) 5038 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 5039 tinfo->user.protocol_version = 4; 5040 if ((ahc->features & AHC_DT) != 0) 5041 tinfo->user.transport_version = 3; 5042 else 5043 tinfo->user.transport_version = 2; 5044 tinfo->goal.protocol_version = 2; 5045 tinfo->goal.transport_version = 2; 5046 tinfo->curr.protocol_version = 2; 5047 tinfo->curr.transport_version = 2; 5048 } 5049 tstate->ultraenb = 0; 5050 } 5051 ahc->user_discenable = discenable; 5052 ahc->user_tagenable = tagenable; 5053 5054 return (ahc->bus_chip_init(ahc)); 5055} 5056 5057void 5058ahc_intr_enable(struct ahc_softc *ahc, int enable) 5059{ 5060 u_int hcntrl; 5061 5062 hcntrl = ahc_inb(ahc, HCNTRL); 5063 hcntrl &= ~INTEN; 5064 ahc->pause &= ~INTEN; 5065 ahc->unpause &= ~INTEN; 5066 if (enable) { 5067 hcntrl |= INTEN; 5068 ahc->pause |= INTEN; 5069 ahc->unpause |= INTEN; 5070 } 5071 ahc_outb(ahc, HCNTRL, hcntrl); 5072} 5073 5074/* 5075 * Ensure that the card is paused in a location 5076 * outside of all critical sections and that all 5077 * pending work is completed prior to returning. 5078 * This routine should only be called from outside 5079 * an interrupt context. 5080 */ 5081void 5082ahc_pause_and_flushwork(struct ahc_softc *ahc) 5083{ 5084 int intstat; 5085 int maxloops; 5086 int paused; 5087 5088 maxloops = 1000; 5089 ahc->flags |= AHC_ALL_INTERRUPTS; 5090 paused = FALSE; 5091 do { 5092 if (paused) 5093 ahc_unpause(ahc); 5094 ahc_intr(ahc); 5095 ahc_pause(ahc); 5096 paused = TRUE; 5097 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO); 5098 ahc_clear_critical_section(ahc); 5099 intstat = ahc_inb(ahc, INTSTAT); 5100 } while (--maxloops 5101 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0) 5102 && ((intstat & INT_PEND) != 0 5103 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0)); 5104 if (maxloops == 0) { 5105 printf("Infinite interrupt loop, INTSTAT = %x", 5106 ahc_inb(ahc, INTSTAT)); 5107 } 5108 ahc_platform_flushwork(ahc); 5109 ahc->flags &= ~AHC_ALL_INTERRUPTS; 5110} 5111 5112int 5113ahc_suspend(struct ahc_softc *ahc) 5114{ 5115 5116 ahc_pause_and_flushwork(ahc); 5117 5118 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 5119 ahc_unpause(ahc); 5120 return (EBUSY); 5121 } 5122 5123#if AHC_TARGET_MODE 5124 /* 5125 * XXX What about ATIOs that have not yet been serviced? 5126 * Perhaps we should just refuse to be suspended if we 5127 * are acting in a target role. 5128 */ 5129 if (ahc->pending_device != NULL) { 5130 ahc_unpause(ahc); 5131 return (EBUSY); 5132 } 5133#endif 5134 ahc_shutdown(ahc); 5135 return (0); 5136} 5137 5138int 5139ahc_resume(struct ahc_softc *ahc) 5140{ 5141 5142 ahc_reset(ahc); 5143 return (0); 5144} 5145 5146/************************** Busy Target Table *********************************/ 5147/* 5148 * Return the untagged transaction id for a given target/channel lun. 5149 * Optionally, clear the entry. 5150 */ 5151u_int 5152ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5153{ 5154 u_int scbid; 5155 u_int target_offset; 5156 5157 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5158 u_int saved_scbptr; 5159 5160 saved_scbptr = ahc_inb(ahc, SCBPTR); 5161 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5162 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5163 ahc_outb(ahc, SCBPTR, saved_scbptr); 5164 } else { 5165 target_offset = TCL_TARGET_OFFSET(tcl); 5166 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5167 } 5168 5169 return (scbid); 5170} 5171 5172void 5173ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5174{ 5175 u_int target_offset; 5176 5177 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5178 u_int saved_scbptr; 5179 5180 saved_scbptr = ahc_inb(ahc, SCBPTR); 5181 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5182 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5183 ahc_outb(ahc, SCBPTR, saved_scbptr); 5184 } else { 5185 target_offset = TCL_TARGET_OFFSET(tcl); 5186 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5187 } 5188} 5189 5190void 5191ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5192{ 5193 u_int target_offset; 5194 5195 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5196 u_int saved_scbptr; 5197 5198 saved_scbptr = ahc_inb(ahc, SCBPTR); 5199 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5200 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5201 ahc_outb(ahc, SCBPTR, saved_scbptr); 5202 } else { 5203 target_offset = TCL_TARGET_OFFSET(tcl); 5204 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5205 } 5206} 5207 5208/************************** SCB and SCB queue management **********************/ 5209int 5210ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5211 char channel, int lun, u_int tag, role_t role) 5212{ 5213 int targ = SCB_GET_TARGET(ahc, scb); 5214 char chan = SCB_GET_CHANNEL(ahc, scb); 5215 int slun = SCB_GET_LUN(scb); 5216 int match; 5217 5218 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5219 if (match != 0) 5220 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5221 if (match != 0) 5222 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5223 if (match != 0) { 5224#if AHC_TARGET_MODE 5225 int group; 5226 5227 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5228 if (role == ROLE_INITIATOR) { 5229 match = (group != XPT_FC_GROUP_TMODE) 5230 && ((tag == scb->hscb->tag) 5231 || (tag == SCB_LIST_NULL)); 5232 } else if (role == ROLE_TARGET) { 5233 match = (group == XPT_FC_GROUP_TMODE) 5234 && ((tag == scb->io_ctx->csio.tag_id) 5235 || (tag == SCB_LIST_NULL)); 5236 } 5237#else /* !AHC_TARGET_MODE */ 5238 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5239#endif /* AHC_TARGET_MODE */ 5240 } 5241 5242 return match; 5243} 5244 5245void 5246ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5247{ 5248 int target; 5249 char channel; 5250 int lun; 5251 5252 target = SCB_GET_TARGET(ahc, scb); 5253 lun = SCB_GET_LUN(scb); 5254 channel = SCB_GET_CHANNEL(ahc, scb); 5255 5256 ahc_search_qinfifo(ahc, target, channel, lun, 5257 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5258 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5259 5260 ahc_platform_freeze_devq(ahc, scb); 5261} 5262 5263void 5264ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5265{ 5266 struct scb *prev_scb; 5267 5268 prev_scb = NULL; 5269 if (ahc_qinfifo_count(ahc) != 0) { 5270 u_int prev_tag; 5271 uint8_t prev_pos; 5272 5273 prev_pos = ahc->qinfifonext - 1; 5274 prev_tag = ahc->qinfifo[prev_pos]; 5275 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5276 } 5277 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5278 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5279 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5280 } else { 5281 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5282 } 5283} 5284 5285static void 5286ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5287 struct scb *scb) 5288{ 5289 if (prev_scb == NULL) { 5290 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5291 } else { 5292 prev_scb->hscb->next = scb->hscb->tag; 5293 ahc_sync_scb(ahc, prev_scb, 5294 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5295 } 5296 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 5297 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5298 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5299} 5300 5301static int 5302ahc_qinfifo_count(struct ahc_softc *ahc) 5303{ 5304 uint8_t qinpos; 5305 uint8_t diff; 5306 5307 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5308 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5309 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5310 } else 5311 qinpos = ahc_inb(ahc, QINPOS); 5312 diff = ahc->qinfifonext - qinpos; 5313 return (diff); 5314} 5315 5316int 5317ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5318 int lun, u_int tag, role_t role, uint32_t status, 5319 ahc_search_action action) 5320{ 5321 struct scb *scb; 5322 struct scb *prev_scb; 5323 uint8_t qinstart; 5324 uint8_t qinpos; 5325 uint8_t qintail; 5326 uint8_t next; 5327 uint8_t prev; 5328 uint8_t curscbptr; 5329 int found; 5330 int have_qregs; 5331 5332 qintail = ahc->qinfifonext; 5333 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5334 if (have_qregs) { 5335 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5336 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5337 } else 5338 qinstart = ahc_inb(ahc, QINPOS); 5339 qinpos = qinstart; 5340 found = 0; 5341 prev_scb = NULL; 5342 5343 if (action == SEARCH_COMPLETE) { 5344 /* 5345 * Don't attempt to run any queued untagged transactions 5346 * until we are done with the abort process. 5347 */ 5348 ahc_freeze_untagged_queues(ahc); 5349 } 5350 5351 /* 5352 * Start with an empty queue. Entries that are not chosen 5353 * for removal will be re-added to the queue as we go. 5354 */ 5355 ahc->qinfifonext = qinpos; 5356 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5357 5358 while (qinpos != qintail) { 5359 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5360 if (scb == NULL) { 5361 printf("qinpos = %d, SCB index = %d\n", 5362 qinpos, ahc->qinfifo[qinpos]); 5363 panic("Loop 1\n"); 5364 } 5365 5366 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5367 /* 5368 * We found an scb that needs to be acted on. 5369 */ 5370 found++; 5371 switch (action) { 5372 case SEARCH_COMPLETE: 5373 { 5374 cam_status ostat; 5375 cam_status cstat; 5376 5377 ostat = ahc_get_transaction_status(scb); 5378 if (ostat == CAM_REQ_INPROG) 5379 ahc_set_transaction_status(scb, status); 5380 cstat = ahc_get_transaction_status(scb); 5381 if (cstat != CAM_REQ_CMP) 5382 ahc_freeze_scb(scb); 5383 if ((scb->flags & SCB_ACTIVE) == 0) 5384 printf("Inactive SCB in qinfifo\n"); 5385 ahc_done(ahc, scb); 5386 5387 /* FALLTHROUGH */ 5388 } 5389 case SEARCH_REMOVE: 5390 break; 5391 case SEARCH_COUNT: 5392 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5393 prev_scb = scb; 5394 break; 5395 } 5396 } else { 5397 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5398 prev_scb = scb; 5399 } 5400 qinpos++; 5401 } 5402 5403 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5404 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5405 } else { 5406 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5407 } 5408 5409 if (action != SEARCH_COUNT 5410 && (found != 0) 5411 && (qinstart != ahc->qinfifonext)) { 5412 /* 5413 * The sequencer may be in the process of dmaing 5414 * down the SCB at the beginning of the queue. 5415 * This could be problematic if either the first, 5416 * or the second SCB is removed from the queue 5417 * (the first SCB includes a pointer to the "next" 5418 * SCB to dma). If we have removed any entries, swap 5419 * the first element in the queue with the next HSCB 5420 * so the sequencer will notice that NEXT_QUEUED_SCB 5421 * has changed during its dma attempt and will retry 5422 * the DMA. 5423 */ 5424 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5425 5426 if (scb == NULL) { 5427 printf("found = %d, qinstart = %d, qinfifionext = %d\n", 5428 found, qinstart, ahc->qinfifonext); 5429 panic("First/Second Qinfifo fixup\n"); 5430 } 5431 /* 5432 * ahc_swap_with_next_hscb forces our next pointer to 5433 * point to the reserved SCB for future commands. Save 5434 * and restore our original next pointer to maintain 5435 * queue integrity. 5436 */ 5437 next = scb->hscb->next; 5438 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5439 ahc_swap_with_next_hscb(ahc, scb); 5440 scb->hscb->next = next; 5441 ahc->qinfifo[qinstart] = scb->hscb->tag; 5442 5443 /* Tell the card about the new head of the qinfifo. */ 5444 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5445 5446 /* Fixup the tail "next" pointer. */ 5447 qintail = ahc->qinfifonext - 1; 5448 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5449 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5450 } 5451 5452 /* 5453 * Search waiting for selection list. 5454 */ 5455 curscbptr = ahc_inb(ahc, SCBPTR); 5456 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5457 prev = SCB_LIST_NULL; 5458 5459 while (next != SCB_LIST_NULL) { 5460 uint8_t scb_index; 5461 5462 ahc_outb(ahc, SCBPTR, next); 5463 scb_index = ahc_inb(ahc, SCB_TAG); 5464 if (scb_index >= ahc->scb_data->numscbs) { 5465 printf("Waiting List inconsistency. " 5466 "SCB index == %d, yet numscbs == %d.", 5467 scb_index, ahc->scb_data->numscbs); 5468 ahc_dump_card_state(ahc); 5469 panic("for safety"); 5470 } 5471 scb = ahc_lookup_scb(ahc, scb_index); 5472 if (scb == NULL) { 5473 printf("scb_index = %d, next = %d\n", 5474 scb_index, next); 5475 panic("Waiting List traversal\n"); 5476 } 5477 if (ahc_match_scb(ahc, scb, target, channel, 5478 lun, SCB_LIST_NULL, role)) { 5479 /* 5480 * We found an scb that needs to be acted on. 5481 */ 5482 found++; 5483 switch (action) { 5484 case SEARCH_COMPLETE: 5485 { 5486 cam_status ostat; 5487 cam_status cstat; 5488 5489 ostat = ahc_get_transaction_status(scb); 5490 if (ostat == CAM_REQ_INPROG) 5491 ahc_set_transaction_status(scb, 5492 status); 5493 cstat = ahc_get_transaction_status(scb); 5494 if (cstat != CAM_REQ_CMP) 5495 ahc_freeze_scb(scb); 5496 if ((scb->flags & SCB_ACTIVE) == 0) 5497 printf("Inactive SCB in Waiting List\n"); 5498 ahc_done(ahc, scb); 5499 /* FALLTHROUGH */ 5500 } 5501 case SEARCH_REMOVE: 5502 next = ahc_rem_wscb(ahc, next, prev); 5503 break; 5504 case SEARCH_COUNT: 5505 prev = next; 5506 next = ahc_inb(ahc, SCB_NEXT); 5507 break; 5508 } 5509 } else { 5510 5511 prev = next; 5512 next = ahc_inb(ahc, SCB_NEXT); 5513 } 5514 } 5515 ahc_outb(ahc, SCBPTR, curscbptr); 5516 5517 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target, 5518 channel, lun, status, action); 5519 5520 if (action == SEARCH_COMPLETE) 5521 ahc_release_untagged_queues(ahc); 5522 return (found); 5523} 5524 5525int 5526ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx, 5527 int target, char channel, int lun, uint32_t status, 5528 ahc_search_action action) 5529{ 5530 struct scb *scb; 5531 int maxtarget; 5532 int found; 5533 int i; 5534 5535 if (action == SEARCH_COMPLETE) { 5536 /* 5537 * Don't attempt to run any queued untagged transactions 5538 * until we are done with the abort process. 5539 */ 5540 ahc_freeze_untagged_queues(ahc); 5541 } 5542 5543 found = 0; 5544 i = 0; 5545 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5546 5547 maxtarget = 16; 5548 if (target != CAM_TARGET_WILDCARD) { 5549 5550 i = target; 5551 if (channel == 'B') 5552 i += 8; 5553 maxtarget = i + 1; 5554 } 5555 } else { 5556 maxtarget = 0; 5557 } 5558 5559 for (; i < maxtarget; i++) { 5560 struct scb_tailq *untagged_q; 5561 struct scb *next_scb; 5562 5563 untagged_q = &(ahc->untagged_queues[i]); 5564 next_scb = TAILQ_FIRST(untagged_q); 5565 while (next_scb != NULL) { 5566 5567 scb = next_scb; 5568 next_scb = TAILQ_NEXT(scb, links.tqe); 5569 5570 /* 5571 * The head of the list may be the currently 5572 * active untagged command for a device. 5573 * We're only searching for commands that 5574 * have not been started. A transaction 5575 * marked active but still in the qinfifo 5576 * is removed by the qinfifo scanning code 5577 * above. 5578 */ 5579 if ((scb->flags & SCB_ACTIVE) != 0) 5580 continue; 5581 5582 if (ahc_match_scb(ahc, scb, target, channel, lun, 5583 SCB_LIST_NULL, ROLE_INITIATOR) == 0 5584 || (ctx != NULL && ctx != scb->io_ctx)) 5585 continue; 5586 5587 /* 5588 * We found an scb that needs to be acted on. 5589 */ 5590 found++; 5591 switch (action) { 5592 case SEARCH_COMPLETE: 5593 { 5594 cam_status ostat; 5595 cam_status cstat; 5596 5597 ostat = ahc_get_transaction_status(scb); 5598 if (ostat == CAM_REQ_INPROG) 5599 ahc_set_transaction_status(scb, status); 5600 cstat = ahc_get_transaction_status(scb); 5601 if (cstat != CAM_REQ_CMP) 5602 ahc_freeze_scb(scb); 5603 if ((scb->flags & SCB_ACTIVE) == 0) 5604 printf("Inactive SCB in untaggedQ\n"); 5605 ahc_done(ahc, scb); 5606 break; 5607 } 5608 case SEARCH_REMOVE: 5609 scb->flags &= ~SCB_UNTAGGEDQ; 5610 TAILQ_REMOVE(untagged_q, scb, links.tqe); 5611 break; 5612 case SEARCH_COUNT: 5613 break; 5614 } 5615 } 5616 } 5617 5618 if (action == SEARCH_COMPLETE) 5619 ahc_release_untagged_queues(ahc); 5620 return (found); 5621} 5622 5623int 5624ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5625 int lun, u_int tag, int stop_on_first, int remove, 5626 int save_state) 5627{ 5628 struct scb *scbp; 5629 u_int next; 5630 u_int prev; 5631 u_int count; 5632 u_int active_scb; 5633 5634 count = 0; 5635 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5636 prev = SCB_LIST_NULL; 5637 5638 if (save_state) { 5639 /* restore this when we're done */ 5640 active_scb = ahc_inb(ahc, SCBPTR); 5641 } else 5642 /* Silence compiler */ 5643 active_scb = SCB_LIST_NULL; 5644 5645 while (next != SCB_LIST_NULL) { 5646 u_int scb_index; 5647 5648 ahc_outb(ahc, SCBPTR, next); 5649 scb_index = ahc_inb(ahc, SCB_TAG); 5650 if (scb_index >= ahc->scb_data->numscbs) { 5651 printf("Disconnected List inconsistency. " 5652 "SCB index == %d, yet numscbs == %d.", 5653 scb_index, ahc->scb_data->numscbs); 5654 ahc_dump_card_state(ahc); 5655 panic("for safety"); 5656 } 5657 5658 if (next == prev) { 5659 panic("Disconnected List Loop. " 5660 "cur SCBPTR == %x, prev SCBPTR == %x.", 5661 next, prev); 5662 } 5663 scbp = ahc_lookup_scb(ahc, scb_index); 5664 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5665 tag, ROLE_INITIATOR)) { 5666 count++; 5667 if (remove) { 5668 next = 5669 ahc_rem_scb_from_disc_list(ahc, prev, next); 5670 } else { 5671 prev = next; 5672 next = ahc_inb(ahc, SCB_NEXT); 5673 } 5674 if (stop_on_first) 5675 break; 5676 } else { 5677 prev = next; 5678 next = ahc_inb(ahc, SCB_NEXT); 5679 } 5680 } 5681 if (save_state) 5682 ahc_outb(ahc, SCBPTR, active_scb); 5683 return (count); 5684} 5685 5686/* 5687 * Remove an SCB from the on chip list of disconnected transactions. 5688 * This is empty/unused if we are not performing SCB paging. 5689 */ 5690static u_int 5691ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5692{ 5693 u_int next; 5694 5695 ahc_outb(ahc, SCBPTR, scbptr); 5696 next = ahc_inb(ahc, SCB_NEXT); 5697 5698 ahc_outb(ahc, SCB_CONTROL, 0); 5699 5700 ahc_add_curscb_to_free_list(ahc); 5701 5702 if (prev != SCB_LIST_NULL) { 5703 ahc_outb(ahc, SCBPTR, prev); 5704 ahc_outb(ahc, SCB_NEXT, next); 5705 } else 5706 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5707 5708 return (next); 5709} 5710 5711/* 5712 * Add the SCB as selected by SCBPTR onto the on chip list of 5713 * free hardware SCBs. This list is empty/unused if we are not 5714 * performing SCB paging. 5715 */ 5716static void 5717ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5718{ 5719 /* 5720 * Invalidate the tag so that our abort 5721 * routines don't think it's active. 5722 */ 5723 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5724 5725 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5726 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5727 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5728 } 5729} 5730 5731/* 5732 * Manipulate the waiting for selection list and return the 5733 * scb that follows the one that we remove. 5734 */ 5735static u_int 5736ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5737{ 5738 u_int curscb, next; 5739 5740 /* 5741 * Select the SCB we want to abort and 5742 * pull the next pointer out of it. 5743 */ 5744 curscb = ahc_inb(ahc, SCBPTR); 5745 ahc_outb(ahc, SCBPTR, scbpos); 5746 next = ahc_inb(ahc, SCB_NEXT); 5747 5748 /* Clear the necessary fields */ 5749 ahc_outb(ahc, SCB_CONTROL, 0); 5750 5751 ahc_add_curscb_to_free_list(ahc); 5752 5753 /* update the waiting list */ 5754 if (prev == SCB_LIST_NULL) { 5755 /* First in the list */ 5756 ahc_outb(ahc, WAITING_SCBH, next); 5757 5758 /* 5759 * Ensure we aren't attempting to perform 5760 * selection for this entry. 5761 */ 5762 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5763 } else { 5764 /* 5765 * Select the scb that pointed to us 5766 * and update its next pointer. 5767 */ 5768 ahc_outb(ahc, SCBPTR, prev); 5769 ahc_outb(ahc, SCB_NEXT, next); 5770 } 5771 5772 /* 5773 * Point us back at the original scb position. 5774 */ 5775 ahc_outb(ahc, SCBPTR, curscb); 5776 return next; 5777} 5778 5779/******************************** Error Handling ******************************/ 5780/* 5781 * Abort all SCBs that match the given description (target/channel/lun/tag), 5782 * setting their status to the passed in status if the status has not already 5783 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5784 * is paused before it is called. 5785 */ 5786int 5787ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5788 int lun, u_int tag, role_t role, uint32_t status) 5789{ 5790 struct scb *scbp; 5791 struct scb *scbp_next; 5792 u_int active_scb; 5793 int i, j; 5794 int maxtarget; 5795 int minlun; 5796 int maxlun; 5797 5798 int found; 5799 5800 /* 5801 * Don't attempt to run any queued untagged transactions 5802 * until we are done with the abort process. 5803 */ 5804 ahc_freeze_untagged_queues(ahc); 5805 5806 /* restore this when we're done */ 5807 active_scb = ahc_inb(ahc, SCBPTR); 5808 5809 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5810 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5811 5812 /* 5813 * Clean out the busy target table for any untagged commands. 5814 */ 5815 i = 0; 5816 maxtarget = 16; 5817 if (target != CAM_TARGET_WILDCARD) { 5818 i = target; 5819 if (channel == 'B') 5820 i += 8; 5821 maxtarget = i + 1; 5822 } 5823 5824 if (lun == CAM_LUN_WILDCARD) { 5825 5826 /* 5827 * Unless we are using an SCB based 5828 * busy targets table, there is only 5829 * one table entry for all luns of 5830 * a target. 5831 */ 5832 minlun = 0; 5833 maxlun = 1; 5834 if ((ahc->flags & AHC_SCB_BTT) != 0) 5835 maxlun = AHC_NUM_LUNS; 5836 } else { 5837 minlun = lun; 5838 maxlun = lun + 1; 5839 } 5840 5841 if (role != ROLE_TARGET) { 5842 for (;i < maxtarget; i++) { 5843 for (j = minlun;j < maxlun; j++) { 5844 u_int scbid; 5845 u_int tcl; 5846 5847 tcl = BUILD_TCL(i << 4, j); 5848 scbid = ahc_index_busy_tcl(ahc, tcl); 5849 scbp = ahc_lookup_scb(ahc, scbid); 5850 if (scbp == NULL 5851 || ahc_match_scb(ahc, scbp, target, channel, 5852 lun, tag, role) == 0) 5853 continue; 5854 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5855 } 5856 } 5857 5858 /* 5859 * Go through the disconnected list and remove any entries we 5860 * have queued for completion, 0'ing their control byte too. 5861 * We save the active SCB and restore it ourselves, so there 5862 * is no reason for this search to restore it too. 5863 */ 5864 ahc_search_disc_list(ahc, target, channel, lun, tag, 5865 /*stop_on_first*/FALSE, /*remove*/TRUE, 5866 /*save_state*/FALSE); 5867 } 5868 5869 /* 5870 * Go through the hardware SCB array looking for commands that 5871 * were active but not on any list. In some cases, these remnants 5872 * might not still have mappings in the scbindex array (e.g. unexpected 5873 * bus free with the same scb queued for an abort). Don't hold this 5874 * against them. 5875 */ 5876 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5877 u_int scbid; 5878 5879 ahc_outb(ahc, SCBPTR, i); 5880 scbid = ahc_inb(ahc, SCB_TAG); 5881 scbp = ahc_lookup_scb(ahc, scbid); 5882 if ((scbp == NULL && scbid != SCB_LIST_NULL) 5883 || (scbp != NULL 5884 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 5885 ahc_add_curscb_to_free_list(ahc); 5886 } 5887 5888 /* 5889 * Go through the pending CCB list and look for 5890 * commands for this target that are still active. 5891 * These are other tagged commands that were 5892 * disconnected when the reset occurred. 5893 */ 5894 scbp_next = LIST_FIRST(&ahc->pending_scbs); 5895 while (scbp_next != NULL) { 5896 scbp = scbp_next; 5897 scbp_next = LIST_NEXT(scbp, pending_links); 5898 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 5899 cam_status ostat; 5900 5901 ostat = ahc_get_transaction_status(scbp); 5902 if (ostat == CAM_REQ_INPROG) 5903 ahc_set_transaction_status(scbp, status); 5904 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) 5905 ahc_freeze_scb(scbp); 5906 if ((scbp->flags & SCB_ACTIVE) == 0) 5907 printf("Inactive SCB on pending list\n"); 5908 ahc_done(ahc, scbp); 5909 found++; 5910 } 5911 } 5912 ahc_outb(ahc, SCBPTR, active_scb); 5913 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 5914 ahc_release_untagged_queues(ahc); 5915 return found; 5916} 5917 5918static void 5919ahc_reset_current_bus(struct ahc_softc *ahc) 5920{ 5921 uint8_t scsiseq; 5922 5923 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5924 scsiseq = ahc_inb(ahc, SCSISEQ); 5925 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5926 ahc_flush_device_writes(ahc); 5927 ahc_delay(AHC_BUSRESET_DELAY); 5928 /* Turn off the bus reset */ 5929 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5930 5931 ahc_clear_intstat(ahc); 5932 5933 /* Re-enable reset interrupts */ 5934 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5935} 5936 5937int 5938ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5939{ 5940 struct ahc_devinfo devinfo; 5941 u_int initiator, target, max_scsiid; 5942 u_int sblkctl; 5943 u_int scsiseq; 5944 u_int simode1; 5945 int found; 5946 int restart_needed; 5947 char cur_channel; 5948 5949 ahc->pending_device = NULL; 5950 5951 ahc_compile_devinfo(&devinfo, 5952 CAM_TARGET_WILDCARD, 5953 CAM_TARGET_WILDCARD, 5954 CAM_LUN_WILDCARD, 5955 channel, ROLE_UNKNOWN); 5956 ahc_pause(ahc); 5957 5958 /* Make sure the sequencer is in a safe location. */ 5959 ahc_clear_critical_section(ahc); 5960 5961 /* 5962 * Run our command complete fifos to ensure that we perform 5963 * completion processing on any commands that 'completed' 5964 * before the reset occurred. 5965 */ 5966 ahc_run_qoutfifo(ahc); 5967#if AHC_TARGET_MODE 5968 /* 5969 * XXX - In Twin mode, the tqinfifo may have commands 5970 * for an unaffected channel in it. However, if 5971 * we have run out of ATIO resources to drain that 5972 * queue, we may not get them all out here. Further, 5973 * the blocked transactions for the reset channel 5974 * should just be killed off, irrespecitve of whether 5975 * we are blocked on ATIO resources. Write a routine 5976 * to compact the tqinfifo appropriately. 5977 */ 5978 if ((ahc->flags & AHC_TARGETROLE) != 0) { 5979 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 5980 } 5981#endif 5982 5983 /* 5984 * Reset the bus if we are initiating this reset 5985 */ 5986 sblkctl = ahc_inb(ahc, SBLKCTL); 5987 cur_channel = 'A'; 5988 if ((ahc->features & AHC_TWIN) != 0 5989 && ((sblkctl & SELBUSB) != 0)) 5990 cur_channel = 'B'; 5991 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 5992 if (cur_channel != channel) { 5993 /* Case 1: Command for another bus is active 5994 * Stealthily reset the other bus without 5995 * upsetting the current bus. 5996 */ 5997 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5998 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5999#if AHC_TARGET_MODE 6000 /* 6001 * Bus resets clear ENSELI, so we cannot 6002 * defer re-enabling bus reset interrupts 6003 * if we are in target mode. 6004 */ 6005 if ((ahc->flags & AHC_TARGETROLE) != 0) 6006 simode1 |= ENSCSIRST; 6007#endif 6008 ahc_outb(ahc, SIMODE1, simode1); 6009 if (initiate_reset) 6010 ahc_reset_current_bus(ahc); 6011 ahc_clear_intstat(ahc); 6012 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6013 ahc_outb(ahc, SBLKCTL, sblkctl); 6014 restart_needed = FALSE; 6015 } else { 6016 /* Case 2: A command from this bus is active or we're idle */ 6017 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 6018#if AHC_TARGET_MODE 6019 /* 6020 * Bus resets clear ENSELI, so we cannot 6021 * defer re-enabling bus reset interrupts 6022 * if we are in target mode. 6023 */ 6024 if ((ahc->flags & AHC_TARGETROLE) != 0) 6025 simode1 |= ENSCSIRST; 6026#endif 6027 ahc_outb(ahc, SIMODE1, simode1); 6028 if (initiate_reset) 6029 ahc_reset_current_bus(ahc); 6030 ahc_clear_intstat(ahc); 6031 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6032 restart_needed = TRUE; 6033 } 6034 6035 /* 6036 * Clean up all the state information for the 6037 * pending transactions on this bus. 6038 */ 6039 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 6040 CAM_LUN_WILDCARD, SCB_LIST_NULL, 6041 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 6042 6043 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 6044 6045#ifdef AHC_TARGET_MODE 6046 /* 6047 * Send an immediate notify ccb to all target more peripheral 6048 * drivers affected by this action. 6049 */ 6050 for (target = 0; target <= max_scsiid; target++) { 6051 struct ahc_tmode_tstate* tstate; 6052 u_int lun; 6053 6054 tstate = ahc->enabled_targets[target]; 6055 if (tstate == NULL) 6056 continue; 6057 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 6058 struct ahc_tmode_lstate* lstate; 6059 6060 lstate = tstate->enabled_luns[lun]; 6061 if (lstate == NULL) 6062 continue; 6063 6064 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 6065 EVENT_TYPE_BUS_RESET, /*arg*/0); 6066 ahc_send_lstate_events(ahc, lstate); 6067 } 6068 } 6069#endif 6070 /* Notify the XPT that a bus reset occurred */ 6071 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD, 6072 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 6073 6074 /* 6075 * Revert to async/narrow transfers until we renegotiate. 6076 */ 6077 for (target = 0; target <= max_scsiid; target++) { 6078 6079 if (ahc->enabled_targets[target] == NULL) 6080 continue; 6081 for (initiator = 0; initiator <= max_scsiid; initiator++) { 6082 struct ahc_devinfo devinfo; 6083 6084 ahc_compile_devinfo(&devinfo, target, initiator, 6085 CAM_LUN_WILDCARD, 6086 channel, ROLE_UNKNOWN); 6087 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6088 AHC_TRANS_CUR, /*paused*/TRUE); 6089 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 6090 /*period*/0, /*offset*/0, 6091 /*ppr_options*/0, AHC_TRANS_CUR, 6092 /*paused*/TRUE); 6093 } 6094 } 6095 6096 if (restart_needed) 6097 ahc_restart(ahc); 6098 else 6099 ahc_unpause(ahc); 6100 return found; 6101} 6102 6103 6104/***************************** Residual Processing ****************************/ 6105/* 6106 * Calculate the residual for a just completed SCB. 6107 */ 6108void 6109ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6110{ 6111 struct hardware_scb *hscb; 6112 struct status_pkt *spkt; 6113 uint32_t sgptr; 6114 uint32_t resid_sgptr; 6115 uint32_t resid; 6116 6117 /* 6118 * 5 cases. 6119 * 1) No residual. 6120 * SG_RESID_VALID clear in sgptr. 6121 * 2) Transferless command 6122 * 3) Never performed any transfers. 6123 * sgptr has SG_FULL_RESID set. 6124 * 4) No residual but target did not 6125 * save data pointers after the 6126 * last transfer, so sgptr was 6127 * never updated. 6128 * 5) We have a partial residual. 6129 * Use residual_sgptr to determine 6130 * where we are. 6131 */ 6132 6133 hscb = scb->hscb; 6134 sgptr = ahc_le32toh(hscb->sgptr); 6135 if ((sgptr & SG_RESID_VALID) == 0) 6136 /* Case 1 */ 6137 return; 6138 sgptr &= ~SG_RESID_VALID; 6139 6140 if ((sgptr & SG_LIST_NULL) != 0) 6141 /* Case 2 */ 6142 return; 6143 6144 spkt = &hscb->shared_data.status; 6145 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr); 6146 if ((sgptr & SG_FULL_RESID) != 0) { 6147 /* Case 3 */ 6148 resid = ahc_get_transfer_length(scb); 6149 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 6150 /* Case 4 */ 6151 return; 6152 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 6153 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 6154 } else { 6155 struct ahc_dma_seg *sg; 6156 6157 /* 6158 * Remainder of the SG where the transfer 6159 * stopped. 6160 */ 6161 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6162 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6163 6164 /* The residual sg_ptr always points to the next sg */ 6165 sg--; 6166 6167 /* 6168 * Add up the contents of all residual 6169 * SG segments that are after the SG where 6170 * the transfer stopped. 6171 */ 6172 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6173 sg++; 6174 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 6175 } 6176 } 6177 if ((scb->flags & SCB_SENSE) == 0) 6178 ahc_set_residual(scb, resid); 6179 else 6180 ahc_set_sense_residual(scb, resid); 6181 6182#ifdef AHC_DEBUG 6183 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6184 ahc_print_path(ahc, scb); 6185 printf("Handled %sResidual of %d bytes\n", 6186 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6187 } 6188#endif 6189} 6190 6191/******************************* Target Mode **********************************/ 6192#ifdef AHC_TARGET_MODE 6193/* 6194 * Add a target mode event to this lun's queue 6195 */ 6196static void 6197ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6198 u_int initiator_id, u_int event_type, u_int event_arg) 6199{ 6200 struct ahc_tmode_event *event; 6201 int pending; 6202 6203 xpt_freeze_devq(lstate->path, /*count*/1); 6204 if (lstate->event_w_idx >= lstate->event_r_idx) 6205 pending = lstate->event_w_idx - lstate->event_r_idx; 6206 else 6207 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6208 - (lstate->event_r_idx - lstate->event_w_idx); 6209 6210 if (event_type == EVENT_TYPE_BUS_RESET 6211 || event_type == MSG_BUS_DEV_RESET) { 6212 /* 6213 * Any earlier events are irrelevant, so reset our buffer. 6214 * This has the effect of allowing us to deal with reset 6215 * floods (an external device holding down the reset line) 6216 * without losing the event that is really interesting. 6217 */ 6218 lstate->event_r_idx = 0; 6219 lstate->event_w_idx = 0; 6220 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6221 } 6222 6223 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6224 xpt_print_path(lstate->path); 6225 printf("immediate event %x:%x lost\n", 6226 lstate->event_buffer[lstate->event_r_idx].event_type, 6227 lstate->event_buffer[lstate->event_r_idx].event_arg); 6228 lstate->event_r_idx++; 6229 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6230 lstate->event_r_idx = 0; 6231 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6232 } 6233 6234 event = &lstate->event_buffer[lstate->event_w_idx]; 6235 event->initiator_id = initiator_id; 6236 event->event_type = event_type; 6237 event->event_arg = event_arg; 6238 lstate->event_w_idx++; 6239 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6240 lstate->event_w_idx = 0; 6241} 6242 6243/* 6244 * Send any target mode events queued up waiting 6245 * for immediate notify resources. 6246 */ 6247void 6248ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6249{ 6250 struct ccb_hdr *ccbh; 6251 struct ccb_immed_notify *inot; 6252 6253 while (lstate->event_r_idx != lstate->event_w_idx 6254 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6255 struct ahc_tmode_event *event; 6256 6257 event = &lstate->event_buffer[lstate->event_r_idx]; 6258 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6259 inot = (struct ccb_immed_notify *)ccbh; 6260 switch (event->event_type) { 6261 case EVENT_TYPE_BUS_RESET: 6262 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6263 break; 6264 default: 6265 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6266 inot->message_args[0] = event->event_type; 6267 inot->message_args[1] = event->event_arg; 6268 break; 6269 } 6270 inot->initiator_id = event->initiator_id; 6271 inot->sense_len = 0; 6272 xpt_done((union ccb *)inot); 6273 lstate->event_r_idx++; 6274 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6275 lstate->event_r_idx = 0; 6276 } 6277} 6278#endif 6279 6280/******************** Sequencer Program Patching/Download *********************/ 6281 6282#ifdef AHC_DUMP_SEQ 6283void 6284ahc_dumpseq(struct ahc_softc* ahc) 6285{ 6286 int i; 6287 6288 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6289 ahc_outb(ahc, SEQADDR0, 0); 6290 ahc_outb(ahc, SEQADDR1, 0); 6291 for (i = 0; i < ahc->instruction_ram_size; i++) { 6292 uint8_t ins_bytes[4]; 6293 6294 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6295 printf("0x%08x\n", ins_bytes[0] << 24 6296 | ins_bytes[1] << 16 6297 | ins_bytes[2] << 8 6298 | ins_bytes[3]); 6299 } 6300} 6301#endif 6302 6303static int 6304ahc_loadseq(struct ahc_softc *ahc) 6305{ 6306 struct cs cs_table[num_critical_sections]; 6307 u_int begin_set[num_critical_sections]; 6308 u_int end_set[num_critical_sections]; 6309 struct patch *cur_patch; 6310 u_int cs_count; 6311 u_int cur_cs; 6312 u_int i; 6313 u_int skip_addr; 6314 u_int sg_prefetch_cnt; 6315 int downloaded; 6316 uint8_t download_consts[7]; 6317 6318 /* 6319 * Start out with 0 critical sections 6320 * that apply to this firmware load. 6321 */ 6322 cs_count = 0; 6323 cur_cs = 0; 6324 memset(begin_set, 0, sizeof(begin_set)); 6325 memset(end_set, 0, sizeof(end_set)); 6326 6327 /* Setup downloadable constant table */ 6328 download_consts[QOUTFIFO_OFFSET] = 0; 6329 if (ahc->targetcmds != NULL) 6330 download_consts[QOUTFIFO_OFFSET] += 32; 6331 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6332 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6333 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6334 sg_prefetch_cnt = ahc->pci_cachesize; 6335 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6336 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6337 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6338 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6339 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6340 6341 cur_patch = patches; 6342 downloaded = 0; 6343 skip_addr = 0; 6344 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6345 ahc_outb(ahc, SEQADDR0, 0); 6346 ahc_outb(ahc, SEQADDR1, 0); 6347 6348 for (i = 0; i < sizeof(seqprog)/4; i++) { 6349 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6350 /* 6351 * Don't download this instruction as it 6352 * is in a patch that was removed. 6353 */ 6354 continue; 6355 } 6356 6357 if (downloaded == ahc->instruction_ram_size) { 6358 /* 6359 * We're about to exceed the instruction 6360 * storage capacity for this chip. Fail 6361 * the load. 6362 */ 6363 printf("\n%s: Program too large for instruction memory " 6364 "size of %d!\n", ahc_name(ahc), 6365 ahc->instruction_ram_size); 6366 return (ENOMEM); 6367 } 6368 6369 /* 6370 * Move through the CS table until we find a CS 6371 * that might apply to this instruction. 6372 */ 6373 for (; cur_cs < num_critical_sections; cur_cs++) { 6374 if (critical_sections[cur_cs].end <= i) { 6375 if (begin_set[cs_count] == TRUE 6376 && end_set[cs_count] == FALSE) { 6377 cs_table[cs_count].end = downloaded; 6378 end_set[cs_count] = TRUE; 6379 cs_count++; 6380 } 6381 continue; 6382 } 6383 if (critical_sections[cur_cs].begin <= i 6384 && begin_set[cs_count] == FALSE) { 6385 cs_table[cs_count].begin = downloaded; 6386 begin_set[cs_count] = TRUE; 6387 } 6388 break; 6389 } 6390 ahc_download_instr(ahc, i, download_consts); 6391 downloaded++; 6392 } 6393 6394 ahc->num_critical_sections = cs_count; 6395 if (cs_count != 0) { 6396 6397 cs_count *= sizeof(struct cs); 6398 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 6399 if (ahc->critical_sections == NULL) 6400 panic("ahc_loadseq: Could not malloc"); 6401 memcpy(ahc->critical_sections, cs_table, cs_count); 6402 } 6403 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6404 ahc_restart(ahc); 6405 6406 if (bootverbose) { 6407 printf(" %d instructions downloaded\n", downloaded); 6408 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6409 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6410 } 6411 return (0); 6412} 6413 6414static int 6415ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 6416 u_int start_instr, u_int *skip_addr) 6417{ 6418 struct patch *cur_patch; 6419 struct patch *last_patch; 6420 u_int num_patches; 6421 6422 num_patches = sizeof(patches)/sizeof(struct patch); 6423 last_patch = &patches[num_patches]; 6424 cur_patch = *start_patch; 6425 6426 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6427 6428 if (cur_patch->patch_func(ahc) == 0) { 6429 6430 /* Start rejecting code */ 6431 *skip_addr = start_instr + cur_patch->skip_instr; 6432 cur_patch += cur_patch->skip_patch; 6433 } else { 6434 /* Accepted this patch. Advance to the next 6435 * one and wait for our intruction pointer to 6436 * hit this point. 6437 */ 6438 cur_patch++; 6439 } 6440 } 6441 6442 *start_patch = cur_patch; 6443 if (start_instr < *skip_addr) 6444 /* Still skipping */ 6445 return (0); 6446 6447 return (1); 6448} 6449 6450static void 6451ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6452{ 6453 union ins_formats instr; 6454 struct ins_format1 *fmt1_ins; 6455 struct ins_format3 *fmt3_ins; 6456 u_int opcode; 6457 6458 /* 6459 * The firmware is always compiled into a little endian format. 6460 */ 6461 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6462 6463 fmt1_ins = &instr.format1; 6464 fmt3_ins = NULL; 6465 6466 /* Pull the opcode */ 6467 opcode = instr.format1.opcode; 6468 switch (opcode) { 6469 case AIC_OP_JMP: 6470 case AIC_OP_JC: 6471 case AIC_OP_JNC: 6472 case AIC_OP_CALL: 6473 case AIC_OP_JNE: 6474 case AIC_OP_JNZ: 6475 case AIC_OP_JE: 6476 case AIC_OP_JZ: 6477 { 6478 struct patch *cur_patch; 6479 int address_offset; 6480 u_int address; 6481 u_int skip_addr; 6482 u_int i; 6483 6484 fmt3_ins = &instr.format3; 6485 address_offset = 0; 6486 address = fmt3_ins->address; 6487 cur_patch = patches; 6488 skip_addr = 0; 6489 6490 for (i = 0; i < address;) { 6491 6492 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6493 6494 if (skip_addr > i) { 6495 int end_addr; 6496 6497 end_addr = MIN(address, skip_addr); 6498 address_offset += end_addr - i; 6499 i = skip_addr; 6500 } else { 6501 i++; 6502 } 6503 } 6504 address -= address_offset; 6505 fmt3_ins->address = address; 6506 /* FALLTHROUGH */ 6507 } 6508 case AIC_OP_OR: 6509 case AIC_OP_AND: 6510 case AIC_OP_XOR: 6511 case AIC_OP_ADD: 6512 case AIC_OP_ADC: 6513 case AIC_OP_BMOV: 6514 if (fmt1_ins->parity != 0) { 6515 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6516 } 6517 fmt1_ins->parity = 0; 6518 if ((ahc->features & AHC_CMD_CHAN) == 0 6519 && opcode == AIC_OP_BMOV) { 6520 /* 6521 * Block move was added at the same time 6522 * as the command channel. Verify that 6523 * this is only a move of a single element 6524 * and convert the BMOV to a MOV 6525 * (AND with an immediate of FF). 6526 */ 6527 if (fmt1_ins->immediate != 1) 6528 panic("%s: BMOV not supported\n", 6529 ahc_name(ahc)); 6530 fmt1_ins->opcode = AIC_OP_AND; 6531 fmt1_ins->immediate = 0xff; 6532 } 6533 /* FALLTHROUGH */ 6534 case AIC_OP_ROL: 6535 if ((ahc->features & AHC_ULTRA2) != 0) { 6536 int i, count; 6537 6538 /* Calculate odd parity for the instruction */ 6539 for (i = 0, count = 0; i < 31; i++) { 6540 uint32_t mask; 6541 6542 mask = 0x01 << i; 6543 if ((instr.integer & mask) != 0) 6544 count++; 6545 } 6546 if ((count & 0x01) == 0) 6547 instr.format1.parity = 1; 6548 } else { 6549 /* Compress the instruction for older sequencers */ 6550 if (fmt3_ins != NULL) { 6551 instr.integer = 6552 fmt3_ins->immediate 6553 | (fmt3_ins->source << 8) 6554 | (fmt3_ins->address << 16) 6555 | (fmt3_ins->opcode << 25); 6556 } else { 6557 instr.integer = 6558 fmt1_ins->immediate 6559 | (fmt1_ins->source << 8) 6560 | (fmt1_ins->destination << 16) 6561 | (fmt1_ins->ret << 24) 6562 | (fmt1_ins->opcode << 25); 6563 } 6564 } 6565 /* The sequencer is a little endian cpu */ 6566 instr.integer = ahc_htole32(instr.integer); 6567 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6568 break; 6569 default: 6570 panic("Unknown opcode encountered in seq program"); 6571 break; 6572 } 6573} 6574 6575int 6576ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 6577 const char *name, u_int address, u_int value, 6578 u_int *cur_column, u_int wrap_point) 6579{ 6580 int printed; 6581 u_int printed_mask; 6582 6583 if (cur_column != NULL && *cur_column >= wrap_point) { 6584 printf("\n"); 6585 *cur_column = 0; 6586 } 6587 printed = printf("%s[0x%x]", name, value); 6588 if (table == NULL) { 6589 printed += printf(" "); 6590 *cur_column += printed; 6591 return (printed); 6592 } 6593 printed_mask = 0; 6594 while (printed_mask != 0xFF) { 6595 int entry; 6596 6597 for (entry = 0; entry < num_entries; entry++) { 6598 if (((value & table[entry].mask) 6599 != table[entry].value) 6600 || ((printed_mask & table[entry].mask) 6601 == table[entry].mask)) 6602 continue; 6603 6604 printed += printf("%s%s", 6605 printed_mask == 0 ? ":(" : "|", 6606 table[entry].name); 6607 printed_mask |= table[entry].mask; 6608 6609 break; 6610 } 6611 if (entry >= num_entries) 6612 break; 6613 } 6614 if (printed_mask != 0) 6615 printed += printf(") "); 6616 else 6617 printed += printf(" "); 6618 if (cur_column != NULL) 6619 *cur_column += printed; 6620 return (printed); 6621} 6622 6623void 6624ahc_dump_card_state(struct ahc_softc *ahc) 6625{ 6626 struct scb *scb; 6627 struct scb_tailq *untagged_q; 6628 u_int cur_col; 6629 int paused; 6630 int target; 6631 int maxtarget; 6632 int i; 6633 uint8_t last_phase; 6634 uint8_t qinpos; 6635 uint8_t qintail; 6636 uint8_t qoutpos; 6637 uint8_t scb_index; 6638 uint8_t saved_scbptr; 6639 6640 if (ahc_is_paused(ahc)) { 6641 paused = 1; 6642 } else { 6643 paused = 0; 6644 ahc_pause(ahc); 6645 } 6646 6647 saved_scbptr = ahc_inb(ahc, SCBPTR); 6648 last_phase = ahc_inb(ahc, LASTPHASE); 6649 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 6650 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6651 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6652 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6653 if (paused) 6654 printf("Card was paused\n"); 6655 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 6656 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 6657 ahc_inb(ahc, ARG_2)); 6658 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 6659 ahc_inb(ahc, SCBPTR)); 6660 cur_col = 0; 6661 if ((ahc->features & AHC_DT) != 0) 6662 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 6663 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 6664 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 6665 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 6666 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 6667 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 6668 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 6669 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 6670 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 6671 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 6672 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 6673 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 6674 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 6675 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 6676 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 6677 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 6678 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 6679 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 6680 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 6681 if (cur_col != 0) 6682 printf("\n"); 6683 printf("STACK:"); 6684 for (i = 0; i < STACK_SIZE; i++) 6685 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 6686 printf("\nSCB count = %d\n", ahc->scb_data->numscbs); 6687 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6688 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6689 /* QINFIFO */ 6690 printf("QINFIFO entries: "); 6691 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6692 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6693 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6694 } else 6695 qinpos = ahc_inb(ahc, QINPOS); 6696 qintail = ahc->qinfifonext; 6697 while (qinpos != qintail) { 6698 printf("%d ", ahc->qinfifo[qinpos]); 6699 qinpos++; 6700 } 6701 printf("\n"); 6702 6703 printf("Waiting Queue entries: "); 6704 scb_index = ahc_inb(ahc, WAITING_SCBH); 6705 i = 0; 6706 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6707 ahc_outb(ahc, SCBPTR, scb_index); 6708 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6709 scb_index = ahc_inb(ahc, SCB_NEXT); 6710 } 6711 printf("\n"); 6712 6713 printf("Disconnected Queue entries: "); 6714 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6715 i = 0; 6716 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6717 ahc_outb(ahc, SCBPTR, scb_index); 6718 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6719 scb_index = ahc_inb(ahc, SCB_NEXT); 6720 } 6721 printf("\n"); 6722 6723 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 6724 printf("QOUTFIFO entries: "); 6725 qoutpos = ahc->qoutfifonext; 6726 i = 0; 6727 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6728 printf("%d ", ahc->qoutfifo[qoutpos]); 6729 qoutpos++; 6730 } 6731 printf("\n"); 6732 6733 printf("Sequencer Free SCB List: "); 6734 scb_index = ahc_inb(ahc, FREE_SCBH); 6735 i = 0; 6736 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6737 ahc_outb(ahc, SCBPTR, scb_index); 6738 printf("%d ", scb_index); 6739 scb_index = ahc_inb(ahc, SCB_NEXT); 6740 } 6741 printf("\n"); 6742 6743 printf("Sequencer SCB Info: "); 6744 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6745 ahc_outb(ahc, SCBPTR, i); 6746 cur_col = printf("\n%3d ", i); 6747 6748 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 6749 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 6750 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 6751 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6752 } 6753 printf("\n"); 6754 6755 printf("Pending list: "); 6756 i = 0; 6757 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6758 if (i++ > 256) 6759 break; 6760 cur_col = printf("\n%3d ", scb->hscb->tag); 6761 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 6762 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 6763 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 6764 if ((ahc->flags & AHC_PAGESCBS) == 0) { 6765 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 6766 printf("("); 6767 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 6768 &cur_col, 60); 6769 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6770 printf(")"); 6771 } 6772 } 6773 printf("\n"); 6774 6775 printf("Kernel Free SCB list: "); 6776 i = 0; 6777 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6778 if (i++ > 256) 6779 break; 6780 printf("%d ", scb->hscb->tag); 6781 } 6782 printf("\n"); 6783 6784 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6785 for (target = 0; target <= maxtarget; target++) { 6786 untagged_q = &ahc->untagged_queues[target]; 6787 if (TAILQ_FIRST(untagged_q) == NULL) 6788 continue; 6789 printf("Untagged Q(%d): ", target); 6790 i = 0; 6791 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6792 if (i++ > 256) 6793 break; 6794 printf("%d ", scb->hscb->tag); 6795 } 6796 printf("\n"); 6797 } 6798 6799 ahc_platform_dump_card_state(ahc); 6800 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 6801 ahc_outb(ahc, SCBPTR, saved_scbptr); 6802 if (paused == 0) 6803 ahc_unpause(ahc); 6804} 6805 6806/************************* Target Mode ****************************************/ 6807#ifdef AHC_TARGET_MODE 6808cam_status 6809ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 6810 struct ahc_tmode_tstate **tstate, 6811 struct ahc_tmode_lstate **lstate, 6812 int notfound_failure) 6813{ 6814 6815 if ((ahc->features & AHC_TARGETMODE) == 0) 6816 return (CAM_REQ_INVALID); 6817 6818 /* 6819 * Handle the 'black hole' device that sucks up 6820 * requests to unattached luns on enabled targets. 6821 */ 6822 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 6823 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 6824 *tstate = NULL; 6825 *lstate = ahc->black_hole; 6826 } else { 6827 u_int max_id; 6828 6829 max_id = (ahc->features & AHC_WIDE) ? 15 : 7; 6830 if (ccb->ccb_h.target_id > max_id) 6831 return (CAM_TID_INVALID); 6832 6833 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 6834 return (CAM_LUN_INVALID); 6835 6836 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 6837 *lstate = NULL; 6838 if (*tstate != NULL) 6839 *lstate = 6840 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 6841 } 6842 6843 if (notfound_failure != 0 && *lstate == NULL) 6844 return (CAM_PATH_INVALID); 6845 6846 return (CAM_REQ_CMP); 6847} 6848 6849void 6850ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 6851{ 6852 struct ahc_tmode_tstate *tstate; 6853 struct ahc_tmode_lstate *lstate; 6854 struct ccb_en_lun *cel; 6855 cam_status status; 6856 u_long s; 6857 u_int target; 6858 u_int lun; 6859 u_int target_mask; 6860 u_int our_id; 6861 int error; 6862 char channel; 6863 6864 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 6865 /*notfound_failure*/FALSE); 6866 6867 if (status != CAM_REQ_CMP) { 6868 ccb->ccb_h.status = status; 6869 return; 6870 } 6871 6872 if (cam_sim_bus(sim) == 0) 6873 our_id = ahc->our_id; 6874 else 6875 our_id = ahc->our_id_b; 6876 6877 if (ccb->ccb_h.target_id != our_id) { 6878 /* 6879 * our_id represents our initiator ID, or 6880 * the ID of the first target to have an 6881 * enabled lun in target mode. There are 6882 * two cases that may preclude enabling a 6883 * target id other than our_id. 6884 * 6885 * o our_id is for an active initiator role. 6886 * Since the hardware does not support 6887 * reselections to the initiator role at 6888 * anything other than our_id, and our_id 6889 * is used by the hardware to indicate the 6890 * ID to use for both select-out and 6891 * reselect-out operations, the only target 6892 * ID we can support in this mode is our_id. 6893 * 6894 * o The MULTARGID feature is not available and 6895 * a previous target mode ID has been enabled. 6896 */ 6897 if ((ahc->features & AHC_MULTIROLE) != 0) { 6898 6899 if ((ahc->features & AHC_MULTI_TID) != 0 6900 && (ahc->flags & AHC_INITIATORROLE) != 0) { 6901 /* 6902 * Only allow additional targets if 6903 * the initiator role is disabled. 6904 * The hardware cannot handle a re-select-in 6905 * on the initiator id during a re-select-out 6906 * on a different target id. 6907 */ 6908 status = CAM_TID_INVALID; 6909 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 6910 || ahc->enabled_luns > 0) { 6911 /* 6912 * Only allow our target id to change 6913 * if the initiator role is not configured 6914 * and there are no enabled luns which 6915 * are attached to the currently registered 6916 * scsi id. 6917 */ 6918 status = CAM_TID_INVALID; 6919 } 6920 } else if ((ahc->features & AHC_MULTI_TID) == 0 6921 && ahc->enabled_luns > 0) { 6922 6923 status = CAM_TID_INVALID; 6924 } 6925 } 6926 6927 if (status != CAM_REQ_CMP) { 6928 ccb->ccb_h.status = status; 6929 return; 6930 } 6931 6932 /* 6933 * We now have an id that is valid. 6934 * If we aren't in target mode, switch modes. 6935 */ 6936 if ((ahc->flags & AHC_TARGETROLE) == 0 6937 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 6938 u_long s; 6939 ahc_flag saved_flags; 6940 6941 printf("Configuring Target Mode\n"); 6942 ahc_lock(ahc, &s); 6943 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 6944 ccb->ccb_h.status = CAM_BUSY; 6945 ahc_unlock(ahc, &s); 6946 return; 6947 } 6948 saved_flags = ahc->flags; 6949 ahc->flags |= AHC_TARGETROLE; 6950 if ((ahc->features & AHC_MULTIROLE) == 0) 6951 ahc->flags &= ~AHC_INITIATORROLE; 6952 ahc_pause(ahc); 6953 error = ahc_loadseq(ahc); 6954 if (error != 0) { 6955 /* 6956 * Restore original configuration and notify 6957 * the caller that we cannot support target mode. 6958 * Since the adapter started out in this 6959 * configuration, the firmware load will succeed, 6960 * so there is no point in checking ahc_loadseq's 6961 * return value. 6962 */ 6963 ahc->flags = saved_flags; 6964 (void)ahc_loadseq(ahc); 6965 ahc_unpause(ahc); 6966 ahc_unlock(ahc, &s); 6967 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 6968 return; 6969 } 6970 ahc_unlock(ahc, &s); 6971 } 6972 cel = &ccb->cel; 6973 target = ccb->ccb_h.target_id; 6974 lun = ccb->ccb_h.target_lun; 6975 channel = SIM_CHANNEL(ahc, sim); 6976 target_mask = 0x01 << target; 6977 if (channel == 'B') 6978 target_mask <<= 8; 6979 6980 if (cel->enable != 0) { 6981 u_int scsiseq; 6982 6983 /* Are we already enabled?? */ 6984 if (lstate != NULL) { 6985 xpt_print_path(ccb->ccb_h.path); 6986 printf("Lun already enabled\n"); 6987 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 6988 return; 6989 } 6990 6991 if (cel->grp6_len != 0 6992 || cel->grp7_len != 0) { 6993 /* 6994 * Don't (yet?) support vendor 6995 * specific commands. 6996 */ 6997 ccb->ccb_h.status = CAM_REQ_INVALID; 6998 printf("Non-zero Group Codes\n"); 6999 return; 7000 } 7001 7002 /* 7003 * Seems to be okay. 7004 * Setup our data structures. 7005 */ 7006 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 7007 tstate = ahc_alloc_tstate(ahc, target, channel); 7008 if (tstate == NULL) { 7009 xpt_print_path(ccb->ccb_h.path); 7010 printf("Couldn't allocate tstate\n"); 7011 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7012 return; 7013 } 7014 } 7015 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 7016 if (lstate == NULL) { 7017 xpt_print_path(ccb->ccb_h.path); 7018 printf("Couldn't allocate lstate\n"); 7019 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7020 return; 7021 } 7022 memset(lstate, 0, sizeof(*lstate)); 7023 status = xpt_create_path(&lstate->path, /*periph*/NULL, 7024 xpt_path_path_id(ccb->ccb_h.path), 7025 xpt_path_target_id(ccb->ccb_h.path), 7026 xpt_path_lun_id(ccb->ccb_h.path)); 7027 if (status != CAM_REQ_CMP) { 7028 free(lstate, M_DEVBUF); 7029 xpt_print_path(ccb->ccb_h.path); 7030 printf("Couldn't allocate path\n"); 7031 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7032 return; 7033 } 7034 SLIST_INIT(&lstate->accept_tios); 7035 SLIST_INIT(&lstate->immed_notifies); 7036 ahc_lock(ahc, &s); 7037 ahc_pause(ahc); 7038 if (target != CAM_TARGET_WILDCARD) { 7039 tstate->enabled_luns[lun] = lstate; 7040 ahc->enabled_luns++; 7041 7042 if ((ahc->features & AHC_MULTI_TID) != 0) { 7043 u_int targid_mask; 7044 7045 targid_mask = ahc_inb(ahc, TARGID) 7046 | (ahc_inb(ahc, TARGID + 1) << 8); 7047 7048 targid_mask |= target_mask; 7049 ahc_outb(ahc, TARGID, targid_mask); 7050 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 7051 7052 ahc_update_scsiid(ahc, targid_mask); 7053 } else { 7054 u_int our_id; 7055 char channel; 7056 7057 channel = SIM_CHANNEL(ahc, sim); 7058 our_id = SIM_SCSI_ID(ahc, sim); 7059 7060 /* 7061 * This can only happen if selections 7062 * are not enabled 7063 */ 7064 if (target != our_id) { 7065 u_int sblkctl; 7066 char cur_channel; 7067 int swap; 7068 7069 sblkctl = ahc_inb(ahc, SBLKCTL); 7070 cur_channel = (sblkctl & SELBUSB) 7071 ? 'B' : 'A'; 7072 if ((ahc->features & AHC_TWIN) == 0) 7073 cur_channel = 'A'; 7074 swap = cur_channel != channel; 7075 if (channel == 'A') 7076 ahc->our_id = target; 7077 else 7078 ahc->our_id_b = target; 7079 7080 if (swap) 7081 ahc_outb(ahc, SBLKCTL, 7082 sblkctl ^ SELBUSB); 7083 7084 ahc_outb(ahc, SCSIID, target); 7085 7086 if (swap) 7087 ahc_outb(ahc, SBLKCTL, sblkctl); 7088 } 7089 } 7090 } else 7091 ahc->black_hole = lstate; 7092 /* Allow select-in operations */ 7093 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 7094 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7095 scsiseq |= ENSELI; 7096 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7097 scsiseq = ahc_inb(ahc, SCSISEQ); 7098 scsiseq |= ENSELI; 7099 ahc_outb(ahc, SCSISEQ, scsiseq); 7100 } 7101 ahc_unpause(ahc); 7102 ahc_unlock(ahc, &s); 7103 ccb->ccb_h.status = CAM_REQ_CMP; 7104 xpt_print_path(ccb->ccb_h.path); 7105 printf("Lun now enabled for target mode\n"); 7106 } else { 7107 struct scb *scb; 7108 int i, empty; 7109 7110 if (lstate == NULL) { 7111 ccb->ccb_h.status = CAM_LUN_INVALID; 7112 return; 7113 } 7114 7115 ahc_lock(ahc, &s); 7116 7117 ccb->ccb_h.status = CAM_REQ_CMP; 7118 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7119 struct ccb_hdr *ccbh; 7120 7121 ccbh = &scb->io_ctx->ccb_h; 7122 if (ccbh->func_code == XPT_CONT_TARGET_IO 7123 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 7124 printf("CTIO pending\n"); 7125 ccb->ccb_h.status = CAM_REQ_INVALID; 7126 ahc_unlock(ahc, &s); 7127 return; 7128 } 7129 } 7130 7131 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 7132 printf("ATIOs pending\n"); 7133 ccb->ccb_h.status = CAM_REQ_INVALID; 7134 } 7135 7136 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 7137 printf("INOTs pending\n"); 7138 ccb->ccb_h.status = CAM_REQ_INVALID; 7139 } 7140 7141 if (ccb->ccb_h.status != CAM_REQ_CMP) { 7142 ahc_unlock(ahc, &s); 7143 return; 7144 } 7145 7146 xpt_print_path(ccb->ccb_h.path); 7147 printf("Target mode disabled\n"); 7148 xpt_free_path(lstate->path); 7149 free(lstate, M_DEVBUF); 7150 7151 ahc_pause(ahc); 7152 /* Can we clean up the target too? */ 7153 if (target != CAM_TARGET_WILDCARD) { 7154 tstate->enabled_luns[lun] = NULL; 7155 ahc->enabled_luns--; 7156 for (empty = 1, i = 0; i < 8; i++) 7157 if (tstate->enabled_luns[i] != NULL) { 7158 empty = 0; 7159 break; 7160 } 7161 7162 if (empty) { 7163 ahc_free_tstate(ahc, target, channel, 7164 /*force*/FALSE); 7165 if (ahc->features & AHC_MULTI_TID) { 7166 u_int targid_mask; 7167 7168 targid_mask = ahc_inb(ahc, TARGID) 7169 | (ahc_inb(ahc, TARGID + 1) 7170 << 8); 7171 7172 targid_mask &= ~target_mask; 7173 ahc_outb(ahc, TARGID, targid_mask); 7174 ahc_outb(ahc, TARGID+1, 7175 (targid_mask >> 8)); 7176 ahc_update_scsiid(ahc, targid_mask); 7177 } 7178 } 7179 } else { 7180 7181 ahc->black_hole = NULL; 7182 7183 /* 7184 * We can't allow selections without 7185 * our black hole device. 7186 */ 7187 empty = TRUE; 7188 } 7189 if (ahc->enabled_luns == 0) { 7190 /* Disallow select-in */ 7191 u_int scsiseq; 7192 7193 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7194 scsiseq &= ~ENSELI; 7195 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7196 scsiseq = ahc_inb(ahc, SCSISEQ); 7197 scsiseq &= ~ENSELI; 7198 ahc_outb(ahc, SCSISEQ, scsiseq); 7199 7200 if ((ahc->features & AHC_MULTIROLE) == 0) { 7201 printf("Configuring Initiator Mode\n"); 7202 ahc->flags &= ~AHC_TARGETROLE; 7203 ahc->flags |= AHC_INITIATORROLE; 7204 ahc_pause(ahc); 7205 /* 7206 * Returning to a configuration that 7207 * fit previously will always succeed. 7208 */ 7209 (void)ahc_loadseq(ahc); 7210 } 7211 } 7212 ahc_unpause(ahc); 7213 ahc_unlock(ahc, &s); 7214 } 7215} 7216 7217static void 7218ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7219{ 7220 u_int scsiid_mask; 7221 u_int scsiid; 7222 7223 if ((ahc->features & AHC_MULTI_TID) == 0) 7224 panic("ahc_update_scsiid called on non-multitid unit\n"); 7225 7226 /* 7227 * Since we will rely on the TARGID mask 7228 * for selection enables, ensure that OID 7229 * in SCSIID is not set to some other ID 7230 * that we don't want to allow selections on. 7231 */ 7232 if ((ahc->features & AHC_ULTRA2) != 0) 7233 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7234 else 7235 scsiid = ahc_inb(ahc, SCSIID); 7236 scsiid_mask = 0x1 << (scsiid & OID); 7237 if ((targid_mask & scsiid_mask) == 0) { 7238 u_int our_id; 7239 7240 /* ffs counts from 1 */ 7241 our_id = ffs(targid_mask); 7242 if (our_id == 0) 7243 our_id = ahc->our_id; 7244 else 7245 our_id--; 7246 scsiid &= TID; 7247 scsiid |= our_id; 7248 } 7249 if ((ahc->features & AHC_ULTRA2) != 0) 7250 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7251 else 7252 ahc_outb(ahc, SCSIID, scsiid); 7253} 7254 7255void 7256ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7257{ 7258 struct target_cmd *cmd; 7259 7260 /* 7261 * If the card supports auto-access pause, 7262 * we can access the card directly regardless 7263 * of whether it is paused or not. 7264 */ 7265 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7266 paused = TRUE; 7267 7268 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7269 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7270 7271 /* 7272 * Only advance through the queue if we 7273 * have the resources to process the command. 7274 */ 7275 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7276 break; 7277 7278 cmd->cmd_valid = 0; 7279 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 7280 ahc->shared_data_dmamap, 7281 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7282 sizeof(struct target_cmd), 7283 BUS_DMASYNC_PREREAD); 7284 ahc->tqinfifonext++; 7285 7286 /* 7287 * Lazily update our position in the target mode incoming 7288 * command queue as seen by the sequencer. 7289 */ 7290 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7291 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7292 u_int hs_mailbox; 7293 7294 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7295 hs_mailbox &= ~HOST_TQINPOS; 7296 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7297 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7298 } else { 7299 if (!paused) 7300 ahc_pause(ahc); 7301 ahc_outb(ahc, KERNEL_TQINPOS, 7302 ahc->tqinfifonext & HOST_TQINPOS); 7303 if (!paused) 7304 ahc_unpause(ahc); 7305 } 7306 } 7307 } 7308} 7309 7310static int 7311ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7312{ 7313 struct ahc_tmode_tstate *tstate; 7314 struct ahc_tmode_lstate *lstate; 7315 struct ccb_accept_tio *atio; 7316 uint8_t *byte; 7317 int initiator; 7318 int target; 7319 int lun; 7320 7321 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7322 target = SCSIID_OUR_ID(cmd->scsiid); 7323 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7324 7325 byte = cmd->bytes; 7326 tstate = ahc->enabled_targets[target]; 7327 lstate = NULL; 7328 if (tstate != NULL) 7329 lstate = tstate->enabled_luns[lun]; 7330 7331 /* 7332 * Commands for disabled luns go to the black hole driver. 7333 */ 7334 if (lstate == NULL) 7335 lstate = ahc->black_hole; 7336 7337 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7338 if (atio == NULL) { 7339 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7340 /* 7341 * Wait for more ATIOs from the peripheral driver for this lun. 7342 */ 7343 if (bootverbose) 7344 printf("%s: ATIOs exhausted\n", ahc_name(ahc)); 7345 return (1); 7346 } else 7347 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7348#if 0 7349 printf("Incoming command from %d for %d:%d%s\n", 7350 initiator, target, lun, 7351 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7352#endif 7353 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7354 7355 if (lstate == ahc->black_hole) { 7356 /* Fill in the wildcards */ 7357 atio->ccb_h.target_id = target; 7358 atio->ccb_h.target_lun = lun; 7359 } 7360 7361 /* 7362 * Package it up and send it off to 7363 * whomever has this lun enabled. 7364 */ 7365 atio->sense_len = 0; 7366 atio->init_id = initiator; 7367 if (byte[0] != 0xFF) { 7368 /* Tag was included */ 7369 atio->tag_action = *byte++; 7370 atio->tag_id = *byte++; 7371 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 7372 } else { 7373 atio->ccb_h.flags = 0; 7374 } 7375 byte++; 7376 7377 /* Okay. Now determine the cdb size based on the command code */ 7378 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7379 case 0: 7380 atio->cdb_len = 6; 7381 break; 7382 case 1: 7383 case 2: 7384 atio->cdb_len = 10; 7385 break; 7386 case 4: 7387 atio->cdb_len = 16; 7388 break; 7389 case 5: 7390 atio->cdb_len = 12; 7391 break; 7392 case 3: 7393 default: 7394 /* Only copy the opcode. */ 7395 atio->cdb_len = 1; 7396 printf("Reserved or VU command code type encountered\n"); 7397 break; 7398 } 7399 7400 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7401 7402 atio->ccb_h.status |= CAM_CDB_RECVD; 7403 7404 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7405 /* 7406 * We weren't allowed to disconnect. 7407 * We're hanging on the bus until a 7408 * continue target I/O comes in response 7409 * to this accept tio. 7410 */ 7411#if 0 7412 printf("Received Immediate Command %d:%d:%d - %p\n", 7413 initiator, target, lun, ahc->pending_device); 7414#endif 7415 ahc->pending_device = lstate; 7416 ahc_freeze_ccb((union ccb *)atio); 7417 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7418 } 7419 xpt_done((union ccb*)atio); 7420 return (0); 7421} 7422 7423#endif 7424