agpreg.h revision 119368
1/*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/agp/agpreg.h 119368 2003-08-23 18:00:31Z mdodd $ 27 */ 28 29#ifndef _PCI_AGPREG_H_ 30#define _PCI_AGPREG_H_ 31 32/* 33 * Offsets for various AGP configuration registers. 34 */ 35#define AGP_APBASE 0x10 36#define AGP_CAPPTR 0x34 37 38/* 39 * Offsets from the AGP Capability pointer. 40 */ 41#define AGP_CAPID 0x0 42#define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20) 43#define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16) 44#define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8) 45#define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0) 46 47#define AGP_STATUS 0x4 48#define AGP_COMMAND 0x8 49 50/* 51 * Config offsets for Intel AGP chipsets. 52 */ 53#define AGP_INTEL_NBXCFG 0x50 54#define AGP_INTEL_ERRSTS 0x91 55#define AGP_INTEL_AGPCTRL 0xb0 56#define AGP_INTEL_APSIZE 0xb4 57#define AGP_INTEL_ATTBASE 0xb8 58 59/* 60 * Config offsets for Intel i820/i840/i845/i850/i860/i865 AGP chipsets. 61 */ 62#define AGP_INTEL_MCHCFG 0x50 63#define AGP_INTEL_I820_RDCR 0x51 64#define AGP_INTEL_I845_MCHCFG 0x51 65#define AGP_INTEL_I8XX_ERRSTS 0xc8 66 67/* 68 * Config offsets for VIA AGP chipsets. 69 */ 70#define AGP_VIA_GARTCTRL 0x80 71#define AGP_VIA_APSIZE 0x84 72#define AGP_VIA_ATTBASE 0x88 73 74/* 75 * Config offsets for SiS AGP chipsets. 76 */ 77#define AGP_SIS_ATTBASE 0x90 78#define AGP_SIS_WINCTRL 0x94 79#define AGP_SIS_TLBCTRL 0x97 80#define AGP_SIS_TLBFLUSH 0x98 81 82/* 83 * Config offsets for Ali AGP chipsets. 84 */ 85#define AGP_ALI_AGPCTRL 0xb8 86#define AGP_ALI_ATTBASE 0xbc 87#define AGP_ALI_TLBCTRL 0xc0 88 89/* 90 * Config offsets for the AMD 751 chipset. 91 */ 92#define AGP_AMD751_APBASE 0x10 93#define AGP_AMD751_REGISTERS 0x14 94#define AGP_AMD751_APCTRL 0xac 95#define AGP_AMD751_MODECTRL 0xb0 96#define AGP_AMD751_MODECTRL_SYNEN 0x80 97#define AGP_AMD751_MODECTRL2 0xb2 98#define AGP_AMD751_MODECTRL2_G1LM 0x01 99#define AGP_AMD751_MODECTRL2_GPDCE 0x02 100#define AGP_AMD751_MODECTRL2_NGSE 0x08 101 102/* 103 * Memory mapped register offsets for AMD 751 chipset. 104 */ 105#define AGP_AMD751_CAPS 0x00 106#define AGP_AMD751_CAPS_EHI 0x0800 107#define AGP_AMD751_CAPS_P2P 0x0400 108#define AGP_AMD751_CAPS_MPC 0x0200 109#define AGP_AMD751_CAPS_VBE 0x0100 110#define AGP_AMD751_CAPS_REV 0x00ff 111#define AGP_AMD751_STATUS 0x02 112#define AGP_AMD751_STATUS_P2PS 0x0800 113#define AGP_AMD751_STATUS_GCS 0x0400 114#define AGP_AMD751_STATUS_MPS 0x0200 115#define AGP_AMD751_STATUS_VBES 0x0100 116#define AGP_AMD751_STATUS_P2PE 0x0008 117#define AGP_AMD751_STATUS_GCE 0x0004 118#define AGP_AMD751_STATUS_VBEE 0x0001 119#define AGP_AMD751_ATTBASE 0x04 120#define AGP_AMD751_TLBCTRL 0x0c 121 122/* 123 * Config registers for i810 device 0 124 */ 125#define AGP_I810_SMRAM 0x70 126#define AGP_I810_SMRAM_GMS 0xc0 127#define AGP_I810_SMRAM_GMS_DISABLED 0x00 128#define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 129#define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 130#define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 131#define AGP_I810_MISCC 0x72 132#define AGP_I810_MISCC_WINSIZE 0x0001 133#define AGP_I810_MISCC_WINSIZE_64 0x0000 134#define AGP_I810_MISCC_WINSIZE_32 0x0001 135#define AGP_I810_MISCC_PLCK 0x0008 136#define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 137#define AGP_I810_MISCC_PLCK_LOCKED 0x0008 138#define AGP_I810_MISCC_WPTC 0x0030 139#define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 140#define AGP_I810_MISCC_WPTC_62 0x0010 141#define AGP_I810_MISCC_WPTC_50 0x0020 142#define AGP_I810_MISCC_WPTC_37 0x0030 143#define AGP_I810_MISCC_RPTC 0x00c0 144#define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 145#define AGP_I810_MISCC_RPTC_62 0x0040 146#define AGP_I810_MISCC_RPTC_50 0x0080 147#define AGP_I810_MISCC_RPTC_37 0x00c0 148 149/* 150 * Config registers for i810 device 1 151 */ 152#define AGP_I810_GMADR 0x10 153#define AGP_I810_MMADR 0x14 154 155/* 156 * Memory mapped register offsets for i810 chipset. 157 */ 158#define AGP_I810_PGTBL_CTL 0x2020 159#define AGP_I810_DRT 0x3000 160#define AGP_I810_DRT_UNPOPULATED 0x00 161#define AGP_I810_DRT_POPULATED 0x01 162#define AGP_I810_GTT 0x10000 163 164/* 165 * Config registers for i830MG device 0 166 */ 167#define AGP_I830_GCC1 0x52 168#define AGP_I830_GCC1_DEV2 0x08 169#define AGP_I830_GCC1_DEV2_ENABLED 0x00 170#define AGP_I830_GCC1_DEV2_DISABLED 0x08 171#define AGP_I830_GCC1_GMS 0x70 172#define AGP_I830_GCC1_GMS_STOLEN_512 0x20 173#define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 174#define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 175#define AGP_I830_GCC1_GMASIZE 0x01 176#define AGP_I830_GCC1_GMASIZE_64 0x01 177#define AGP_I830_GCC1_GMASIZE_128 0x00 178 179/* 180 * Config registers for 852GM/855GM/865G device 0 181 */ 182#define AGP_I855_GCC1 0x52 183#define AGP_I855_GCC1_DEV2 0x08 184#define AGP_I855_GCC1_DEV2_ENABLED 0x00 185#define AGP_I855_GCC1_DEV2_DISABLED 0x08 186#define AGP_I855_GCC1_GMS 0x70 187#define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 188#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 189#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 190#define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 191#define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 192#define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 193 194/* 195 * 852GM/855GM variant identification 196 */ 197#define AGP_I85X_CAPID 0x44 198#define AGP_I85X_VARIANT_MASK 0x7 199#define AGP_I85X_VARIANT_SHIFT 5 200#define AGP_I855_GME 0x0 201#define AGP_I855_GM 0x4 202#define AGP_I852_GME 0x2 203#define AGP_I852_GM 0x5 204 205/* 206 * NVIDIA nForce/nForce2 registers 207 */ 208#define AGP_NVIDIA_0_APBASE 0x10 209#define AGP_NVIDIA_0_APSIZE 0x80 210#define AGP_NVIDIA_1_WBC 0xf0 211#define AGP_NVIDIA_2_GARTCTRL 0xd0 212#define AGP_NVIDIA_2_APBASE 0xd8 213#define AGP_NVIDIA_2_APLIMIT 0xdc 214#define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4) 215#define AGP_NVIDIA_3_APBASE 0x50 216#define AGP_NVIDIA_3_APLIMIT 0x54 217 218#endif /* !_PCI_AGPREG_H_ */ 219