agpreg.h revision 171433
161452Sdfr/*- 261452Sdfr * Copyright (c) 2000 Doug Rabson 361452Sdfr * All rights reserved. 461452Sdfr * 561452Sdfr * Redistribution and use in source and binary forms, with or without 661452Sdfr * modification, are permitted provided that the following conditions 761452Sdfr * are met: 861452Sdfr * 1. Redistributions of source code must retain the above copyright 961452Sdfr * notice, this list of conditions and the following disclaimer. 1061452Sdfr * 2. Redistributions in binary form must reproduce the above copyright 1161452Sdfr * notice, this list of conditions and the following disclaimer in the 1261452Sdfr * documentation and/or other materials provided with the distribution. 1361452Sdfr * 1461452Sdfr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1561452Sdfr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1661452Sdfr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1761452Sdfr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1861452Sdfr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1961452Sdfr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2061452Sdfr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2161452Sdfr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2261452Sdfr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2361452Sdfr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2461452Sdfr * SUCH DAMAGE. 2561452Sdfr * 2661452Sdfr * $FreeBSD: head/sys/dev/agp/agpreg.h 171433 2007-07-13 16:28:12Z anholt $ 2761452Sdfr */ 2861452Sdfr 2961452Sdfr#ifndef _PCI_AGPREG_H_ 3061452Sdfr#define _PCI_AGPREG_H_ 3161452Sdfr 3261452Sdfr/* 3361452Sdfr * Offsets for various AGP configuration registers. 3461452Sdfr */ 35153580Sjhb#define AGP_APBASE PCIR_BAR(0) 3661452Sdfr 3761452Sdfr/* 3861452Sdfr * Offsets from the AGP Capability pointer. 3961452Sdfr */ 4061452Sdfr#define AGP_CAPID 0x0 4161452Sdfr#define AGP_STATUS 0x4 4261452Sdfr#define AGP_COMMAND 0x8 43127873Simp#define AGP_STATUS_AGP3 0x0008 44127873Simp#define AGP_STATUS_RQ_MASK 0xff000000 45127873Simp#define AGP_COMMAND_RQ_MASK 0xff000000 46127873Simp#define AGP_STATUS_ARQSZ_MASK 0xe000 47127873Simp#define AGP_COMMAND_ARQSZ_MASK 0xe000 48127873Simp#define AGP_STATUS_CAL_MASK 0x1c00 49127873Simp#define AGP_COMMAND_CAL_MASK 0x1c00 50127873Simp#define AGP_STATUS_ISOCH 0x10000 51127873Simp#define AGP_STATUS_SBA 0x0200 52127873Simp#define AGP_STATUS_ITA_COH 0x0100 53127873Simp#define AGP_STATUS_GART64 0x0080 54127873Simp#define AGP_STATUS_HTRANS 0x0040 55127873Simp#define AGP_STATUS_64BIT 0x0020 56127873Simp#define AGP_STATUS_FW 0x0010 57127873Simp#define AGP_COMMAND_RQ_MASK 0xff000000 58127873Simp#define AGP_COMMAND_ARQSZ_MASK 0xe000 59127873Simp#define AGP_COMMAND_CAL_MASK 0x1c00 60127873Simp#define AGP_COMMAND_SBA 0x0200 61127873Simp#define AGP_COMMAND_AGP 0x0100 62127873Simp#define AGP_COMMAND_GART64 0x0080 63127873Simp#define AGP_COMMAND_64BIT 0x0020 64127873Simp#define AGP_COMMAND_FW 0x0010 6561452Sdfr 6661452Sdfr/* 6761452Sdfr * Config offsets for Intel AGP chipsets. 6861452Sdfr */ 6961452Sdfr#define AGP_INTEL_NBXCFG 0x50 7061452Sdfr#define AGP_INTEL_ERRSTS 0x91 7161452Sdfr#define AGP_INTEL_AGPCTRL 0xb0 7261452Sdfr#define AGP_INTEL_APSIZE 0xb4 7361452Sdfr#define AGP_INTEL_ATTBASE 0xb8 7461452Sdfr 7561452Sdfr/* 76165815Sjkim * Config offsets for Intel i8xx/E7xxx AGP chipsets. 7786192Skuriyama */ 7886192Skuriyama#define AGP_INTEL_MCHCFG 0x50 7986192Skuriyama#define AGP_INTEL_I820_RDCR 0x51 80165815Sjkim#define AGP_INTEL_I845_AGPM 0x51 8186192Skuriyama#define AGP_INTEL_I8XX_ERRSTS 0xc8 8286192Skuriyama 8386192Skuriyama/* 84129189Sjhb * Config offsets for VIA AGP 2.x chipsets. 8561452Sdfr */ 8661452Sdfr#define AGP_VIA_GARTCTRL 0x80 8761452Sdfr#define AGP_VIA_APSIZE 0x84 8861452Sdfr#define AGP_VIA_ATTBASE 0x88 8961452Sdfr 9061452Sdfr/* 91129189Sjhb * Config offsets for VIA AGP 3.0 chipsets. 92129189Sjhb */ 93129189Sjhb#define AGP3_VIA_GARTCTRL 0x90 94129189Sjhb#define AGP3_VIA_APSIZE 0x94 95129189Sjhb#define AGP3_VIA_ATTBASE 0x98 96133406Sanholt#define AGP_VIA_AGPSEL 0xfd 97129189Sjhb 98129189Sjhb/* 9961452Sdfr * Config offsets for SiS AGP chipsets. 10061452Sdfr */ 10161452Sdfr#define AGP_SIS_ATTBASE 0x90 10261452Sdfr#define AGP_SIS_WINCTRL 0x94 10361452Sdfr#define AGP_SIS_TLBCTRL 0x97 10461452Sdfr#define AGP_SIS_TLBFLUSH 0x98 10561452Sdfr 10661452Sdfr/* 10761452Sdfr * Config offsets for Ali AGP chipsets. 10861452Sdfr */ 10961452Sdfr#define AGP_ALI_AGPCTRL 0xb8 11061452Sdfr#define AGP_ALI_ATTBASE 0xbc 11161452Sdfr#define AGP_ALI_TLBCTRL 0xc0 11261452Sdfr 11361452Sdfr/* 11461452Sdfr * Config offsets for the AMD 751 chipset. 11561452Sdfr */ 11687479Scokane#define AGP_AMD751_APBASE 0x10 11761452Sdfr#define AGP_AMD751_REGISTERS 0x14 11861452Sdfr#define AGP_AMD751_APCTRL 0xac 11961452Sdfr#define AGP_AMD751_MODECTRL 0xb0 12061501Sdfr#define AGP_AMD751_MODECTRL_SYNEN 0x80 12161501Sdfr#define AGP_AMD751_MODECTRL2 0xb2 12261501Sdfr#define AGP_AMD751_MODECTRL2_G1LM 0x01 12361501Sdfr#define AGP_AMD751_MODECTRL2_GPDCE 0x02 12461501Sdfr#define AGP_AMD751_MODECTRL2_NGSE 0x08 12561452Sdfr 12661452Sdfr/* 12761452Sdfr * Memory mapped register offsets for AMD 751 chipset. 12861452Sdfr */ 12961452Sdfr#define AGP_AMD751_CAPS 0x00 13061452Sdfr#define AGP_AMD751_CAPS_EHI 0x0800 13161452Sdfr#define AGP_AMD751_CAPS_P2P 0x0400 13261452Sdfr#define AGP_AMD751_CAPS_MPC 0x0200 13361452Sdfr#define AGP_AMD751_CAPS_VBE 0x0100 13461452Sdfr#define AGP_AMD751_CAPS_REV 0x00ff 13561452Sdfr#define AGP_AMD751_STATUS 0x02 13661452Sdfr#define AGP_AMD751_STATUS_P2PS 0x0800 13761452Sdfr#define AGP_AMD751_STATUS_GCS 0x0400 13861452Sdfr#define AGP_AMD751_STATUS_MPS 0x0200 13961452Sdfr#define AGP_AMD751_STATUS_VBES 0x0100 14061452Sdfr#define AGP_AMD751_STATUS_P2PE 0x0008 14161452Sdfr#define AGP_AMD751_STATUS_GCE 0x0004 14261452Sdfr#define AGP_AMD751_STATUS_VBEE 0x0001 14361452Sdfr#define AGP_AMD751_ATTBASE 0x04 14461452Sdfr#define AGP_AMD751_TLBCTRL 0x0c 14561452Sdfr 14663010Sdfr/* 14763010Sdfr * Config registers for i810 device 0 14863010Sdfr */ 14963010Sdfr#define AGP_I810_SMRAM 0x70 15063010Sdfr#define AGP_I810_SMRAM_GMS 0xc0 15163010Sdfr#define AGP_I810_SMRAM_GMS_DISABLED 0x00 15263010Sdfr#define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 15363010Sdfr#define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 15463010Sdfr#define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 15563010Sdfr#define AGP_I810_MISCC 0x72 15663010Sdfr#define AGP_I810_MISCC_WINSIZE 0x0001 15763010Sdfr#define AGP_I810_MISCC_WINSIZE_64 0x0000 15863010Sdfr#define AGP_I810_MISCC_WINSIZE_32 0x0001 15963010Sdfr#define AGP_I810_MISCC_PLCK 0x0008 16063010Sdfr#define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 16163010Sdfr#define AGP_I810_MISCC_PLCK_LOCKED 0x0008 16263010Sdfr#define AGP_I810_MISCC_WPTC 0x0030 16363010Sdfr#define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 16463010Sdfr#define AGP_I810_MISCC_WPTC_62 0x0010 16563010Sdfr#define AGP_I810_MISCC_WPTC_50 0x0020 16663010Sdfr#define AGP_I810_MISCC_WPTC_37 0x0030 16763010Sdfr#define AGP_I810_MISCC_RPTC 0x00c0 16863010Sdfr#define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 16963010Sdfr#define AGP_I810_MISCC_RPTC_62 0x0040 17063010Sdfr#define AGP_I810_MISCC_RPTC_50 0x0080 17163010Sdfr#define AGP_I810_MISCC_RPTC_37 0x00c0 17261452Sdfr 17363010Sdfr/* 17463010Sdfr * Config registers for i810 device 1 17563010Sdfr */ 17663010Sdfr#define AGP_I810_GMADR 0x10 17763010Sdfr#define AGP_I810_MMADR 0x14 17863010Sdfr 17963010Sdfr/* 18063010Sdfr * Memory mapped register offsets for i810 chipset. 18163010Sdfr */ 18263010Sdfr#define AGP_I810_PGTBL_CTL 0x2020 183171433Sanholt/** 184171433Sanholt * This field determines the actual size of the global GTT on the 965 185171433Sanholt * and G33 186171433Sanholt */ 187171433Sanholt#define AGP_I810_PGTBL_SIZE_MASK 0x0000000e 188171433Sanholt#define AGP_I810_PGTBL_SIZE_512KB (0 << 1) 189171433Sanholt#define AGP_I810_PGTBL_SIZE_256KB (1 << 1) 190171433Sanholt#define AGP_I810_PGTBL_SIZE_128KB (2 << 1) 19163010Sdfr#define AGP_I810_DRT 0x3000 19263010Sdfr#define AGP_I810_DRT_UNPOPULATED 0x00 19363010Sdfr#define AGP_I810_DRT_POPULATED 0x01 19463010Sdfr#define AGP_I810_GTT 0x10000 195171433Sanholt 196103243Sanholt/* 197103243Sanholt * Config registers for i830MG device 0 198103243Sanholt */ 199103243Sanholt#define AGP_I830_GCC1 0x52 200103243Sanholt#define AGP_I830_GCC1_DEV2 0x08 201103243Sanholt#define AGP_I830_GCC1_DEV2_ENABLED 0x00 202103243Sanholt#define AGP_I830_GCC1_DEV2_DISABLED 0x08 203171433Sanholt#define AGP_I830_GCC1_GMS 0xf0 /* Top bit reserved pre-G33 */ 204103243Sanholt#define AGP_I830_GCC1_GMS_STOLEN_512 0x20 205103243Sanholt#define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 206103243Sanholt#define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 207103243Sanholt#define AGP_I830_GCC1_GMASIZE 0x01 208103243Sanholt#define AGP_I830_GCC1_GMASIZE_64 0x01 209103243Sanholt#define AGP_I830_GCC1_GMASIZE_128 0x00 21063010Sdfr 211110814Sanholt/* 212110814Sanholt * Config registers for 852GM/855GM/865G device 0 213110814Sanholt */ 214110814Sanholt#define AGP_I855_GCC1 0x52 215110814Sanholt#define AGP_I855_GCC1_DEV2 0x08 216110814Sanholt#define AGP_I855_GCC1_DEV2_ENABLED 0x00 217110814Sanholt#define AGP_I855_GCC1_DEV2_DISABLED 0x08 218110814Sanholt#define AGP_I855_GCC1_GMS 0x70 219110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 220110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 221110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 222110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 223110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 224110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 225110814Sanholt 226110814Sanholt/* 227110814Sanholt * 852GM/855GM variant identification 228110814Sanholt */ 229110814Sanholt#define AGP_I85X_CAPID 0x44 230110814Sanholt#define AGP_I85X_VARIANT_MASK 0x7 231110814Sanholt#define AGP_I85X_VARIANT_SHIFT 5 232110814Sanholt#define AGP_I855_GME 0x0 233110814Sanholt#define AGP_I855_GM 0x4 234110814Sanholt#define AGP_I852_GME 0x2 235110814Sanholt#define AGP_I852_GM 0x5 236110814Sanholt 237119368Smdodd/* 238153031Sanholt * 915G registers 239153031Sanholt */ 240153031Sanholt#define AGP_I915_GMADR 0x18 241153031Sanholt#define AGP_I915_MMADR 0x10 242153031Sanholt#define AGP_I915_GTTADR 0x1C 243153031Sanholt#define AGP_I915_GCC1_GMS_STOLEN_48M 0x60 244153031Sanholt#define AGP_I915_GCC1_GMS_STOLEN_64M 0x70 245153031Sanholt#define AGP_I915_DEVEN 0x54 246153031Sanholt#define AGP_I915_DEVEN_D2F0 0x08 247153031Sanholt#define AGP_I915_DEVEN_D2F0_ENABLED 0x08 248153031Sanholt#define AGP_I915_DEVEN_D2F0_DISABLED 0x00 249153031Sanholt#define AGP_I915_MSAC 0x62 250153031Sanholt#define AGP_I915_MSAC_GMASIZE 0x02 251153031Sanholt#define AGP_I915_MSAC_GMASIZE_128 0x02 252153031Sanholt#define AGP_I915_MSAC_GMASIZE_256 0x00 253153031Sanholt 254153031Sanholt/* 255171433Sanholt * G965 registers 256171433Sanholt */ 257171433Sanholt#define AGP_I965_GTTMMADR 0x10 258171433Sanholt#define AGP_I965_MSAC 0x62 259171433Sanholt#define AGP_I965_MSAC_GMASIZE_128 0x00 260171433Sanholt#define AGP_I965_MSAC_GMASIZE_256 0x02 261171433Sanholt#define AGP_I965_MSAC_GMASIZE_512 0x06 262171433Sanholt 263171433Sanholt/* 264171433Sanholt * G33 registers 265171433Sanholt */ 266171433Sanholt#define AGP_G33_GCC1_GMS_STOLEN_128M 0x80 267171433Sanholt#define AGP_G33_GCC1_GMS_STOLEN_256M 0x90 268171433Sanholt 269171433Sanholt/* 270119368Smdodd * NVIDIA nForce/nForce2 registers 271119368Smdodd */ 272119368Smdodd#define AGP_NVIDIA_0_APBASE 0x10 273119368Smdodd#define AGP_NVIDIA_0_APSIZE 0x80 274119368Smdodd#define AGP_NVIDIA_1_WBC 0xf0 275119368Smdodd#define AGP_NVIDIA_2_GARTCTRL 0xd0 276119368Smdodd#define AGP_NVIDIA_2_APBASE 0xd8 277119368Smdodd#define AGP_NVIDIA_2_APLIMIT 0xdc 278119368Smdodd#define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4) 279119368Smdodd#define AGP_NVIDIA_3_APBASE 0x50 280119368Smdodd#define AGP_NVIDIA_3_APLIMIT 0x54 281119368Smdodd 282133852Sobrien/* 283133852Sobrien * AMD64 GART registers 284133852Sobrien */ 285133852Sobrien#define AGP_AMD64_APCTRL 0x90 286133852Sobrien#define AGP_AMD64_APBASE 0x94 287133852Sobrien#define AGP_AMD64_ATTBASE 0x98 288133852Sobrien#define AGP_AMD64_CACHECTRL 0x9c 289133852Sobrien#define AGP_AMD64_APCTRL_GARTEN 0x00000001 290133852Sobrien#define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e 291133852Sobrien#define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010 292133852Sobrien#define AGP_AMD64_APCTRL_DISGARTIO 0x00000020 293133852Sobrien#define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040 294133852Sobrien#define AGP_AMD64_APBASE_MASK 0x00007fff 295133852Sobrien#define AGP_AMD64_ATTBASE_MASK 0xfffffff0 296133852Sobrien#define AGP_AMD64_CACHECTRL_INVGART 0x00000001 297133852Sobrien#define AGP_AMD64_CACHECTRL_PTEERR 0x00000002 298133852Sobrien 299150236Sanholt/* 300150645Sjkim * NVIDIA nForce3 registers 301150645Sjkim */ 302150645Sjkim#define AGP_AMD64_NVIDIA_0_APBASE 0x10 303150645Sjkim#define AGP_AMD64_NVIDIA_1_APBASE1 0x50 304150645Sjkim#define AGP_AMD64_NVIDIA_1_APLIMIT1 0x54 305150645Sjkim#define AGP_AMD64_NVIDIA_1_APSIZE 0xa8 306150645Sjkim#define AGP_AMD64_NVIDIA_1_APBASE2 0xd8 307150645Sjkim#define AGP_AMD64_NVIDIA_1_APLIMIT2 0xdc 308150645Sjkim 309150645Sjkim/* 310150645Sjkim * ULi M1689 registers 311150645Sjkim */ 312150645Sjkim#define AGP_AMD64_ULI_APBASE 0x10 313150645Sjkim#define AGP_AMD64_ULI_HTT_FEATURE 0x50 314150645Sjkim#define AGP_AMD64_ULI_ENU_SCR 0x54 315150645Sjkim 316150645Sjkim/* 317150236Sanholt * ATI IGP registers 318150236Sanholt */ 319150236Sanholt#define ATI_GART_MMADDR 0x14 320150236Sanholt#define ATI_RS100_APSIZE 0xac 321150236Sanholt#define ATI_RS100_IG_AGPMODE 0xb0 322150236Sanholt#define ATI_RS300_APSIZE 0xf8 323150236Sanholt#define ATI_RS300_IG_AGPMODE 0xfc 324150236Sanholt#define ATI_GART_FEATURE_ID 0x00 325150236Sanholt#define ATI_GART_BASE 0x04 326150236Sanholt#define ATI_GART_CACHE_CNTRL 0x0c 327150236Sanholt 32861452Sdfr#endif /* !_PCI_AGPREG_H_ */ 329