agpreg.h revision 127873
161452Sdfr/*- 261452Sdfr * Copyright (c) 2000 Doug Rabson 361452Sdfr * All rights reserved. 461452Sdfr * 561452Sdfr * Redistribution and use in source and binary forms, with or without 661452Sdfr * modification, are permitted provided that the following conditions 761452Sdfr * are met: 861452Sdfr * 1. Redistributions of source code must retain the above copyright 961452Sdfr * notice, this list of conditions and the following disclaimer. 1061452Sdfr * 2. Redistributions in binary form must reproduce the above copyright 1161452Sdfr * notice, this list of conditions and the following disclaimer in the 1261452Sdfr * documentation and/or other materials provided with the distribution. 1361452Sdfr * 1461452Sdfr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1561452Sdfr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1661452Sdfr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1761452Sdfr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1861452Sdfr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1961452Sdfr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2061452Sdfr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2161452Sdfr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2261452Sdfr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2361452Sdfr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2461452Sdfr * SUCH DAMAGE. 2561452Sdfr * 2661452Sdfr * $FreeBSD: head/sys/dev/agp/agpreg.h 127873 2004-04-05 02:32:07Z imp $ 2761452Sdfr */ 2861452Sdfr 2961452Sdfr#ifndef _PCI_AGPREG_H_ 3061452Sdfr#define _PCI_AGPREG_H_ 3161452Sdfr 3261452Sdfr/* 3361452Sdfr * Offsets for various AGP configuration registers. 3461452Sdfr */ 3561452Sdfr#define AGP_APBASE 0x10 3661452Sdfr#define AGP_CAPPTR 0x34 3761452Sdfr 3861452Sdfr/* 3961452Sdfr * Offsets from the AGP Capability pointer. 4061452Sdfr */ 4161452Sdfr#define AGP_CAPID 0x0 4261452Sdfr#define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20) 4361452Sdfr#define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16) 4461452Sdfr#define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8) 4561452Sdfr#define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0) 4661452Sdfr 4761452Sdfr#define AGP_STATUS 0x4 4861452Sdfr#define AGP_COMMAND 0x8 49127873Simp#define AGP_STATUS_AGP3 0x0008 50127873Simp#define AGP_STATUS_RQ_MASK 0xff000000 51127873Simp#define AGP_COMMAND_RQ_MASK 0xff000000 52127873Simp#define AGP_STATUS_ARQSZ_MASK 0xe000 53127873Simp#define AGP_COMMAND_ARQSZ_MASK 0xe000 54127873Simp#define AGP_STATUS_CAL_MASK 0x1c00 55127873Simp#define AGP_COMMAND_CAL_MASK 0x1c00 56127873Simp#define AGP_STATUS_ISOCH 0x10000 57127873Simp#define AGP_STATUS_SBA 0x0200 58127873Simp#define AGP_STATUS_ITA_COH 0x0100 59127873Simp#define AGP_STATUS_GART64 0x0080 60127873Simp#define AGP_STATUS_HTRANS 0x0040 61127873Simp#define AGP_STATUS_64BIT 0x0020 62127873Simp#define AGP_STATUS_FW 0x0010 63127873Simp#define AGP_COMMAND_RQ_MASK 0xff000000 64127873Simp#define AGP_COMMAND_ARQSZ_MASK 0xe000 65127873Simp#define AGP_COMMAND_CAL_MASK 0x1c00 66127873Simp#define AGP_COMMAND_SBA 0x0200 67127873Simp#define AGP_COMMAND_AGP 0x0100 68127873Simp#define AGP_COMMAND_GART64 0x0080 69127873Simp#define AGP_COMMAND_64BIT 0x0020 70127873Simp#define AGP_COMMAND_FW 0x0010 7161452Sdfr 7261452Sdfr/* 7361452Sdfr * Config offsets for Intel AGP chipsets. 7461452Sdfr */ 7561452Sdfr#define AGP_INTEL_NBXCFG 0x50 7661452Sdfr#define AGP_INTEL_ERRSTS 0x91 7761452Sdfr#define AGP_INTEL_AGPCTRL 0xb0 7861452Sdfr#define AGP_INTEL_APSIZE 0xb4 7961452Sdfr#define AGP_INTEL_ATTBASE 0xb8 8061452Sdfr 8161452Sdfr/* 82115349Sjhb * Config offsets for Intel i820/i840/i845/i850/i860/i865 AGP chipsets. 8386192Skuriyama */ 8486192Skuriyama#define AGP_INTEL_MCHCFG 0x50 8586192Skuriyama#define AGP_INTEL_I820_RDCR 0x51 8686192Skuriyama#define AGP_INTEL_I845_MCHCFG 0x51 8786192Skuriyama#define AGP_INTEL_I8XX_ERRSTS 0xc8 8886192Skuriyama 8986192Skuriyama/* 9061452Sdfr * Config offsets for VIA AGP chipsets. 9161452Sdfr */ 9261452Sdfr#define AGP_VIA_GARTCTRL 0x80 9361452Sdfr#define AGP_VIA_APSIZE 0x84 9461452Sdfr#define AGP_VIA_ATTBASE 0x88 9561452Sdfr 9661452Sdfr/* 9761452Sdfr * Config offsets for SiS AGP chipsets. 9861452Sdfr */ 9961452Sdfr#define AGP_SIS_ATTBASE 0x90 10061452Sdfr#define AGP_SIS_WINCTRL 0x94 10161452Sdfr#define AGP_SIS_TLBCTRL 0x97 10261452Sdfr#define AGP_SIS_TLBFLUSH 0x98 10361452Sdfr 10461452Sdfr/* 10561452Sdfr * Config offsets for Ali AGP chipsets. 10661452Sdfr */ 10761452Sdfr#define AGP_ALI_AGPCTRL 0xb8 10861452Sdfr#define AGP_ALI_ATTBASE 0xbc 10961452Sdfr#define AGP_ALI_TLBCTRL 0xc0 11061452Sdfr 11161452Sdfr/* 11261452Sdfr * Config offsets for the AMD 751 chipset. 11361452Sdfr */ 11487479Scokane#define AGP_AMD751_APBASE 0x10 11561452Sdfr#define AGP_AMD751_REGISTERS 0x14 11661452Sdfr#define AGP_AMD751_APCTRL 0xac 11761452Sdfr#define AGP_AMD751_MODECTRL 0xb0 11861501Sdfr#define AGP_AMD751_MODECTRL_SYNEN 0x80 11961501Sdfr#define AGP_AMD751_MODECTRL2 0xb2 12061501Sdfr#define AGP_AMD751_MODECTRL2_G1LM 0x01 12161501Sdfr#define AGP_AMD751_MODECTRL2_GPDCE 0x02 12261501Sdfr#define AGP_AMD751_MODECTRL2_NGSE 0x08 12361452Sdfr 12461452Sdfr/* 12561452Sdfr * Memory mapped register offsets for AMD 751 chipset. 12661452Sdfr */ 12761452Sdfr#define AGP_AMD751_CAPS 0x00 12861452Sdfr#define AGP_AMD751_CAPS_EHI 0x0800 12961452Sdfr#define AGP_AMD751_CAPS_P2P 0x0400 13061452Sdfr#define AGP_AMD751_CAPS_MPC 0x0200 13161452Sdfr#define AGP_AMD751_CAPS_VBE 0x0100 13261452Sdfr#define AGP_AMD751_CAPS_REV 0x00ff 13361452Sdfr#define AGP_AMD751_STATUS 0x02 13461452Sdfr#define AGP_AMD751_STATUS_P2PS 0x0800 13561452Sdfr#define AGP_AMD751_STATUS_GCS 0x0400 13661452Sdfr#define AGP_AMD751_STATUS_MPS 0x0200 13761452Sdfr#define AGP_AMD751_STATUS_VBES 0x0100 13861452Sdfr#define AGP_AMD751_STATUS_P2PE 0x0008 13961452Sdfr#define AGP_AMD751_STATUS_GCE 0x0004 14061452Sdfr#define AGP_AMD751_STATUS_VBEE 0x0001 14161452Sdfr#define AGP_AMD751_ATTBASE 0x04 14261452Sdfr#define AGP_AMD751_TLBCTRL 0x0c 14361452Sdfr 14463010Sdfr/* 14563010Sdfr * Config registers for i810 device 0 14663010Sdfr */ 14763010Sdfr#define AGP_I810_SMRAM 0x70 14863010Sdfr#define AGP_I810_SMRAM_GMS 0xc0 14963010Sdfr#define AGP_I810_SMRAM_GMS_DISABLED 0x00 15063010Sdfr#define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 15163010Sdfr#define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 15263010Sdfr#define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 15363010Sdfr#define AGP_I810_MISCC 0x72 15463010Sdfr#define AGP_I810_MISCC_WINSIZE 0x0001 15563010Sdfr#define AGP_I810_MISCC_WINSIZE_64 0x0000 15663010Sdfr#define AGP_I810_MISCC_WINSIZE_32 0x0001 15763010Sdfr#define AGP_I810_MISCC_PLCK 0x0008 15863010Sdfr#define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 15963010Sdfr#define AGP_I810_MISCC_PLCK_LOCKED 0x0008 16063010Sdfr#define AGP_I810_MISCC_WPTC 0x0030 16163010Sdfr#define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 16263010Sdfr#define AGP_I810_MISCC_WPTC_62 0x0010 16363010Sdfr#define AGP_I810_MISCC_WPTC_50 0x0020 16463010Sdfr#define AGP_I810_MISCC_WPTC_37 0x0030 16563010Sdfr#define AGP_I810_MISCC_RPTC 0x00c0 16663010Sdfr#define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 16763010Sdfr#define AGP_I810_MISCC_RPTC_62 0x0040 16863010Sdfr#define AGP_I810_MISCC_RPTC_50 0x0080 16963010Sdfr#define AGP_I810_MISCC_RPTC_37 0x00c0 17061452Sdfr 17163010Sdfr/* 17263010Sdfr * Config registers for i810 device 1 17363010Sdfr */ 17463010Sdfr#define AGP_I810_GMADR 0x10 17563010Sdfr#define AGP_I810_MMADR 0x14 17663010Sdfr 17763010Sdfr/* 17863010Sdfr * Memory mapped register offsets for i810 chipset. 17963010Sdfr */ 18063010Sdfr#define AGP_I810_PGTBL_CTL 0x2020 18163010Sdfr#define AGP_I810_DRT 0x3000 18263010Sdfr#define AGP_I810_DRT_UNPOPULATED 0x00 18363010Sdfr#define AGP_I810_DRT_POPULATED 0x01 18463010Sdfr#define AGP_I810_GTT 0x10000 185103243Sanholt 186103243Sanholt/* 187103243Sanholt * Config registers for i830MG device 0 188103243Sanholt */ 189103243Sanholt#define AGP_I830_GCC1 0x52 190103243Sanholt#define AGP_I830_GCC1_DEV2 0x08 191103243Sanholt#define AGP_I830_GCC1_DEV2_ENABLED 0x00 192103243Sanholt#define AGP_I830_GCC1_DEV2_DISABLED 0x08 193103243Sanholt#define AGP_I830_GCC1_GMS 0x70 194103243Sanholt#define AGP_I830_GCC1_GMS_STOLEN_512 0x20 195103243Sanholt#define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 196103243Sanholt#define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 197103243Sanholt#define AGP_I830_GCC1_GMASIZE 0x01 198103243Sanholt#define AGP_I830_GCC1_GMASIZE_64 0x01 199103243Sanholt#define AGP_I830_GCC1_GMASIZE_128 0x00 20063010Sdfr 201110814Sanholt/* 202110814Sanholt * Config registers for 852GM/855GM/865G device 0 203110814Sanholt */ 204110814Sanholt#define AGP_I855_GCC1 0x52 205110814Sanholt#define AGP_I855_GCC1_DEV2 0x08 206110814Sanholt#define AGP_I855_GCC1_DEV2_ENABLED 0x00 207110814Sanholt#define AGP_I855_GCC1_DEV2_DISABLED 0x08 208110814Sanholt#define AGP_I855_GCC1_GMS 0x70 209110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 210110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 211110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 212110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 213110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 214110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 215110814Sanholt 216110814Sanholt/* 217110814Sanholt * 852GM/855GM variant identification 218110814Sanholt */ 219110814Sanholt#define AGP_I85X_CAPID 0x44 220110814Sanholt#define AGP_I85X_VARIANT_MASK 0x7 221110814Sanholt#define AGP_I85X_VARIANT_SHIFT 5 222110814Sanholt#define AGP_I855_GME 0x0 223110814Sanholt#define AGP_I855_GM 0x4 224110814Sanholt#define AGP_I852_GME 0x2 225110814Sanholt#define AGP_I852_GM 0x5 226110814Sanholt 227119368Smdodd/* 228119368Smdodd * NVIDIA nForce/nForce2 registers 229119368Smdodd */ 230119368Smdodd#define AGP_NVIDIA_0_APBASE 0x10 231119368Smdodd#define AGP_NVIDIA_0_APSIZE 0x80 232119368Smdodd#define AGP_NVIDIA_1_WBC 0xf0 233119368Smdodd#define AGP_NVIDIA_2_GARTCTRL 0xd0 234119368Smdodd#define AGP_NVIDIA_2_APBASE 0xd8 235119368Smdodd#define AGP_NVIDIA_2_APLIMIT 0xdc 236119368Smdodd#define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4) 237119368Smdodd#define AGP_NVIDIA_3_APBASE 0x50 238119368Smdodd#define AGP_NVIDIA_3_APLIMIT 0x54 239119368Smdodd 24061452Sdfr#endif /* !_PCI_AGPREG_H_ */ 241