agpreg.h revision 103243
161452Sdfr/*- 261452Sdfr * Copyright (c) 2000 Doug Rabson 361452Sdfr * All rights reserved. 461452Sdfr * 561452Sdfr * Redistribution and use in source and binary forms, with or without 661452Sdfr * modification, are permitted provided that the following conditions 761452Sdfr * are met: 861452Sdfr * 1. Redistributions of source code must retain the above copyright 961452Sdfr * notice, this list of conditions and the following disclaimer. 1061452Sdfr * 2. Redistributions in binary form must reproduce the above copyright 1161452Sdfr * notice, this list of conditions and the following disclaimer in the 1261452Sdfr * documentation and/or other materials provided with the distribution. 1361452Sdfr * 1461452Sdfr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1561452Sdfr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1661452Sdfr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1761452Sdfr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1861452Sdfr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1961452Sdfr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2061452Sdfr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2161452Sdfr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2261452Sdfr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2361452Sdfr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2461452Sdfr * SUCH DAMAGE. 2561452Sdfr * 2661452Sdfr * $FreeBSD: head/sys/dev/agp/agpreg.h 103243 2002-09-12 04:23:18Z anholt $ 2761452Sdfr */ 2861452Sdfr 2961452Sdfr#ifndef _PCI_AGPREG_H_ 3061452Sdfr#define _PCI_AGPREG_H_ 3161452Sdfr 3261452Sdfr/* 3361452Sdfr * Offsets for various AGP configuration registers. 3461452Sdfr */ 3561452Sdfr#define AGP_APBASE 0x10 3661452Sdfr#define AGP_CAPPTR 0x34 3761452Sdfr 3861452Sdfr/* 3961452Sdfr * Offsets from the AGP Capability pointer. 4061452Sdfr */ 4161452Sdfr#define AGP_CAPID 0x0 4261452Sdfr#define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20) 4361452Sdfr#define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16) 4461452Sdfr#define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8) 4561452Sdfr#define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0) 4661452Sdfr 4761452Sdfr#define AGP_STATUS 0x4 4861452Sdfr#define AGP_COMMAND 0x8 4961452Sdfr 5061452Sdfr/* 5161452Sdfr * Config offsets for Intel AGP chipsets. 5261452Sdfr */ 5361452Sdfr#define AGP_INTEL_NBXCFG 0x50 5461452Sdfr#define AGP_INTEL_ERRSTS 0x91 5561452Sdfr#define AGP_INTEL_AGPCTRL 0xb0 5661452Sdfr#define AGP_INTEL_APSIZE 0xb4 5761452Sdfr#define AGP_INTEL_ATTBASE 0xb8 5861452Sdfr 5961452Sdfr/* 6086192Skuriyama * Config offsets for Intel i820/i840/i845/i850/i860 AGP chipsets. 6186192Skuriyama */ 6286192Skuriyama#define AGP_INTEL_MCHCFG 0x50 6386192Skuriyama#define AGP_INTEL_I820_RDCR 0x51 6486192Skuriyama#define AGP_INTEL_I845_MCHCFG 0x51 6586192Skuriyama#define AGP_INTEL_I8XX_ERRSTS 0xc8 6686192Skuriyama 6786192Skuriyama/* 6861452Sdfr * Config offsets for VIA AGP chipsets. 6961452Sdfr */ 7061452Sdfr#define AGP_VIA_GARTCTRL 0x80 7161452Sdfr#define AGP_VIA_APSIZE 0x84 7261452Sdfr#define AGP_VIA_ATTBASE 0x88 7361452Sdfr 7461452Sdfr/* 7561452Sdfr * Config offsets for SiS AGP chipsets. 7661452Sdfr */ 7761452Sdfr#define AGP_SIS_ATTBASE 0x90 7861452Sdfr#define AGP_SIS_WINCTRL 0x94 7961452Sdfr#define AGP_SIS_TLBCTRL 0x97 8061452Sdfr#define AGP_SIS_TLBFLUSH 0x98 8161452Sdfr 8261452Sdfr/* 8361452Sdfr * Config offsets for Ali AGP chipsets. 8461452Sdfr */ 8561452Sdfr#define AGP_ALI_AGPCTRL 0xb8 8661452Sdfr#define AGP_ALI_ATTBASE 0xbc 8761452Sdfr#define AGP_ALI_TLBCTRL 0xc0 8861452Sdfr 8961452Sdfr/* 9061452Sdfr * Config offsets for the AMD 751 chipset. 9161452Sdfr */ 9287479Scokane#define AGP_AMD751_APBASE 0x10 9361452Sdfr#define AGP_AMD751_REGISTERS 0x14 9461452Sdfr#define AGP_AMD751_APCTRL 0xac 9561452Sdfr#define AGP_AMD751_MODECTRL 0xb0 9661501Sdfr#define AGP_AMD751_MODECTRL_SYNEN 0x80 9761501Sdfr#define AGP_AMD751_MODECTRL2 0xb2 9861501Sdfr#define AGP_AMD751_MODECTRL2_G1LM 0x01 9961501Sdfr#define AGP_AMD751_MODECTRL2_GPDCE 0x02 10061501Sdfr#define AGP_AMD751_MODECTRL2_NGSE 0x08 10161452Sdfr 10261452Sdfr/* 10361452Sdfr * Memory mapped register offsets for AMD 751 chipset. 10461452Sdfr */ 10561452Sdfr#define AGP_AMD751_CAPS 0x00 10661452Sdfr#define AGP_AMD751_CAPS_EHI 0x0800 10761452Sdfr#define AGP_AMD751_CAPS_P2P 0x0400 10861452Sdfr#define AGP_AMD751_CAPS_MPC 0x0200 10961452Sdfr#define AGP_AMD751_CAPS_VBE 0x0100 11061452Sdfr#define AGP_AMD751_CAPS_REV 0x00ff 11161452Sdfr#define AGP_AMD751_STATUS 0x02 11261452Sdfr#define AGP_AMD751_STATUS_P2PS 0x0800 11361452Sdfr#define AGP_AMD751_STATUS_GCS 0x0400 11461452Sdfr#define AGP_AMD751_STATUS_MPS 0x0200 11561452Sdfr#define AGP_AMD751_STATUS_VBES 0x0100 11661452Sdfr#define AGP_AMD751_STATUS_P2PE 0x0008 11761452Sdfr#define AGP_AMD751_STATUS_GCE 0x0004 11861452Sdfr#define AGP_AMD751_STATUS_VBEE 0x0001 11961452Sdfr#define AGP_AMD751_ATTBASE 0x04 12061452Sdfr#define AGP_AMD751_TLBCTRL 0x0c 12161452Sdfr 12263010Sdfr/* 12363010Sdfr * Config registers for i810 device 0 12463010Sdfr */ 12563010Sdfr#define AGP_I810_SMRAM 0x70 12663010Sdfr#define AGP_I810_SMRAM_GMS 0xc0 12763010Sdfr#define AGP_I810_SMRAM_GMS_DISABLED 0x00 12863010Sdfr#define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 12963010Sdfr#define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 13063010Sdfr#define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 13163010Sdfr#define AGP_I810_MISCC 0x72 13263010Sdfr#define AGP_I810_MISCC_WINSIZE 0x0001 13363010Sdfr#define AGP_I810_MISCC_WINSIZE_64 0x0000 13463010Sdfr#define AGP_I810_MISCC_WINSIZE_32 0x0001 13563010Sdfr#define AGP_I810_MISCC_PLCK 0x0008 13663010Sdfr#define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 13763010Sdfr#define AGP_I810_MISCC_PLCK_LOCKED 0x0008 13863010Sdfr#define AGP_I810_MISCC_WPTC 0x0030 13963010Sdfr#define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 14063010Sdfr#define AGP_I810_MISCC_WPTC_62 0x0010 14163010Sdfr#define AGP_I810_MISCC_WPTC_50 0x0020 14263010Sdfr#define AGP_I810_MISCC_WPTC_37 0x0030 14363010Sdfr#define AGP_I810_MISCC_RPTC 0x00c0 14463010Sdfr#define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 14563010Sdfr#define AGP_I810_MISCC_RPTC_62 0x0040 14663010Sdfr#define AGP_I810_MISCC_RPTC_50 0x0080 14763010Sdfr#define AGP_I810_MISCC_RPTC_37 0x00c0 14861452Sdfr 14963010Sdfr/* 15063010Sdfr * Config registers for i810 device 1 15163010Sdfr */ 15263010Sdfr#define AGP_I810_GMADR 0x10 15363010Sdfr#define AGP_I810_MMADR 0x14 15463010Sdfr 15563010Sdfr/* 15663010Sdfr * Memory mapped register offsets for i810 chipset. 15763010Sdfr */ 15863010Sdfr#define AGP_I810_PGTBL_CTL 0x2020 15963010Sdfr#define AGP_I810_DRT 0x3000 16063010Sdfr#define AGP_I810_DRT_UNPOPULATED 0x00 16163010Sdfr#define AGP_I810_DRT_POPULATED 0x01 16263010Sdfr#define AGP_I810_GTT 0x10000 163103243Sanholt 164103243Sanholt/* 165103243Sanholt * Config registers for i830MG device 0 166103243Sanholt */ 167103243Sanholt#define AGP_I830_GCC1 0x52 168103243Sanholt#define AGP_I830_GCC1_DEV2 0x08 169103243Sanholt#define AGP_I830_GCC1_DEV2_ENABLED 0x00 170103243Sanholt#define AGP_I830_GCC1_DEV2_DISABLED 0x08 171103243Sanholt#define AGP_I830_GCC1_GMS 0x70 172103243Sanholt#define AGP_I830_GCC1_GMS_STOLEN_512 0x20 173103243Sanholt#define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 174103243Sanholt#define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 175103243Sanholt#define AGP_I830_GCC1_GMASIZE 0x01 176103243Sanholt#define AGP_I830_GCC1_GMASIZE_64 0x01 177103243Sanholt#define AGP_I830_GCC1_GMASIZE_128 0x00 17863010Sdfr 17961452Sdfr#endif /* !_PCI_AGPREG_H_ */ 180