161452Sdfr/*- 261452Sdfr * Copyright (c) 2000 Doug Rabson 361452Sdfr * All rights reserved. 461452Sdfr * 561452Sdfr * Redistribution and use in source and binary forms, with or without 661452Sdfr * modification, are permitted provided that the following conditions 761452Sdfr * are met: 861452Sdfr * 1. Redistributions of source code must retain the above copyright 961452Sdfr * notice, this list of conditions and the following disclaimer. 1061452Sdfr * 2. Redistributions in binary form must reproduce the above copyright 1161452Sdfr * notice, this list of conditions and the following disclaimer in the 1261452Sdfr * documentation and/or other materials provided with the distribution. 1361452Sdfr * 1461452Sdfr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1561452Sdfr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1661452Sdfr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1761452Sdfr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1861452Sdfr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1961452Sdfr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2061452Sdfr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2161452Sdfr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2261452Sdfr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2361452Sdfr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2461452Sdfr * SUCH DAMAGE. 2561452Sdfr * 2661452Sdfr * $FreeBSD: releng/10.3/sys/dev/agp/agpreg.h 235782 2012-05-22 10:59:26Z kib $ 2761452Sdfr */ 2861452Sdfr 2961452Sdfr#ifndef _PCI_AGPREG_H_ 3061452Sdfr#define _PCI_AGPREG_H_ 3161452Sdfr 3261452Sdfr/* 3361452Sdfr * Offsets for various AGP configuration registers. 3461452Sdfr */ 35153580Sjhb#define AGP_APBASE PCIR_BAR(0) 3661452Sdfr 3761452Sdfr/* 3861452Sdfr * Offsets from the AGP Capability pointer. 3961452Sdfr */ 4061452Sdfr#define AGP_CAPID 0x0 4161452Sdfr#define AGP_STATUS 0x4 4261452Sdfr#define AGP_COMMAND 0x8 43127873Simp#define AGP_STATUS_AGP3 0x0008 44127873Simp#define AGP_STATUS_RQ_MASK 0xff000000 45127873Simp#define AGP_COMMAND_RQ_MASK 0xff000000 46127873Simp#define AGP_STATUS_ARQSZ_MASK 0xe000 47127873Simp#define AGP_COMMAND_ARQSZ_MASK 0xe000 48127873Simp#define AGP_STATUS_CAL_MASK 0x1c00 49127873Simp#define AGP_COMMAND_CAL_MASK 0x1c00 50127873Simp#define AGP_STATUS_ISOCH 0x10000 51127873Simp#define AGP_STATUS_SBA 0x0200 52127873Simp#define AGP_STATUS_ITA_COH 0x0100 53127873Simp#define AGP_STATUS_GART64 0x0080 54127873Simp#define AGP_STATUS_HTRANS 0x0040 55127873Simp#define AGP_STATUS_64BIT 0x0020 56127873Simp#define AGP_STATUS_FW 0x0010 57127873Simp#define AGP_COMMAND_RQ_MASK 0xff000000 58127873Simp#define AGP_COMMAND_ARQSZ_MASK 0xe000 59127873Simp#define AGP_COMMAND_CAL_MASK 0x1c00 60127873Simp#define AGP_COMMAND_SBA 0x0200 61127873Simp#define AGP_COMMAND_AGP 0x0100 62127873Simp#define AGP_COMMAND_GART64 0x0080 63127873Simp#define AGP_COMMAND_64BIT 0x0020 64127873Simp#define AGP_COMMAND_FW 0x0010 6561452Sdfr 6661452Sdfr/* 6761452Sdfr * Config offsets for Intel AGP chipsets. 6861452Sdfr */ 6961452Sdfr#define AGP_INTEL_NBXCFG 0x50 7061452Sdfr#define AGP_INTEL_ERRSTS 0x91 7161452Sdfr#define AGP_INTEL_AGPCTRL 0xb0 7261452Sdfr#define AGP_INTEL_APSIZE 0xb4 7361452Sdfr#define AGP_INTEL_ATTBASE 0xb8 7461452Sdfr 7561452Sdfr/* 76165815Sjkim * Config offsets for Intel i8xx/E7xxx AGP chipsets. 7786192Skuriyama */ 7886192Skuriyama#define AGP_INTEL_MCHCFG 0x50 7986192Skuriyama#define AGP_INTEL_I820_RDCR 0x51 80165815Sjkim#define AGP_INTEL_I845_AGPM 0x51 8186192Skuriyama#define AGP_INTEL_I8XX_ERRSTS 0xc8 8286192Skuriyama 8386192Skuriyama/* 84129189Sjhb * Config offsets for VIA AGP 2.x chipsets. 8561452Sdfr */ 8661452Sdfr#define AGP_VIA_GARTCTRL 0x80 8761452Sdfr#define AGP_VIA_APSIZE 0x84 8861452Sdfr#define AGP_VIA_ATTBASE 0x88 8961452Sdfr 9061452Sdfr/* 91129189Sjhb * Config offsets for VIA AGP 3.0 chipsets. 92129189Sjhb */ 93129189Sjhb#define AGP3_VIA_GARTCTRL 0x90 94129189Sjhb#define AGP3_VIA_APSIZE 0x94 95129189Sjhb#define AGP3_VIA_ATTBASE 0x98 96133406Sanholt#define AGP_VIA_AGPSEL 0xfd 97129189Sjhb 98129189Sjhb/* 9961452Sdfr * Config offsets for SiS AGP chipsets. 10061452Sdfr */ 10161452Sdfr#define AGP_SIS_ATTBASE 0x90 10261452Sdfr#define AGP_SIS_WINCTRL 0x94 10361452Sdfr#define AGP_SIS_TLBCTRL 0x97 10461452Sdfr#define AGP_SIS_TLBFLUSH 0x98 10561452Sdfr 10661452Sdfr/* 10761452Sdfr * Config offsets for Ali AGP chipsets. 10861452Sdfr */ 10961452Sdfr#define AGP_ALI_AGPCTRL 0xb8 11061452Sdfr#define AGP_ALI_ATTBASE 0xbc 11161452Sdfr#define AGP_ALI_TLBCTRL 0xc0 11261452Sdfr 11361452Sdfr/* 11461452Sdfr * Config offsets for the AMD 751 chipset. 11561452Sdfr */ 11687479Scokane#define AGP_AMD751_APBASE 0x10 11761452Sdfr#define AGP_AMD751_REGISTERS 0x14 11861452Sdfr#define AGP_AMD751_APCTRL 0xac 11961452Sdfr#define AGP_AMD751_MODECTRL 0xb0 12061501Sdfr#define AGP_AMD751_MODECTRL_SYNEN 0x80 12161501Sdfr#define AGP_AMD751_MODECTRL2 0xb2 12261501Sdfr#define AGP_AMD751_MODECTRL2_G1LM 0x01 12361501Sdfr#define AGP_AMD751_MODECTRL2_GPDCE 0x02 12461501Sdfr#define AGP_AMD751_MODECTRL2_NGSE 0x08 12561452Sdfr 12661452Sdfr/* 12761452Sdfr * Memory mapped register offsets for AMD 751 chipset. 12861452Sdfr */ 12961452Sdfr#define AGP_AMD751_CAPS 0x00 13061452Sdfr#define AGP_AMD751_CAPS_EHI 0x0800 13161452Sdfr#define AGP_AMD751_CAPS_P2P 0x0400 13261452Sdfr#define AGP_AMD751_CAPS_MPC 0x0200 13361452Sdfr#define AGP_AMD751_CAPS_VBE 0x0100 13461452Sdfr#define AGP_AMD751_CAPS_REV 0x00ff 13561452Sdfr#define AGP_AMD751_STATUS 0x02 13661452Sdfr#define AGP_AMD751_STATUS_P2PS 0x0800 13761452Sdfr#define AGP_AMD751_STATUS_GCS 0x0400 13861452Sdfr#define AGP_AMD751_STATUS_MPS 0x0200 13961452Sdfr#define AGP_AMD751_STATUS_VBES 0x0100 14061452Sdfr#define AGP_AMD751_STATUS_P2PE 0x0008 14161452Sdfr#define AGP_AMD751_STATUS_GCE 0x0004 14261452Sdfr#define AGP_AMD751_STATUS_VBEE 0x0001 14361452Sdfr#define AGP_AMD751_ATTBASE 0x04 14461452Sdfr#define AGP_AMD751_TLBCTRL 0x0c 14561452Sdfr 14663010Sdfr/* 14763010Sdfr * Config registers for i810 device 0 14863010Sdfr */ 14963010Sdfr#define AGP_I810_SMRAM 0x70 15063010Sdfr#define AGP_I810_SMRAM_GMS 0xc0 15163010Sdfr#define AGP_I810_SMRAM_GMS_DISABLED 0x00 15263010Sdfr#define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 15363010Sdfr#define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 15463010Sdfr#define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 15563010Sdfr#define AGP_I810_MISCC 0x72 15663010Sdfr#define AGP_I810_MISCC_WINSIZE 0x0001 15763010Sdfr#define AGP_I810_MISCC_WINSIZE_64 0x0000 15863010Sdfr#define AGP_I810_MISCC_WINSIZE_32 0x0001 15963010Sdfr#define AGP_I810_MISCC_PLCK 0x0008 16063010Sdfr#define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 16163010Sdfr#define AGP_I810_MISCC_PLCK_LOCKED 0x0008 16263010Sdfr#define AGP_I810_MISCC_WPTC 0x0030 16363010Sdfr#define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 16463010Sdfr#define AGP_I810_MISCC_WPTC_62 0x0010 16563010Sdfr#define AGP_I810_MISCC_WPTC_50 0x0020 16663010Sdfr#define AGP_I810_MISCC_WPTC_37 0x0030 16763010Sdfr#define AGP_I810_MISCC_RPTC 0x00c0 16863010Sdfr#define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 16963010Sdfr#define AGP_I810_MISCC_RPTC_62 0x0040 17063010Sdfr#define AGP_I810_MISCC_RPTC_50 0x0080 17163010Sdfr#define AGP_I810_MISCC_RPTC_37 0x00c0 17261452Sdfr 17363010Sdfr/* 17463010Sdfr * Config registers for i810 device 1 17563010Sdfr */ 17663010Sdfr#define AGP_I810_GMADR 0x10 17763010Sdfr#define AGP_I810_MMADR 0x14 17863010Sdfr 179235782Skib#define I810_PTE_VALID 0x00000001 180235782Skib 18163010Sdfr/* 182235782Skib * Cache control 183235782Skib * 184235782Skib * Pre-Sandybridge bits 185235782Skib */ 186235782Skib#define I810_PTE_MAIN_UNCACHED 0x00000000 187235782Skib#define I810_PTE_LOCAL 0x00000002 /* Non-snooped main phys memory */ 188235782Skib#define I830_PTE_SYSTEM_CACHED 0x00000006 /* Snooped main phys memory */ 189235782Skib 190235782Skib/* 191235782Skib * Sandybridge 192235782Skib * LLC - Last Level Cache 193235782Skib * MMC - Mid Level Cache 194235782Skib */ 195235782Skib#define GEN6_PTE_RESERVED 0x00000000 196235782Skib#define GEN6_PTE_UNCACHED 0x00000002 /* Do not cache */ 197235782Skib#define GEN6_PTE_LLC 0x00000004 /* Cache in LLC */ 198235782Skib#define GEN6_PTE_LLC_MLC 0x00000006 /* Cache in LLC and MLC */ 199235782Skib#define GEN6_PTE_GFDT 0x00000008 /* Graphics Data Type */ 200235782Skib 201235782Skib/* 20263010Sdfr * Memory mapped register offsets for i810 chipset. 20363010Sdfr */ 20463010Sdfr#define AGP_I810_PGTBL_CTL 0x2020 205235782Skib#define AGP_I810_PGTBL_ENABLED 0x00000001 206171433Sanholt/** 207171433Sanholt * This field determines the actual size of the global GTT on the 965 208171433Sanholt * and G33 209171433Sanholt */ 210171433Sanholt#define AGP_I810_PGTBL_SIZE_MASK 0x0000000e 211171433Sanholt#define AGP_I810_PGTBL_SIZE_512KB (0 << 1) 212171433Sanholt#define AGP_I810_PGTBL_SIZE_256KB (1 << 1) 213235782Skib#define AGP_I810_PGTBL_SIZE_128KB (2 << 1) 214235782Skib#define AGP_I810_PGTBL_SIZE_1MB (3 << 1) 215235782Skib#define AGP_I810_PGTBL_SIZE_2MB (4 << 1) 216235782Skib#define AGP_I810_PGTBL_SIZE_1_5MB (5 << 1) 217235782Skib#define AGP_G33_GCC1_SIZE_MASK (3 << 8) 218235782Skib#define AGP_G33_GCC1_SIZE_1M (1 << 8) 219235782Skib#define AGP_G33_GCC1_SIZE_2M (2 << 8) 220235782Skib#define AGP_G4x_GCC1_SIZE_MASK (0xf << 8) 221235782Skib#define AGP_G4x_GCC1_SIZE_1M (0x1 << 8) 222235782Skib#define AGP_G4x_GCC1_SIZE_2M (0x3 << 8) 223235782Skib#define AGP_G4x_GCC1_SIZE_VT_EN (0x8 << 8) 224235782Skib#define AGP_G4x_GCC1_SIZE_VT_1M \ 225235782Skib (AGP_G4x_GCC1_SIZE_1M | AGP_G4x_GCC1_SIZE_VT_EN) 226235782Skib#define AGP_G4x_GCC1_SIZE_VT_1_5M ((0x2 << 8) | AGP_G4x_GCC1_SIZE_VT_EN) 227235782Skib#define AGP_G4x_GCC1_SIZE_VT_2M \ 228235782Skib (AGP_G4x_GCC1_SIZE_2M | AGP_G4x_GCC1_SIZE_VT_EN) 229235782Skib 23063010Sdfr#define AGP_I810_DRT 0x3000 23163010Sdfr#define AGP_I810_DRT_UNPOPULATED 0x00 23263010Sdfr#define AGP_I810_DRT_POPULATED 0x01 23363010Sdfr#define AGP_I810_GTT 0x10000 234171433Sanholt 235103243Sanholt/* 236103243Sanholt * Config registers for i830MG device 0 237103243Sanholt */ 238103243Sanholt#define AGP_I830_GCC1 0x52 239103243Sanholt#define AGP_I830_GCC1_DEV2 0x08 240103243Sanholt#define AGP_I830_GCC1_DEV2_ENABLED 0x00 241103243Sanholt#define AGP_I830_GCC1_DEV2_DISABLED 0x08 242171433Sanholt#define AGP_I830_GCC1_GMS 0xf0 /* Top bit reserved pre-G33 */ 243103243Sanholt#define AGP_I830_GCC1_GMS_STOLEN_512 0x20 244103243Sanholt#define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 245103243Sanholt#define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 246103243Sanholt#define AGP_I830_GCC1_GMASIZE 0x01 247103243Sanholt#define AGP_I830_GCC1_GMASIZE_64 0x01 248103243Sanholt#define AGP_I830_GCC1_GMASIZE_128 0x00 249235782Skib#define AGP_I830_HIC 0x70 25063010Sdfr 251110814Sanholt/* 252110814Sanholt * Config registers for 852GM/855GM/865G device 0 253110814Sanholt */ 254110814Sanholt#define AGP_I855_GCC1 0x52 255110814Sanholt#define AGP_I855_GCC1_DEV2 0x08 256110814Sanholt#define AGP_I855_GCC1_DEV2_ENABLED 0x00 257110814Sanholt#define AGP_I855_GCC1_DEV2_DISABLED 0x08 258183555Srnoland#define AGP_I855_GCC1_GMS 0xf0 /* Top bit reserved pre-G33 */ 259110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 260110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 261110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 262110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 263110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 264110814Sanholt#define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 265110814Sanholt 266110814Sanholt/* 267110814Sanholt * 852GM/855GM variant identification 268110814Sanholt */ 269110814Sanholt#define AGP_I85X_CAPID 0x44 270110814Sanholt#define AGP_I85X_VARIANT_MASK 0x7 271110814Sanholt#define AGP_I85X_VARIANT_SHIFT 5 272110814Sanholt#define AGP_I855_GME 0x0 273110814Sanholt#define AGP_I855_GM 0x4 274110814Sanholt#define AGP_I852_GME 0x2 275110814Sanholt#define AGP_I852_GM 0x5 276110814Sanholt 277119368Smdodd/* 278153031Sanholt * 915G registers 279153031Sanholt */ 280153031Sanholt#define AGP_I915_GMADR 0x18 281153031Sanholt#define AGP_I915_MMADR 0x10 282153031Sanholt#define AGP_I915_GTTADR 0x1C 283153031Sanholt#define AGP_I915_GCC1_GMS_STOLEN_48M 0x60 284153031Sanholt#define AGP_I915_GCC1_GMS_STOLEN_64M 0x70 285153031Sanholt#define AGP_I915_DEVEN 0x54 286235782Skib#define AGP_SB_DEVEN_D2EN 0x10 /* SB+ has IGD enabled bit */ 287235782Skib#define AGP_SB_DEVEN_D2EN_ENABLED 0x10 /* in different place */ 288235782Skib#define AGP_SB_DEVEN_D2EN_DISABLED 0x00 289153031Sanholt#define AGP_I915_DEVEN_D2F0 0x08 290153031Sanholt#define AGP_I915_DEVEN_D2F0_ENABLED 0x08 291153031Sanholt#define AGP_I915_DEVEN_D2F0_DISABLED 0x00 292153031Sanholt#define AGP_I915_MSAC 0x62 293153031Sanholt#define AGP_I915_MSAC_GMASIZE 0x02 294153031Sanholt#define AGP_I915_MSAC_GMASIZE_128 0x02 295153031Sanholt#define AGP_I915_MSAC_GMASIZE_256 0x00 296235782Skib#define AGP_I915_IFPADDR 0x60 297153031Sanholt 298153031Sanholt/* 299171433Sanholt * G965 registers 300171433Sanholt */ 301171433Sanholt#define AGP_I965_GTTMMADR 0x10 302171433Sanholt#define AGP_I965_MSAC 0x62 303171433Sanholt#define AGP_I965_MSAC_GMASIZE_128 0x00 304171433Sanholt#define AGP_I965_MSAC_GMASIZE_256 0x02 305171433Sanholt#define AGP_I965_MSAC_GMASIZE_512 0x06 306183555Srnoland#define AGP_I965_PGTBL_SIZE_1MB (3 << 1) 307183555Srnoland#define AGP_I965_PGTBL_SIZE_2MB (4 << 1) 308183555Srnoland#define AGP_I965_PGTBL_SIZE_1_5MB (5 << 1) 309235782Skib#define AGP_I965_PGTBL_CTL2 0x20c4 310235782Skib#define AGP_I965_IFPADDR 0x70 311171433Sanholt 312171433Sanholt/* 313171433Sanholt * G33 registers 314171433Sanholt */ 315183555Srnoland#define AGP_G33_MGGC_GGMS_MASK (3 << 8) 316183555Srnoland#define AGP_G33_MGGC_GGMS_SIZE_1M (1 << 8) 317183555Srnoland#define AGP_G33_MGGC_GGMS_SIZE_2M (2 << 8) 318171433Sanholt#define AGP_G33_GCC1_GMS_STOLEN_128M 0x80 319171433Sanholt#define AGP_G33_GCC1_GMS_STOLEN_256M 0x90 320171433Sanholt 321171433Sanholt/* 322183555Srnoland * G4X registers 323183555Srnoland */ 324235782Skib#define AGP_G4X_GMADR 0x20 325235782Skib#define AGP_G4X_MMADR 0x10 326235782Skib#define AGP_G4X_GTTADR 0x18 327183555Srnoland#define AGP_G4X_GCC1_GMS_STOLEN_96M 0xa0 328183555Srnoland#define AGP_G4X_GCC1_GMS_STOLEN_160M 0xb0 329183555Srnoland#define AGP_G4X_GCC1_GMS_STOLEN_224M 0xc0 330183555Srnoland#define AGP_G4X_GCC1_GMS_STOLEN_352M 0xd0 331183555Srnoland 332183555Srnoland/* 333235782Skib * SandyBridge/IvyBridge registers 334235782Skib */ 335235782Skib#define AGP_SNB_GCC1 0x50 336235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_MASK 0xF8 337235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_32M (1 << 3) 338235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_64M (2 << 3) 339235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_96M (3 << 3) 340235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_128M (4 << 3) 341235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_160M (5 << 3) 342235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_192M (6 << 3) 343235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_224M (7 << 3) 344235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_256M (8 << 3) 345235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_288M (9 << 3) 346235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_320M (0xa << 3) 347235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_352M (0xb << 3) 348235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_384M (0xc << 3) 349235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_416M (0xd << 3) 350235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_448M (0xe << 3) 351235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_480M (0xf << 3) 352235782Skib#define AGP_SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) 353235782Skib#define AGP_SNB_GTT_SIZE_0M (0 << 8) 354235782Skib#define AGP_SNB_GTT_SIZE_1M (1 << 8) 355235782Skib#define AGP_SNB_GTT_SIZE_2M (2 << 8) 356235782Skib#define AGP_SNB_GTT_SIZE_MASK (3 << 8) 357235782Skib 358235782Skib#define AGP_SNB_GFX_MODE 0x02520 359235782Skib 360235782Skib/* 361119368Smdodd * NVIDIA nForce/nForce2 registers 362119368Smdodd */ 363119368Smdodd#define AGP_NVIDIA_0_APBASE 0x10 364119368Smdodd#define AGP_NVIDIA_0_APSIZE 0x80 365119368Smdodd#define AGP_NVIDIA_1_WBC 0xf0 366119368Smdodd#define AGP_NVIDIA_2_GARTCTRL 0xd0 367119368Smdodd#define AGP_NVIDIA_2_APBASE 0xd8 368119368Smdodd#define AGP_NVIDIA_2_APLIMIT 0xdc 369119368Smdodd#define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4) 370119368Smdodd#define AGP_NVIDIA_3_APBASE 0x50 371119368Smdodd#define AGP_NVIDIA_3_APLIMIT 0x54 372119368Smdodd 373133852Sobrien/* 374133852Sobrien * AMD64 GART registers 375133852Sobrien */ 376133852Sobrien#define AGP_AMD64_APCTRL 0x90 377133852Sobrien#define AGP_AMD64_APBASE 0x94 378133852Sobrien#define AGP_AMD64_ATTBASE 0x98 379133852Sobrien#define AGP_AMD64_CACHECTRL 0x9c 380133852Sobrien#define AGP_AMD64_APCTRL_GARTEN 0x00000001 381133852Sobrien#define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e 382133852Sobrien#define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010 383133852Sobrien#define AGP_AMD64_APCTRL_DISGARTIO 0x00000020 384133852Sobrien#define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040 385133852Sobrien#define AGP_AMD64_APBASE_MASK 0x00007fff 386133852Sobrien#define AGP_AMD64_ATTBASE_MASK 0xfffffff0 387133852Sobrien#define AGP_AMD64_CACHECTRL_INVGART 0x00000001 388133852Sobrien#define AGP_AMD64_CACHECTRL_PTEERR 0x00000002 389133852Sobrien 390150236Sanholt/* 391150645Sjkim * NVIDIA nForce3 registers 392150645Sjkim */ 393150645Sjkim#define AGP_AMD64_NVIDIA_0_APBASE 0x10 394150645Sjkim#define AGP_AMD64_NVIDIA_1_APBASE1 0x50 395150645Sjkim#define AGP_AMD64_NVIDIA_1_APLIMIT1 0x54 396150645Sjkim#define AGP_AMD64_NVIDIA_1_APSIZE 0xa8 397150645Sjkim#define AGP_AMD64_NVIDIA_1_APBASE2 0xd8 398150645Sjkim#define AGP_AMD64_NVIDIA_1_APLIMIT2 0xdc 399150645Sjkim 400150645Sjkim/* 401150645Sjkim * ULi M1689 registers 402150645Sjkim */ 403150645Sjkim#define AGP_AMD64_ULI_APBASE 0x10 404150645Sjkim#define AGP_AMD64_ULI_HTT_FEATURE 0x50 405150645Sjkim#define AGP_AMD64_ULI_ENU_SCR 0x54 406150645Sjkim 407150645Sjkim/* 408150236Sanholt * ATI IGP registers 409150236Sanholt */ 410150236Sanholt#define ATI_GART_MMADDR 0x14 411150236Sanholt#define ATI_RS100_APSIZE 0xac 412150236Sanholt#define ATI_RS100_IG_AGPMODE 0xb0 413150236Sanholt#define ATI_RS300_APSIZE 0xf8 414150236Sanholt#define ATI_RS300_IG_AGPMODE 0xfc 415150236Sanholt#define ATI_GART_FEATURE_ID 0x00 416150236Sanholt#define ATI_GART_BASE 0x04 417150236Sanholt#define ATI_GART_CACHE_CNTRL 0x0c 418150236Sanholt 41961452Sdfr#endif /* !_PCI_AGPREG_H_ */ 420