adwcam.c revision 67888
140024Sgibbs/* 240024Sgibbs * CAM SCSI interface for the the Advanced Systems Inc. 340024Sgibbs * Second Generation SCSI controllers. 440024Sgibbs * 540024Sgibbs * Product specific probe and attach routines can be found in: 640024Sgibbs * 756979Sgibbs * adw_pci.c ABP[3]940UW, ABP950UW, ABP3940U2W 840024Sgibbs * 956979Sgibbs * Copyright (c) 1998, 1999, 2000 Justin Gibbs. 1040024Sgibbs * All rights reserved. 1140024Sgibbs * 1240024Sgibbs * Redistribution and use in source and binary forms, with or without 1340024Sgibbs * modification, are permitted provided that the following conditions 1440024Sgibbs * are met: 1540024Sgibbs * 1. Redistributions of source code must retain the above copyright 1640024Sgibbs * notice, this list of conditions, and the following disclaimer, 1756979Sgibbs * without modification. 1840024Sgibbs * 2. The name of the author may not be used to endorse or promote products 1940024Sgibbs * derived from this software without specific prior written permission. 2040024Sgibbs * 2140024Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2240024Sgibbs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2340024Sgibbs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2440024Sgibbs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2540024Sgibbs * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2640024Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2740024Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2840024Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2940024Sgibbs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3040024Sgibbs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3140024Sgibbs * SUCH DAMAGE. 3240024Sgibbs * 3350477Speter * $FreeBSD: head/sys/dev/advansys/adwcam.c 67888 2000-10-29 15:47:16Z dwmalone $ 3440024Sgibbs */ 3540024Sgibbs/* 3640024Sgibbs * Ported from: 3740024Sgibbs * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 3840024Sgibbs * 3940024Sgibbs * Copyright (c) 1995-1998 Advanced System Products, Inc. 4040024Sgibbs * All Rights Reserved. 4140024Sgibbs * 4240024Sgibbs * Redistribution and use in source and binary forms, with or without 4340024Sgibbs * modification, are permitted provided that redistributions of source 4440024Sgibbs * code retain the above copyright notice and this comment without 4540024Sgibbs * modification. 4640024Sgibbs */ 4740024Sgibbs 4840024Sgibbs#include <sys/param.h> 4940024Sgibbs#include <sys/systm.h> 5040024Sgibbs#include <sys/kernel.h> 5140024Sgibbs#include <sys/malloc.h> 5256979Sgibbs#include <sys/bus.h> 5340024Sgibbs 5440024Sgibbs#include <machine/bus_pio.h> 5540024Sgibbs#include <machine/bus_memio.h> 5640024Sgibbs#include <machine/bus.h> 5756979Sgibbs#include <machine/resource.h> 5840024Sgibbs 5956979Sgibbs#include <sys/rman.h> 6056979Sgibbs 6140024Sgibbs#include <cam/cam.h> 6240024Sgibbs#include <cam/cam_ccb.h> 6340024Sgibbs#include <cam/cam_sim.h> 6440024Sgibbs#include <cam/cam_xpt_sim.h> 6540024Sgibbs#include <cam/cam_debug.h> 6640024Sgibbs 6740024Sgibbs#include <cam/scsi/scsi_message.h> 6840024Sgibbs 6940024Sgibbs#include <dev/advansys/adwvar.h> 7040024Sgibbs 7140024Sgibbs/* Definitions for our use of the SIM private CCB area */ 7240024Sgibbs#define ccb_acb_ptr spriv_ptr0 7340024Sgibbs#define ccb_adw_ptr spriv_ptr1 7440024Sgibbs 7540024Sgibbs#define MIN(a, b) (((a) < (b)) ? (a) : (b)) 7640024Sgibbs 7740024Sgibbsu_long adw_unit; 7840024Sgibbs 7957679Sgibbsstatic __inline cam_status adwccbstatus(union ccb*); 8040024Sgibbsstatic __inline struct acb* adwgetacb(struct adw_softc *adw); 8140024Sgibbsstatic __inline void adwfreeacb(struct adw_softc *adw, 8240024Sgibbs struct acb *acb); 8340024Sgibbs 8440024Sgibbsstatic void adwmapmem(void *arg, bus_dma_segment_t *segs, 8540024Sgibbs int nseg, int error); 8640024Sgibbsstatic struct sg_map_node* 8740024Sgibbs adwallocsgmap(struct adw_softc *adw); 8840024Sgibbsstatic int adwallocacbs(struct adw_softc *adw); 8940024Sgibbs 9040024Sgibbsstatic void adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs, 9140024Sgibbs int nseg, int error); 9240024Sgibbsstatic void adw_action(struct cam_sim *sim, union ccb *ccb); 9340024Sgibbsstatic void adw_poll(struct cam_sim *sim); 9440024Sgibbsstatic void adw_async(void *callback_arg, u_int32_t code, 9540024Sgibbs struct cam_path *path, void *arg); 9640024Sgibbsstatic void adwprocesserror(struct adw_softc *adw, struct acb *acb); 9740024Sgibbsstatic void adwtimeout(void *arg); 9840024Sgibbsstatic void adw_handle_device_reset(struct adw_softc *adw, 9940024Sgibbs u_int target); 10040024Sgibbsstatic void adw_handle_bus_reset(struct adw_softc *adw, 10140024Sgibbs int initiated); 10240024Sgibbs 10357679Sgibbsstatic __inline cam_status 10457679Sgibbsadwccbstatus(union ccb* ccb) 10557679Sgibbs{ 10657679Sgibbs return (ccb->ccb_h.status & CAM_STATUS_MASK); 10757679Sgibbs} 10857679Sgibbs 10940024Sgibbsstatic __inline struct acb* 11040024Sgibbsadwgetacb(struct adw_softc *adw) 11140024Sgibbs{ 11240024Sgibbs struct acb* acb; 11340024Sgibbs int s; 11440024Sgibbs 11540024Sgibbs s = splcam(); 11640024Sgibbs if ((acb = SLIST_FIRST(&adw->free_acb_list)) != NULL) { 11740024Sgibbs SLIST_REMOVE_HEAD(&adw->free_acb_list, links); 11840024Sgibbs } else if (adw->num_acbs < adw->max_acbs) { 11940024Sgibbs adwallocacbs(adw); 12040024Sgibbs acb = SLIST_FIRST(&adw->free_acb_list); 12140024Sgibbs if (acb == NULL) 12240024Sgibbs printf("%s: Can't malloc ACB\n", adw_name(adw)); 12340024Sgibbs else { 12440024Sgibbs SLIST_REMOVE_HEAD(&adw->free_acb_list, links); 12540024Sgibbs } 12640024Sgibbs } 12740024Sgibbs splx(s); 12840024Sgibbs 12940024Sgibbs return (acb); 13040024Sgibbs} 13140024Sgibbs 13240024Sgibbsstatic __inline void 13340024Sgibbsadwfreeacb(struct adw_softc *adw, struct acb *acb) 13440024Sgibbs{ 13540024Sgibbs int s; 13640024Sgibbs 13740024Sgibbs s = splcam(); 13840024Sgibbs if ((acb->state & ACB_ACTIVE) != 0) 13940024Sgibbs LIST_REMOVE(&acb->ccb->ccb_h, sim_links.le); 14040024Sgibbs if ((acb->state & ACB_RELEASE_SIMQ) != 0) 14140024Sgibbs acb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 14240024Sgibbs else if ((adw->state & ADW_RESOURCE_SHORTAGE) != 0 14340024Sgibbs && (acb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) { 14440024Sgibbs acb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 14540024Sgibbs adw->state &= ~ADW_RESOURCE_SHORTAGE; 14640024Sgibbs } 14740024Sgibbs acb->state = ACB_FREE; 14840024Sgibbs SLIST_INSERT_HEAD(&adw->free_acb_list, acb, links); 14940024Sgibbs splx(s); 15040024Sgibbs} 15140024Sgibbs 15240024Sgibbsstatic void 15340024Sgibbsadwmapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error) 15440024Sgibbs{ 15540024Sgibbs bus_addr_t *busaddrp; 15640024Sgibbs 15740024Sgibbs busaddrp = (bus_addr_t *)arg; 15840024Sgibbs *busaddrp = segs->ds_addr; 15940024Sgibbs} 16040024Sgibbs 16140024Sgibbsstatic struct sg_map_node * 16240024Sgibbsadwallocsgmap(struct adw_softc *adw) 16340024Sgibbs{ 16440024Sgibbs struct sg_map_node *sg_map; 16540024Sgibbs 16640024Sgibbs sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 16740024Sgibbs 16840024Sgibbs if (sg_map == NULL) 16940024Sgibbs return (NULL); 17040024Sgibbs 17140024Sgibbs /* Allocate S/G space for the next batch of ACBS */ 17240024Sgibbs if (bus_dmamem_alloc(adw->sg_dmat, (void **)&sg_map->sg_vaddr, 17340024Sgibbs BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { 17440024Sgibbs free(sg_map, M_DEVBUF); 17540024Sgibbs return (NULL); 17640024Sgibbs } 17740024Sgibbs 17840024Sgibbs SLIST_INSERT_HEAD(&adw->sg_maps, sg_map, links); 17940024Sgibbs 18040024Sgibbs bus_dmamap_load(adw->sg_dmat, sg_map->sg_dmamap, sg_map->sg_vaddr, 18140024Sgibbs PAGE_SIZE, adwmapmem, &sg_map->sg_physaddr, /*flags*/0); 18240024Sgibbs 18340024Sgibbs bzero(sg_map->sg_vaddr, PAGE_SIZE); 18440024Sgibbs return (sg_map); 18540024Sgibbs} 18640024Sgibbs 18740024Sgibbs/* 18840024Sgibbs * Allocate another chunk of CCB's. Return count of entries added. 18940024Sgibbs * Assumed to be called at splcam(). 19040024Sgibbs */ 19140024Sgibbsstatic int 19240024Sgibbsadwallocacbs(struct adw_softc *adw) 19340024Sgibbs{ 19440024Sgibbs struct acb *next_acb; 19540024Sgibbs struct sg_map_node *sg_map; 19640024Sgibbs bus_addr_t busaddr; 19740024Sgibbs struct adw_sg_block *blocks; 19840024Sgibbs int newcount; 19940024Sgibbs int i; 20040024Sgibbs 20140024Sgibbs next_acb = &adw->acbs[adw->num_acbs]; 20240024Sgibbs sg_map = adwallocsgmap(adw); 20340024Sgibbs 20440024Sgibbs if (sg_map == NULL) 20540024Sgibbs return (0); 20640024Sgibbs 20740024Sgibbs blocks = sg_map->sg_vaddr; 20840024Sgibbs busaddr = sg_map->sg_physaddr; 20940024Sgibbs 21040024Sgibbs newcount = (PAGE_SIZE / (ADW_SG_BLOCKCNT * sizeof(*blocks))); 21140024Sgibbs for (i = 0; adw->num_acbs < adw->max_acbs && i < newcount; i++) { 21240024Sgibbs int error; 21340024Sgibbs 21440024Sgibbs error = bus_dmamap_create(adw->buffer_dmat, /*flags*/0, 21540024Sgibbs &next_acb->dmamap); 21640024Sgibbs if (error != 0) 21740024Sgibbs break; 21856979Sgibbs next_acb->queue.scsi_req_baddr = acbvtob(adw, next_acb); 21956979Sgibbs next_acb->queue.scsi_req_bo = acbvtobo(adw, next_acb); 22056979Sgibbs next_acb->queue.sense_baddr = 22156979Sgibbs acbvtob(adw, next_acb) + offsetof(struct acb, sense_data); 22240024Sgibbs next_acb->sg_blocks = blocks; 22340024Sgibbs next_acb->sg_busaddr = busaddr; 22440024Sgibbs next_acb->state = ACB_FREE; 22540024Sgibbs SLIST_INSERT_HEAD(&adw->free_acb_list, next_acb, links); 22640024Sgibbs blocks += ADW_SG_BLOCKCNT; 22740024Sgibbs busaddr += ADW_SG_BLOCKCNT * sizeof(*blocks); 22840024Sgibbs next_acb++; 22940024Sgibbs adw->num_acbs++; 23040024Sgibbs } 23140024Sgibbs return (i); 23240024Sgibbs} 23340024Sgibbs 23440024Sgibbsstatic void 23540024Sgibbsadwexecuteacb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 23640024Sgibbs{ 23740024Sgibbs struct acb *acb; 23840024Sgibbs union ccb *ccb; 23940024Sgibbs struct adw_softc *adw; 24040420Sgibbs int s; 24140024Sgibbs 24240024Sgibbs acb = (struct acb *)arg; 24340024Sgibbs ccb = acb->ccb; 24440024Sgibbs adw = (struct adw_softc *)ccb->ccb_h.ccb_adw_ptr; 24540024Sgibbs 24640024Sgibbs if (error != 0) { 24740024Sgibbs if (error != EFBIG) 24840024Sgibbs printf("%s: Unexepected error 0x%x returned from " 24940024Sgibbs "bus_dmamap_load\n", adw_name(adw), error); 25040024Sgibbs if (ccb->ccb_h.status == CAM_REQ_INPROG) { 25140024Sgibbs xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 25240024Sgibbs ccb->ccb_h.status = CAM_REQ_TOO_BIG|CAM_DEV_QFRZN; 25340024Sgibbs } 25440024Sgibbs adwfreeacb(adw, acb); 25540024Sgibbs xpt_done(ccb); 25640024Sgibbs return; 25740024Sgibbs } 25840024Sgibbs 25940024Sgibbs if (nseg != 0) { 26040024Sgibbs bus_dmasync_op_t op; 26140024Sgibbs 26240024Sgibbs acb->queue.data_addr = dm_segs[0].ds_addr; 26340024Sgibbs acb->queue.data_cnt = ccb->csio.dxfer_len; 26440024Sgibbs if (nseg > 1) { 26540024Sgibbs struct adw_sg_block *sg_block; 26640024Sgibbs struct adw_sg_elm *sg; 26740024Sgibbs bus_addr_t sg_busaddr; 26840024Sgibbs u_int sg_index; 26940024Sgibbs bus_dma_segment_t *end_seg; 27040024Sgibbs 27140024Sgibbs end_seg = dm_segs + nseg; 27240024Sgibbs 27340024Sgibbs sg_busaddr = acb->sg_busaddr; 27440024Sgibbs sg_index = 0; 27540024Sgibbs /* Copy the segments into our SG list */ 27640024Sgibbs for (sg_block = acb->sg_blocks;; sg_block++) { 27756979Sgibbs u_int i; 27840024Sgibbs 27940024Sgibbs sg = sg_block->sg_list; 28056979Sgibbs for (i = 0; i < ADW_NO_OF_SG_PER_BLOCK; i++) { 28156979Sgibbs if (dm_segs >= end_seg) 28256979Sgibbs break; 28356979Sgibbs 28440024Sgibbs sg->sg_addr = dm_segs->ds_addr; 28540024Sgibbs sg->sg_count = dm_segs->ds_len; 28640024Sgibbs sg++; 28740024Sgibbs dm_segs++; 28840024Sgibbs } 28956979Sgibbs sg_block->sg_cnt = i; 29056979Sgibbs sg_index += i; 29140024Sgibbs if (dm_segs == end_seg) { 29240024Sgibbs sg_block->sg_busaddr_next = 0; 29340024Sgibbs break; 29440024Sgibbs } else { 29540024Sgibbs sg_busaddr += 29640024Sgibbs sizeof(struct adw_sg_block); 29740024Sgibbs sg_block->sg_busaddr_next = sg_busaddr; 29840024Sgibbs } 29940024Sgibbs } 30040024Sgibbs acb->queue.sg_real_addr = acb->sg_busaddr; 30140024Sgibbs } else { 30240024Sgibbs acb->queue.sg_real_addr = 0; 30340024Sgibbs } 30440024Sgibbs 30540024Sgibbs if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 30640024Sgibbs op = BUS_DMASYNC_PREREAD; 30740024Sgibbs else 30840024Sgibbs op = BUS_DMASYNC_PREWRITE; 30940024Sgibbs 31040024Sgibbs bus_dmamap_sync(adw->buffer_dmat, acb->dmamap, op); 31140024Sgibbs 31240024Sgibbs } else { 31340024Sgibbs acb->queue.data_addr = 0; 31440024Sgibbs acb->queue.data_cnt = 0; 31540024Sgibbs acb->queue.sg_real_addr = 0; 31640024Sgibbs } 31740024Sgibbs 31840024Sgibbs s = splcam(); 31940024Sgibbs 32040024Sgibbs /* 32140024Sgibbs * Last time we need to check if this CCB needs to 32240024Sgibbs * be aborted. 32340024Sgibbs */ 32440024Sgibbs if (ccb->ccb_h.status != CAM_REQ_INPROG) { 32540024Sgibbs if (nseg != 0) 32640024Sgibbs bus_dmamap_unload(adw->buffer_dmat, acb->dmamap); 32740024Sgibbs adwfreeacb(adw, acb); 32840024Sgibbs xpt_done(ccb); 32940024Sgibbs splx(s); 33040024Sgibbs return; 33140024Sgibbs } 33257679Sgibbs 33340024Sgibbs acb->state |= ACB_ACTIVE; 33440024Sgibbs ccb->ccb_h.status |= CAM_SIM_QUEUED; 33540024Sgibbs LIST_INSERT_HEAD(&adw->pending_ccbs, &ccb->ccb_h, sim_links.le); 33640024Sgibbs ccb->ccb_h.timeout_ch = 33740024Sgibbs timeout(adwtimeout, (caddr_t)acb, 33840024Sgibbs (ccb->ccb_h.timeout * hz) / 1000); 33940024Sgibbs 34056979Sgibbs adw_send_acb(adw, acb, acbvtob(adw, acb)); 34140024Sgibbs 34240024Sgibbs splx(s); 34340024Sgibbs} 34440024Sgibbs 34540024Sgibbsstatic void 34640024Sgibbsadw_action(struct cam_sim *sim, union ccb *ccb) 34740024Sgibbs{ 34840024Sgibbs struct adw_softc *adw; 34940024Sgibbs 35040024Sgibbs CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("adw_action\n")); 35140024Sgibbs 35240024Sgibbs adw = (struct adw_softc *)cam_sim_softc(sim); 35340024Sgibbs 35440024Sgibbs switch (ccb->ccb_h.func_code) { 35540024Sgibbs /* Common cases first */ 35640024Sgibbs case XPT_SCSI_IO: /* Execute the requested I/O operation */ 35740024Sgibbs { 35840024Sgibbs struct ccb_scsiio *csio; 35940024Sgibbs struct ccb_hdr *ccbh; 36040024Sgibbs struct acb *acb; 36140024Sgibbs 36240024Sgibbs csio = &ccb->csio; 36340024Sgibbs ccbh = &ccb->ccb_h; 36456979Sgibbs 36540024Sgibbs /* Max supported CDB length is 12 bytes */ 36640024Sgibbs if (csio->cdb_len > 12) { 36740024Sgibbs ccb->ccb_h.status = CAM_REQ_INVALID; 36840024Sgibbs xpt_done(ccb); 36940024Sgibbs return; 37040024Sgibbs } 37140024Sgibbs 37240024Sgibbs if ((acb = adwgetacb(adw)) == NULL) { 37340024Sgibbs int s; 37440024Sgibbs 37540024Sgibbs s = splcam(); 37640024Sgibbs adw->state |= ADW_RESOURCE_SHORTAGE; 37740024Sgibbs splx(s); 37840024Sgibbs xpt_freeze_simq(sim, /*count*/1); 37940024Sgibbs ccb->ccb_h.status = CAM_REQUEUE_REQ; 38040024Sgibbs xpt_done(ccb); 38140024Sgibbs return; 38240024Sgibbs } 38340024Sgibbs 38456979Sgibbs /* Link acb and ccb so we can find one from the other */ 38540024Sgibbs acb->ccb = ccb; 38640024Sgibbs ccb->ccb_h.ccb_acb_ptr = acb; 38740024Sgibbs ccb->ccb_h.ccb_adw_ptr = adw; 38840024Sgibbs 38940024Sgibbs acb->queue.cntl = 0; 39056979Sgibbs acb->queue.target_cmd = 0; 39140024Sgibbs acb->queue.target_id = ccb->ccb_h.target_id; 39240024Sgibbs acb->queue.target_lun = ccb->ccb_h.target_lun; 39340024Sgibbs 39456979Sgibbs acb->queue.mflag = 0; 39540024Sgibbs acb->queue.sense_len = 39640024Sgibbs MIN(csio->sense_len, sizeof(acb->sense_data)); 39740024Sgibbs acb->queue.cdb_len = csio->cdb_len; 39856979Sgibbs if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0) { 39956979Sgibbs switch (csio->tag_action) { 40056979Sgibbs case MSG_SIMPLE_Q_TAG: 40157679Sgibbs acb->queue.scsi_cntl = ADW_QSC_SIMPLE_Q_TAG; 40256979Sgibbs break; 40356979Sgibbs case MSG_HEAD_OF_Q_TAG: 40456979Sgibbs acb->queue.scsi_cntl = ADW_QSC_HEAD_OF_Q_TAG; 40556979Sgibbs break; 40656979Sgibbs case MSG_ORDERED_Q_TAG: 40756979Sgibbs acb->queue.scsi_cntl = ADW_QSC_ORDERED_Q_TAG; 40856979Sgibbs break; 40957679Sgibbs default: 41057679Sgibbs acb->queue.scsi_cntl = ADW_QSC_NO_TAGMSG; 41157679Sgibbs break; 41256979Sgibbs } 41356979Sgibbs } else 41456979Sgibbs acb->queue.scsi_cntl = ADW_QSC_NO_TAGMSG; 41540024Sgibbs 41656979Sgibbs if ((ccb->ccb_h.flags & CAM_DIS_DISCONNECT) != 0) 41756979Sgibbs acb->queue.scsi_cntl |= ADW_QSC_NO_DISC; 41840024Sgibbs 41940024Sgibbs acb->queue.done_status = 0; 42040024Sgibbs acb->queue.scsi_status = 0; 42140024Sgibbs acb->queue.host_status = 0; 42256979Sgibbs acb->queue.sg_wk_ix = 0; 42340024Sgibbs if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 42440024Sgibbs if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 42540024Sgibbs bcopy(csio->cdb_io.cdb_ptr, 42640024Sgibbs acb->queue.cdb, csio->cdb_len); 42740024Sgibbs } else { 42840024Sgibbs /* I guess I could map it in... */ 42940024Sgibbs ccb->ccb_h.status = CAM_REQ_INVALID; 43040024Sgibbs adwfreeacb(adw, acb); 43140024Sgibbs xpt_done(ccb); 43240024Sgibbs return; 43340024Sgibbs } 43440024Sgibbs } else { 43540024Sgibbs bcopy(csio->cdb_io.cdb_bytes, 43640024Sgibbs acb->queue.cdb, csio->cdb_len); 43740024Sgibbs } 43840024Sgibbs 43940024Sgibbs /* 44040024Sgibbs * If we have any data to send with this command, 44140024Sgibbs * map it into bus space. 44240024Sgibbs */ 44340024Sgibbs if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 44440024Sgibbs if ((ccbh->flags & CAM_SCATTER_VALID) == 0) { 44540024Sgibbs /* 44640024Sgibbs * We've been given a pointer 44740024Sgibbs * to a single buffer. 44840024Sgibbs */ 44940024Sgibbs if ((ccbh->flags & CAM_DATA_PHYS) == 0) { 45040024Sgibbs int s; 45140024Sgibbs int error; 45240024Sgibbs 45340024Sgibbs s = splsoftvm(); 45440024Sgibbs error = 45540024Sgibbs bus_dmamap_load(adw->buffer_dmat, 45640024Sgibbs acb->dmamap, 45740024Sgibbs csio->data_ptr, 45840024Sgibbs csio->dxfer_len, 45940024Sgibbs adwexecuteacb, 46040024Sgibbs acb, /*flags*/0); 46140024Sgibbs if (error == EINPROGRESS) { 46240024Sgibbs /* 46340024Sgibbs * So as to maintain ordering, 46440024Sgibbs * freeze the controller queue 46540024Sgibbs * until our mapping is 46640024Sgibbs * returned. 46740024Sgibbs */ 46840024Sgibbs xpt_freeze_simq(sim, 1); 46940024Sgibbs acb->state |= CAM_RELEASE_SIMQ; 47040024Sgibbs } 47140024Sgibbs splx(s); 47240024Sgibbs } else { 47340024Sgibbs struct bus_dma_segment seg; 47440024Sgibbs 47540024Sgibbs /* Pointer to physical buffer */ 47640024Sgibbs seg.ds_addr = 47740024Sgibbs (bus_addr_t)csio->data_ptr; 47840024Sgibbs seg.ds_len = csio->dxfer_len; 47940024Sgibbs adwexecuteacb(acb, &seg, 1, 0); 48040024Sgibbs } 48140024Sgibbs } else { 48240024Sgibbs struct bus_dma_segment *segs; 48340024Sgibbs 48440024Sgibbs if ((ccbh->flags & CAM_DATA_PHYS) != 0) 48540024Sgibbs panic("adw_action - Physical " 48640024Sgibbs "segment pointers " 48740024Sgibbs "unsupported"); 48840024Sgibbs 48940024Sgibbs if ((ccbh->flags&CAM_SG_LIST_PHYS)==0) 49040024Sgibbs panic("adw_action - Virtual " 49140024Sgibbs "segment addresses " 49240024Sgibbs "unsupported"); 49340024Sgibbs 49440024Sgibbs /* Just use the segments provided */ 49540024Sgibbs segs = (struct bus_dma_segment *)csio->data_ptr; 49640024Sgibbs adwexecuteacb(acb, segs, csio->sglist_cnt, 49740024Sgibbs (csio->sglist_cnt < ADW_SGSIZE) 49840024Sgibbs ? 0 : EFBIG); 49940024Sgibbs } 50040024Sgibbs } else { 50140024Sgibbs adwexecuteacb(acb, NULL, 0, 0); 50240024Sgibbs } 50340024Sgibbs break; 50440024Sgibbs } 50540024Sgibbs case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 50640024Sgibbs { 50740024Sgibbs adw_idle_cmd_status_t status; 50840024Sgibbs 50957679Sgibbs status = adw_idle_cmd_send(adw, ADW_IDLE_CMD_DEVICE_RESET, 51057679Sgibbs ccb->ccb_h.target_id); 51140024Sgibbs if (status == ADW_IDLE_CMD_SUCCESS) { 51240024Sgibbs ccb->ccb_h.status = CAM_REQ_CMP; 51340024Sgibbs if (bootverbose) { 51440024Sgibbs xpt_print_path(ccb->ccb_h.path); 51540024Sgibbs printf("BDR Delivered\n"); 51640024Sgibbs } 51740024Sgibbs } else 51840024Sgibbs ccb->ccb_h.status = CAM_REQ_CMP_ERR; 51940024Sgibbs xpt_done(ccb); 52040024Sgibbs break; 52140024Sgibbs } 52240024Sgibbs case XPT_ABORT: /* Abort the specified CCB */ 52340024Sgibbs /* XXX Implement */ 52440024Sgibbs ccb->ccb_h.status = CAM_REQ_INVALID; 52540024Sgibbs xpt_done(ccb); 52640024Sgibbs break; 52740024Sgibbs case XPT_SET_TRAN_SETTINGS: 52840024Sgibbs { 52940024Sgibbs struct ccb_trans_settings *cts; 53040024Sgibbs u_int target_mask; 53140024Sgibbs int s; 53240024Sgibbs 53340024Sgibbs cts = &ccb->cts; 53440024Sgibbs target_mask = 0x01 << ccb->ccb_h.target_id; 53540024Sgibbs 53640024Sgibbs s = splcam(); 53740024Sgibbs if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 53856979Sgibbs u_int sdtrdone; 53956979Sgibbs 54056979Sgibbs sdtrdone = adw_lram_read_16(adw, ADW_MC_SDTR_DONE); 54140024Sgibbs if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 54240024Sgibbs u_int discenb; 54340024Sgibbs 54440024Sgibbs discenb = 54540024Sgibbs adw_lram_read_16(adw, ADW_MC_DISC_ENABLE); 54640024Sgibbs 54740024Sgibbs if ((cts->flags & CCB_TRANS_DISC_ENB) != 0) 54840024Sgibbs discenb |= target_mask; 54940024Sgibbs else 55040024Sgibbs discenb &= ~target_mask; 55140024Sgibbs 55240024Sgibbs adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, 55340024Sgibbs discenb); 55440024Sgibbs } 55540024Sgibbs 55640024Sgibbs if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 55740024Sgibbs 55840024Sgibbs if ((cts->flags & CCB_TRANS_TAG_ENB) != 0) 55940024Sgibbs adw->tagenb |= target_mask; 56040024Sgibbs else 56140024Sgibbs adw->tagenb &= ~target_mask; 56240024Sgibbs } 56340024Sgibbs 56440024Sgibbs if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) { 56540024Sgibbs u_int wdtrenb_orig; 56640024Sgibbs u_int wdtrenb; 56740024Sgibbs u_int wdtrdone; 56840024Sgibbs 56940024Sgibbs wdtrenb_orig = 57040024Sgibbs adw_lram_read_16(adw, ADW_MC_WDTR_ABLE); 57140024Sgibbs wdtrenb = wdtrenb_orig; 57240024Sgibbs wdtrdone = adw_lram_read_16(adw, 57340024Sgibbs ADW_MC_WDTR_DONE); 57440024Sgibbs switch (cts->bus_width) { 57540024Sgibbs case MSG_EXT_WDTR_BUS_32_BIT: 57640024Sgibbs case MSG_EXT_WDTR_BUS_16_BIT: 57740024Sgibbs wdtrenb |= target_mask; 57840024Sgibbs break; 57940024Sgibbs case MSG_EXT_WDTR_BUS_8_BIT: 58040024Sgibbs default: 58140024Sgibbs wdtrenb &= ~target_mask; 58240024Sgibbs break; 58340024Sgibbs } 58440024Sgibbs if (wdtrenb != wdtrenb_orig) { 58540024Sgibbs adw_lram_write_16(adw, 58640024Sgibbs ADW_MC_WDTR_ABLE, 58740024Sgibbs wdtrenb); 58840024Sgibbs wdtrdone &= ~target_mask; 58940024Sgibbs adw_lram_write_16(adw, 59040024Sgibbs ADW_MC_WDTR_DONE, 59140024Sgibbs wdtrdone); 59256979Sgibbs /* Wide negotiation forces async */ 59356979Sgibbs sdtrdone &= ~target_mask; 59456979Sgibbs adw_lram_write_16(adw, 59556979Sgibbs ADW_MC_SDTR_DONE, 59656979Sgibbs sdtrdone); 59740024Sgibbs } 59840024Sgibbs } 59940024Sgibbs 60046581Sken if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) 60146581Sken || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) { 60256979Sgibbs u_int sdtr_orig; 60356979Sgibbs u_int sdtr; 60456979Sgibbs u_int sdtrable_orig; 60556979Sgibbs u_int sdtrable; 60640024Sgibbs 60756979Sgibbs sdtr = adw_get_chip_sdtr(adw, 60856979Sgibbs ccb->ccb_h.target_id); 60956979Sgibbs sdtr_orig = sdtr; 61056979Sgibbs sdtrable = adw_lram_read_16(adw, 61156979Sgibbs ADW_MC_SDTR_ABLE); 61256979Sgibbs sdtrable_orig = sdtrable; 61340024Sgibbs 61446581Sken if ((cts->valid 61546581Sken & CCB_TRANS_SYNC_RATE_VALID) != 0) { 61646581Sken 61756979Sgibbs sdtr = 61856979Sgibbs adw_find_sdtr(adw, 61956979Sgibbs cts->sync_period); 62040024Sgibbs } 62140024Sgibbs 62240024Sgibbs if ((cts->valid 62340024Sgibbs & CCB_TRANS_SYNC_OFFSET_VALID) != 0) { 62440024Sgibbs if (cts->sync_offset == 0) 62556979Sgibbs sdtr = ADW_MC_SDTR_ASYNC; 62640024Sgibbs } 62740024Sgibbs 62856979Sgibbs if (sdtr == ADW_MC_SDTR_ASYNC) 62956979Sgibbs sdtrable &= ~target_mask; 63056979Sgibbs else 63156979Sgibbs sdtrable |= target_mask; 63256979Sgibbs if (sdtr != sdtr_orig 63356979Sgibbs || sdtrable != sdtrable_orig) { 63456979Sgibbs adw_set_chip_sdtr(adw, 63556979Sgibbs ccb->ccb_h.target_id, 63656979Sgibbs sdtr); 63756979Sgibbs sdtrdone &= ~target_mask; 63840024Sgibbs adw_lram_write_16(adw, ADW_MC_SDTR_ABLE, 63956979Sgibbs sdtrable); 64040024Sgibbs adw_lram_write_16(adw, ADW_MC_SDTR_DONE, 64140024Sgibbs sdtrdone); 64256979Sgibbs 64340024Sgibbs } 64440024Sgibbs } 64540024Sgibbs } 64640024Sgibbs splx(s); 64740024Sgibbs ccb->ccb_h.status = CAM_REQ_CMP; 64840024Sgibbs xpt_done(ccb); 64940024Sgibbs break; 65040024Sgibbs } 65140024Sgibbs case XPT_GET_TRAN_SETTINGS: 65240024Sgibbs /* Get default/user set transfer settings for the target */ 65340024Sgibbs { 65440024Sgibbs struct ccb_trans_settings *cts; 65540024Sgibbs u_int target_mask; 65640024Sgibbs 65740024Sgibbs cts = &ccb->cts; 65840024Sgibbs target_mask = 0x01 << ccb->ccb_h.target_id; 65940024Sgibbs if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) { 66056979Sgibbs u_int mc_sdtr; 66156979Sgibbs 66240024Sgibbs cts->flags = 0; 66340024Sgibbs if ((adw->user_discenb & target_mask) != 0) 66440024Sgibbs cts->flags |= CCB_TRANS_DISC_ENB; 66540024Sgibbs 66640024Sgibbs if ((adw->user_tagenb & target_mask) != 0) 66740024Sgibbs cts->flags |= CCB_TRANS_TAG_ENB; 66840024Sgibbs 66940024Sgibbs if ((adw->user_wdtr & target_mask) != 0) 67040024Sgibbs cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 67140024Sgibbs else 67240024Sgibbs cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT; 67340024Sgibbs 67456979Sgibbs mc_sdtr = adw_get_user_sdtr(adw, ccb->ccb_h.target_id); 67556979Sgibbs cts->sync_period = adw_find_period(adw, mc_sdtr); 67656979Sgibbs if (cts->sync_period != 0) 67740024Sgibbs cts->sync_offset = 15; /* XXX ??? */ 67856979Sgibbs else 67956979Sgibbs cts->sync_offset = 0; 68040024Sgibbs 68140024Sgibbs cts->valid = CCB_TRANS_SYNC_RATE_VALID 68240024Sgibbs | CCB_TRANS_SYNC_OFFSET_VALID 68340024Sgibbs | CCB_TRANS_BUS_WIDTH_VALID 68440024Sgibbs | CCB_TRANS_DISC_VALID 68540024Sgibbs | CCB_TRANS_TQ_VALID; 68640024Sgibbs ccb->ccb_h.status = CAM_REQ_CMP; 68740024Sgibbs } else { 68840024Sgibbs u_int targ_tinfo; 68940024Sgibbs 69040024Sgibbs cts->flags = 0; 69140024Sgibbs if ((adw_lram_read_16(adw, ADW_MC_DISC_ENABLE) 69240024Sgibbs & target_mask) != 0) 69340024Sgibbs cts->flags |= CCB_TRANS_DISC_ENB; 69440024Sgibbs 69540024Sgibbs if ((adw->tagenb & target_mask) != 0) 69640024Sgibbs cts->flags |= CCB_TRANS_TAG_ENB; 69740024Sgibbs 69840024Sgibbs targ_tinfo = 69940024Sgibbs adw_lram_read_16(adw, 70040024Sgibbs ADW_MC_DEVICE_HSHK_CFG_TABLE 70140024Sgibbs + (2 * ccb->ccb_h.target_id)); 70240024Sgibbs 70340024Sgibbs if ((targ_tinfo & ADW_HSHK_CFG_WIDE_XFR) != 0) 70440024Sgibbs cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 70540024Sgibbs else 70640024Sgibbs cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT; 70740024Sgibbs 70840024Sgibbs cts->sync_period = 70956979Sgibbs adw_hshk_cfg_period_factor(targ_tinfo); 71040024Sgibbs 71140024Sgibbs cts->sync_offset = targ_tinfo & ADW_HSHK_CFG_OFFSET; 71240024Sgibbs if (cts->sync_period == 0) 71340024Sgibbs cts->sync_offset = 0; 71440024Sgibbs 71540024Sgibbs if (cts->sync_offset == 0) 71640024Sgibbs cts->sync_period = 0; 71740024Sgibbs } 71840024Sgibbs cts->valid = CCB_TRANS_SYNC_RATE_VALID 71940024Sgibbs | CCB_TRANS_SYNC_OFFSET_VALID 72040024Sgibbs | CCB_TRANS_BUS_WIDTH_VALID 72140024Sgibbs | CCB_TRANS_DISC_VALID 72240024Sgibbs | CCB_TRANS_TQ_VALID; 72340024Sgibbs ccb->ccb_h.status = CAM_REQ_CMP; 72440024Sgibbs xpt_done(ccb); 72540024Sgibbs break; 72640024Sgibbs } 72740024Sgibbs case XPT_CALC_GEOMETRY: 72840024Sgibbs { 72940024Sgibbs struct ccb_calc_geometry *ccg; 73040024Sgibbs u_int32_t size_mb; 73140024Sgibbs u_int32_t secs_per_cylinder; 73240024Sgibbs int extended; 73340024Sgibbs 73440024Sgibbs /* 73540024Sgibbs * XXX Use Adaptec translation until I find out how to 73640024Sgibbs * get this information from the card. 73740024Sgibbs */ 73840024Sgibbs ccg = &ccb->ccg; 73940024Sgibbs size_mb = ccg->volume_size 74040024Sgibbs / ((1024L * 1024L) / ccg->block_size); 74140024Sgibbs extended = 1; 74240024Sgibbs 74340024Sgibbs if (size_mb > 1024 && extended) { 74440024Sgibbs ccg->heads = 255; 74540024Sgibbs ccg->secs_per_track = 63; 74640024Sgibbs } else { 74740024Sgibbs ccg->heads = 64; 74840024Sgibbs ccg->secs_per_track = 32; 74940024Sgibbs } 75040024Sgibbs secs_per_cylinder = ccg->heads * ccg->secs_per_track; 75140024Sgibbs ccg->cylinders = ccg->volume_size / secs_per_cylinder; 75240024Sgibbs ccb->ccb_h.status = CAM_REQ_CMP; 75340024Sgibbs xpt_done(ccb); 75440024Sgibbs break; 75540024Sgibbs } 75640024Sgibbs case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 75740024Sgibbs { 75857679Sgibbs int failure; 75940024Sgibbs 76057679Sgibbs failure = adw_reset_bus(adw); 76157679Sgibbs if (failure != 0) { 76240024Sgibbs ccb->ccb_h.status = CAM_REQ_CMP_ERR; 76357679Sgibbs } else { 76457679Sgibbs if (bootverbose) { 76557679Sgibbs xpt_print_path(adw->path); 76657679Sgibbs printf("Bus Reset Delivered\n"); 76757679Sgibbs } 76857679Sgibbs ccb->ccb_h.status = CAM_REQ_CMP; 76956979Sgibbs } 77040024Sgibbs xpt_done(ccb); 77140024Sgibbs break; 77240024Sgibbs } 77340024Sgibbs case XPT_TERM_IO: /* Terminate the I/O process */ 77440024Sgibbs /* XXX Implement */ 77540024Sgibbs ccb->ccb_h.status = CAM_REQ_INVALID; 77640024Sgibbs xpt_done(ccb); 77740024Sgibbs break; 77840024Sgibbs case XPT_PATH_INQ: /* Path routing inquiry */ 77940024Sgibbs { 78040024Sgibbs struct ccb_pathinq *cpi = &ccb->cpi; 78140024Sgibbs 78240024Sgibbs cpi->version_num = 1; 78340024Sgibbs cpi->hba_inquiry = PI_WIDE_16|PI_SDTR_ABLE|PI_TAG_ABLE; 78440024Sgibbs cpi->target_sprt = 0; 78540024Sgibbs cpi->hba_misc = 0; 78640024Sgibbs cpi->hba_eng_cnt = 0; 78740024Sgibbs cpi->max_target = ADW_MAX_TID; 78840024Sgibbs cpi->max_lun = ADW_MAX_LUN; 78940024Sgibbs cpi->initiator_id = adw->initiator_id; 79040024Sgibbs cpi->bus_id = cam_sim_bus(sim); 79146581Sken cpi->base_transfer_speed = 3300; 79240024Sgibbs strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 79340024Sgibbs strncpy(cpi->hba_vid, "AdvanSys", HBA_IDLEN); 79440024Sgibbs strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 79540024Sgibbs cpi->unit_number = cam_sim_unit(sim); 79640024Sgibbs cpi->ccb_h.status = CAM_REQ_CMP; 79740024Sgibbs xpt_done(ccb); 79840024Sgibbs break; 79940024Sgibbs } 80040024Sgibbs default: 80140024Sgibbs ccb->ccb_h.status = CAM_REQ_INVALID; 80240024Sgibbs xpt_done(ccb); 80340024Sgibbs break; 80440024Sgibbs } 80540024Sgibbs} 80640024Sgibbs 80740024Sgibbsstatic void 80840024Sgibbsadw_poll(struct cam_sim *sim) 80940024Sgibbs{ 81040024Sgibbs adw_intr(cam_sim_softc(sim)); 81140024Sgibbs} 81240024Sgibbs 81340024Sgibbsstatic void 81440024Sgibbsadw_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg) 81540024Sgibbs{ 81640024Sgibbs} 81740024Sgibbs 81840024Sgibbsstruct adw_softc * 81956979Sgibbsadw_alloc(device_t dev, struct resource *regs, int regs_type, int regs_id) 82040024Sgibbs{ 82140024Sgibbs struct adw_softc *adw; 82240024Sgibbs int i; 82340024Sgibbs 82440024Sgibbs /* 82540024Sgibbs * Allocate a storage area for us 82640024Sgibbs */ 82767888Sdwmalone adw = malloc(sizeof(struct adw_softc), M_DEVBUF, M_NOWAIT | M_ZERO); 82840024Sgibbs if (adw == NULL) { 82956979Sgibbs printf("adw%d: cannot malloc!\n", device_get_unit(dev)); 83040024Sgibbs return NULL; 83140024Sgibbs } 83240024Sgibbs LIST_INIT(&adw->pending_ccbs); 83340024Sgibbs SLIST_INIT(&adw->sg_maps); 83456979Sgibbs adw->device = dev; 83556979Sgibbs adw->unit = device_get_unit(dev); 83656979Sgibbs adw->regs_res_type = regs_type; 83756979Sgibbs adw->regs_res_id = regs_id; 83856979Sgibbs adw->regs = regs; 83956979Sgibbs adw->tag = rman_get_bustag(regs); 84056979Sgibbs adw->bsh = rman_get_bushandle(regs); 84140024Sgibbs i = adw->unit / 10; 84240024Sgibbs adw->name = malloc(sizeof("adw") + i + 1, M_DEVBUF, M_NOWAIT); 84340024Sgibbs if (adw->name == NULL) { 84456979Sgibbs printf("adw%d: cannot malloc name!\n", adw->unit); 84540024Sgibbs free(adw, M_DEVBUF); 84640024Sgibbs return NULL; 84740024Sgibbs } 84840024Sgibbs sprintf(adw->name, "adw%d", adw->unit); 84940024Sgibbs return(adw); 85040024Sgibbs} 85140024Sgibbs 85240024Sgibbsvoid 85340024Sgibbsadw_free(struct adw_softc *adw) 85440024Sgibbs{ 85540024Sgibbs switch (adw->init_level) { 85656979Sgibbs case 9: 85740024Sgibbs { 85840024Sgibbs struct sg_map_node *sg_map; 85940024Sgibbs 86040024Sgibbs while ((sg_map = SLIST_FIRST(&adw->sg_maps)) != NULL) { 86140024Sgibbs SLIST_REMOVE_HEAD(&adw->sg_maps, links); 86240024Sgibbs bus_dmamap_unload(adw->sg_dmat, 86340024Sgibbs sg_map->sg_dmamap); 86440024Sgibbs bus_dmamem_free(adw->sg_dmat, sg_map->sg_vaddr, 86540024Sgibbs sg_map->sg_dmamap); 86640024Sgibbs free(sg_map, M_DEVBUF); 86740024Sgibbs } 86840024Sgibbs bus_dma_tag_destroy(adw->sg_dmat); 86940024Sgibbs } 87056979Sgibbs case 8: 87140024Sgibbs bus_dmamap_unload(adw->acb_dmat, adw->acb_dmamap); 87256979Sgibbs case 7: 87340024Sgibbs bus_dmamem_free(adw->acb_dmat, adw->acbs, 87440024Sgibbs adw->acb_dmamap); 87540024Sgibbs bus_dmamap_destroy(adw->acb_dmat, adw->acb_dmamap); 87656979Sgibbs case 6: 87756979Sgibbs bus_dma_tag_destroy(adw->acb_dmat); 87856979Sgibbs case 5: 87956979Sgibbs bus_dmamap_unload(adw->carrier_dmat, adw->carrier_dmamap); 88056979Sgibbs case 4: 88156979Sgibbs bus_dmamem_free(adw->carrier_dmat, adw->carriers, 88256979Sgibbs adw->carrier_dmamap); 88356979Sgibbs bus_dmamap_destroy(adw->carrier_dmat, adw->carrier_dmamap); 88440024Sgibbs case 3: 88556979Sgibbs bus_dma_tag_destroy(adw->carrier_dmat); 88640024Sgibbs case 2: 88740024Sgibbs bus_dma_tag_destroy(adw->buffer_dmat); 88840024Sgibbs case 1: 88940024Sgibbs bus_dma_tag_destroy(adw->parent_dmat); 89040024Sgibbs case 0: 89140024Sgibbs break; 89240024Sgibbs } 89340024Sgibbs free(adw->name, M_DEVBUF); 89440024Sgibbs free(adw, M_DEVBUF); 89540024Sgibbs} 89640024Sgibbs 89740024Sgibbsint 89840024Sgibbsadw_init(struct adw_softc *adw) 89940024Sgibbs{ 90040024Sgibbs struct adw_eeprom eep_config; 90156979Sgibbs u_int tid; 90256979Sgibbs u_int i; 90340024Sgibbs u_int16_t checksum; 90440024Sgibbs u_int16_t scsicfg1; 90540024Sgibbs 90640024Sgibbs checksum = adw_eeprom_read(adw, &eep_config); 90740024Sgibbs bcopy(eep_config.serial_number, adw->serial_number, 90840024Sgibbs sizeof(adw->serial_number)); 90940024Sgibbs if (checksum != eep_config.checksum) { 91040024Sgibbs u_int16_t serial_number[3]; 91140024Sgibbs 91256979Sgibbs adw->flags |= ADW_EEPROM_FAILED; 91340024Sgibbs printf("%s: EEPROM checksum failed. Restoring Defaults\n", 91440024Sgibbs adw_name(adw)); 91540024Sgibbs 91640024Sgibbs /* 91740024Sgibbs * Restore the default EEPROM settings. 91840024Sgibbs * Assume the 6 byte board serial number that was read 91940024Sgibbs * from EEPROM is correct even if the EEPROM checksum 92040024Sgibbs * failed. 92140024Sgibbs */ 92256979Sgibbs bcopy(adw->default_eeprom, &eep_config, sizeof(eep_config)); 92340024Sgibbs bcopy(adw->serial_number, eep_config.serial_number, 92440024Sgibbs sizeof(serial_number)); 92540024Sgibbs adw_eeprom_write(adw, &eep_config); 92640024Sgibbs } 92740024Sgibbs 92840024Sgibbs /* Pull eeprom information into our softc. */ 92940024Sgibbs adw->bios_ctrl = eep_config.bios_ctrl; 93040024Sgibbs adw->user_wdtr = eep_config.wdtr_able; 93156979Sgibbs for (tid = 0; tid < ADW_MAX_TID; tid++) { 93256979Sgibbs u_int mc_sdtr; 93356979Sgibbs u_int16_t tid_mask; 93456979Sgibbs 93556979Sgibbs tid_mask = 0x1 << tid; 93656979Sgibbs if ((adw->features & ADW_ULTRA) != 0) { 93756979Sgibbs /* 93856979Sgibbs * Ultra chips store sdtr and ultraenb 93956979Sgibbs * bits in their seeprom, so we must 94056979Sgibbs * construct valid mc_sdtr entries for 94156979Sgibbs * indirectly. 94256979Sgibbs */ 94356979Sgibbs if (eep_config.sync1.sync_enable & tid_mask) { 94456979Sgibbs if (eep_config.sync2.ultra_enable & tid_mask) 94556979Sgibbs mc_sdtr = ADW_MC_SDTR_20; 94656979Sgibbs else 94756979Sgibbs mc_sdtr = ADW_MC_SDTR_10; 94856979Sgibbs } else 94956979Sgibbs mc_sdtr = ADW_MC_SDTR_ASYNC; 95056979Sgibbs } else { 95156979Sgibbs switch (ADW_TARGET_GROUP(tid)) { 95256979Sgibbs case 3: 95356979Sgibbs mc_sdtr = eep_config.sync4.sdtr4; 95456979Sgibbs break; 95556979Sgibbs case 2: 95656979Sgibbs mc_sdtr = eep_config.sync3.sdtr3; 95756979Sgibbs break; 95856979Sgibbs case 1: 95956979Sgibbs mc_sdtr = eep_config.sync2.sdtr2; 96056979Sgibbs break; 96156979Sgibbs default: /* Shut up compiler */ 96256979Sgibbs case 0: 96356979Sgibbs mc_sdtr = eep_config.sync1.sdtr1; 96456979Sgibbs break; 96556979Sgibbs } 96656979Sgibbs mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid); 96756979Sgibbs mc_sdtr &= 0xFF; 96856979Sgibbs } 96956979Sgibbs adw_set_user_sdtr(adw, tid, mc_sdtr); 97056979Sgibbs } 97140024Sgibbs adw->user_tagenb = eep_config.tagqng_able; 97240024Sgibbs adw->user_discenb = eep_config.disc_enable; 97340024Sgibbs adw->max_acbs = eep_config.max_host_qng; 97440024Sgibbs adw->initiator_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 97540024Sgibbs 97640024Sgibbs /* 97740024Sgibbs * Sanity check the number of host openings. 97840024Sgibbs */ 97940024Sgibbs if (adw->max_acbs > ADW_DEF_MAX_HOST_QNG) 98040024Sgibbs adw->max_acbs = ADW_DEF_MAX_HOST_QNG; 98140024Sgibbs else if (adw->max_acbs < ADW_DEF_MIN_HOST_QNG) { 98240024Sgibbs /* If the value is zero, assume it is uninitialized. */ 98340024Sgibbs if (adw->max_acbs == 0) 98440024Sgibbs adw->max_acbs = ADW_DEF_MAX_HOST_QNG; 98540024Sgibbs else 98640024Sgibbs adw->max_acbs = ADW_DEF_MIN_HOST_QNG; 98740024Sgibbs } 98840024Sgibbs 98940024Sgibbs scsicfg1 = 0; 99056979Sgibbs if ((adw->features & ADW_ULTRA2) != 0) { 99156979Sgibbs switch (eep_config.termination_lvd) { 99256979Sgibbs default: 99356979Sgibbs printf("%s: Invalid EEPROM LVD Termination Settings.\n", 99456979Sgibbs adw_name(adw)); 99556979Sgibbs printf("%s: Reverting to Automatic LVD Termination\n", 99656979Sgibbs adw_name(adw)); 99756979Sgibbs /* FALLTHROUGH */ 99856979Sgibbs case ADW_EEPROM_TERM_AUTO: 99956979Sgibbs break; 100056979Sgibbs case ADW_EEPROM_TERM_BOTH_ON: 100156979Sgibbs scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_LO; 100256979Sgibbs /* FALLTHROUGH */ 100356979Sgibbs case ADW_EEPROM_TERM_HIGH_ON: 100456979Sgibbs scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_HI; 100556979Sgibbs /* FALLTHROUGH */ 100656979Sgibbs case ADW_EEPROM_TERM_OFF: 100756979Sgibbs scsicfg1 |= ADW2_SCSI_CFG1_DIS_TERM_DRV; 100856979Sgibbs break; 100956979Sgibbs } 101056979Sgibbs } 101156979Sgibbs 101256979Sgibbs switch (eep_config.termination_se) { 101340024Sgibbs default: 101456979Sgibbs printf("%s: Invalid SE EEPROM Termination Settings.\n", 101540024Sgibbs adw_name(adw)); 101656979Sgibbs printf("%s: Reverting to Automatic SE Termination\n", 101740024Sgibbs adw_name(adw)); 101840024Sgibbs /* FALLTHROUGH */ 101940024Sgibbs case ADW_EEPROM_TERM_AUTO: 102040024Sgibbs break; 102140024Sgibbs case ADW_EEPROM_TERM_BOTH_ON: 102240024Sgibbs scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L; 102340024Sgibbs /* FALLTHROUGH */ 102440024Sgibbs case ADW_EEPROM_TERM_HIGH_ON: 102540024Sgibbs scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H; 102640024Sgibbs /* FALLTHROUGH */ 102740024Sgibbs case ADW_EEPROM_TERM_OFF: 102840024Sgibbs scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_MANUAL; 102940024Sgibbs break; 103040024Sgibbs } 103140024Sgibbs printf("%s: SCSI ID %d, ", adw_name(adw), adw->initiator_id); 103240024Sgibbs 103340024Sgibbs /* DMA tag for mapping buffers into device visible space. */ 103449860Sgibbs if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/1, /*boundary*/0, 103556979Sgibbs /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 103640024Sgibbs /*highaddr*/BUS_SPACE_MAXADDR, 103740024Sgibbs /*filter*/NULL, /*filterarg*/NULL, 103840024Sgibbs /*maxsize*/MAXBSIZE, /*nsegments*/ADW_SGSIZE, 103940024Sgibbs /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 104040024Sgibbs /*flags*/BUS_DMA_ALLOCNOW, 104140024Sgibbs &adw->buffer_dmat) != 0) { 104256979Sgibbs return (ENOMEM); 104340024Sgibbs } 104440024Sgibbs 104540024Sgibbs adw->init_level++; 104640024Sgibbs 104756979Sgibbs /* DMA tag for our ccb carrier structures */ 104856979Sgibbs if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/0x10, 104956979Sgibbs /*boundary*/0, 105056979Sgibbs /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 105156979Sgibbs /*highaddr*/BUS_SPACE_MAXADDR, 105256979Sgibbs /*filter*/NULL, /*filterarg*/NULL, 105356979Sgibbs (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1) 105456979Sgibbs * sizeof(struct adw_carrier), 105556979Sgibbs /*nsegments*/1, 105656979Sgibbs /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 105756979Sgibbs /*flags*/0, &adw->carrier_dmat) != 0) { 105856979Sgibbs return (ENOMEM); 105956979Sgibbs } 106056979Sgibbs 106156979Sgibbs adw->init_level++; 106256979Sgibbs 106356979Sgibbs /* Allocation for our ccb carrier structures */ 106456979Sgibbs if (bus_dmamem_alloc(adw->carrier_dmat, (void **)&adw->carriers, 106556979Sgibbs BUS_DMA_NOWAIT, &adw->carrier_dmamap) != 0) { 106656979Sgibbs return (ENOMEM); 106756979Sgibbs } 106856979Sgibbs 106956979Sgibbs adw->init_level++; 107056979Sgibbs 107156979Sgibbs /* And permanently map them */ 107256979Sgibbs bus_dmamap_load(adw->carrier_dmat, adw->carrier_dmamap, 107356979Sgibbs adw->carriers, 107456979Sgibbs (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1) 107556979Sgibbs * sizeof(struct adw_carrier), 107656979Sgibbs adwmapmem, &adw->carrier_busbase, /*flags*/0); 107756979Sgibbs 107856979Sgibbs /* Clear them out. */ 107956979Sgibbs bzero(adw->carriers, (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1) 108056979Sgibbs * sizeof(struct adw_carrier)); 108156979Sgibbs 108256979Sgibbs /* Setup our free carrier list */ 108356979Sgibbs adw->free_carriers = adw->carriers; 108456979Sgibbs for (i = 0; i < adw->max_acbs + ADW_NUM_CARRIER_QUEUES; i++) { 108556979Sgibbs adw->carriers[i].carr_offset = 108656979Sgibbs carriervtobo(adw, &adw->carriers[i]); 108756979Sgibbs adw->carriers[i].carr_ba = 108856979Sgibbs carriervtob(adw, &adw->carriers[i]); 108956979Sgibbs adw->carriers[i].areq_ba = 0; 109056979Sgibbs adw->carriers[i].next_ba = 109156979Sgibbs carriervtobo(adw, &adw->carriers[i+1]); 109256979Sgibbs } 109356979Sgibbs /* Terminal carrier. Never leaves the freelist */ 109456979Sgibbs adw->carriers[i].carr_offset = 109556979Sgibbs carriervtobo(adw, &adw->carriers[i]); 109656979Sgibbs adw->carriers[i].carr_ba = 109756979Sgibbs carriervtob(adw, &adw->carriers[i]); 109856979Sgibbs adw->carriers[i].areq_ba = 0; 109956979Sgibbs adw->carriers[i].next_ba = ~0; 110056979Sgibbs 110156979Sgibbs adw->init_level++; 110256979Sgibbs 110356979Sgibbs /* DMA tag for our acb structures */ 110449860Sgibbs if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/1, /*boundary*/0, 110540024Sgibbs /*lowaddr*/BUS_SPACE_MAXADDR, 110640024Sgibbs /*highaddr*/BUS_SPACE_MAXADDR, 110740024Sgibbs /*filter*/NULL, /*filterarg*/NULL, 110840024Sgibbs adw->max_acbs * sizeof(struct acb), 110940024Sgibbs /*nsegments*/1, 111040024Sgibbs /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 111140024Sgibbs /*flags*/0, &adw->acb_dmat) != 0) { 111256979Sgibbs return (ENOMEM); 111340024Sgibbs } 111440024Sgibbs 111540024Sgibbs adw->init_level++; 111640024Sgibbs 111740024Sgibbs /* Allocation for our ccbs */ 111840024Sgibbs if (bus_dmamem_alloc(adw->acb_dmat, (void **)&adw->acbs, 111956979Sgibbs BUS_DMA_NOWAIT, &adw->acb_dmamap) != 0) 112056979Sgibbs return (ENOMEM); 112140024Sgibbs 112240024Sgibbs adw->init_level++; 112340024Sgibbs 112440024Sgibbs /* And permanently map them */ 112540024Sgibbs bus_dmamap_load(adw->acb_dmat, adw->acb_dmamap, 112640024Sgibbs adw->acbs, 112740024Sgibbs adw->max_acbs * sizeof(struct acb), 112840024Sgibbs adwmapmem, &adw->acb_busbase, /*flags*/0); 112940024Sgibbs 113040024Sgibbs /* Clear them out. */ 113140024Sgibbs bzero(adw->acbs, adw->max_acbs * sizeof(struct acb)); 113240024Sgibbs 113340024Sgibbs /* DMA tag for our S/G structures. We allocate in page sized chunks */ 113449860Sgibbs if (bus_dma_tag_create(adw->parent_dmat, /*alignment*/1, /*boundary*/0, 113540024Sgibbs /*lowaddr*/BUS_SPACE_MAXADDR, 113640024Sgibbs /*highaddr*/BUS_SPACE_MAXADDR, 113740024Sgibbs /*filter*/NULL, /*filterarg*/NULL, 113840024Sgibbs PAGE_SIZE, /*nsegments*/1, 113940024Sgibbs /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 114040024Sgibbs /*flags*/0, &adw->sg_dmat) != 0) { 114156979Sgibbs return (ENOMEM); 114240024Sgibbs } 114340024Sgibbs 114440024Sgibbs adw->init_level++; 114540024Sgibbs 114640024Sgibbs /* Allocate our first batch of ccbs */ 114740024Sgibbs if (adwallocacbs(adw) == 0) 114856979Sgibbs return (ENOMEM); 114940024Sgibbs 115056979Sgibbs if (adw_init_chip(adw, scsicfg1) != 0) 115156979Sgibbs return (ENXIO); 115256979Sgibbs 115356979Sgibbs printf("Queue Depth %d\n", adw->max_acbs); 115456979Sgibbs 115540024Sgibbs return (0); 115640024Sgibbs} 115740024Sgibbs 115840024Sgibbs/* 115940024Sgibbs * Attach all the sub-devices we can find 116040024Sgibbs */ 116140024Sgibbsint 116240024Sgibbsadw_attach(struct adw_softc *adw) 116340024Sgibbs{ 116440024Sgibbs struct ccb_setasync csa; 116540024Sgibbs struct cam_devq *devq; 116656979Sgibbs int s; 116756979Sgibbs int error; 116840024Sgibbs 116956979Sgibbs error = 0; 117056979Sgibbs s = splcam(); 117156979Sgibbs /* Hook up our interrupt handler */ 117256979Sgibbs if ((error = bus_setup_intr(adw->device, adw->irq, INTR_TYPE_CAM, 117356979Sgibbs adw_intr, adw, &adw->ih)) != 0) { 117456979Sgibbs device_printf(adw->device, "bus_setup_intr() failed: %d\n", 117556979Sgibbs error); 117656979Sgibbs goto fail; 117756979Sgibbs } 117856979Sgibbs 117940024Sgibbs /* Start the Risc processor now that we are fully configured. */ 118040024Sgibbs adw_outw(adw, ADW_RISC_CSR, ADW_RISC_CSR_RUN); 118140024Sgibbs 118240024Sgibbs /* 118340024Sgibbs * Create the device queue for our SIM. 118440024Sgibbs */ 118540024Sgibbs devq = cam_simq_alloc(adw->max_acbs); 118640024Sgibbs if (devq == NULL) 118756979Sgibbs return (ENOMEM); 118840024Sgibbs 118940024Sgibbs /* 119040024Sgibbs * Construct our SIM entry. 119140024Sgibbs */ 119240024Sgibbs adw->sim = cam_sim_alloc(adw_action, adw_poll, "adw", adw, adw->unit, 119340024Sgibbs 1, adw->max_acbs, devq); 119456979Sgibbs if (adw->sim == NULL) { 119556979Sgibbs error = ENOMEM; 119656979Sgibbs goto fail; 119756979Sgibbs } 119840024Sgibbs 119940024Sgibbs /* 120040024Sgibbs * Register the bus. 120140024Sgibbs */ 120240024Sgibbs if (xpt_bus_register(adw->sim, 0) != CAM_SUCCESS) { 120340024Sgibbs cam_sim_free(adw->sim, /*free devq*/TRUE); 120456979Sgibbs error = ENOMEM; 120556979Sgibbs goto fail; 120640024Sgibbs } 120740024Sgibbs 120840024Sgibbs if (xpt_create_path(&adw->path, /*periph*/NULL, cam_sim_path(adw->sim), 120940024Sgibbs CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) 121040024Sgibbs == CAM_REQ_CMP) { 121140024Sgibbs xpt_setup_ccb(&csa.ccb_h, adw->path, /*priority*/5); 121240024Sgibbs csa.ccb_h.func_code = XPT_SASYNC_CB; 121340024Sgibbs csa.event_enable = AC_LOST_DEVICE; 121440024Sgibbs csa.callback = adw_async; 121540024Sgibbs csa.callback_arg = adw; 121640024Sgibbs xpt_action((union ccb *)&csa); 121740024Sgibbs } 121840024Sgibbs 121956979Sgibbsfail: 122056979Sgibbs splx(s); 122156979Sgibbs return (error); 122240024Sgibbs} 122340024Sgibbs 122440024Sgibbsvoid 122540024Sgibbsadw_intr(void *arg) 122640024Sgibbs{ 122740024Sgibbs struct adw_softc *adw; 122840024Sgibbs u_int int_stat; 122940024Sgibbs 123040024Sgibbs adw = (struct adw_softc *)arg; 123140024Sgibbs if ((adw_inw(adw, ADW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR) == 0) 123240024Sgibbs return; 123340024Sgibbs 123440024Sgibbs /* Reading the register clears the interrupt. */ 123540024Sgibbs int_stat = adw_inb(adw, ADW_INTR_STATUS_REG); 123640024Sgibbs 123740024Sgibbs if ((int_stat & ADW_INTR_STATUS_INTRB) != 0) { 123856979Sgibbs u_int intrb_code; 123956979Sgibbs 124056979Sgibbs /* Async Microcode Event */ 124156979Sgibbs intrb_code = adw_lram_read_8(adw, ADW_MC_INTRB_CODE); 124256979Sgibbs switch (intrb_code) { 124356979Sgibbs case ADW_ASYNC_CARRIER_READY_FAILURE: 124456979Sgibbs /* 124556979Sgibbs * The RISC missed our update of 124656979Sgibbs * the commandq. 124756979Sgibbs */ 124856979Sgibbs if (LIST_FIRST(&adw->pending_ccbs) != NULL) 124956979Sgibbs adw_tickle_risc(adw, ADW_TICKLE_A); 125040024Sgibbs break; 125156979Sgibbs case ADW_ASYNC_SCSI_BUS_RESET_DET: 125256979Sgibbs /* 125356979Sgibbs * The firmware detected a SCSI Bus reset. 125456979Sgibbs */ 125556979Sgibbs printf("Someone Reset the Bus\n"); 125656979Sgibbs adw_handle_bus_reset(adw, /*initiated*/FALSE); 125756979Sgibbs break; 125856979Sgibbs case ADW_ASYNC_RDMA_FAILURE: 125956979Sgibbs /* 126056979Sgibbs * Handle RDMA failure by resetting the 126156979Sgibbs * SCSI Bus and chip. 126256979Sgibbs */ 126356979Sgibbs#if XXX 126456979Sgibbs AdvResetChipAndSB(adv_dvc_varp); 126556979Sgibbs#endif 126656979Sgibbs break; 126756979Sgibbs 126856979Sgibbs case ADW_ASYNC_HOST_SCSI_BUS_RESET: 126956979Sgibbs /* 127056979Sgibbs * Host generated SCSI bus reset occurred. 127156979Sgibbs */ 127240024Sgibbs adw_handle_bus_reset(adw, /*initiated*/TRUE); 127356979Sgibbs break; 127456979Sgibbs default: 127556979Sgibbs printf("adw_intr: unknown async code 0x%x\n", 127656979Sgibbs intrb_code); 127740024Sgibbs break; 127840024Sgibbs } 127940024Sgibbs } 128040024Sgibbs 128140024Sgibbs /* 128256979Sgibbs * Run down the RequestQ. 128340024Sgibbs */ 128456979Sgibbs while ((adw->responseq->next_ba & ADW_RQ_DONE) != 0) { 128556979Sgibbs struct adw_carrier *free_carrier; 128656979Sgibbs struct acb *acb; 128756979Sgibbs union ccb *ccb; 128840024Sgibbs 128956979Sgibbs#if 0 129056979Sgibbs printf("0x%x, 0x%x, 0x%x, 0x%x\n", 129156979Sgibbs adw->responseq->carr_offset, 129256979Sgibbs adw->responseq->carr_ba, 129356979Sgibbs adw->responseq->areq_ba, 129456979Sgibbs adw->responseq->next_ba); 129556979Sgibbs#endif 129656979Sgibbs /* 129756979Sgibbs * The firmware copies the adw_scsi_req_q.acb_baddr 129856979Sgibbs * field into the areq_ba field of the carrier. 129956979Sgibbs */ 130056979Sgibbs acb = acbbotov(adw, adw->responseq->areq_ba); 130140024Sgibbs 130240024Sgibbs /* 130356979Sgibbs * The least significant four bits of the next_ba 130456979Sgibbs * field are used as flags. Mask them out and then 130556979Sgibbs * advance through the list. 130640024Sgibbs */ 130756979Sgibbs free_carrier = adw->responseq; 130856979Sgibbs adw->responseq = 130956979Sgibbs carrierbotov(adw, free_carrier->next_ba & ADW_NEXT_BA_MASK); 131056979Sgibbs free_carrier->next_ba = adw->free_carriers->carr_offset; 131156979Sgibbs adw->free_carriers = free_carrier; 131240024Sgibbs 131340024Sgibbs /* Process CCB */ 131440024Sgibbs ccb = acb->ccb; 131540024Sgibbs untimeout(adwtimeout, acb, ccb->ccb_h.timeout_ch); 131640024Sgibbs if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 131740024Sgibbs bus_dmasync_op_t op; 131840024Sgibbs 131940024Sgibbs if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 132040024Sgibbs op = BUS_DMASYNC_POSTREAD; 132140024Sgibbs else 132240024Sgibbs op = BUS_DMASYNC_POSTWRITE; 132340024Sgibbs bus_dmamap_sync(adw->buffer_dmat, acb->dmamap, op); 132440024Sgibbs bus_dmamap_unload(adw->buffer_dmat, acb->dmamap); 132540024Sgibbs ccb->csio.resid = acb->queue.data_cnt; 132640024Sgibbs } else 132740024Sgibbs ccb->csio.resid = 0; 132840024Sgibbs 132940024Sgibbs /* Common Cases inline... */ 133040024Sgibbs if (acb->queue.host_status == QHSTA_NO_ERROR 133140024Sgibbs && (acb->queue.done_status == QD_NO_ERROR 133240024Sgibbs || acb->queue.done_status == QD_WITH_ERROR)) { 133340024Sgibbs ccb->csio.scsi_status = acb->queue.scsi_status; 133440024Sgibbs ccb->ccb_h.status = 0; 133540024Sgibbs switch (ccb->csio.scsi_status) { 133640024Sgibbs case SCSI_STATUS_OK: 133740024Sgibbs ccb->ccb_h.status |= CAM_REQ_CMP; 133840024Sgibbs break; 133940024Sgibbs case SCSI_STATUS_CHECK_COND: 134040024Sgibbs case SCSI_STATUS_CMD_TERMINATED: 134140024Sgibbs bcopy(&acb->sense_data, &ccb->csio.sense_data, 134240024Sgibbs ccb->csio.sense_len); 134340024Sgibbs ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 134440024Sgibbs ccb->csio.sense_resid = acb->queue.sense_len; 134540024Sgibbs /* FALLTHROUGH */ 134640024Sgibbs default: 134740024Sgibbs ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR 134840024Sgibbs | CAM_DEV_QFRZN; 134940024Sgibbs xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 135040024Sgibbs break; 135140024Sgibbs } 135240024Sgibbs adwfreeacb(adw, acb); 135340024Sgibbs xpt_done(ccb); 135440024Sgibbs } else { 135540024Sgibbs adwprocesserror(adw, acb); 135640024Sgibbs } 135740024Sgibbs } 135840024Sgibbs} 135940024Sgibbs 136040024Sgibbsstatic void 136140024Sgibbsadwprocesserror(struct adw_softc *adw, struct acb *acb) 136240024Sgibbs{ 136340024Sgibbs union ccb *ccb; 136440024Sgibbs 136540024Sgibbs ccb = acb->ccb; 136640024Sgibbs if (acb->queue.done_status == QD_ABORTED_BY_HOST) { 136740024Sgibbs ccb->ccb_h.status = CAM_REQ_ABORTED; 136840024Sgibbs } else { 136940024Sgibbs 137040024Sgibbs switch (acb->queue.host_status) { 137140024Sgibbs case QHSTA_M_SEL_TIMEOUT: 137240024Sgibbs ccb->ccb_h.status = CAM_SEL_TIMEOUT; 137340024Sgibbs break; 137440024Sgibbs case QHSTA_M_SXFR_OFF_UFLW: 137540024Sgibbs case QHSTA_M_SXFR_OFF_OFLW: 137640024Sgibbs case QHSTA_M_DATA_OVER_RUN: 137740024Sgibbs ccb->ccb_h.status = CAM_DATA_RUN_ERR; 137840024Sgibbs break; 137940024Sgibbs case QHSTA_M_SXFR_DESELECTED: 138040024Sgibbs case QHSTA_M_UNEXPECTED_BUS_FREE: 138140024Sgibbs ccb->ccb_h.status = CAM_UNEXP_BUSFREE; 138240024Sgibbs break; 138357679Sgibbs case QHSTA_M_SCSI_BUS_RESET: 138457679Sgibbs case QHSTA_M_SCSI_BUS_RESET_UNSOL: 138557679Sgibbs ccb->ccb_h.status = CAM_SCSI_BUS_RESET; 138657679Sgibbs break; 138757679Sgibbs case QHSTA_M_BUS_DEVICE_RESET: 138857679Sgibbs ccb->ccb_h.status = CAM_BDR_SENT; 138957679Sgibbs break; 139040024Sgibbs case QHSTA_M_QUEUE_ABORTED: 139140024Sgibbs /* BDR or Bus Reset */ 139257679Sgibbs printf("Saw Queue Aborted\n"); 139340024Sgibbs ccb->ccb_h.status = adw->last_reset; 139440024Sgibbs break; 139540024Sgibbs case QHSTA_M_SXFR_SDMA_ERR: 139640024Sgibbs case QHSTA_M_SXFR_SXFR_PERR: 139740024Sgibbs case QHSTA_M_RDMA_PERR: 139840024Sgibbs ccb->ccb_h.status = CAM_UNCOR_PARITY; 139940024Sgibbs break; 140040024Sgibbs case QHSTA_M_WTM_TIMEOUT: 140140024Sgibbs case QHSTA_M_SXFR_WD_TMO: 140256979Sgibbs { 140340024Sgibbs /* The SCSI bus hung in a phase */ 140457679Sgibbs xpt_print_path(adw->path); 140557679Sgibbs printf("Watch Dog timer expired. Reseting bus\n"); 140657679Sgibbs adw_reset_bus(adw); 140740024Sgibbs break; 140856979Sgibbs } 140940024Sgibbs case QHSTA_M_SXFR_XFR_PH_ERR: 141040024Sgibbs ccb->ccb_h.status = CAM_SEQUENCE_FAIL; 141140024Sgibbs break; 141240024Sgibbs case QHSTA_M_SXFR_UNKNOWN_ERROR: 141340024Sgibbs break; 141440024Sgibbs case QHSTA_M_BAD_CMPL_STATUS_IN: 141540024Sgibbs /* No command complete after a status message */ 141640024Sgibbs ccb->ccb_h.status = CAM_SEQUENCE_FAIL; 141740024Sgibbs break; 141840024Sgibbs case QHSTA_M_AUTO_REQ_SENSE_FAIL: 141940024Sgibbs ccb->ccb_h.status = CAM_AUTOSENSE_FAIL; 142040024Sgibbs break; 142140024Sgibbs case QHSTA_M_INVALID_DEVICE: 142240024Sgibbs ccb->ccb_h.status = CAM_PATH_INVALID; 142340024Sgibbs break; 142440024Sgibbs case QHSTA_M_NO_AUTO_REQ_SENSE: 142540024Sgibbs /* 142640024Sgibbs * User didn't request sense, but we got a 142740024Sgibbs * check condition. 142840024Sgibbs */ 142940024Sgibbs ccb->csio.scsi_status = acb->queue.scsi_status; 143040024Sgibbs ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 143140024Sgibbs break; 143240024Sgibbs default: 143340024Sgibbs panic("%s: Unhandled Host status error %x", 143440024Sgibbs adw_name(adw), acb->queue.host_status); 143540024Sgibbs /* NOTREACHED */ 143640024Sgibbs } 143740024Sgibbs } 143857679Sgibbs if ((acb->state & ACB_RECOVERY_ACB) != 0) { 143957679Sgibbs if (ccb->ccb_h.status == CAM_SCSI_BUS_RESET 144057679Sgibbs || ccb->ccb_h.status == CAM_BDR_SENT) 144157679Sgibbs ccb->ccb_h.status = CAM_CMD_TIMEOUT; 144257679Sgibbs } 144340024Sgibbs if (ccb->ccb_h.status != CAM_REQ_CMP) { 144440024Sgibbs xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 144540024Sgibbs ccb->ccb_h.status |= CAM_DEV_QFRZN; 144640024Sgibbs } 144740024Sgibbs adwfreeacb(adw, acb); 144840024Sgibbs xpt_done(ccb); 144940024Sgibbs} 145040024Sgibbs 145140024Sgibbsstatic void 145240024Sgibbsadwtimeout(void *arg) 145340024Sgibbs{ 145440024Sgibbs struct acb *acb; 145540024Sgibbs union ccb *ccb; 145640024Sgibbs struct adw_softc *adw; 145740024Sgibbs adw_idle_cmd_status_t status; 145857679Sgibbs int target_id; 145940024Sgibbs int s; 146040024Sgibbs 146140024Sgibbs acb = (struct acb *)arg; 146240024Sgibbs ccb = acb->ccb; 146340024Sgibbs adw = (struct adw_softc *)ccb->ccb_h.ccb_adw_ptr; 146440024Sgibbs xpt_print_path(ccb->ccb_h.path); 146540024Sgibbs printf("ACB %p - timed out\n", (void *)acb); 146640024Sgibbs 146740024Sgibbs s = splcam(); 146840024Sgibbs 146940024Sgibbs if ((acb->state & ACB_ACTIVE) == 0) { 147040024Sgibbs xpt_print_path(ccb->ccb_h.path); 147140024Sgibbs printf("ACB %p - timed out CCB already completed\n", 147240024Sgibbs (void *)acb); 147340024Sgibbs splx(s); 147440024Sgibbs return; 147540024Sgibbs } 147640024Sgibbs 147757679Sgibbs acb->state |= ACB_RECOVERY_ACB; 147857679Sgibbs target_id = ccb->ccb_h.target_id; 147957679Sgibbs 148040024Sgibbs /* Attempt a BDR first */ 148157679Sgibbs status = adw_idle_cmd_send(adw, ADW_IDLE_CMD_DEVICE_RESET, 148257679Sgibbs ccb->ccb_h.target_id); 148340024Sgibbs splx(s); 148440024Sgibbs if (status == ADW_IDLE_CMD_SUCCESS) { 148540024Sgibbs printf("%s: BDR Delivered. No longer in timeout\n", 148640024Sgibbs adw_name(adw)); 148757679Sgibbs adw_handle_device_reset(adw, target_id); 148840024Sgibbs } else { 148957679Sgibbs adw_reset_bus(adw); 149057679Sgibbs xpt_print_path(adw->path); 149157679Sgibbs printf("Bus Reset Delivered. No longer in timeout\n"); 149240024Sgibbs } 149340024Sgibbs} 149440024Sgibbs 149540024Sgibbsstatic void 149640024Sgibbsadw_handle_device_reset(struct adw_softc *adw, u_int target) 149740024Sgibbs{ 149840024Sgibbs struct cam_path *path; 149940024Sgibbs cam_status error; 150040024Sgibbs 150140024Sgibbs error = xpt_create_path(&path, /*periph*/NULL, cam_sim_path(adw->sim), 150240024Sgibbs target, CAM_LUN_WILDCARD); 150340024Sgibbs 150440024Sgibbs if (error == CAM_REQ_CMP) { 150540024Sgibbs xpt_async(AC_SENT_BDR, path, NULL); 150640024Sgibbs xpt_free_path(path); 150740024Sgibbs } 150840024Sgibbs adw->last_reset = CAM_BDR_SENT; 150940024Sgibbs} 151040024Sgibbs 151140024Sgibbsstatic void 151240024Sgibbsadw_handle_bus_reset(struct adw_softc *adw, int initiated) 151340024Sgibbs{ 151440024Sgibbs if (initiated) { 151540024Sgibbs /* 151640024Sgibbs * The microcode currently sets the SCSI Bus Reset signal 151740024Sgibbs * while handling the AscSendIdleCmd() IDLE_CMD_SCSI_RESET 151840024Sgibbs * command above. But the SCSI Bus Reset Hold Time in the 151940024Sgibbs * microcode is not deterministic (it may in fact be for less 152040024Sgibbs * than the SCSI Spec. minimum of 25 us). Therefore on return 152140024Sgibbs * the Adv Library sets the SCSI Bus Reset signal for 152240024Sgibbs * ADW_SCSI_RESET_HOLD_TIME_US, which is defined to be greater 152340024Sgibbs * than 25 us. 152440024Sgibbs */ 152540024Sgibbs u_int scsi_ctrl; 152640024Sgibbs 152740024Sgibbs scsi_ctrl = adw_inw(adw, ADW_SCSI_CTRL) & ~ADW_SCSI_CTRL_RSTOUT; 152840024Sgibbs adw_outw(adw, ADW_SCSI_CTRL, scsi_ctrl | ADW_SCSI_CTRL_RSTOUT); 152940024Sgibbs DELAY(ADW_SCSI_RESET_HOLD_TIME_US); 153040024Sgibbs adw_outw(adw, ADW_SCSI_CTRL, scsi_ctrl); 153140024Sgibbs 153240024Sgibbs /* 153340024Sgibbs * We will perform the async notification when the 153440024Sgibbs * SCSI Reset interrupt occurs. 153540024Sgibbs */ 153640024Sgibbs } else 153740024Sgibbs xpt_async(AC_BUS_RESET, adw->path, NULL); 153840024Sgibbs adw->last_reset = CAM_SCSI_BUS_RESET; 153940024Sgibbs} 1540