adwcam.c revision 117126
1/* 2 * CAM SCSI interface for the the Advanced Systems Inc. 3 * Second Generation SCSI controllers. 4 * 5 * Product specific probe and attach routines can be found in: 6 * 7 * adw_pci.c ABP[3]940UW, ABP950UW, ABP3940U2W 8 * 9 * Copyright (c) 1998, 1999, 2000 Justin Gibbs. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions, and the following disclaimer, 17 * without modification. 18 * 2. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/advansys/adwcam.c 117126 2003-07-01 15:52:06Z scottl $ 34 */ 35/* 36 * Ported from: 37 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 38 * 39 * Copyright (c) 1995-1998 Advanced System Products, Inc. 40 * All Rights Reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that redistributions of source 44 * code retain the above copyright notice and this comment without 45 * modification. 46 */ 47 48#include <sys/param.h> 49#include <sys/systm.h> 50#include <sys/kernel.h> 51#include <sys/malloc.h> 52#include <sys/lock.h> 53#include <sys/mutex.h> 54#include <sys/bus.h> 55 56#include <machine/bus_pio.h> 57#include <machine/bus_memio.h> 58#include <machine/bus.h> 59#include <machine/resource.h> 60 61#include <sys/rman.h> 62 63#include <cam/cam.h> 64#include <cam/cam_ccb.h> 65#include <cam/cam_sim.h> 66#include <cam/cam_xpt_sim.h> 67#include <cam/cam_debug.h> 68 69#include <cam/scsi/scsi_message.h> 70 71#include <dev/advansys/adwvar.h> 72 73/* Definitions for our use of the SIM private CCB area */ 74#define ccb_acb_ptr spriv_ptr0 75#define ccb_adw_ptr spriv_ptr1 76 77u_long adw_unit; 78 79static __inline cam_status adwccbstatus(union ccb*); 80static __inline struct acb* adwgetacb(struct adw_softc *adw); 81static __inline void adwfreeacb(struct adw_softc *adw, 82 struct acb *acb); 83 84static void adwmapmem(void *arg, bus_dma_segment_t *segs, 85 int nseg, int error); 86static struct sg_map_node* 87 adwallocsgmap(struct adw_softc *adw); 88static int adwallocacbs(struct adw_softc *adw); 89 90static void adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs, 91 int nseg, int error); 92static void adw_action(struct cam_sim *sim, union ccb *ccb); 93static void adw_poll(struct cam_sim *sim); 94static void adw_async(void *callback_arg, u_int32_t code, 95 struct cam_path *path, void *arg); 96static void adwprocesserror(struct adw_softc *adw, struct acb *acb); 97static void adwtimeout(void *arg); 98static void adw_handle_device_reset(struct adw_softc *adw, 99 u_int target); 100static void adw_handle_bus_reset(struct adw_softc *adw, 101 int initiated); 102 103static __inline cam_status 104adwccbstatus(union ccb* ccb) 105{ 106 return (ccb->ccb_h.status & CAM_STATUS_MASK); 107} 108 109static __inline struct acb* 110adwgetacb(struct adw_softc *adw) 111{ 112 struct acb* acb; 113 int s; 114 115 s = splcam(); 116 if ((acb = SLIST_FIRST(&adw->free_acb_list)) != NULL) { 117 SLIST_REMOVE_HEAD(&adw->free_acb_list, links); 118 } else if (adw->num_acbs < adw->max_acbs) { 119 adwallocacbs(adw); 120 acb = SLIST_FIRST(&adw->free_acb_list); 121 if (acb == NULL) 122 printf("%s: Can't malloc ACB\n", adw_name(adw)); 123 else { 124 SLIST_REMOVE_HEAD(&adw->free_acb_list, links); 125 } 126 } 127 splx(s); 128 129 return (acb); 130} 131 132static __inline void 133adwfreeacb(struct adw_softc *adw, struct acb *acb) 134{ 135 int s; 136 137 s = splcam(); 138 if ((acb->state & ACB_ACTIVE) != 0) 139 LIST_REMOVE(&acb->ccb->ccb_h, sim_links.le); 140 if ((acb->state & ACB_RELEASE_SIMQ) != 0) 141 acb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 142 else if ((adw->state & ADW_RESOURCE_SHORTAGE) != 0 143 && (acb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) { 144 acb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 145 adw->state &= ~ADW_RESOURCE_SHORTAGE; 146 } 147 acb->state = ACB_FREE; 148 SLIST_INSERT_HEAD(&adw->free_acb_list, acb, links); 149 splx(s); 150} 151 152static void 153adwmapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error) 154{ 155 bus_addr_t *busaddrp; 156 157 busaddrp = (bus_addr_t *)arg; 158 *busaddrp = segs->ds_addr; 159} 160 161static struct sg_map_node * 162adwallocsgmap(struct adw_softc *adw) 163{ 164 struct sg_map_node *sg_map; 165 166 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 167 168 if (sg_map == NULL) 169 return (NULL); 170 171 /* Allocate S/G space for the next batch of ACBS */ 172 if (bus_dmamem_alloc(adw->sg_dmat, (void **)&sg_map->sg_vaddr, 173 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { 174 free(sg_map, M_DEVBUF); 175 return (NULL); 176 } 177 178 SLIST_INSERT_HEAD(&adw->sg_maps, sg_map, links); 179 180 bus_dmamap_load(adw->sg_dmat, sg_map->sg_dmamap, sg_map->sg_vaddr, 181 PAGE_SIZE, adwmapmem, &sg_map->sg_physaddr, /*flags*/0); 182 183 bzero(sg_map->sg_vaddr, PAGE_SIZE); 184 return (sg_map); 185} 186 187/* 188 * Allocate another chunk of CCB's. Return count of entries added. 189 * Assumed to be called at splcam(). 190 */ 191static int 192adwallocacbs(struct adw_softc *adw) 193{ 194 struct acb *next_acb; 195 struct sg_map_node *sg_map; 196 bus_addr_t busaddr; 197 struct adw_sg_block *blocks; 198 int newcount; 199 int i; 200 201 next_acb = &adw->acbs[adw->num_acbs]; 202 sg_map = adwallocsgmap(adw); 203 204 if (sg_map == NULL) 205 return (0); 206 207 blocks = sg_map->sg_vaddr; 208 busaddr = sg_map->sg_physaddr; 209 210 newcount = (PAGE_SIZE / (ADW_SG_BLOCKCNT * sizeof(*blocks))); 211 for (i = 0; adw->num_acbs < adw->max_acbs && i < newcount; i++) { 212 int error; 213 214 error = bus_dmamap_create(adw->buffer_dmat, /*flags*/0, 215 &next_acb->dmamap); 216 if (error != 0) 217 break; 218 next_acb->queue.scsi_req_baddr = acbvtob(adw, next_acb); 219 next_acb->queue.scsi_req_bo = acbvtobo(adw, next_acb); 220 next_acb->queue.sense_baddr = 221 acbvtob(adw, next_acb) + offsetof(struct acb, sense_data); 222 next_acb->sg_blocks = blocks; 223 next_acb->sg_busaddr = busaddr; 224 next_acb->state = ACB_FREE; 225 SLIST_INSERT_HEAD(&adw->free_acb_list, next_acb, links); 226 blocks += ADW_SG_BLOCKCNT; 227 busaddr += ADW_SG_BLOCKCNT * sizeof(*blocks); 228 next_acb++; 229 adw->num_acbs++; 230 } 231 return (i); 232} 233 234static void 235adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 236{ 237 struct acb *acb; 238 union ccb *ccb; 239 struct adw_softc *adw; 240 int s; 241 242 acb = (struct acb *)arg; 243 ccb = acb->ccb; 244 adw = (struct adw_softc *)ccb->ccb_h.ccb_adw_ptr; 245 246 if (error != 0) { 247 if (error != EFBIG) 248 printf("%s: Unexepected error 0x%x returned from " 249 "bus_dmamap_load\n", adw_name(adw), error); 250 if (ccb->ccb_h.status == CAM_REQ_INPROG) { 251 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 252 ccb->ccb_h.status = CAM_REQ_TOO_BIG|CAM_DEV_QFRZN; 253 } 254 adwfreeacb(adw, acb); 255 xpt_done(ccb); 256 return; 257 } 258 259 if (nseg != 0) { 260 bus_dmasync_op_t op; 261 262 acb->queue.data_addr = dm_segs[0].ds_addr; 263 acb->queue.data_cnt = ccb->csio.dxfer_len; 264 if (nseg > 1) { 265 struct adw_sg_block *sg_block; 266 struct adw_sg_elm *sg; 267 bus_addr_t sg_busaddr; 268 u_int sg_index; 269 bus_dma_segment_t *end_seg; 270 271 end_seg = dm_segs + nseg; 272 273 sg_busaddr = acb->sg_busaddr; 274 sg_index = 0; 275 /* Copy the segments into our SG list */ 276 for (sg_block = acb->sg_blocks;; sg_block++) { 277 u_int i; 278 279 sg = sg_block->sg_list; 280 for (i = 0; i < ADW_NO_OF_SG_PER_BLOCK; i++) { 281 if (dm_segs >= end_seg) 282 break; 283 284 sg->sg_addr = dm_segs->ds_addr; 285 sg->sg_count = dm_segs->ds_len; 286 sg++; 287 dm_segs++; 288 } 289 sg_block->sg_cnt = i; 290 sg_index += i; 291 if (dm_segs == end_seg) { 292 sg_block->sg_busaddr_next = 0; 293 break; 294 } else { 295 sg_busaddr += 296 sizeof(struct adw_sg_block); 297 sg_block->sg_busaddr_next = sg_busaddr; 298 } 299 } 300 acb->queue.sg_real_addr = acb->sg_busaddr; 301 } else { 302 acb->queue.sg_real_addr = 0; 303 } 304 305 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 306 op = BUS_DMASYNC_PREREAD; 307 else 308 op = BUS_DMASYNC_PREWRITE; 309 310 bus_dmamap_sync(adw->buffer_dmat, acb->dmamap, op); 311 312 } else { 313 acb->queue.data_addr = 0; 314 acb->queue.data_cnt = 0; 315 acb->queue.sg_real_addr = 0; 316 } 317 318 s = splcam(); 319 320 /* 321 * Last time we need to check if this CCB needs to 322 * be aborted. 323 */ 324 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 325 if (nseg != 0) 326 bus_dmamap_unload(adw->buffer_dmat, acb->dmamap); 327 adwfreeacb(adw, acb); 328 xpt_done(ccb); 329 splx(s); 330 return; 331 } 332 333 acb->state |= ACB_ACTIVE; 334 ccb->ccb_h.status |= CAM_SIM_QUEUED; 335 LIST_INSERT_HEAD(&adw->pending_ccbs, &ccb->ccb_h, sim_links.le); 336 ccb->ccb_h.timeout_ch = 337 timeout(adwtimeout, (caddr_t)acb, 338 (ccb->ccb_h.timeout * hz) / 1000); 339 340 adw_send_acb(adw, acb, acbvtob(adw, acb)); 341 342 splx(s); 343} 344 345static void 346adw_action(struct cam_sim *sim, union ccb *ccb) 347{ 348 struct adw_softc *adw; 349 350 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("adw_action\n")); 351 352 adw = (struct adw_softc *)cam_sim_softc(sim); 353 354 switch (ccb->ccb_h.func_code) { 355 /* Common cases first */ 356 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 357 { 358 struct ccb_scsiio *csio; 359 struct ccb_hdr *ccbh; 360 struct acb *acb; 361 362 csio = &ccb->csio; 363 ccbh = &ccb->ccb_h; 364 365 /* Max supported CDB length is 12 bytes */ 366 if (csio->cdb_len > 12) { 367 ccb->ccb_h.status = CAM_REQ_INVALID; 368 xpt_done(ccb); 369 return; 370 } 371 372 if ((acb = adwgetacb(adw)) == NULL) { 373 int s; 374 375 s = splcam(); 376 adw->state |= ADW_RESOURCE_SHORTAGE; 377 splx(s); 378 xpt_freeze_simq(sim, /*count*/1); 379 ccb->ccb_h.status = CAM_REQUEUE_REQ; 380 xpt_done(ccb); 381 return; 382 } 383 384 /* Link acb and ccb so we can find one from the other */ 385 acb->ccb = ccb; 386 ccb->ccb_h.ccb_acb_ptr = acb; 387 ccb->ccb_h.ccb_adw_ptr = adw; 388 389 acb->queue.cntl = 0; 390 acb->queue.target_cmd = 0; 391 acb->queue.target_id = ccb->ccb_h.target_id; 392 acb->queue.target_lun = ccb->ccb_h.target_lun; 393 394 acb->queue.mflag = 0; 395 acb->queue.sense_len = 396 MIN(csio->sense_len, sizeof(acb->sense_data)); 397 acb->queue.cdb_len = csio->cdb_len; 398 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0) { 399 switch (csio->tag_action) { 400 case MSG_SIMPLE_Q_TAG: 401 acb->queue.scsi_cntl = ADW_QSC_SIMPLE_Q_TAG; 402 break; 403 case MSG_HEAD_OF_Q_TAG: 404 acb->queue.scsi_cntl = ADW_QSC_HEAD_OF_Q_TAG; 405 break; 406 case MSG_ORDERED_Q_TAG: 407 acb->queue.scsi_cntl = ADW_QSC_ORDERED_Q_TAG; 408 break; 409 default: 410 acb->queue.scsi_cntl = ADW_QSC_NO_TAGMSG; 411 break; 412 } 413 } else 414 acb->queue.scsi_cntl = ADW_QSC_NO_TAGMSG; 415 416 if ((ccb->ccb_h.flags & CAM_DIS_DISCONNECT) != 0) 417 acb->queue.scsi_cntl |= ADW_QSC_NO_DISC; 418 419 acb->queue.done_status = 0; 420 acb->queue.scsi_status = 0; 421 acb->queue.host_status = 0; 422 acb->queue.sg_wk_ix = 0; 423 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 424 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 425 bcopy(csio->cdb_io.cdb_ptr, 426 acb->queue.cdb, csio->cdb_len); 427 } else { 428 /* I guess I could map it in... */ 429 ccb->ccb_h.status = CAM_REQ_INVALID; 430 adwfreeacb(adw, acb); 431 xpt_done(ccb); 432 return; 433 } 434 } else { 435 bcopy(csio->cdb_io.cdb_bytes, 436 acb->queue.cdb, csio->cdb_len); 437 } 438 439 /* 440 * If we have any data to send with this command, 441 * map it into bus space. 442 */ 443 if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 444 if ((ccbh->flags & CAM_SCATTER_VALID) == 0) { 445 /* 446 * We've been given a pointer 447 * to a single buffer. 448 */ 449 if ((ccbh->flags & CAM_DATA_PHYS) == 0) { 450 int s; 451 int error; 452 453 s = splsoftvm(); 454 error = 455 bus_dmamap_load(adw->buffer_dmat, 456 acb->dmamap, 457 csio->data_ptr, 458 csio->dxfer_len, 459 adwexecuteacb, 460 acb, /*flags*/0); 461 if (error == EINPROGRESS) { 462 /* 463 * So as to maintain ordering, 464 * freeze the controller queue 465 * until our mapping is 466 * returned. 467 */ 468 xpt_freeze_simq(sim, 1); 469 acb->state |= CAM_RELEASE_SIMQ; 470 } 471 splx(s); 472 } else { 473 struct bus_dma_segment seg; 474 475 /* Pointer to physical buffer */ 476 seg.ds_addr = 477 (bus_addr_t)csio->data_ptr; 478 seg.ds_len = csio->dxfer_len; 479 adwexecuteacb(acb, &seg, 1, 0); 480 } 481 } else { 482 struct bus_dma_segment *segs; 483 484 if ((ccbh->flags & CAM_DATA_PHYS) != 0) 485 panic("adw_action - Physical " 486 "segment pointers " 487 "unsupported"); 488 489 if ((ccbh->flags&CAM_SG_LIST_PHYS)==0) 490 panic("adw_action - Virtual " 491 "segment addresses " 492 "unsupported"); 493 494 /* Just use the segments provided */ 495 segs = (struct bus_dma_segment *)csio->data_ptr; 496 adwexecuteacb(acb, segs, csio->sglist_cnt, 497 (csio->sglist_cnt < ADW_SGSIZE) 498 ? 0 : EFBIG); 499 } 500 } else { 501 adwexecuteacb(acb, NULL, 0, 0); 502 } 503 break; 504 } 505 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 506 { 507 adw_idle_cmd_status_t status; 508 509 status = adw_idle_cmd_send(adw, ADW_IDLE_CMD_DEVICE_RESET, 510 ccb->ccb_h.target_id); 511 if (status == ADW_IDLE_CMD_SUCCESS) { 512 ccb->ccb_h.status = CAM_REQ_CMP; 513 if (bootverbose) { 514 xpt_print_path(ccb->ccb_h.path); 515 printf("BDR Delivered\n"); 516 } 517 } else 518 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 519 xpt_done(ccb); 520 break; 521 } 522 case XPT_ABORT: /* Abort the specified CCB */ 523 /* XXX Implement */ 524 ccb->ccb_h.status = CAM_REQ_INVALID; 525 xpt_done(ccb); 526 break; 527 case XPT_SET_TRAN_SETTINGS: 528 { 529 struct ccb_trans_settings *cts; 530 u_int target_mask; 531 int s; 532 533 cts = &ccb->cts; 534 target_mask = 0x01 << ccb->ccb_h.target_id; 535 536 s = splcam(); 537 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 538 u_int sdtrdone; 539 540 sdtrdone = adw_lram_read_16(adw, ADW_MC_SDTR_DONE); 541 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 542 u_int discenb; 543 544 discenb = 545 adw_lram_read_16(adw, ADW_MC_DISC_ENABLE); 546 547 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0) 548 discenb |= target_mask; 549 else 550 discenb &= ~target_mask; 551 552 adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, 553 discenb); 554 } 555 556 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 557 558 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0) 559 adw->tagenb |= target_mask; 560 else 561 adw->tagenb &= ~target_mask; 562 } 563 564 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) { 565 u_int wdtrenb_orig; 566 u_int wdtrenb; 567 u_int wdtrdone; 568 569 wdtrenb_orig = 570 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE); 571 wdtrenb = wdtrenb_orig; 572 wdtrdone = adw_lram_read_16(adw, 573 ADW_MC_WDTR_DONE); 574 switch (cts->bus_width) { 575 case MSG_EXT_WDTR_BUS_32_BIT: 576 case MSG_EXT_WDTR_BUS_16_BIT: 577 wdtrenb |= target_mask; 578 break; 579 case MSG_EXT_WDTR_BUS_8_BIT: 580 default: 581 wdtrenb &= ~target_mask; 582 break; 583 } 584 if (wdtrenb != wdtrenb_orig) { 585 adw_lram_write_16(adw, 586 ADW_MC_WDTR_ABLE, 587 wdtrenb); 588 wdtrdone &= ~target_mask; 589 adw_lram_write_16(adw, 590 ADW_MC_WDTR_DONE, 591 wdtrdone); 592 /* Wide negotiation forces async */ 593 sdtrdone &= ~target_mask; 594 adw_lram_write_16(adw, 595 ADW_MC_SDTR_DONE, 596 sdtrdone); 597 } 598 } 599 600 if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) 601 || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) { 602 u_int sdtr_orig; 603 u_int sdtr; 604 u_int sdtrable_orig; 605 u_int sdtrable; 606 607 sdtr = adw_get_chip_sdtr(adw, 608 ccb->ccb_h.target_id); 609 sdtr_orig = sdtr; 610 sdtrable = adw_lram_read_16(adw, 611 ADW_MC_SDTR_ABLE); 612 sdtrable_orig = sdtrable; 613 614 if ((cts->valid 615 & CCB_TRANS_SYNC_RATE_VALID) != 0) { 616 617 sdtr = 618 adw_find_sdtr(adw, 619 cts->sync_period); 620 } 621 622 if ((cts->valid 623 & CCB_TRANS_SYNC_OFFSET_VALID) != 0) { 624 if (cts->sync_offset == 0) 625 sdtr = ADW_MC_SDTR_ASYNC; 626 } 627 628 if (sdtr == ADW_MC_SDTR_ASYNC) 629 sdtrable &= ~target_mask; 630 else 631 sdtrable |= target_mask; 632 if (sdtr != sdtr_orig 633 || sdtrable != sdtrable_orig) { 634 adw_set_chip_sdtr(adw, 635 ccb->ccb_h.target_id, 636 sdtr); 637 sdtrdone &= ~target_mask; 638 adw_lram_write_16(adw, ADW_MC_SDTR_ABLE, 639 sdtrable); 640 adw_lram_write_16(adw, ADW_MC_SDTR_DONE, 641 sdtrdone); 642 643 } 644 } 645 } 646 splx(s); 647 ccb->ccb_h.status = CAM_REQ_CMP; 648 xpt_done(ccb); 649 break; 650 } 651 case XPT_GET_TRAN_SETTINGS: 652 /* Get default/user set transfer settings for the target */ 653 { 654 struct ccb_trans_settings *cts; 655 u_int target_mask; 656 657 cts = &ccb->cts; 658 target_mask = 0x01 << ccb->ccb_h.target_id; 659 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) { 660 u_int mc_sdtr; 661 662 cts->flags = 0; 663 if ((adw->user_discenb & target_mask) != 0) 664 cts->flags |= CCB_TRANS_DISC_ENB; 665 666 if ((adw->user_tagenb & target_mask) != 0) 667 cts->flags |= CCB_TRANS_TAG_ENB; 668 669 if ((adw->user_wdtr & target_mask) != 0) 670 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 671 else 672 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT; 673 674 mc_sdtr = adw_get_user_sdtr(adw, ccb->ccb_h.target_id); 675 cts->sync_period = adw_find_period(adw, mc_sdtr); 676 if (cts->sync_period != 0) 677 cts->sync_offset = 15; /* XXX ??? */ 678 else 679 cts->sync_offset = 0; 680 681 cts->valid = CCB_TRANS_SYNC_RATE_VALID 682 | CCB_TRANS_SYNC_OFFSET_VALID 683 | CCB_TRANS_BUS_WIDTH_VALID 684 | CCB_TRANS_DISC_VALID 685 | CCB_TRANS_TQ_VALID; 686 ccb->ccb_h.status = CAM_REQ_CMP; 687 } else { 688 u_int targ_tinfo; 689 690 cts->flags = 0; 691 if ((adw_lram_read_16(adw, ADW_MC_DISC_ENABLE) 692 & target_mask) != 0) 693 cts->flags |= CCB_TRANS_DISC_ENB; 694 695 if ((adw->tagenb & target_mask) != 0) 696 cts->flags |= CCB_TRANS_TAG_ENB; 697 698 targ_tinfo = 699 adw_lram_read_16(adw, 700 ADW_MC_DEVICE_HSHK_CFG_TABLE 701 + (2 * ccb->ccb_h.target_id)); 702 703 if ((targ_tinfo & ADW_HSHK_CFG_WIDE_XFR) != 0) 704 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 705 else 706 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT; 707 708 cts->sync_period = 709 adw_hshk_cfg_period_factor(targ_tinfo); 710 711 cts->sync_offset = targ_tinfo & ADW_HSHK_CFG_OFFSET; 712 if (cts->sync_period == 0) 713 cts->sync_offset = 0; 714 715 if (cts->sync_offset == 0) 716 cts->sync_period = 0; 717 } 718 cts->valid = CCB_TRANS_SYNC_RATE_VALID 719 | CCB_TRANS_SYNC_OFFSET_VALID 720 | CCB_TRANS_BUS_WIDTH_VALID 721 | CCB_TRANS_DISC_VALID 722 | CCB_TRANS_TQ_VALID; 723 ccb->ccb_h.status = CAM_REQ_CMP; 724 xpt_done(ccb); 725 break; 726 } 727 case XPT_CALC_GEOMETRY: 728 { 729 /* 730 * XXX Use Adaptec translation until I find out how to 731 * get this information from the card. 732 */ 733 cam_calc_geometry(&ccb->ccg, /*extended*/1); 734 xpt_done(ccb); 735 break; 736 } 737 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 738 { 739 int failure; 740 741 failure = adw_reset_bus(adw); 742 if (failure != 0) { 743 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 744 } else { 745 if (bootverbose) { 746 xpt_print_path(adw->path); 747 printf("Bus Reset Delivered\n"); 748 } 749 ccb->ccb_h.status = CAM_REQ_CMP; 750 } 751 xpt_done(ccb); 752 break; 753 } 754 case XPT_TERM_IO: /* Terminate the I/O process */ 755 /* XXX Implement */ 756 ccb->ccb_h.status = CAM_REQ_INVALID; 757 xpt_done(ccb); 758 break; 759 case XPT_PATH_INQ: /* Path routing inquiry */ 760 { 761 struct ccb_pathinq *cpi = &ccb->cpi; 762 763 cpi->version_num = 1; 764 cpi->hba_inquiry = PI_WIDE_16|PI_SDTR_ABLE|PI_TAG_ABLE; 765 cpi->target_sprt = 0; 766 cpi->hba_misc = 0; 767 cpi->hba_eng_cnt = 0; 768 cpi->max_target = ADW_MAX_TID; 769 cpi->max_lun = ADW_MAX_LUN; 770 cpi->initiator_id = adw->initiator_id; 771 cpi->bus_id = cam_sim_bus(sim); 772 cpi->base_transfer_speed = 3300; 773 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 774 strncpy(cpi->hba_vid, "AdvanSys", HBA_IDLEN); 775 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 776 cpi->unit_number = cam_sim_unit(sim); 777 cpi->ccb_h.status = CAM_REQ_CMP; 778 xpt_done(ccb); 779 break; 780 } 781 default: 782 ccb->ccb_h.status = CAM_REQ_INVALID; 783 xpt_done(ccb); 784 break; 785 } 786} 787 788static void 789adw_poll(struct cam_sim *sim) 790{ 791 adw_intr(cam_sim_softc(sim)); 792} 793 794static void 795adw_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg) 796{ 797} 798 799struct adw_softc * 800adw_alloc(device_t dev, struct resource *regs, int regs_type, int regs_id) 801{ 802 struct adw_softc *adw; 803 int i; 804 805 /* 806 * Allocate a storage area for us 807 */ 808 adw = malloc(sizeof(struct adw_softc), M_DEVBUF, M_NOWAIT | M_ZERO); 809 if (adw == NULL) { 810 printf("adw%d: cannot malloc!\n", device_get_unit(dev)); 811 return NULL; 812 } 813 LIST_INIT(&adw->pending_ccbs); 814 SLIST_INIT(&adw->sg_maps); 815 adw->device = dev; 816 adw->unit = device_get_unit(dev); 817 adw->regs_res_type = regs_type; 818 adw->regs_res_id = regs_id; 819 adw->regs = regs; 820 adw->tag = rman_get_bustag(regs); 821 adw->bsh = rman_get_bushandle(regs); 822 i = adw->unit / 10; 823 adw->name = malloc(sizeof("adw") + i + 1, M_DEVBUF, M_NOWAIT); 824 if (adw->name == NULL) { 825 printf("adw%d: cannot malloc name!\n", adw->unit); 826 free(adw, M_DEVBUF); 827 return NULL; 828 } 829 sprintf(adw->name, "adw%d", adw->unit); 830 return(adw); 831} 832 833void 834adw_free(struct adw_softc *adw) 835{ 836 switch (adw->init_level) { 837 case 9: 838 { 839 struct sg_map_node *sg_map; 840 841 while ((sg_map = SLIST_FIRST(&adw->sg_maps)) != NULL) { 842 SLIST_REMOVE_HEAD(&adw->sg_maps, links); 843 bus_dmamap_unload(adw->sg_dmat, 844 sg_map->sg_dmamap); 845 bus_dmamem_free(adw->sg_dmat, sg_map->sg_vaddr, 846 sg_map->sg_dmamap); 847 free(sg_map, M_DEVBUF); 848 } 849 bus_dma_tag_destroy(adw->sg_dmat); 850 } 851 case 8: 852 bus_dmamap_unload(adw->acb_dmat, adw->acb_dmamap); 853 case 7: 854 bus_dmamem_free(adw->acb_dmat, adw->acbs, 855 adw->acb_dmamap); 856 bus_dmamap_destroy(adw->acb_dmat, adw->acb_dmamap); 857 case 6: 858 bus_dma_tag_destroy(adw->acb_dmat); 859 case 5: 860 bus_dmamap_unload(adw->carrier_dmat, adw->carrier_dmamap); 861 case 4: 862 bus_dmamem_free(adw->carrier_dmat, adw->carriers, 863 adw->carrier_dmamap); 864 bus_dmamap_destroy(adw->carrier_dmat, adw->carrier_dmamap); 865 case 3: 866 bus_dma_tag_destroy(adw->carrier_dmat); 867 case 2: 868 bus_dma_tag_destroy(adw->buffer_dmat); 869 case 1: 870 bus_dma_tag_destroy(adw->parent_dmat); 871 case 0: 872 break; 873 } 874 free(adw->name, M_DEVBUF); 875 free(adw, M_DEVBUF); 876} 877 878int 879adw_init(struct adw_softc *adw) 880{ 881 struct adw_eeprom eep_config; 882 u_int tid; 883 u_int i; 884 u_int16_t checksum; 885 u_int16_t scsicfg1; 886 887 checksum = adw_eeprom_read(adw, &eep_config); 888 bcopy(eep_config.serial_number, adw->serial_number, 889 sizeof(adw->serial_number)); 890 if (checksum != eep_config.checksum) { 891 u_int16_t serial_number[3]; 892 893 adw->flags |= ADW_EEPROM_FAILED; 894 printf("%s: EEPROM checksum failed. Restoring Defaults\n", 895 adw_name(adw)); 896 897 /* 898 * Restore the default EEPROM settings. 899 * Assume the 6 byte board serial number that was read 900 * from EEPROM is correct even if the EEPROM checksum 901 * failed. 902 */ 903 bcopy(adw->default_eeprom, &eep_config, sizeof(eep_config)); 904 bcopy(adw->serial_number, eep_config.serial_number, 905 sizeof(serial_number)); 906 adw_eeprom_write(adw, &eep_config); 907 } 908 909 /* Pull eeprom information into our softc. */ 910 adw->bios_ctrl = eep_config.bios_ctrl; 911 adw->user_wdtr = eep_config.wdtr_able; 912 for (tid = 0; tid < ADW_MAX_TID; tid++) { 913 u_int mc_sdtr; 914 u_int16_t tid_mask; 915 916 tid_mask = 0x1 << tid; 917 if ((adw->features & ADW_ULTRA) != 0) { 918 /* 919 * Ultra chips store sdtr and ultraenb 920 * bits in their seeprom, so we must 921 * construct valid mc_sdtr entries for 922 * indirectly. 923 */ 924 if (eep_config.sync1.sync_enable & tid_mask) { 925 if (eep_config.sync2.ultra_enable & tid_mask) 926 mc_sdtr = ADW_MC_SDTR_20; 927 else 928 mc_sdtr = ADW_MC_SDTR_10; 929 } else 930 mc_sdtr = ADW_MC_SDTR_ASYNC; 931 } else { 932 switch (ADW_TARGET_GROUP(tid)) { 933 case 3: 934 mc_sdtr = eep_config.sync4.sdtr4; 935 break; 936 case 2: 937 mc_sdtr = eep_config.sync3.sdtr3; 938 break; 939 case 1: 940 mc_sdtr = eep_config.sync2.sdtr2; 941 break; 942 default: /* Shut up compiler */ 943 case 0: 944 mc_sdtr = eep_config.sync1.sdtr1; 945 break; 946 } 947 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid); 948 mc_sdtr &= 0xFF; 949 } 950 adw_set_user_sdtr(adw, tid, mc_sdtr); 951 } 952 adw->user_tagenb = eep_config.tagqng_able; 953 adw->user_discenb = eep_config.disc_enable; 954 adw->max_acbs = eep_config.max_host_qng; 955 adw->initiator_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 956 957 /* 958 * Sanity check the number of host openings. 959 */ 960 if (adw->max_acbs > ADW_DEF_MAX_HOST_QNG) 961 adw->max_acbs = ADW_DEF_MAX_HOST_QNG; 962 else if (adw->max_acbs < ADW_DEF_MIN_HOST_QNG) { 963 /* If the value is zero, assume it is uninitialized. */ 964 if (adw->max_acbs == 0) 965 adw->max_acbs = ADW_DEF_MAX_HOST_QNG; 966 else 967 adw->max_acbs = ADW_DEF_MIN_HOST_QNG; 968 } 969 970 scsicfg1 = 0; 971 if ((adw->features & ADW_ULTRA2) != 0) { 972 switch (eep_config.termination_lvd) { 973 default: 974 printf("%s: Invalid EEPROM LVD Termination Settings.\n", 975 adw_name(adw)); 976 printf("%s: Reverting to Automatic LVD Termination\n", 977 adw_name(adw)); 978 /* FALLTHROUGH */ 979 case ADW_EEPROM_TERM_AUTO: 980 break; 981 case ADW_EEPROM_TERM_BOTH_ON: 982 scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_LO; 983 /* FALLTHROUGH */ 984 case ADW_EEPROM_TERM_HIGH_ON: 985 scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_HI; 986 /* FALLTHROUGH */ 987 case ADW_EEPROM_TERM_OFF: 988 scsicfg1 |= ADW2_SCSI_CFG1_DIS_TERM_DRV; 989 break; 990 } 991 } 992 993 switch (eep_config.termination_se) { 994 default: 995 printf("%s: Invalid SE EEPROM Termination Settings.\n", 996 adw_name(adw)); 997 printf("%s: Reverting to Automatic SE Termination\n", 998 adw_name(adw)); 999 /* FALLTHROUGH */ 1000 case ADW_EEPROM_TERM_AUTO: 1001 break; 1002 case ADW_EEPROM_TERM_BOTH_ON: 1003 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L; 1004 /* FALLTHROUGH */ 1005 case ADW_EEPROM_TERM_HIGH_ON: 1006 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H; 1007 /* FALLTHROUGH */ 1008 case ADW_EEPROM_TERM_OFF: 1009 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_MANUAL; 1010 break; 1011 } 1012 printf("%s: SCSI ID %d, ", adw_name(adw), adw->initiator_id); 1013 1014 /* DMA tag for mapping buffers into device visible space. */ 1015 if (bus_dma_tag_create( 1016 /* parent */ adw->parent_dmat, 1017 /* alignment */ 1, 1018 /* boundary */ 0, 1019 /* lowaddr */ BUS_SPACE_MAXADDR_32BIT, 1020 /* highaddr */ BUS_SPACE_MAXADDR, 1021 /* filter */ NULL, 1022 /* filterarg */ NULL, 1023 /* maxsize */ MAXBSIZE, 1024 /* nsegments */ ADW_SGSIZE, 1025 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT, 1026 /* flags */ BUS_DMA_ALLOCNOW, 1027 /* lockfunc */ busdma_lock_mutex, 1028 /* lockarg */ &Giant, 1029 &adw->buffer_dmat) != 0) { 1030 return (ENOMEM); 1031 } 1032 1033 adw->init_level++; 1034 1035 /* DMA tag for our ccb carrier structures */ 1036 if (bus_dma_tag_create( 1037 /* parent */ adw->parent_dmat, 1038 /* alignment */ 0x10, 1039 /* boundary */ 0, 1040 /* lowaddr */ BUS_SPACE_MAXADDR_32BIT, 1041 /* highaddr */ BUS_SPACE_MAXADDR, 1042 /* filter */ NULL, 1043 /* filterarg */ NULL, 1044 /* maxsize */ (adw->max_acbs + 1045 ADW_NUM_CARRIER_QUEUES + 1) * 1046 sizeof(struct adw_carrier), 1047 /* nsegments */ 1, 1048 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT, 1049 /* flags */ 0, 1050 /* lockfunc */ busdma_lock_mutex, 1051 /* lockarg */ &Giant, 1052 &adw->carrier_dmat) != 0) { 1053 return (ENOMEM); 1054 } 1055 1056 adw->init_level++; 1057 1058 /* Allocation for our ccb carrier structures */ 1059 if (bus_dmamem_alloc(adw->carrier_dmat, (void **)&adw->carriers, 1060 BUS_DMA_NOWAIT, &adw->carrier_dmamap) != 0) { 1061 return (ENOMEM); 1062 } 1063 1064 adw->init_level++; 1065 1066 /* And permanently map them */ 1067 bus_dmamap_load(adw->carrier_dmat, adw->carrier_dmamap, 1068 adw->carriers, 1069 (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1) 1070 * sizeof(struct adw_carrier), 1071 adwmapmem, &adw->carrier_busbase, /*flags*/0); 1072 1073 /* Clear them out. */ 1074 bzero(adw->carriers, (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1) 1075 * sizeof(struct adw_carrier)); 1076 1077 /* Setup our free carrier list */ 1078 adw->free_carriers = adw->carriers; 1079 for (i = 0; i < adw->max_acbs + ADW_NUM_CARRIER_QUEUES; i++) { 1080 adw->carriers[i].carr_offset = 1081 carriervtobo(adw, &adw->carriers[i]); 1082 adw->carriers[i].carr_ba = 1083 carriervtob(adw, &adw->carriers[i]); 1084 adw->carriers[i].areq_ba = 0; 1085 adw->carriers[i].next_ba = 1086 carriervtobo(adw, &adw->carriers[i+1]); 1087 } 1088 /* Terminal carrier. Never leaves the freelist */ 1089 adw->carriers[i].carr_offset = 1090 carriervtobo(adw, &adw->carriers[i]); 1091 adw->carriers[i].carr_ba = 1092 carriervtob(adw, &adw->carriers[i]); 1093 adw->carriers[i].areq_ba = 0; 1094 adw->carriers[i].next_ba = ~0; 1095 1096 adw->init_level++; 1097 1098 /* DMA tag for our acb structures */ 1099 if (bus_dma_tag_create( 1100 /* parent */ adw->parent_dmat, 1101 /* alignment */ 1, 1102 /* boundary */ 0, 1103 /* lowaddr */ BUS_SPACE_MAXADDR, 1104 /* highaddr */ BUS_SPACE_MAXADDR, 1105 /* filter */ NULL, 1106 /* filterarg */ NULL, 1107 /* maxsize */ adw->max_acbs * sizeof(struct acb), 1108 /* nsegments */ 1, 1109 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT, 1110 /* flags */ 0, 1111 /* lockfunc */ busdma_lock_mutex, 1112 /* lockarg */ &Giant, 1113 &adw->acb_dmat) != 0) { 1114 return (ENOMEM); 1115 } 1116 1117 adw->init_level++; 1118 1119 /* Allocation for our ccbs */ 1120 if (bus_dmamem_alloc(adw->acb_dmat, (void **)&adw->acbs, 1121 BUS_DMA_NOWAIT, &adw->acb_dmamap) != 0) 1122 return (ENOMEM); 1123 1124 adw->init_level++; 1125 1126 /* And permanently map them */ 1127 bus_dmamap_load(adw->acb_dmat, adw->acb_dmamap, 1128 adw->acbs, 1129 adw->max_acbs * sizeof(struct acb), 1130 adwmapmem, &adw->acb_busbase, /*flags*/0); 1131 1132 /* Clear them out. */ 1133 bzero(adw->acbs, adw->max_acbs * sizeof(struct acb)); 1134 1135 /* DMA tag for our S/G structures. We allocate in page sized chunks */ 1136 if (bus_dma_tag_create( 1137 /* parent */ adw->parent_dmat, 1138 /* alignment */ 1, 1139 /* boundary */ 0, 1140 /* lowaddr */ BUS_SPACE_MAXADDR, 1141 /* highaddr */ BUS_SPACE_MAXADDR, 1142 /* filter */ NULL, 1143 /* filterarg */ NULL, 1144 /* maxsize */ PAGE_SIZE, 1145 /* nsegments */ 1, 1146 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT, 1147 /* flags */ 0, 1148 /* lockfunc */ busdma_lock_mutex, 1149 /* lockarg */ &Giant, 1150 &adw->sg_dmat) != 0) { 1151 return (ENOMEM); 1152 } 1153 1154 adw->init_level++; 1155 1156 /* Allocate our first batch of ccbs */ 1157 if (adwallocacbs(adw) == 0) 1158 return (ENOMEM); 1159 1160 if (adw_init_chip(adw, scsicfg1) != 0) 1161 return (ENXIO); 1162 1163 printf("Queue Depth %d\n", adw->max_acbs); 1164 1165 return (0); 1166} 1167 1168/* 1169 * Attach all the sub-devices we can find 1170 */ 1171int 1172adw_attach(struct adw_softc *adw) 1173{ 1174 struct ccb_setasync csa; 1175 struct cam_devq *devq; 1176 int s; 1177 int error; 1178 1179 error = 0; 1180 s = splcam(); 1181 /* Hook up our interrupt handler */ 1182 if ((error = bus_setup_intr(adw->device, adw->irq, 1183 INTR_TYPE_CAM | INTR_ENTROPY, adw_intr, 1184 adw, &adw->ih)) != 0) { 1185 device_printf(adw->device, "bus_setup_intr() failed: %d\n", 1186 error); 1187 goto fail; 1188 } 1189 1190 /* Start the Risc processor now that we are fully configured. */ 1191 adw_outw(adw, ADW_RISC_CSR, ADW_RISC_CSR_RUN); 1192 1193 /* 1194 * Create the device queue for our SIM. 1195 */ 1196 devq = cam_simq_alloc(adw->max_acbs); 1197 if (devq == NULL) 1198 return (ENOMEM); 1199 1200 /* 1201 * Construct our SIM entry. 1202 */ 1203 adw->sim = cam_sim_alloc(adw_action, adw_poll, "adw", adw, adw->unit, 1204 1, adw->max_acbs, devq); 1205 if (adw->sim == NULL) { 1206 error = ENOMEM; 1207 goto fail; 1208 } 1209 1210 /* 1211 * Register the bus. 1212 */ 1213 if (xpt_bus_register(adw->sim, 0) != CAM_SUCCESS) { 1214 cam_sim_free(adw->sim, /*free devq*/TRUE); 1215 error = ENOMEM; 1216 goto fail; 1217 } 1218 1219 if (xpt_create_path(&adw->path, /*periph*/NULL, cam_sim_path(adw->sim), 1220 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) 1221 == CAM_REQ_CMP) { 1222 xpt_setup_ccb(&csa.ccb_h, adw->path, /*priority*/5); 1223 csa.ccb_h.func_code = XPT_SASYNC_CB; 1224 csa.event_enable = AC_LOST_DEVICE; 1225 csa.callback = adw_async; 1226 csa.callback_arg = adw; 1227 xpt_action((union ccb *)&csa); 1228 } 1229 1230fail: 1231 splx(s); 1232 return (error); 1233} 1234 1235void 1236adw_intr(void *arg) 1237{ 1238 struct adw_softc *adw; 1239 u_int int_stat; 1240 1241 adw = (struct adw_softc *)arg; 1242 if ((adw_inw(adw, ADW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR) == 0) 1243 return; 1244 1245 /* Reading the register clears the interrupt. */ 1246 int_stat = adw_inb(adw, ADW_INTR_STATUS_REG); 1247 1248 if ((int_stat & ADW_INTR_STATUS_INTRB) != 0) { 1249 u_int intrb_code; 1250 1251 /* Async Microcode Event */ 1252 intrb_code = adw_lram_read_8(adw, ADW_MC_INTRB_CODE); 1253 switch (intrb_code) { 1254 case ADW_ASYNC_CARRIER_READY_FAILURE: 1255 /* 1256 * The RISC missed our update of 1257 * the commandq. 1258 */ 1259 if (LIST_FIRST(&adw->pending_ccbs) != NULL) 1260 adw_tickle_risc(adw, ADW_TICKLE_A); 1261 break; 1262 case ADW_ASYNC_SCSI_BUS_RESET_DET: 1263 /* 1264 * The firmware detected a SCSI Bus reset. 1265 */ 1266 printf("Someone Reset the Bus\n"); 1267 adw_handle_bus_reset(adw, /*initiated*/FALSE); 1268 break; 1269 case ADW_ASYNC_RDMA_FAILURE: 1270 /* 1271 * Handle RDMA failure by resetting the 1272 * SCSI Bus and chip. 1273 */ 1274#if XXX 1275 AdvResetChipAndSB(adv_dvc_varp); 1276#endif 1277 break; 1278 1279 case ADW_ASYNC_HOST_SCSI_BUS_RESET: 1280 /* 1281 * Host generated SCSI bus reset occurred. 1282 */ 1283 adw_handle_bus_reset(adw, /*initiated*/TRUE); 1284 break; 1285 default: 1286 printf("adw_intr: unknown async code 0x%x\n", 1287 intrb_code); 1288 break; 1289 } 1290 } 1291 1292 /* 1293 * Run down the RequestQ. 1294 */ 1295 while ((adw->responseq->next_ba & ADW_RQ_DONE) != 0) { 1296 struct adw_carrier *free_carrier; 1297 struct acb *acb; 1298 union ccb *ccb; 1299 1300#if 0 1301 printf("0x%x, 0x%x, 0x%x, 0x%x\n", 1302 adw->responseq->carr_offset, 1303 adw->responseq->carr_ba, 1304 adw->responseq->areq_ba, 1305 adw->responseq->next_ba); 1306#endif 1307 /* 1308 * The firmware copies the adw_scsi_req_q.acb_baddr 1309 * field into the areq_ba field of the carrier. 1310 */ 1311 acb = acbbotov(adw, adw->responseq->areq_ba); 1312 1313 /* 1314 * The least significant four bits of the next_ba 1315 * field are used as flags. Mask them out and then 1316 * advance through the list. 1317 */ 1318 free_carrier = adw->responseq; 1319 adw->responseq = 1320 carrierbotov(adw, free_carrier->next_ba & ADW_NEXT_BA_MASK); 1321 free_carrier->next_ba = adw->free_carriers->carr_offset; 1322 adw->free_carriers = free_carrier; 1323 1324 /* Process CCB */ 1325 ccb = acb->ccb; 1326 untimeout(adwtimeout, acb, ccb->ccb_h.timeout_ch); 1327 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1328 bus_dmasync_op_t op; 1329 1330 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 1331 op = BUS_DMASYNC_POSTREAD; 1332 else 1333 op = BUS_DMASYNC_POSTWRITE; 1334 bus_dmamap_sync(adw->buffer_dmat, acb->dmamap, op); 1335 bus_dmamap_unload(adw->buffer_dmat, acb->dmamap); 1336 ccb->csio.resid = acb->queue.data_cnt; 1337 } else 1338 ccb->csio.resid = 0; 1339 1340 /* Common Cases inline... */ 1341 if (acb->queue.host_status == QHSTA_NO_ERROR 1342 && (acb->queue.done_status == QD_NO_ERROR 1343 || acb->queue.done_status == QD_WITH_ERROR)) { 1344 ccb->csio.scsi_status = acb->queue.scsi_status; 1345 ccb->ccb_h.status = 0; 1346 switch (ccb->csio.scsi_status) { 1347 case SCSI_STATUS_OK: 1348 ccb->ccb_h.status |= CAM_REQ_CMP; 1349 break; 1350 case SCSI_STATUS_CHECK_COND: 1351 case SCSI_STATUS_CMD_TERMINATED: 1352 bcopy(&acb->sense_data, &ccb->csio.sense_data, 1353 ccb->csio.sense_len); 1354 ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 1355 ccb->csio.sense_resid = acb->queue.sense_len; 1356 /* FALLTHROUGH */ 1357 default: 1358 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR 1359 | CAM_DEV_QFRZN; 1360 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 1361 break; 1362 } 1363 adwfreeacb(adw, acb); 1364 xpt_done(ccb); 1365 } else { 1366 adwprocesserror(adw, acb); 1367 } 1368 } 1369} 1370 1371static void 1372adwprocesserror(struct adw_softc *adw, struct acb *acb) 1373{ 1374 union ccb *ccb; 1375 1376 ccb = acb->ccb; 1377 if (acb->queue.done_status == QD_ABORTED_BY_HOST) { 1378 ccb->ccb_h.status = CAM_REQ_ABORTED; 1379 } else { 1380 1381 switch (acb->queue.host_status) { 1382 case QHSTA_M_SEL_TIMEOUT: 1383 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 1384 break; 1385 case QHSTA_M_SXFR_OFF_UFLW: 1386 case QHSTA_M_SXFR_OFF_OFLW: 1387 case QHSTA_M_DATA_OVER_RUN: 1388 ccb->ccb_h.status = CAM_DATA_RUN_ERR; 1389 break; 1390 case QHSTA_M_SXFR_DESELECTED: 1391 case QHSTA_M_UNEXPECTED_BUS_FREE: 1392 ccb->ccb_h.status = CAM_UNEXP_BUSFREE; 1393 break; 1394 case QHSTA_M_SCSI_BUS_RESET: 1395 case QHSTA_M_SCSI_BUS_RESET_UNSOL: 1396 ccb->ccb_h.status = CAM_SCSI_BUS_RESET; 1397 break; 1398 case QHSTA_M_BUS_DEVICE_RESET: 1399 ccb->ccb_h.status = CAM_BDR_SENT; 1400 break; 1401 case QHSTA_M_QUEUE_ABORTED: 1402 /* BDR or Bus Reset */ 1403 printf("Saw Queue Aborted\n"); 1404 ccb->ccb_h.status = adw->last_reset; 1405 break; 1406 case QHSTA_M_SXFR_SDMA_ERR: 1407 case QHSTA_M_SXFR_SXFR_PERR: 1408 case QHSTA_M_RDMA_PERR: 1409 ccb->ccb_h.status = CAM_UNCOR_PARITY; 1410 break; 1411 case QHSTA_M_WTM_TIMEOUT: 1412 case QHSTA_M_SXFR_WD_TMO: 1413 { 1414 /* The SCSI bus hung in a phase */ 1415 xpt_print_path(adw->path); 1416 printf("Watch Dog timer expired. Reseting bus\n"); 1417 adw_reset_bus(adw); 1418 break; 1419 } 1420 case QHSTA_M_SXFR_XFR_PH_ERR: 1421 ccb->ccb_h.status = CAM_SEQUENCE_FAIL; 1422 break; 1423 case QHSTA_M_SXFR_UNKNOWN_ERROR: 1424 break; 1425 case QHSTA_M_BAD_CMPL_STATUS_IN: 1426 /* No command complete after a status message */ 1427 ccb->ccb_h.status = CAM_SEQUENCE_FAIL; 1428 break; 1429 case QHSTA_M_AUTO_REQ_SENSE_FAIL: 1430 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL; 1431 break; 1432 case QHSTA_M_INVALID_DEVICE: 1433 ccb->ccb_h.status = CAM_PATH_INVALID; 1434 break; 1435 case QHSTA_M_NO_AUTO_REQ_SENSE: 1436 /* 1437 * User didn't request sense, but we got a 1438 * check condition. 1439 */ 1440 ccb->csio.scsi_status = acb->queue.scsi_status; 1441 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 1442 break; 1443 default: 1444 panic("%s: Unhandled Host status error %x", 1445 adw_name(adw), acb->queue.host_status); 1446 /* NOTREACHED */ 1447 } 1448 } 1449 if ((acb->state & ACB_RECOVERY_ACB) != 0) { 1450 if (ccb->ccb_h.status == CAM_SCSI_BUS_RESET 1451 || ccb->ccb_h.status == CAM_BDR_SENT) 1452 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 1453 } 1454 if (ccb->ccb_h.status != CAM_REQ_CMP) { 1455 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 1456 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1457 } 1458 adwfreeacb(adw, acb); 1459 xpt_done(ccb); 1460} 1461 1462static void 1463adwtimeout(void *arg) 1464{ 1465 struct acb *acb; 1466 union ccb *ccb; 1467 struct adw_softc *adw; 1468 adw_idle_cmd_status_t status; 1469 int target_id; 1470 int s; 1471 1472 acb = (struct acb *)arg; 1473 ccb = acb->ccb; 1474 adw = (struct adw_softc *)ccb->ccb_h.ccb_adw_ptr; 1475 xpt_print_path(ccb->ccb_h.path); 1476 printf("ACB %p - timed out\n", (void *)acb); 1477 1478 s = splcam(); 1479 1480 if ((acb->state & ACB_ACTIVE) == 0) { 1481 xpt_print_path(ccb->ccb_h.path); 1482 printf("ACB %p - timed out CCB already completed\n", 1483 (void *)acb); 1484 splx(s); 1485 return; 1486 } 1487 1488 acb->state |= ACB_RECOVERY_ACB; 1489 target_id = ccb->ccb_h.target_id; 1490 1491 /* Attempt a BDR first */ 1492 status = adw_idle_cmd_send(adw, ADW_IDLE_CMD_DEVICE_RESET, 1493 ccb->ccb_h.target_id); 1494 splx(s); 1495 if (status == ADW_IDLE_CMD_SUCCESS) { 1496 printf("%s: BDR Delivered. No longer in timeout\n", 1497 adw_name(adw)); 1498 adw_handle_device_reset(adw, target_id); 1499 } else { 1500 adw_reset_bus(adw); 1501 xpt_print_path(adw->path); 1502 printf("Bus Reset Delivered. No longer in timeout\n"); 1503 } 1504} 1505 1506static void 1507adw_handle_device_reset(struct adw_softc *adw, u_int target) 1508{ 1509 struct cam_path *path; 1510 cam_status error; 1511 1512 error = xpt_create_path(&path, /*periph*/NULL, cam_sim_path(adw->sim), 1513 target, CAM_LUN_WILDCARD); 1514 1515 if (error == CAM_REQ_CMP) { 1516 xpt_async(AC_SENT_BDR, path, NULL); 1517 xpt_free_path(path); 1518 } 1519 adw->last_reset = CAM_BDR_SENT; 1520} 1521 1522static void 1523adw_handle_bus_reset(struct adw_softc *adw, int initiated) 1524{ 1525 if (initiated) { 1526 /* 1527 * The microcode currently sets the SCSI Bus Reset signal 1528 * while handling the AscSendIdleCmd() IDLE_CMD_SCSI_RESET 1529 * command above. But the SCSI Bus Reset Hold Time in the 1530 * microcode is not deterministic (it may in fact be for less 1531 * than the SCSI Spec. minimum of 25 us). Therefore on return 1532 * the Adv Library sets the SCSI Bus Reset signal for 1533 * ADW_SCSI_RESET_HOLD_TIME_US, which is defined to be greater 1534 * than 25 us. 1535 */ 1536 u_int scsi_ctrl; 1537 1538 scsi_ctrl = adw_inw(adw, ADW_SCSI_CTRL) & ~ADW_SCSI_CTRL_RSTOUT; 1539 adw_outw(adw, ADW_SCSI_CTRL, scsi_ctrl | ADW_SCSI_CTRL_RSTOUT); 1540 DELAY(ADW_SCSI_RESET_HOLD_TIME_US); 1541 adw_outw(adw, ADW_SCSI_CTRL, scsi_ctrl); 1542 1543 /* 1544 * We will perform the async notification when the 1545 * SCSI Reset interrupt occurs. 1546 */ 1547 } else 1548 xpt_async(AC_BUS_RESET, adw->path, NULL); 1549 adw->last_reset = CAM_SCSI_BUS_RESET; 1550} 1551