cvmx-wqe.h revision 210286
1/***********************license start*************** 2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 * 23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31 * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33 * 34 * 35 * For any questions regarding licensing please contact marketing@caviumnetworks.com 36 * 37 ***********************license end**************************************/ 38 39 40 41 42 43 44/** 45 * @file 46 * 47 * This header file defines the work queue entry (wqe) data structure. 48 * Since this is a commonly used structure that depends on structures 49 * from several hardware blocks, those definitions have been placed 50 * in this file to create a single point of definition of the wqe 51 * format. 52 * Data structures are still named according to the block that they 53 * relate to. 54 * 55 * This file must not depend on any other header files, except for cvmx.h!!! 56 * 57 * 58 * <hr>$Revision: 41586 $<hr> 59 * 60 * 61 */ 62 63 64#ifndef __CVMX_WQE_H__ 65#define __CVMX_WQE_H__ 66 67#ifdef __cplusplus 68extern "C" { 69#endif 70 71#define OCT_TAG_TYPE_STRING(x) (((x) == CVMX_POW_TAG_TYPE_ORDERED) ? "ORDERED" : \ 72 (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ? "ATOMIC" : \ 73 (((x) == CVMX_POW_TAG_TYPE_NULL) ? "NULL" : \ 74 "NULL_NULL"))) 75 76 77/** 78 * HW decode / err_code in work queue entry 79 */ 80typedef union 81{ 82 uint64_t u64; 83 84 /** Use this struct if the hardware determines that the packet is IP */ 85 struct 86 { 87 uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */ 88 uint64_t ip_offset : 8; /**< HW sets to the number of L2 bytes prior to the IP */ 89 uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */ 90 uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */ 91 uint64_t unassigned : 1; 92 uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */ 93 uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */ 94 uint64_t pr : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */ 95 uint64_t unassigned2 : 8; 96 uint64_t dec_ipcomp : 1; /**< the packet needs to be decompressed */ 97 uint64_t tcp_or_udp : 1; /**< the packet is either TCP or UDP */ 98 uint64_t dec_ipsec : 1; /**< the packet needs to be decrypted (ESP or AH) */ 99 uint64_t is_v6 : 1; /**< the packet is IPv6 */ 100 101 // (rcv_error, not_IP, IP_exc, is_frag, L4_error, software, etc.) 102 103 uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */ 104 // exceptional conditions below 105 uint64_t L4_error : 1; /**< the receive interface hardware detected an L4 error (only applies if !is_frag) 106 (only applies if !rcv_error && !not_IP && !IP_exc && !is_frag) 107 failure indicated in err_code below, decode: 108 - 1 = Malformed L4 109 - 2 = L4 Checksum Error: the L4 checksum value is 110 - 3 = UDP Length Error: The UDP length field would make the UDP data longer than what 111 remains in the IP packet (as defined by the IP header length field). 112 - 4 = Bad L4 Port: either the source or destination TCP/UDP port is 0. 113 - 8 = TCP FIN Only: the packet is TCP and only the FIN flag set. 114 - 9 = TCP No Flags: the packet is TCP and no flags are set. 115 - 10 = TCP FIN RST: the packet is TCP and both FIN and RST are set. 116 - 11 = TCP SYN URG: the packet is TCP and both SYN and URG are set. 117 - 12 = TCP SYN RST: the packet is TCP and both SYN and RST are set. 118 - 13 = TCP SYN FIN: the packet is TCP and both SYN and FIN are set. */ 119 120 121 122 uint64_t is_frag : 1; /**< set if the packet is a fragment */ 123 uint64_t IP_exc : 1; /**< the receive interface hardware detected an IP error / exception 124 (only applies if !rcv_error && !not_IP) failure indicated in err_code below, decode: 125 - 1 = Not IP: the IP version field is neither 4 nor 6. 126 - 2 = IPv4 Header Checksum Error: the IPv4 header has a checksum violation. 127 - 3 = IP Malformed Header: the packet is not long enough to contain the IP header. 128 - 4 = IP Malformed: the packet is not long enough to contain the bytes indicated by the IP 129 header. Pad is allowed. 130 - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 Hop Count field are zero. 131 - 6 = IP Options */ 132 133 uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */ 134 uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */ 135 uint64_t not_IP : 1; /**< set if the packet may not be IP (must be zero in this case) */ 136 uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error (must be zero in this case) */ 137 /* lower err_code = first-level descriptor of the work */ 138 /* zero for packet submitted by hardware that isn't on the slow path */ 139 140 uint64_t err_code : 8; /**< type is cvmx_pip_err_t */ 141 } s; 142 143 /**< use this to get at the 16 vlan bits */ 144 struct 145 { 146 uint64_t unused1 :16; 147 uint64_t vlan :16; 148 uint64_t unused2 :32; 149 } svlan; 150 151 /**< use this struct if the hardware could not determine that the packet is ip */ 152 struct 153 { 154 uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */ 155 uint64_t unused : 8; 156 uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */ 157 uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */ 158 uint64_t unassigned : 1; 159 uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */ 160 uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */ 161 uint64_t pr : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */ 162 uint64_t unassigned2 :12; 163 uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */ 164 uint64_t unassigned3 : 1; 165 uint64_t is_rarp : 1; /**< set if the hardware determined that the packet is rarp */ 166 uint64_t is_arp : 1; /**< set if the hardware determined that the packet is arp */ 167 uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */ 168 uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */ 169 uint64_t not_IP : 1; /**< set if the packet may not be IP (must be one in this case) */ 170 uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error. 171 Failure indicated in err_code below, decode: 172 - 1 = partial error: a packet was partially received, but internal 173 buffering / bandwidth was not adequate to receive the entire packet. 174 - 2 = jabber error: the RGMII packet was too large and is truncated. 175 - 3 = overrun error: the RGMII packet is longer than allowed and had 176 an FCS error. 177 - 4 = oversize error: the RGMII packet is longer than allowed. 178 - 5 = alignment error: the RGMII packet is not an integer number of bytes 179 and had an FCS error (100M and 10M only). 180 - 6 = fragment error: the RGMII packet is shorter than allowed and had an 181 FCS error. 182 - 7 = GMX FCS error: the RGMII packet had an FCS error. 183 - 8 = undersize error: the RGMII packet is shorter than allowed. 184 - 9 = extend error: the RGMII packet had an extend error. 185 - 10 = length mismatch error: the RGMII packet had a length that did not 186 match the length field in the L2 HDR. 187 - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII packet had one or more 188 data reception errors (RXERR) or the SPI4 packet had one or more DIP4 189 errors. 190 - 12 = RGMII skip error/SPI4 Abort Error: the RGMII packet was not large 191 enough to cover the skipped bytes or the SPI4 packet was terminated 192 with an About EOPS. 193 - 13 = RGMII nibble error/SPI4 Port NXA Error: the RGMII packet had a 194 studder error (data not repeated - 10/100M only) or the SPI4 packet 195 was sent to an NXA. 196 - 16 = FCS error: a SPI4.2 packet had an FCS error. 197 - 17 = Skip error: a packet was not large enough to cover the skipped bytes. 198 - 18 = L2 header malformed: the packet is not long enough to contain the L2 */ 199 200 201 /* lower err_code = first-level descriptor of the work */ 202 /* zero for packet submitted by hardware that isn't on the slow path */ 203 uint64_t err_code : 8; // type is cvmx_pip_err_t (union, so can't use directly 204 } snoip; 205 206} cvmx_pip_wqe_word2; 207 208 209 210 211 212 213 214 215/** 216 * Work queue entry format 217 * 218 * must be 8-byte aligned 219 */ 220typedef struct 221{ 222 223 /***************************************************************** 224 * WORD 0 225 * HW WRITE: the following 64 bits are filled by HW when a packet arrives 226 */ 227 228 /** 229 * raw chksum result generated by the HW 230 */ 231 uint16_t hw_chksum; 232 /** 233 * Field unused by hardware - available for software 234 */ 235 uint8_t unused; 236 /** 237 * Next pointer used by hardware for list maintenance. 238 * May be written/read by HW before the work queue 239 * entry is scheduled to a PP 240 * (Only 36 bits used in Octeon 1) 241 */ 242 uint64_t next_ptr : 40; 243 244 245 /***************************************************************** 246 * WORD 1 247 * HW WRITE: the following 64 bits are filled by HW when a packet arrives 248 */ 249 250 /** 251 * HW sets to the total number of bytes in the packet 252 */ 253 uint64_t len :16; 254 /** 255 * HW sets this to input physical port 256 */ 257 uint64_t ipprt : 6; 258 259 /** 260 * HW sets this to what it thought the priority of the input packet was 261 */ 262 uint64_t qos : 3; 263 264 /** 265 * the group that the work queue entry will be scheduled to 266 */ 267 uint64_t grp : 4; 268 /** 269 * the type of the tag (ORDERED, ATOMIC, NULL) 270 */ 271 cvmx_pow_tag_type_t tag_type : 3; 272 /** 273 * the synchronization/ordering tag 274 */ 275 uint64_t tag :32; 276 277 /** 278 * WORD 2 279 * HW WRITE: the following 64-bits are filled in by hardware when a packet arrives 280 * This indicates a variety of status and error conditions. 281 */ 282 cvmx_pip_wqe_word2 word2; 283 284 /** 285 * Pointer to the first segment of the packet. 286 */ 287 cvmx_buf_ptr_t packet_ptr; 288 289 /** 290 * HW WRITE: octeon will fill in a programmable amount from the 291 * packet, up to (at most, but perhaps less) the amount 292 * needed to fill the work queue entry to 128 bytes 293 * If the packet is recognized to be IP, the hardware starts (except that 294 * the IPv4 header is padded for appropriate alignment) writing here where 295 * the IP header starts. 296 * If the packet is not recognized to be IP, the hardware starts writing 297 * the beginning of the packet here. 298 */ 299 uint8_t packet_data[96]; 300 301 302 /** 303 * If desired, SW can make the work Q entry any length. For the 304 * purposes of discussion here, Assume 128B always, as this is all that 305 * the hardware deals with. 306 * 307 */ 308 309} CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t; 310 311#ifdef __cplusplus 312} 313#endif 314 315#endif /* __CVMX_WQE_H__ */ 316