xref: /freebsd-10.3-release/sys/contrib/octeon-sdk/cvmx-spx0-defs.h

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/**
 * cvmx-spx0-defs.h
 *
 * Configuration and status register (CSR) type definitions for
 * Octeon spx0.
 *
 * This file is auto generated. Do not edit.
 *
 * <hr>$Revision$<hr>
 *
 */
#ifndef __CVMX_SPX0_DEFS_H__
#define __CVMX_SPX0_DEFS_H__

#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SPX0_PLL_BW_CTL CVMX_SPX0_PLL_BW_CTL_FUNC()
static inline uint64_t CVMX_SPX0_PLL_BW_CTL_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
		cvmx_warn("CVMX_SPX0_PLL_BW_CTL not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180090000388ull);
}
#else
#define CVMX_SPX0_PLL_BW_CTL (CVMX_ADD_IO_SEG(0x0001180090000388ull))
#endif
#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
#define CVMX_SPX0_PLL_SETTING CVMX_SPX0_PLL_SETTING_FUNC()
static inline uint64_t CVMX_SPX0_PLL_SETTING_FUNC(void)
{
	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
		cvmx_warn("CVMX_SPX0_PLL_SETTING not supported on this chip\n");
	return CVMX_ADD_IO_SEG(0x0001180090000380ull);
}
#else
#define CVMX_SPX0_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180090000380ull))
#endif

/**
 * cvmx_spx0_pll_bw_ctl
 */
union cvmx_spx0_pll_bw_ctl {
	uint64_t u64;
	struct cvmx_spx0_pll_bw_ctl_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_5_63                : 59;
	uint64_t bw_ctl                       : 5;  /**< Core PLL bandwidth control */
#else
	uint64_t bw_ctl                       : 5;
	uint64_t reserved_5_63                : 59;
#endif
	} s;
	struct cvmx_spx0_pll_bw_ctl_s         cn38xx;
	struct cvmx_spx0_pll_bw_ctl_s         cn38xxp2;
};
typedef union cvmx_spx0_pll_bw_ctl cvmx_spx0_pll_bw_ctl_t;

/**
 * cvmx_spx0_pll_setting
 */
union cvmx_spx0_pll_setting {
	uint64_t u64;
	struct cvmx_spx0_pll_setting_s {
#ifdef __BIG_ENDIAN_BITFIELD
	uint64_t reserved_17_63               : 47;
	uint64_t setting                      : 17; /**< Core PLL setting */
#else
	uint64_t setting                      : 17;
	uint64_t reserved_17_63               : 47;
#endif
	} s;
	struct cvmx_spx0_pll_setting_s        cn38xx;
	struct cvmx_spx0_pll_setting_s        cn38xxp2;
};
typedef union cvmx_spx0_pll_setting cvmx_spx0_pll_setting_t;

#endif