cvmx-spx0-defs.h revision 215990 
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39
40
41/**
42 * cvmx-spx0-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon spx0.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52#ifndef __CVMX_SPX0_TYPEDEFS_H__
53#define __CVMX_SPX0_TYPEDEFS_H__
54
55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56#define CVMX_SPX0_PLL_BW_CTL CVMX_SPX0_PLL_BW_CTL_FUNC()
57static inline uint64_t CVMX_SPX0_PLL_BW_CTL_FUNC(void)
58{
59	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
60		cvmx_warn("CVMX_SPX0_PLL_BW_CTL not supported on this chip\n");
61	return CVMX_ADD_IO_SEG(0x0001180090000388ull);
62}
63#else
64#define CVMX_SPX0_PLL_BW_CTL (CVMX_ADD_IO_SEG(0x0001180090000388ull))
65#endif
66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67#define CVMX_SPX0_PLL_SETTING CVMX_SPX0_PLL_SETTING_FUNC()
68static inline uint64_t CVMX_SPX0_PLL_SETTING_FUNC(void)
69{
70	if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
71		cvmx_warn("CVMX_SPX0_PLL_SETTING not supported on this chip\n");
72	return CVMX_ADD_IO_SEG(0x0001180090000380ull);
73}
74#else
75#define CVMX_SPX0_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180090000380ull))
76#endif
77
78/**
79 * cvmx_spx0_pll_bw_ctl
80 */
81union cvmx_spx0_pll_bw_ctl
82{
83	uint64_t u64;
84	struct cvmx_spx0_pll_bw_ctl_s
85	{
86#if __BYTE_ORDER == __BIG_ENDIAN
87	uint64_t reserved_5_63                : 59;
88	uint64_t bw_ctl                       : 5;  /**< Core PLL bandwidth control */
89#else
90	uint64_t bw_ctl                       : 5;
91	uint64_t reserved_5_63                : 59;
92#endif
93	} s;
94	struct cvmx_spx0_pll_bw_ctl_s         cn38xx;
95	struct cvmx_spx0_pll_bw_ctl_s         cn38xxp2;
96};
97typedef union cvmx_spx0_pll_bw_ctl cvmx_spx0_pll_bw_ctl_t;
98
99/**
100 * cvmx_spx0_pll_setting
101 */
102union cvmx_spx0_pll_setting
103{
104	uint64_t u64;
105	struct cvmx_spx0_pll_setting_s
106	{
107#if __BYTE_ORDER == __BIG_ENDIAN
108	uint64_t reserved_17_63               : 47;
109	uint64_t setting                      : 17; /**< Core PLL setting */
110#else
111	uint64_t setting                      : 17;
112	uint64_t reserved_17_63               : 47;
113#endif
114	} s;
115	struct cvmx_spx0_pll_setting_s        cn38xx;
116	struct cvmx_spx0_pll_setting_s        cn38xxp2;
117};
118typedef union cvmx_spx0_pll_setting cvmx_spx0_pll_setting_t;
119
120#endif
121