cvmx-spx0-defs.h revision 215976
1203954Srdivacky/***********************license start*************** 2203954Srdivacky * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3203954Srdivacky * reserved. 4203954Srdivacky * 5203954Srdivacky * 6203954Srdivacky * Redistribution and use in source and binary forms, with or without 7203954Srdivacky * modification, are permitted provided that the following conditions are 8203954Srdivacky * met: 9203954Srdivacky * 10203954Srdivacky * * Redistributions of source code must retain the above copyright 11203954Srdivacky * notice, this list of conditions and the following disclaimer. 12203954Srdivacky * 13203954Srdivacky * * Redistributions in binary form must reproduce the above 14203954Srdivacky * copyright notice, this list of conditions and the following 15203954Srdivacky * disclaimer in the documentation and/or other materials provided 16203954Srdivacky * with the distribution. 17203954Srdivacky 18203954Srdivacky * * Neither the name of Cavium Networks nor the names of 19203954Srdivacky * its contributors may be used to endorse or promote products 20203954Srdivacky * derived from this software without specific prior written 21203954Srdivacky * permission. 22203954Srdivacky 23203954Srdivacky * This Software, including technical data, may be subject to U.S. export control 24203954Srdivacky * laws, including the U.S. Export Administration Act and its associated 25203954Srdivacky * regulations, and may be subject to export or import regulations in other 26218893Sdim * countries. 27203954Srdivacky 28203954Srdivacky * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29203954Srdivacky * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30218893Sdim * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31203954Srdivacky * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32203954Srdivacky * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33203954Srdivacky * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34203954Srdivacky * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35203954Srdivacky * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36203954Srdivacky * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37218893Sdim * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38203954Srdivacky ***********************license end**************************************/ 39203954Srdivacky 40218893Sdim 41203954Srdivacky/** 42203954Srdivacky * cvmx-spx0-defs.h 43218893Sdim * 44203954Srdivacky * Configuration and status register (CSR) type definitions for 45203954Srdivacky * Octeon spx0. 46203954Srdivacky * 47218893Sdim * This file is auto generated. Do not edit. 48203954Srdivacky * 49203954Srdivacky * <hr>$Revision$<hr> 50203954Srdivacky * 51218893Sdim */ 52203954Srdivacky#ifndef __CVMX_SPX0_TYPEDEFS_H__ 53203954Srdivacky#define __CVMX_SPX0_TYPEDEFS_H__ 54203954Srdivacky 55218893Sdim#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56203954Srdivacky#define CVMX_SPX0_PLL_BW_CTL CVMX_SPX0_PLL_BW_CTL_FUNC() 57203954Srdivackystatic inline uint64_t CVMX_SPX0_PLL_BW_CTL_FUNC(void) 58218893Sdim{ 59203954Srdivacky if (!(OCTEON_IS_MODEL(OCTEON_CN38XX))) 60203954Srdivacky cvmx_warn("CVMX_SPX0_PLL_BW_CTL not supported on this chip\n"); 61203954Srdivacky return CVMX_ADD_IO_SEG(0x0001180090000388ull); 62218893Sdim} 63203954Srdivacky#else 64203954Srdivacky#define CVMX_SPX0_PLL_BW_CTL (CVMX_ADD_IO_SEG(0x0001180090000388ull)) 65203954Srdivacky#endif 66203954Srdivacky#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67218893Sdim#define CVMX_SPX0_PLL_SETTING CVMX_SPX0_PLL_SETTING_FUNC() 68203954Srdivackystatic inline uint64_t CVMX_SPX0_PLL_SETTING_FUNC(void) 69203954Srdivacky{ 70218893Sdim if (!(OCTEON_IS_MODEL(OCTEON_CN38XX))) 71203954Srdivacky cvmx_warn("CVMX_SPX0_PLL_SETTING not supported on this chip\n"); 72203954Srdivacky return CVMX_ADD_IO_SEG(0x0001180090000380ull); 73203954Srdivacky} 74203954Srdivacky#else 75203954Srdivacky#define CVMX_SPX0_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180090000380ull)) 76203954Srdivacky#endif 77203954Srdivacky 78203954Srdivacky/** 79203954Srdivacky * cvmx_spx0_pll_bw_ctl 80218893Sdim */ 81203954Srdivackyunion cvmx_spx0_pll_bw_ctl 82203954Srdivacky{ 83203954Srdivacky uint64_t u64; 84218893Sdim struct cvmx_spx0_pll_bw_ctl_s 85203954Srdivacky { 86203954Srdivacky#if __BYTE_ORDER == __BIG_ENDIAN 87203954Srdivacky uint64_t reserved_5_63 : 59; 88203954Srdivacky uint64_t bw_ctl : 5; /**< Core PLL bandwidth control */ 89218893Sdim#else 90218893Sdim uint64_t bw_ctl : 5; 91203954Srdivacky uint64_t reserved_5_63 : 59; 92203954Srdivacky#endif 93203954Srdivacky } s; 94218893Sdim struct cvmx_spx0_pll_bw_ctl_s cn38xx; 95203954Srdivacky struct cvmx_spx0_pll_bw_ctl_s cn38xxp2; 96203954Srdivacky}; 97203954Srdivackytypedef union cvmx_spx0_pll_bw_ctl cvmx_spx0_pll_bw_ctl_t; 98203954Srdivacky 99218893Sdim/** 100203954Srdivacky * cvmx_spx0_pll_setting 101203954Srdivacky */ 102203954Srdivackyunion cvmx_spx0_pll_setting 103203954Srdivacky{ 104203954Srdivacky uint64_t u64; 105203954Srdivacky struct cvmx_spx0_pll_setting_s 106203954Srdivacky { 107203954Srdivacky#if __BYTE_ORDER == __BIG_ENDIAN 108203954Srdivacky uint64_t reserved_17_63 : 47; 109203954Srdivacky uint64_t setting : 17; /**< Core PLL setting */ 110203954Srdivacky#else 111203954Srdivacky uint64_t setting : 17; 112203954Srdivacky uint64_t reserved_17_63 : 47; 113203954Srdivacky#endif 114 } s; 115 struct cvmx_spx0_pll_setting_s cn38xx; 116 struct cvmx_spx0_pll_setting_s cn38xxp2; 117}; 118typedef union cvmx_spx0_pll_setting cvmx_spx0_pll_setting_t; 119 120#endif 121