cvmx-sli-defs.h revision 215976
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-sli-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon sli. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_SLI_TYPEDEFS_H__ 53#define __CVMX_SLI_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_SLI_BIST_STATUS CVMX_SLI_BIST_STATUS_FUNC() 57static inline uint64_t CVMX_SLI_BIST_STATUS_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 60 cvmx_warn("CVMX_SLI_BIST_STATUS not supported on this chip\n"); 61 return 0x0000000000000580ull; 62} 63#else 64#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67static inline uint64_t CVMX_SLI_CTL_PORTX(unsigned long offset) 68{ 69 if (!( 70 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 71 cvmx_warn("CVMX_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset); 72 return 0x0000000000000050ull + ((offset) & 1) * 16; 73} 74#else 75#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 1) * 16) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78#define CVMX_SLI_CTL_STATUS CVMX_SLI_CTL_STATUS_FUNC() 79static inline uint64_t CVMX_SLI_CTL_STATUS_FUNC(void) 80{ 81 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 82 cvmx_warn("CVMX_SLI_CTL_STATUS not supported on this chip\n"); 83 return 0x0000000000000570ull; 84} 85#else 86#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89#define CVMX_SLI_DATA_OUT_CNT CVMX_SLI_DATA_OUT_CNT_FUNC() 90static inline uint64_t CVMX_SLI_DATA_OUT_CNT_FUNC(void) 91{ 92 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 93 cvmx_warn("CVMX_SLI_DATA_OUT_CNT not supported on this chip\n"); 94 return 0x00000000000005F0ull; 95} 96#else 97#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100#define CVMX_SLI_DBG_DATA CVMX_SLI_DBG_DATA_FUNC() 101static inline uint64_t CVMX_SLI_DBG_DATA_FUNC(void) 102{ 103 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 104 cvmx_warn("CVMX_SLI_DBG_DATA not supported on this chip\n"); 105 return 0x0000000000000310ull; 106} 107#else 108#define CVMX_SLI_DBG_DATA (0x0000000000000310ull) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111#define CVMX_SLI_DBG_SELECT CVMX_SLI_DBG_SELECT_FUNC() 112static inline uint64_t CVMX_SLI_DBG_SELECT_FUNC(void) 113{ 114 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 115 cvmx_warn("CVMX_SLI_DBG_SELECT not supported on this chip\n"); 116 return 0x0000000000000300ull; 117} 118#else 119#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122static inline uint64_t CVMX_SLI_DMAX_CNT(unsigned long offset) 123{ 124 if (!( 125 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 126 cvmx_warn("CVMX_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset); 127 return 0x0000000000000400ull + ((offset) & 1) * 16; 128} 129#else 130#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133static inline uint64_t CVMX_SLI_DMAX_INT_LEVEL(unsigned long offset) 134{ 135 if (!( 136 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 137 cvmx_warn("CVMX_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset); 138 return 0x00000000000003E0ull + ((offset) & 1) * 16; 139} 140#else 141#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144static inline uint64_t CVMX_SLI_DMAX_TIM(unsigned long offset) 145{ 146 if (!( 147 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 148 cvmx_warn("CVMX_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset); 149 return 0x0000000000000420ull + ((offset) & 1) * 16; 150} 151#else 152#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155#define CVMX_SLI_INT_ENB_CIU CVMX_SLI_INT_ENB_CIU_FUNC() 156static inline uint64_t CVMX_SLI_INT_ENB_CIU_FUNC(void) 157{ 158 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 159 cvmx_warn("CVMX_SLI_INT_ENB_CIU not supported on this chip\n"); 160 return 0x0000000000003CD0ull; 161} 162#else 163#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166static inline uint64_t CVMX_SLI_INT_ENB_PORTX(unsigned long offset) 167{ 168 if (!( 169 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 170 cvmx_warn("CVMX_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset); 171 return 0x0000000000000340ull + ((offset) & 1) * 16; 172} 173#else 174#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177#define CVMX_SLI_INT_SUM CVMX_SLI_INT_SUM_FUNC() 178static inline uint64_t CVMX_SLI_INT_SUM_FUNC(void) 179{ 180 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 181 cvmx_warn("CVMX_SLI_INT_SUM not supported on this chip\n"); 182 return 0x0000000000000330ull; 183} 184#else 185#define CVMX_SLI_INT_SUM (0x0000000000000330ull) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188#define CVMX_SLI_LAST_WIN_RDATA0 CVMX_SLI_LAST_WIN_RDATA0_FUNC() 189static inline uint64_t CVMX_SLI_LAST_WIN_RDATA0_FUNC(void) 190{ 191 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 192 cvmx_warn("CVMX_SLI_LAST_WIN_RDATA0 not supported on this chip\n"); 193 return 0x0000000000000600ull; 194} 195#else 196#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199#define CVMX_SLI_LAST_WIN_RDATA1 CVMX_SLI_LAST_WIN_RDATA1_FUNC() 200static inline uint64_t CVMX_SLI_LAST_WIN_RDATA1_FUNC(void) 201{ 202 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 203 cvmx_warn("CVMX_SLI_LAST_WIN_RDATA1 not supported on this chip\n"); 204 return 0x0000000000000610ull; 205} 206#else 207#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210#define CVMX_SLI_MAC_CREDIT_CNT CVMX_SLI_MAC_CREDIT_CNT_FUNC() 211static inline uint64_t CVMX_SLI_MAC_CREDIT_CNT_FUNC(void) 212{ 213 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 214 cvmx_warn("CVMX_SLI_MAC_CREDIT_CNT not supported on this chip\n"); 215 return 0x0000000000003D70ull; 216} 217#else 218#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221#define CVMX_SLI_MAC_NUMBER CVMX_SLI_MAC_NUMBER_FUNC() 222static inline uint64_t CVMX_SLI_MAC_NUMBER_FUNC(void) 223{ 224 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 225 cvmx_warn("CVMX_SLI_MAC_NUMBER not supported on this chip\n"); 226 return 0x0000000000003E00ull; 227} 228#else 229#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull) 230#endif 231#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232#define CVMX_SLI_MEM_ACCESS_CTL CVMX_SLI_MEM_ACCESS_CTL_FUNC() 233static inline uint64_t CVMX_SLI_MEM_ACCESS_CTL_FUNC(void) 234{ 235 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 236 cvmx_warn("CVMX_SLI_MEM_ACCESS_CTL not supported on this chip\n"); 237 return 0x00000000000002F0ull; 238} 239#else 240#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243static inline uint64_t CVMX_SLI_MEM_ACCESS_SUBIDX(unsigned long offset) 244{ 245 if (!( 246 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27)))))) 247 cvmx_warn("CVMX_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset); 248 return 0x00000000000001A0ull + ((offset) & 31) * 16 - 16*12; 249} 250#else 251#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000001A0ull + ((offset) & 31) * 16 - 16*12) 252#endif 253#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254#define CVMX_SLI_MSI_ENB0 CVMX_SLI_MSI_ENB0_FUNC() 255static inline uint64_t CVMX_SLI_MSI_ENB0_FUNC(void) 256{ 257 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 258 cvmx_warn("CVMX_SLI_MSI_ENB0 not supported on this chip\n"); 259 return 0x0000000000003C50ull; 260} 261#else 262#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull) 263#endif 264#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265#define CVMX_SLI_MSI_ENB1 CVMX_SLI_MSI_ENB1_FUNC() 266static inline uint64_t CVMX_SLI_MSI_ENB1_FUNC(void) 267{ 268 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 269 cvmx_warn("CVMX_SLI_MSI_ENB1 not supported on this chip\n"); 270 return 0x0000000000003C60ull; 271} 272#else 273#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull) 274#endif 275#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276#define CVMX_SLI_MSI_ENB2 CVMX_SLI_MSI_ENB2_FUNC() 277static inline uint64_t CVMX_SLI_MSI_ENB2_FUNC(void) 278{ 279 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 280 cvmx_warn("CVMX_SLI_MSI_ENB2 not supported on this chip\n"); 281 return 0x0000000000003C70ull; 282} 283#else 284#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull) 285#endif 286#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287#define CVMX_SLI_MSI_ENB3 CVMX_SLI_MSI_ENB3_FUNC() 288static inline uint64_t CVMX_SLI_MSI_ENB3_FUNC(void) 289{ 290 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 291 cvmx_warn("CVMX_SLI_MSI_ENB3 not supported on this chip\n"); 292 return 0x0000000000003C80ull; 293} 294#else 295#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull) 296#endif 297#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298#define CVMX_SLI_MSI_RCV0 CVMX_SLI_MSI_RCV0_FUNC() 299static inline uint64_t CVMX_SLI_MSI_RCV0_FUNC(void) 300{ 301 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 302 cvmx_warn("CVMX_SLI_MSI_RCV0 not supported on this chip\n"); 303 return 0x0000000000003C10ull; 304} 305#else 306#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull) 307#endif 308#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309#define CVMX_SLI_MSI_RCV1 CVMX_SLI_MSI_RCV1_FUNC() 310static inline uint64_t CVMX_SLI_MSI_RCV1_FUNC(void) 311{ 312 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 313 cvmx_warn("CVMX_SLI_MSI_RCV1 not supported on this chip\n"); 314 return 0x0000000000003C20ull; 315} 316#else 317#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull) 318#endif 319#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320#define CVMX_SLI_MSI_RCV2 CVMX_SLI_MSI_RCV2_FUNC() 321static inline uint64_t CVMX_SLI_MSI_RCV2_FUNC(void) 322{ 323 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 324 cvmx_warn("CVMX_SLI_MSI_RCV2 not supported on this chip\n"); 325 return 0x0000000000003C30ull; 326} 327#else 328#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull) 329#endif 330#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331#define CVMX_SLI_MSI_RCV3 CVMX_SLI_MSI_RCV3_FUNC() 332static inline uint64_t CVMX_SLI_MSI_RCV3_FUNC(void) 333{ 334 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 335 cvmx_warn("CVMX_SLI_MSI_RCV3 not supported on this chip\n"); 336 return 0x0000000000003C40ull; 337} 338#else 339#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull) 340#endif 341#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342#define CVMX_SLI_MSI_RD_MAP CVMX_SLI_MSI_RD_MAP_FUNC() 343static inline uint64_t CVMX_SLI_MSI_RD_MAP_FUNC(void) 344{ 345 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 346 cvmx_warn("CVMX_SLI_MSI_RD_MAP not supported on this chip\n"); 347 return 0x0000000000003CA0ull; 348} 349#else 350#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull) 351#endif 352#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 353#define CVMX_SLI_MSI_W1C_ENB0 CVMX_SLI_MSI_W1C_ENB0_FUNC() 354static inline uint64_t CVMX_SLI_MSI_W1C_ENB0_FUNC(void) 355{ 356 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 357 cvmx_warn("CVMX_SLI_MSI_W1C_ENB0 not supported on this chip\n"); 358 return 0x0000000000003CF0ull; 359} 360#else 361#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull) 362#endif 363#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 364#define CVMX_SLI_MSI_W1C_ENB1 CVMX_SLI_MSI_W1C_ENB1_FUNC() 365static inline uint64_t CVMX_SLI_MSI_W1C_ENB1_FUNC(void) 366{ 367 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 368 cvmx_warn("CVMX_SLI_MSI_W1C_ENB1 not supported on this chip\n"); 369 return 0x0000000000003D00ull; 370} 371#else 372#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull) 373#endif 374#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 375#define CVMX_SLI_MSI_W1C_ENB2 CVMX_SLI_MSI_W1C_ENB2_FUNC() 376static inline uint64_t CVMX_SLI_MSI_W1C_ENB2_FUNC(void) 377{ 378 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 379 cvmx_warn("CVMX_SLI_MSI_W1C_ENB2 not supported on this chip\n"); 380 return 0x0000000000003D10ull; 381} 382#else 383#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull) 384#endif 385#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386#define CVMX_SLI_MSI_W1C_ENB3 CVMX_SLI_MSI_W1C_ENB3_FUNC() 387static inline uint64_t CVMX_SLI_MSI_W1C_ENB3_FUNC(void) 388{ 389 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 390 cvmx_warn("CVMX_SLI_MSI_W1C_ENB3 not supported on this chip\n"); 391 return 0x0000000000003D20ull; 392} 393#else 394#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull) 395#endif 396#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397#define CVMX_SLI_MSI_W1S_ENB0 CVMX_SLI_MSI_W1S_ENB0_FUNC() 398static inline uint64_t CVMX_SLI_MSI_W1S_ENB0_FUNC(void) 399{ 400 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 401 cvmx_warn("CVMX_SLI_MSI_W1S_ENB0 not supported on this chip\n"); 402 return 0x0000000000003D30ull; 403} 404#else 405#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull) 406#endif 407#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408#define CVMX_SLI_MSI_W1S_ENB1 CVMX_SLI_MSI_W1S_ENB1_FUNC() 409static inline uint64_t CVMX_SLI_MSI_W1S_ENB1_FUNC(void) 410{ 411 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 412 cvmx_warn("CVMX_SLI_MSI_W1S_ENB1 not supported on this chip\n"); 413 return 0x0000000000003D40ull; 414} 415#else 416#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull) 417#endif 418#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 419#define CVMX_SLI_MSI_W1S_ENB2 CVMX_SLI_MSI_W1S_ENB2_FUNC() 420static inline uint64_t CVMX_SLI_MSI_W1S_ENB2_FUNC(void) 421{ 422 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 423 cvmx_warn("CVMX_SLI_MSI_W1S_ENB2 not supported on this chip\n"); 424 return 0x0000000000003D50ull; 425} 426#else 427#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull) 428#endif 429#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430#define CVMX_SLI_MSI_W1S_ENB3 CVMX_SLI_MSI_W1S_ENB3_FUNC() 431static inline uint64_t CVMX_SLI_MSI_W1S_ENB3_FUNC(void) 432{ 433 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 434 cvmx_warn("CVMX_SLI_MSI_W1S_ENB3 not supported on this chip\n"); 435 return 0x0000000000003D60ull; 436} 437#else 438#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull) 439#endif 440#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441#define CVMX_SLI_MSI_WR_MAP CVMX_SLI_MSI_WR_MAP_FUNC() 442static inline uint64_t CVMX_SLI_MSI_WR_MAP_FUNC(void) 443{ 444 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 445 cvmx_warn("CVMX_SLI_MSI_WR_MAP not supported on this chip\n"); 446 return 0x0000000000003C90ull; 447} 448#else 449#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull) 450#endif 451#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC() 453static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void) 454{ 455 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 456 cvmx_warn("CVMX_SLI_PCIE_MSI_RCV not supported on this chip\n"); 457 return 0x0000000000003CB0ull; 458} 459#else 460#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull) 461#endif 462#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463#define CVMX_SLI_PCIE_MSI_RCV_B1 CVMX_SLI_PCIE_MSI_RCV_B1_FUNC() 464static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B1_FUNC(void) 465{ 466 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 467 cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n"); 468 return 0x0000000000000650ull; 469} 470#else 471#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull) 472#endif 473#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474#define CVMX_SLI_PCIE_MSI_RCV_B2 CVMX_SLI_PCIE_MSI_RCV_B2_FUNC() 475static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B2_FUNC(void) 476{ 477 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 478 cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n"); 479 return 0x0000000000000660ull; 480} 481#else 482#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull) 483#endif 484#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485#define CVMX_SLI_PCIE_MSI_RCV_B3 CVMX_SLI_PCIE_MSI_RCV_B3_FUNC() 486static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B3_FUNC(void) 487{ 488 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 489 cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n"); 490 return 0x0000000000000670ull; 491} 492#else 493#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull) 494#endif 495#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496static inline uint64_t CVMX_SLI_PKTX_CNTS(unsigned long offset) 497{ 498 if (!( 499 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 500 cvmx_warn("CVMX_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset); 501 return 0x0000000000002400ull + ((offset) & 31) * 16; 502} 503#else 504#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16) 505#endif 506#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507static inline uint64_t CVMX_SLI_PKTX_INSTR_BADDR(unsigned long offset) 508{ 509 if (!( 510 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 511 cvmx_warn("CVMX_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset); 512 return 0x0000000000002800ull + ((offset) & 31) * 16; 513} 514#else 515#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16) 516#endif 517#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518static inline uint64_t CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset) 519{ 520 if (!( 521 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 522 cvmx_warn("CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 523 return 0x0000000000002C00ull + ((offset) & 31) * 16; 524} 525#else 526#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16) 527#endif 528#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529static inline uint64_t CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset) 530{ 531 if (!( 532 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 533 cvmx_warn("CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 534 return 0x0000000000003000ull + ((offset) & 31) * 16; 535} 536#else 537#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16) 538#endif 539#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540static inline uint64_t CVMX_SLI_PKTX_INSTR_HEADER(unsigned long offset) 541{ 542 if (!( 543 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 544 cvmx_warn("CVMX_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset); 545 return 0x0000000000003400ull + ((offset) & 31) * 16; 546} 547#else 548#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16) 549#endif 550#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551static inline uint64_t CVMX_SLI_PKTX_IN_BP(unsigned long offset) 552{ 553 if (!( 554 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 555 cvmx_warn("CVMX_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset); 556 return 0x0000000000003800ull + ((offset) & 31) * 16; 557} 558#else 559#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16) 560#endif 561#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562static inline uint64_t CVMX_SLI_PKTX_OUT_SIZE(unsigned long offset) 563{ 564 if (!( 565 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 566 cvmx_warn("CVMX_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset); 567 return 0x0000000000000C00ull + ((offset) & 31) * 16; 568} 569#else 570#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16) 571#endif 572#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 573static inline uint64_t CVMX_SLI_PKTX_SLIST_BADDR(unsigned long offset) 574{ 575 if (!( 576 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 577 cvmx_warn("CVMX_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset); 578 return 0x0000000000001400ull + ((offset) & 31) * 16; 579} 580#else 581#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16) 582#endif 583#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 584static inline uint64_t CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset) 585{ 586 if (!( 587 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 588 cvmx_warn("CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 589 return 0x0000000000001800ull + ((offset) & 31) * 16; 590} 591#else 592#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16) 593#endif 594#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 595static inline uint64_t CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset) 596{ 597 if (!( 598 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 599 cvmx_warn("CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 600 return 0x0000000000001C00ull + ((offset) & 31) * 16; 601} 602#else 603#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16) 604#endif 605#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 606#define CVMX_SLI_PKT_CNT_INT CVMX_SLI_PKT_CNT_INT_FUNC() 607static inline uint64_t CVMX_SLI_PKT_CNT_INT_FUNC(void) 608{ 609 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 610 cvmx_warn("CVMX_SLI_PKT_CNT_INT not supported on this chip\n"); 611 return 0x0000000000001130ull; 612} 613#else 614#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull) 615#endif 616#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617#define CVMX_SLI_PKT_CNT_INT_ENB CVMX_SLI_PKT_CNT_INT_ENB_FUNC() 618static inline uint64_t CVMX_SLI_PKT_CNT_INT_ENB_FUNC(void) 619{ 620 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 621 cvmx_warn("CVMX_SLI_PKT_CNT_INT_ENB not supported on this chip\n"); 622 return 0x0000000000001150ull; 623} 624#else 625#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull) 626#endif 627#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628#define CVMX_SLI_PKT_CTL CVMX_SLI_PKT_CTL_FUNC() 629static inline uint64_t CVMX_SLI_PKT_CTL_FUNC(void) 630{ 631 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 632 cvmx_warn("CVMX_SLI_PKT_CTL not supported on this chip\n"); 633 return 0x0000000000001220ull; 634} 635#else 636#define CVMX_SLI_PKT_CTL (0x0000000000001220ull) 637#endif 638#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 639#define CVMX_SLI_PKT_DATA_OUT_ES CVMX_SLI_PKT_DATA_OUT_ES_FUNC() 640static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ES_FUNC(void) 641{ 642 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 643 cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ES not supported on this chip\n"); 644 return 0x00000000000010B0ull; 645} 646#else 647#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull) 648#endif 649#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650#define CVMX_SLI_PKT_DATA_OUT_NS CVMX_SLI_PKT_DATA_OUT_NS_FUNC() 651static inline uint64_t CVMX_SLI_PKT_DATA_OUT_NS_FUNC(void) 652{ 653 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 654 cvmx_warn("CVMX_SLI_PKT_DATA_OUT_NS not supported on this chip\n"); 655 return 0x00000000000010A0ull; 656} 657#else 658#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull) 659#endif 660#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661#define CVMX_SLI_PKT_DATA_OUT_ROR CVMX_SLI_PKT_DATA_OUT_ROR_FUNC() 662static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ROR_FUNC(void) 663{ 664 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 665 cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ROR not supported on this chip\n"); 666 return 0x0000000000001090ull; 667} 668#else 669#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull) 670#endif 671#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672#define CVMX_SLI_PKT_DPADDR CVMX_SLI_PKT_DPADDR_FUNC() 673static inline uint64_t CVMX_SLI_PKT_DPADDR_FUNC(void) 674{ 675 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 676 cvmx_warn("CVMX_SLI_PKT_DPADDR not supported on this chip\n"); 677 return 0x0000000000001080ull; 678} 679#else 680#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull) 681#endif 682#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 683#define CVMX_SLI_PKT_INPUT_CONTROL CVMX_SLI_PKT_INPUT_CONTROL_FUNC() 684static inline uint64_t CVMX_SLI_PKT_INPUT_CONTROL_FUNC(void) 685{ 686 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 687 cvmx_warn("CVMX_SLI_PKT_INPUT_CONTROL not supported on this chip\n"); 688 return 0x0000000000001170ull; 689} 690#else 691#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull) 692#endif 693#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 694#define CVMX_SLI_PKT_INSTR_ENB CVMX_SLI_PKT_INSTR_ENB_FUNC() 695static inline uint64_t CVMX_SLI_PKT_INSTR_ENB_FUNC(void) 696{ 697 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 698 cvmx_warn("CVMX_SLI_PKT_INSTR_ENB not supported on this chip\n"); 699 return 0x0000000000001000ull; 700} 701#else 702#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull) 703#endif 704#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 705#define CVMX_SLI_PKT_INSTR_RD_SIZE CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC() 706static inline uint64_t CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC(void) 707{ 708 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 709 cvmx_warn("CVMX_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n"); 710 return 0x00000000000011A0ull; 711} 712#else 713#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull) 714#endif 715#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716#define CVMX_SLI_PKT_INSTR_SIZE CVMX_SLI_PKT_INSTR_SIZE_FUNC() 717static inline uint64_t CVMX_SLI_PKT_INSTR_SIZE_FUNC(void) 718{ 719 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 720 cvmx_warn("CVMX_SLI_PKT_INSTR_SIZE not supported on this chip\n"); 721 return 0x0000000000001020ull; 722} 723#else 724#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull) 725#endif 726#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 727#define CVMX_SLI_PKT_INT_LEVELS CVMX_SLI_PKT_INT_LEVELS_FUNC() 728static inline uint64_t CVMX_SLI_PKT_INT_LEVELS_FUNC(void) 729{ 730 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 731 cvmx_warn("CVMX_SLI_PKT_INT_LEVELS not supported on this chip\n"); 732 return 0x0000000000001120ull; 733} 734#else 735#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull) 736#endif 737#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 738#define CVMX_SLI_PKT_IN_BP CVMX_SLI_PKT_IN_BP_FUNC() 739static inline uint64_t CVMX_SLI_PKT_IN_BP_FUNC(void) 740{ 741 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 742 cvmx_warn("CVMX_SLI_PKT_IN_BP not supported on this chip\n"); 743 return 0x0000000000001210ull; 744} 745#else 746#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull) 747#endif 748#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 749static inline uint64_t CVMX_SLI_PKT_IN_DONEX_CNTS(unsigned long offset) 750{ 751 if (!( 752 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))))) 753 cvmx_warn("CVMX_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset); 754 return 0x0000000000002000ull + ((offset) & 31) * 16; 755} 756#else 757#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16) 758#endif 759#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 760#define CVMX_SLI_PKT_IN_INSTR_COUNTS CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC() 761static inline uint64_t CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC(void) 762{ 763 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 764 cvmx_warn("CVMX_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n"); 765 return 0x0000000000001200ull; 766} 767#else 768#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull) 769#endif 770#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 771#define CVMX_SLI_PKT_IN_PCIE_PORT CVMX_SLI_PKT_IN_PCIE_PORT_FUNC() 772static inline uint64_t CVMX_SLI_PKT_IN_PCIE_PORT_FUNC(void) 773{ 774 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 775 cvmx_warn("CVMX_SLI_PKT_IN_PCIE_PORT not supported on this chip\n"); 776 return 0x00000000000011B0ull; 777} 778#else 779#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull) 780#endif 781#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 782#define CVMX_SLI_PKT_IPTR CVMX_SLI_PKT_IPTR_FUNC() 783static inline uint64_t CVMX_SLI_PKT_IPTR_FUNC(void) 784{ 785 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 786 cvmx_warn("CVMX_SLI_PKT_IPTR not supported on this chip\n"); 787 return 0x0000000000001070ull; 788} 789#else 790#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull) 791#endif 792#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 793#define CVMX_SLI_PKT_OUTPUT_WMARK CVMX_SLI_PKT_OUTPUT_WMARK_FUNC() 794static inline uint64_t CVMX_SLI_PKT_OUTPUT_WMARK_FUNC(void) 795{ 796 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 797 cvmx_warn("CVMX_SLI_PKT_OUTPUT_WMARK not supported on this chip\n"); 798 return 0x0000000000001180ull; 799} 800#else 801#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull) 802#endif 803#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 804#define CVMX_SLI_PKT_OUT_BMODE CVMX_SLI_PKT_OUT_BMODE_FUNC() 805static inline uint64_t CVMX_SLI_PKT_OUT_BMODE_FUNC(void) 806{ 807 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 808 cvmx_warn("CVMX_SLI_PKT_OUT_BMODE not supported on this chip\n"); 809 return 0x00000000000010D0ull; 810} 811#else 812#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull) 813#endif 814#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 815#define CVMX_SLI_PKT_OUT_ENB CVMX_SLI_PKT_OUT_ENB_FUNC() 816static inline uint64_t CVMX_SLI_PKT_OUT_ENB_FUNC(void) 817{ 818 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 819 cvmx_warn("CVMX_SLI_PKT_OUT_ENB not supported on this chip\n"); 820 return 0x0000000000001010ull; 821} 822#else 823#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull) 824#endif 825#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 826#define CVMX_SLI_PKT_PCIE_PORT CVMX_SLI_PKT_PCIE_PORT_FUNC() 827static inline uint64_t CVMX_SLI_PKT_PCIE_PORT_FUNC(void) 828{ 829 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 830 cvmx_warn("CVMX_SLI_PKT_PCIE_PORT not supported on this chip\n"); 831 return 0x00000000000010E0ull; 832} 833#else 834#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull) 835#endif 836#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 837#define CVMX_SLI_PKT_PORT_IN_RST CVMX_SLI_PKT_PORT_IN_RST_FUNC() 838static inline uint64_t CVMX_SLI_PKT_PORT_IN_RST_FUNC(void) 839{ 840 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 841 cvmx_warn("CVMX_SLI_PKT_PORT_IN_RST not supported on this chip\n"); 842 return 0x00000000000011F0ull; 843} 844#else 845#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull) 846#endif 847#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 848#define CVMX_SLI_PKT_SLIST_ES CVMX_SLI_PKT_SLIST_ES_FUNC() 849static inline uint64_t CVMX_SLI_PKT_SLIST_ES_FUNC(void) 850{ 851 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 852 cvmx_warn("CVMX_SLI_PKT_SLIST_ES not supported on this chip\n"); 853 return 0x0000000000001050ull; 854} 855#else 856#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull) 857#endif 858#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 859#define CVMX_SLI_PKT_SLIST_NS CVMX_SLI_PKT_SLIST_NS_FUNC() 860static inline uint64_t CVMX_SLI_PKT_SLIST_NS_FUNC(void) 861{ 862 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 863 cvmx_warn("CVMX_SLI_PKT_SLIST_NS not supported on this chip\n"); 864 return 0x0000000000001040ull; 865} 866#else 867#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull) 868#endif 869#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 870#define CVMX_SLI_PKT_SLIST_ROR CVMX_SLI_PKT_SLIST_ROR_FUNC() 871static inline uint64_t CVMX_SLI_PKT_SLIST_ROR_FUNC(void) 872{ 873 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 874 cvmx_warn("CVMX_SLI_PKT_SLIST_ROR not supported on this chip\n"); 875 return 0x0000000000001030ull; 876} 877#else 878#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull) 879#endif 880#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 881#define CVMX_SLI_PKT_TIME_INT CVMX_SLI_PKT_TIME_INT_FUNC() 882static inline uint64_t CVMX_SLI_PKT_TIME_INT_FUNC(void) 883{ 884 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 885 cvmx_warn("CVMX_SLI_PKT_TIME_INT not supported on this chip\n"); 886 return 0x0000000000001140ull; 887} 888#else 889#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull) 890#endif 891#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 892#define CVMX_SLI_PKT_TIME_INT_ENB CVMX_SLI_PKT_TIME_INT_ENB_FUNC() 893static inline uint64_t CVMX_SLI_PKT_TIME_INT_ENB_FUNC(void) 894{ 895 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 896 cvmx_warn("CVMX_SLI_PKT_TIME_INT_ENB not supported on this chip\n"); 897 return 0x0000000000001160ull; 898} 899#else 900#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull) 901#endif 902#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 903static inline uint64_t CVMX_SLI_S2M_PORTX_CTL(unsigned long offset) 904{ 905 if (!( 906 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))))) 907 cvmx_warn("CVMX_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset); 908 return 0x0000000000003D80ull + ((offset) & 1) * 16; 909} 910#else 911#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 1) * 16) 912#endif 913#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 914#define CVMX_SLI_SCRATCH_1 CVMX_SLI_SCRATCH_1_FUNC() 915static inline uint64_t CVMX_SLI_SCRATCH_1_FUNC(void) 916{ 917 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 918 cvmx_warn("CVMX_SLI_SCRATCH_1 not supported on this chip\n"); 919 return 0x00000000000003C0ull; 920} 921#else 922#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull) 923#endif 924#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 925#define CVMX_SLI_SCRATCH_2 CVMX_SLI_SCRATCH_2_FUNC() 926static inline uint64_t CVMX_SLI_SCRATCH_2_FUNC(void) 927{ 928 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 929 cvmx_warn("CVMX_SLI_SCRATCH_2 not supported on this chip\n"); 930 return 0x00000000000003D0ull; 931} 932#else 933#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull) 934#endif 935#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 936#define CVMX_SLI_STATE1 CVMX_SLI_STATE1_FUNC() 937static inline uint64_t CVMX_SLI_STATE1_FUNC(void) 938{ 939 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 940 cvmx_warn("CVMX_SLI_STATE1 not supported on this chip\n"); 941 return 0x0000000000000620ull; 942} 943#else 944#define CVMX_SLI_STATE1 (0x0000000000000620ull) 945#endif 946#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 947#define CVMX_SLI_STATE2 CVMX_SLI_STATE2_FUNC() 948static inline uint64_t CVMX_SLI_STATE2_FUNC(void) 949{ 950 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 951 cvmx_warn("CVMX_SLI_STATE2 not supported on this chip\n"); 952 return 0x0000000000000630ull; 953} 954#else 955#define CVMX_SLI_STATE2 (0x0000000000000630ull) 956#endif 957#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 958#define CVMX_SLI_STATE3 CVMX_SLI_STATE3_FUNC() 959static inline uint64_t CVMX_SLI_STATE3_FUNC(void) 960{ 961 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 962 cvmx_warn("CVMX_SLI_STATE3 not supported on this chip\n"); 963 return 0x0000000000000640ull; 964} 965#else 966#define CVMX_SLI_STATE3 (0x0000000000000640ull) 967#endif 968#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 969#define CVMX_SLI_WINDOW_CTL CVMX_SLI_WINDOW_CTL_FUNC() 970static inline uint64_t CVMX_SLI_WINDOW_CTL_FUNC(void) 971{ 972 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 973 cvmx_warn("CVMX_SLI_WINDOW_CTL not supported on this chip\n"); 974 return 0x00000000000002E0ull; 975} 976#else 977#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull) 978#endif 979#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 980#define CVMX_SLI_WIN_RD_ADDR CVMX_SLI_WIN_RD_ADDR_FUNC() 981static inline uint64_t CVMX_SLI_WIN_RD_ADDR_FUNC(void) 982{ 983 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 984 cvmx_warn("CVMX_SLI_WIN_RD_ADDR not supported on this chip\n"); 985 return 0x0000000000000010ull; 986} 987#else 988#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull) 989#endif 990#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 991#define CVMX_SLI_WIN_RD_DATA CVMX_SLI_WIN_RD_DATA_FUNC() 992static inline uint64_t CVMX_SLI_WIN_RD_DATA_FUNC(void) 993{ 994 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 995 cvmx_warn("CVMX_SLI_WIN_RD_DATA not supported on this chip\n"); 996 return 0x0000000000000040ull; 997} 998#else 999#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull) 1000#endif 1001#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1002#define CVMX_SLI_WIN_WR_ADDR CVMX_SLI_WIN_WR_ADDR_FUNC() 1003static inline uint64_t CVMX_SLI_WIN_WR_ADDR_FUNC(void) 1004{ 1005 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1006 cvmx_warn("CVMX_SLI_WIN_WR_ADDR not supported on this chip\n"); 1007 return 0x0000000000000000ull; 1008} 1009#else 1010#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull) 1011#endif 1012#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1013#define CVMX_SLI_WIN_WR_DATA CVMX_SLI_WIN_WR_DATA_FUNC() 1014static inline uint64_t CVMX_SLI_WIN_WR_DATA_FUNC(void) 1015{ 1016 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1017 cvmx_warn("CVMX_SLI_WIN_WR_DATA not supported on this chip\n"); 1018 return 0x0000000000000020ull; 1019} 1020#else 1021#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull) 1022#endif 1023#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1024#define CVMX_SLI_WIN_WR_MASK CVMX_SLI_WIN_WR_MASK_FUNC() 1025static inline uint64_t CVMX_SLI_WIN_WR_MASK_FUNC(void) 1026{ 1027 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 1028 cvmx_warn("CVMX_SLI_WIN_WR_MASK not supported on this chip\n"); 1029 return 0x0000000000000030ull; 1030} 1031#else 1032#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull) 1033#endif 1034 1035/** 1036 * cvmx_sli_bist_status 1037 * 1038 * SLI_BIST_STATUS = SLI's BIST Status Register 1039 * 1040 * Results from BIST runs of SLI's memories. 1041 */ 1042union cvmx_sli_bist_status 1043{ 1044 uint64_t u64; 1045 struct cvmx_sli_bist_status_s 1046 { 1047#if __BYTE_ORDER == __BIG_ENDIAN 1048 uint64_t reserved_31_63 : 33; 1049 uint64_t n2p0_c : 1; /**< BIST Status for N2P Port0 Cmd */ 1050 uint64_t n2p0_o : 1; /**< BIST Status for N2P Port0 Data */ 1051 uint64_t n2p1_c : 1; /**< BIST Status for N2P Port1 Cmd */ 1052 uint64_t n2p1_o : 1; /**< BIST Status for N2P Port1 Data */ 1053 uint64_t cpl_p0 : 1; /**< BIST Status for CPL Port 0 */ 1054 uint64_t cpl_p1 : 1; /**< BIST Status for CPL Port 1 */ 1055 uint64_t reserved_19_24 : 6; 1056 uint64_t p2n0_c0 : 1; /**< BIST Status for P2N Port0 C0 */ 1057 uint64_t p2n0_c1 : 1; /**< BIST Status for P2N Port0 C1 */ 1058 uint64_t p2n0_n : 1; /**< BIST Status for P2N Port0 N */ 1059 uint64_t p2n0_p0 : 1; /**< BIST Status for P2N Port0 P0 */ 1060 uint64_t p2n0_p1 : 1; /**< BIST Status for P2N Port0 P1 */ 1061 uint64_t p2n1_c0 : 1; /**< BIST Status for P2N Port1 C0 */ 1062 uint64_t p2n1_c1 : 1; /**< BIST Status for P2N Port1 C1 */ 1063 uint64_t p2n1_n : 1; /**< BIST Status for P2N Port1 N */ 1064 uint64_t p2n1_p0 : 1; /**< BIST Status for P2N Port1 P0 */ 1065 uint64_t p2n1_p1 : 1; /**< BIST Status for P2N Port1 P1 */ 1066 uint64_t reserved_6_8 : 3; 1067 uint64_t dsi1_1 : 1; /**< BIST Status for DSI1 Memory 1 */ 1068 uint64_t dsi1_0 : 1; /**< BIST Status for DSI1 Memory 0 */ 1069 uint64_t dsi0_1 : 1; /**< BIST Status for DSI0 Memory 1 */ 1070 uint64_t dsi0_0 : 1; /**< BIST Status for DSI0 Memory 0 */ 1071 uint64_t msi : 1; /**< BIST Status for MSI Memory Map */ 1072 uint64_t ncb_cmd : 1; /**< BIST Status for NCB Outbound Commands */ 1073#else 1074 uint64_t ncb_cmd : 1; 1075 uint64_t msi : 1; 1076 uint64_t dsi0_0 : 1; 1077 uint64_t dsi0_1 : 1; 1078 uint64_t dsi1_0 : 1; 1079 uint64_t dsi1_1 : 1; 1080 uint64_t reserved_6_8 : 3; 1081 uint64_t p2n1_p1 : 1; 1082 uint64_t p2n1_p0 : 1; 1083 uint64_t p2n1_n : 1; 1084 uint64_t p2n1_c1 : 1; 1085 uint64_t p2n1_c0 : 1; 1086 uint64_t p2n0_p1 : 1; 1087 uint64_t p2n0_p0 : 1; 1088 uint64_t p2n0_n : 1; 1089 uint64_t p2n0_c1 : 1; 1090 uint64_t p2n0_c0 : 1; 1091 uint64_t reserved_19_24 : 6; 1092 uint64_t cpl_p1 : 1; 1093 uint64_t cpl_p0 : 1; 1094 uint64_t n2p1_o : 1; 1095 uint64_t n2p1_c : 1; 1096 uint64_t n2p0_o : 1; 1097 uint64_t n2p0_c : 1; 1098 uint64_t reserved_31_63 : 33; 1099#endif 1100 } s; 1101 struct cvmx_sli_bist_status_s cn63xx; 1102 struct cvmx_sli_bist_status_s cn63xxp1; 1103}; 1104typedef union cvmx_sli_bist_status cvmx_sli_bist_status_t; 1105 1106/** 1107 * cvmx_sli_ctl_port# 1108 * 1109 * SLI_CTL_PORTX = SLI's Control Port X 1110 * 1111 * Contains control for access for Port0 1112 */ 1113union cvmx_sli_ctl_portx 1114{ 1115 uint64_t u64; 1116 struct cvmx_sli_ctl_portx_s 1117 { 1118#if __BYTE_ORDER == __BIG_ENDIAN 1119 uint64_t reserved_22_63 : 42; 1120 uint64_t intd : 1; /**< When '0' Intd wire asserted. Before mapping. */ 1121 uint64_t intc : 1; /**< When '0' Intc wire asserted. Before mapping. */ 1122 uint64_t intb : 1; /**< When '0' Intb wire asserted. Before mapping. */ 1123 uint64_t inta : 1; /**< When '0' Inta wire asserted. Before mapping. */ 1124 uint64_t dis_port : 1; /**< When set the output to the MAC is disabled. This 1125 occurs when the MAC reset line transitions from 1126 de-asserted to asserted. Writing a '1' to this 1127 location will clear this condition when the MAC is 1128 no longer in reset and the output to the MAC is at 1129 the begining of a transfer. */ 1130 uint64_t waitl_com : 1; /**< When set '1' casues the SLI to wait for a commit 1131 from the L2C before sending additional completions 1132 to the L2C from a MAC. 1133 Set this for more conservative behavior. Clear 1134 this for more aggressive, higher-performance 1135 behavior */ 1136 uint64_t intd_map : 2; /**< Maps INTD to INTA(00), INTB(01), INTC(10) or 1137 INTD (11). */ 1138 uint64_t intc_map : 2; /**< Maps INTC to INTA(00), INTB(01), INTC(10) or 1139 INTD (11). */ 1140 uint64_t intb_map : 2; /**< Maps INTB to INTA(00), INTB(01), INTC(10) or 1141 INTD (11). */ 1142 uint64_t inta_map : 2; /**< Maps INTA to INTA(00), INTB(01), INTC(10) or 1143 INTD (11). */ 1144 uint64_t ctlp_ro : 1; /**< Relaxed ordering enable for Completion TLPS. */ 1145 uint64_t reserved_6_6 : 1; 1146 uint64_t ptlp_ro : 1; /**< Relaxed ordering enable for Posted TLPS. */ 1147 uint64_t reserved_1_4 : 4; 1148 uint64_t wait_com : 1; /**< When set '1' casues the SLI to wait for a commit 1149 from the L2C before sending additional stores to 1150 the L2C from a MAC. 1151 The SLI will request a commit on the last store 1152 if more than one STORE operation is required on 1153 the NCB. 1154 Most applications will not notice a difference, so 1155 should not set this bit. Setting the bit is more 1156 conservative on ordering, lower performance */ 1157#else 1158 uint64_t wait_com : 1; 1159 uint64_t reserved_1_4 : 4; 1160 uint64_t ptlp_ro : 1; 1161 uint64_t reserved_6_6 : 1; 1162 uint64_t ctlp_ro : 1; 1163 uint64_t inta_map : 2; 1164 uint64_t intb_map : 2; 1165 uint64_t intc_map : 2; 1166 uint64_t intd_map : 2; 1167 uint64_t waitl_com : 1; 1168 uint64_t dis_port : 1; 1169 uint64_t inta : 1; 1170 uint64_t intb : 1; 1171 uint64_t intc : 1; 1172 uint64_t intd : 1; 1173 uint64_t reserved_22_63 : 42; 1174#endif 1175 } s; 1176 struct cvmx_sli_ctl_portx_s cn63xx; 1177 struct cvmx_sli_ctl_portx_s cn63xxp1; 1178}; 1179typedef union cvmx_sli_ctl_portx cvmx_sli_ctl_portx_t; 1180 1181/** 1182 * cvmx_sli_ctl_status 1183 * 1184 * SLI_CTL_STATUS = SLI Control Status Register 1185 * 1186 * Contains control and status for SLI. Writes to this register are not ordered with writes/reads to the MAC Memory space. 1187 * To ensure that a write has completed the user must read the register before making an access(i.e. MAC memory space) 1188 * that requires the value of this register to be updated. 1189 */ 1190union cvmx_sli_ctl_status 1191{ 1192 uint64_t u64; 1193 struct cvmx_sli_ctl_status_s 1194 { 1195#if __BYTE_ORDER == __BIG_ENDIAN 1196 uint64_t reserved_20_63 : 44; 1197 uint64_t p1_ntags : 6; /**< Number of tags available for MAC Port1. 1198 In RC mode 1 tag is needed for each outbound TLP 1199 that requires a CPL TLP. In Endpoint mode the 1200 number of tags required for a TLP request is 1201 1 per 64-bytes of CPL data + 1. 1202 This field should only be written as part of 1203 reset sequence, before issuing any reads, CFGs, or 1204 IO transactions from the core(s). */ 1205 uint64_t p0_ntags : 6; /**< Number of tags available for MAC Port0. 1206 In RC mode 1 tag is needed for each outbound TLP 1207 that requires a CPL TLP. In Endpoint mode the 1208 number of tags required for a TLP request is 1209 1 per 64-bytes of CPL data + 1. 1210 This field should only be written as part of 1211 reset sequence, before issuing any reads, CFGs, or 1212 IO transactions from the core(s). */ 1213 uint64_t chip_rev : 8; /**< The chip revision. */ 1214#else 1215 uint64_t chip_rev : 8; 1216 uint64_t p0_ntags : 6; 1217 uint64_t p1_ntags : 6; 1218 uint64_t reserved_20_63 : 44; 1219#endif 1220 } s; 1221 struct cvmx_sli_ctl_status_s cn63xx; 1222 struct cvmx_sli_ctl_status_s cn63xxp1; 1223}; 1224typedef union cvmx_sli_ctl_status cvmx_sli_ctl_status_t; 1225 1226/** 1227 * cvmx_sli_data_out_cnt 1228 * 1229 * SLI_DATA_OUT_CNT = SLI DATA OUT COUNT 1230 * 1231 * The EXEC data out fifo-count and the data unload counter. 1232 */ 1233union cvmx_sli_data_out_cnt 1234{ 1235 uint64_t u64; 1236 struct cvmx_sli_data_out_cnt_s 1237 { 1238#if __BYTE_ORDER == __BIG_ENDIAN 1239 uint64_t reserved_44_63 : 20; 1240 uint64_t p1_ucnt : 16; /**< MAC Port1 Fifo Unload Count. This counter is 1241 incremented by '1' every time a word is removed 1242 from the Data Out FIFO, whose count is shown in 1243 P0_FCNT. */ 1244 uint64_t p1_fcnt : 6; /**< MAC Port1 Data Out Fifo Count. Number of address 1245 data words to be sent out the MAC port presently 1246 buffered in the FIFO. */ 1247 uint64_t p0_ucnt : 16; /**< MAC Port0 Fifo Unload Count. This counter is 1248 incremented by '1' every time a word is removed 1249 from the Data Out FIFO, whose count is shown in 1250 P0_FCNT. */ 1251 uint64_t p0_fcnt : 6; /**< MAC Port0 Data Out Fifo Count. Number of address 1252 data words to be sent out the MAC port presently 1253 buffered in the FIFO. */ 1254#else 1255 uint64_t p0_fcnt : 6; 1256 uint64_t p0_ucnt : 16; 1257 uint64_t p1_fcnt : 6; 1258 uint64_t p1_ucnt : 16; 1259 uint64_t reserved_44_63 : 20; 1260#endif 1261 } s; 1262 struct cvmx_sli_data_out_cnt_s cn63xx; 1263 struct cvmx_sli_data_out_cnt_s cn63xxp1; 1264}; 1265typedef union cvmx_sli_data_out_cnt cvmx_sli_data_out_cnt_t; 1266 1267/** 1268 * cvmx_sli_dbg_data 1269 * 1270 * SLI_DBG_DATA = SLI Debug Data Register 1271 * 1272 * Value returned on the debug-data lines from the RSLs 1273 */ 1274union cvmx_sli_dbg_data 1275{ 1276 uint64_t u64; 1277 struct cvmx_sli_dbg_data_s 1278 { 1279#if __BYTE_ORDER == __BIG_ENDIAN 1280 uint64_t reserved_18_63 : 46; 1281 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 1282 debug select value. */ 1283 uint64_t data : 17; /**< Value on the debug data lines. */ 1284#else 1285 uint64_t data : 17; 1286 uint64_t dsel_ext : 1; 1287 uint64_t reserved_18_63 : 46; 1288#endif 1289 } s; 1290 struct cvmx_sli_dbg_data_s cn63xx; 1291 struct cvmx_sli_dbg_data_s cn63xxp1; 1292}; 1293typedef union cvmx_sli_dbg_data cvmx_sli_dbg_data_t; 1294 1295/** 1296 * cvmx_sli_dbg_select 1297 * 1298 * SLI_DBG_SELECT = Debug Select Register 1299 * 1300 * Contains the debug select value last written to the RSLs. 1301 */ 1302union cvmx_sli_dbg_select 1303{ 1304 uint64_t u64; 1305 struct cvmx_sli_dbg_select_s 1306 { 1307#if __BYTE_ORDER == __BIG_ENDIAN 1308 uint64_t reserved_33_63 : 31; 1309 uint64_t adbg_sel : 1; /**< When set '1' the SLI_DBG_DATA[DATA] will only be 1310 loaded when SLI_DBG_DATA[DATA] bit [16] is a '1'. 1311 When the debug data comes from an Async-RSL bit 1312 16 is used to tell that the data present is valid. */ 1313 uint64_t dbg_sel : 32; /**< When this register is written the RML will write 1314 all "F"s to the previous RTL to disable it from 1315 sending Debug-Data. The RML will then send a write 1316 to the new RSL with the supplied Debug-Select 1317 value. Because it takes time for the new Debug 1318 Select value to take effect and the requested 1319 Debug-Data to return, time is needed to the new 1320 Debug-Data to arrive. The inititator of the Debug 1321 Select should issue a read to a CSR before reading 1322 the Debug Data (this read could also be to the 1323 SLI_DBG_DATA but the returned value for the first 1324 read will return NS data. */ 1325#else 1326 uint64_t dbg_sel : 32; 1327 uint64_t adbg_sel : 1; 1328 uint64_t reserved_33_63 : 31; 1329#endif 1330 } s; 1331 struct cvmx_sli_dbg_select_s cn63xx; 1332 struct cvmx_sli_dbg_select_s cn63xxp1; 1333}; 1334typedef union cvmx_sli_dbg_select cvmx_sli_dbg_select_t; 1335 1336/** 1337 * cvmx_sli_dma#_cnt 1338 * 1339 * SLI_DMAx_CNT = SLI DMA Count 1340 * 1341 * The DMA Count value. 1342 */ 1343union cvmx_sli_dmax_cnt 1344{ 1345 uint64_t u64; 1346 struct cvmx_sli_dmax_cnt_s 1347 { 1348#if __BYTE_ORDER == __BIG_ENDIAN 1349 uint64_t reserved_32_63 : 32; 1350 uint64_t cnt : 32; /**< The DMA counter. 1351 Writing this field will cause the written value 1352 to be subtracted from DMA. HW will optionally 1353 increment this field after it completes an 1354 OUTBOUND or EXTERNAL-ONLY DMA instruction. These 1355 increments may cause interrupts. Refer to 1356 SLI_DMAx_INT_LEVEL and SLI_INT_SUM[DCNT,DTIME]. */ 1357#else 1358 uint64_t cnt : 32; 1359 uint64_t reserved_32_63 : 32; 1360#endif 1361 } s; 1362 struct cvmx_sli_dmax_cnt_s cn63xx; 1363 struct cvmx_sli_dmax_cnt_s cn63xxp1; 1364}; 1365typedef union cvmx_sli_dmax_cnt cvmx_sli_dmax_cnt_t; 1366 1367/** 1368 * cvmx_sli_dma#_int_level 1369 * 1370 * SLI_DMAx_INT_LEVEL = SLI DMAx Interrupt Level 1371 * 1372 * Thresholds for DMA count and timer interrupts. 1373 */ 1374union cvmx_sli_dmax_int_level 1375{ 1376 uint64_t u64; 1377 struct cvmx_sli_dmax_int_level_s 1378 { 1379#if __BYTE_ORDER == __BIG_ENDIAN 1380 uint64_t time : 32; /**< Whenever the SLI_DMAx_TIM[TIM] timer exceeds 1381 this value, SLI_INT_SUM[DTIME<x>] is set. 1382 The SLI_DMAx_TIM[TIM] timer increments every SLI 1383 clock whenever SLI_DMAx_CNT[CNT]!=0, and is 1384 cleared when SLI_INT_SUM[DTIME<x>] is written with 1385 one. */ 1386 uint64_t cnt : 32; /**< Whenever SLI_DMAx_CNT[CNT] exceeds this value, 1387 SLI_INT_SUM[DCNT<x>] is set. */ 1388#else 1389 uint64_t cnt : 32; 1390 uint64_t time : 32; 1391#endif 1392 } s; 1393 struct cvmx_sli_dmax_int_level_s cn63xx; 1394 struct cvmx_sli_dmax_int_level_s cn63xxp1; 1395}; 1396typedef union cvmx_sli_dmax_int_level cvmx_sli_dmax_int_level_t; 1397 1398/** 1399 * cvmx_sli_dma#_tim 1400 * 1401 * SLI_DMAx_TIM = SLI DMA Timer 1402 * 1403 * The DMA Timer value. 1404 */ 1405union cvmx_sli_dmax_tim 1406{ 1407 uint64_t u64; 1408 struct cvmx_sli_dmax_tim_s 1409 { 1410#if __BYTE_ORDER == __BIG_ENDIAN 1411 uint64_t reserved_32_63 : 32; 1412 uint64_t tim : 32; /**< The DMA timer value. 1413 The timer will increment when SLI_DMAx_CNT[CNT]!=0 1414 and will clear when SLI_DMAx_CNT[CNT]==0 */ 1415#else 1416 uint64_t tim : 32; 1417 uint64_t reserved_32_63 : 32; 1418#endif 1419 } s; 1420 struct cvmx_sli_dmax_tim_s cn63xx; 1421 struct cvmx_sli_dmax_tim_s cn63xxp1; 1422}; 1423typedef union cvmx_sli_dmax_tim cvmx_sli_dmax_tim_t; 1424 1425/** 1426 * cvmx_sli_int_enb_ciu 1427 * 1428 * SLI_INT_ENB_CIU = SLI's Interrupt Enable CIU Register 1429 * 1430 * Used to enable the various interrupting conditions of SLI 1431 */ 1432union cvmx_sli_int_enb_ciu 1433{ 1434 uint64_t u64; 1435 struct cvmx_sli_int_enb_ciu_s 1436 { 1437#if __BYTE_ORDER == __BIG_ENDIAN 1438 uint64_t reserved_61_63 : 3; 1439 uint64_t ill_pad : 1; /**< Illegal packet csr address. */ 1440 uint64_t reserved_58_59 : 2; 1441 uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */ 1442 uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */ 1443 uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */ 1444 uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */ 1445 uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */ 1446 uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */ 1447 uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */ 1448 uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */ 1449 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */ 1450 uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */ 1451 uint64_t reserved_38_47 : 10; 1452 uint64_t dtime : 2; /**< DMA Timer Interrupts */ 1453 uint64_t dcnt : 2; /**< DMA Count Interrupts */ 1454 uint64_t dmafi : 2; /**< DMA set Forced Interrupts */ 1455 uint64_t reserved_18_31 : 14; 1456 uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an 1457 interrupt on the RSL. 1458 THIS SHOULD NEVER BE SET */ 1459 uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an 1460 interrupt on the RSL. 1461 THIS SHOULD NEVER BE SET */ 1462 uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an 1463 interrupt on the RSL. */ 1464 uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an 1465 interrupt on the RSL. */ 1466 uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an 1467 interrupt on the RSL. */ 1468 uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an 1469 interrupt on the RSL. */ 1470 uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an 1471 interrupt on the RSL. */ 1472 uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an 1473 interrupt on the RSL. */ 1474 uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an 1475 interrupt on the RSL. */ 1476 uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an 1477 interrupt on the RSL. */ 1478 uint64_t reserved_6_7 : 2; 1479 uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an 1480 interrupt on the RSL. */ 1481 uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an 1482 interrupt on the RSL. */ 1483 uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an 1484 interrupt on the RSL. */ 1485 uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an 1486 interrupt on the RSL. */ 1487 uint64_t reserved_1_1 : 1; 1488 uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an 1489 interrupt on the RSL. */ 1490#else 1491 uint64_t rml_to : 1; 1492 uint64_t reserved_1_1 : 1; 1493 uint64_t bar0_to : 1; 1494 uint64_t iob2big : 1; 1495 uint64_t pcnt : 1; 1496 uint64_t ptime : 1; 1497 uint64_t reserved_6_7 : 2; 1498 uint64_t m0_up_b0 : 1; 1499 uint64_t m0_up_wi : 1; 1500 uint64_t m0_un_b0 : 1; 1501 uint64_t m0_un_wi : 1; 1502 uint64_t m1_up_b0 : 1; 1503 uint64_t m1_up_wi : 1; 1504 uint64_t m1_un_b0 : 1; 1505 uint64_t m1_un_wi : 1; 1506 uint64_t mio_int0 : 1; 1507 uint64_t mio_int1 : 1; 1508 uint64_t reserved_18_31 : 14; 1509 uint64_t dmafi : 2; 1510 uint64_t dcnt : 2; 1511 uint64_t dtime : 2; 1512 uint64_t reserved_38_47 : 10; 1513 uint64_t pidbof : 1; 1514 uint64_t psldbof : 1; 1515 uint64_t pout_err : 1; 1516 uint64_t pin_bp : 1; 1517 uint64_t pgl_err : 1; 1518 uint64_t pdi_err : 1; 1519 uint64_t pop_err : 1; 1520 uint64_t pins_err : 1; 1521 uint64_t sprt0_err : 1; 1522 uint64_t sprt1_err : 1; 1523 uint64_t reserved_58_59 : 2; 1524 uint64_t ill_pad : 1; 1525 uint64_t reserved_61_63 : 3; 1526#endif 1527 } s; 1528 struct cvmx_sli_int_enb_ciu_s cn63xx; 1529 struct cvmx_sli_int_enb_ciu_s cn63xxp1; 1530}; 1531typedef union cvmx_sli_int_enb_ciu cvmx_sli_int_enb_ciu_t; 1532 1533/** 1534 * cvmx_sli_int_enb_port# 1535 * 1536 * SLI_INT_ENB_PORTX = SLI's Interrupt Enable Register per mac port 1537 * 1538 * Used to allow the generation of interrupts (MSI/INTA) to the PORT X 1539 * 1540 * Notes: 1541 * This CSR is not used when the corresponding MAC is sRIO. 1542 * 1543 */ 1544union cvmx_sli_int_enb_portx 1545{ 1546 uint64_t u64; 1547 struct cvmx_sli_int_enb_portx_s 1548 { 1549#if __BYTE_ORDER == __BIG_ENDIAN 1550 uint64_t reserved_61_63 : 3; 1551 uint64_t ill_pad : 1; /**< Illegal packet csr address. */ 1552 uint64_t reserved_58_59 : 2; 1553 uint64_t sprt1_err : 1; /**< Error Response received on SLI port 1. */ 1554 uint64_t sprt0_err : 1; /**< Error Response received on SLI port 0. */ 1555 uint64_t pins_err : 1; /**< Read Error during packet instruction fetch. */ 1556 uint64_t pop_err : 1; /**< Read Error during packet scatter pointer fetch. */ 1557 uint64_t pdi_err : 1; /**< Read Error during packet data fetch. */ 1558 uint64_t pgl_err : 1; /**< Read Error during gather list fetch. */ 1559 uint64_t pin_bp : 1; /**< Packet Input Count exceeded WMARK. */ 1560 uint64_t pout_err : 1; /**< Packet Out Interrupt, Error From PKO. */ 1561 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell Count Overflow. */ 1562 uint64_t pidbof : 1; /**< Packet Instruction Doorbell Count Overflow. */ 1563 uint64_t reserved_38_47 : 10; 1564 uint64_t dtime : 2; /**< DMA Timer Interrupts */ 1565 uint64_t dcnt : 2; /**< DMA Count Interrupts */ 1566 uint64_t dmafi : 2; /**< DMA set Forced Interrupts */ 1567 uint64_t reserved_20_31 : 12; 1568 uint64_t mac1_int : 1; /**< Enables SLI_INT_SUM[19] to generate an 1569 interrupt to the PCIE-Port1 for MSI/inta. 1570 The valuse of this bit has NO effect on PCIE Port0. 1571 SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */ 1572 uint64_t mac0_int : 1; /**< Enables SLI_INT_SUM[18] to generate an 1573 interrupt to the PCIE-Port0 for MSI/inta. 1574 The valus of this bit has NO effect on PCIE Port1. 1575 SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */ 1576 uint64_t mio_int1 : 1; /**< Enables SLI_INT_SUM[17] to generate an 1577 interrupt to the PCIE core for MSI/inta. 1578 SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */ 1579 uint64_t mio_int0 : 1; /**< Enables SLI_INT_SUM[16] to generate an 1580 interrupt to the PCIE core for MSI/inta. 1581 SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */ 1582 uint64_t m1_un_wi : 1; /**< Enables SLI_INT_SUM[15] to generate an 1583 interrupt to the PCIE core for MSI/inta. */ 1584 uint64_t m1_un_b0 : 1; /**< Enables SLI_INT_SUM[14] to generate an 1585 interrupt to the PCIE core for MSI/inta. */ 1586 uint64_t m1_up_wi : 1; /**< Enables SLI_INT_SUM[13] to generate an 1587 interrupt to the PCIE core for MSI/inta. */ 1588 uint64_t m1_up_b0 : 1; /**< Enables SLI_INT_SUM[12] to generate an 1589 interrupt to the PCIE core for MSI/inta. */ 1590 uint64_t m0_un_wi : 1; /**< Enables SLI_INT_SUM[11] to generate an 1591 interrupt to the PCIE core for MSI/inta. */ 1592 uint64_t m0_un_b0 : 1; /**< Enables SLI_INT_SUM[10] to generate an 1593 interrupt to the PCIE core for MSI/inta. */ 1594 uint64_t m0_up_wi : 1; /**< Enables SLI_INT_SUM[9] to generate an 1595 interrupt to the PCIE core for MSI/inta. */ 1596 uint64_t m0_up_b0 : 1; /**< Enables SLI_INT_SUM[8] to generate an 1597 interrupt to the PCIE core for MSI/inta. */ 1598 uint64_t reserved_6_7 : 2; 1599 uint64_t ptime : 1; /**< Enables SLI_INT_SUM[5] to generate an 1600 interrupt to the PCIE core for MSI/inta. */ 1601 uint64_t pcnt : 1; /**< Enables SLI_INT_SUM[4] to generate an 1602 interrupt to the PCIE core for MSI/inta. */ 1603 uint64_t iob2big : 1; /**< Enables SLI_INT_SUM[3] to generate an 1604 interrupt to the PCIE core for MSI/inta. */ 1605 uint64_t bar0_to : 1; /**< Enables SLI_INT_SUM[2] to generate an 1606 interrupt to the PCIE core for MSI/inta. */ 1607 uint64_t reserved_1_1 : 1; 1608 uint64_t rml_to : 1; /**< Enables SLI_INT_SUM[0] to generate an 1609 interrupt to the PCIE core for MSI/inta. */ 1610#else 1611 uint64_t rml_to : 1; 1612 uint64_t reserved_1_1 : 1; 1613 uint64_t bar0_to : 1; 1614 uint64_t iob2big : 1; 1615 uint64_t pcnt : 1; 1616 uint64_t ptime : 1; 1617 uint64_t reserved_6_7 : 2; 1618 uint64_t m0_up_b0 : 1; 1619 uint64_t m0_up_wi : 1; 1620 uint64_t m0_un_b0 : 1; 1621 uint64_t m0_un_wi : 1; 1622 uint64_t m1_up_b0 : 1; 1623 uint64_t m1_up_wi : 1; 1624 uint64_t m1_un_b0 : 1; 1625 uint64_t m1_un_wi : 1; 1626 uint64_t mio_int0 : 1; 1627 uint64_t mio_int1 : 1; 1628 uint64_t mac0_int : 1; 1629 uint64_t mac1_int : 1; 1630 uint64_t reserved_20_31 : 12; 1631 uint64_t dmafi : 2; 1632 uint64_t dcnt : 2; 1633 uint64_t dtime : 2; 1634 uint64_t reserved_38_47 : 10; 1635 uint64_t pidbof : 1; 1636 uint64_t psldbof : 1; 1637 uint64_t pout_err : 1; 1638 uint64_t pin_bp : 1; 1639 uint64_t pgl_err : 1; 1640 uint64_t pdi_err : 1; 1641 uint64_t pop_err : 1; 1642 uint64_t pins_err : 1; 1643 uint64_t sprt0_err : 1; 1644 uint64_t sprt1_err : 1; 1645 uint64_t reserved_58_59 : 2; 1646 uint64_t ill_pad : 1; 1647 uint64_t reserved_61_63 : 3; 1648#endif 1649 } s; 1650 struct cvmx_sli_int_enb_portx_s cn63xx; 1651 struct cvmx_sli_int_enb_portx_s cn63xxp1; 1652}; 1653typedef union cvmx_sli_int_enb_portx cvmx_sli_int_enb_portx_t; 1654 1655/** 1656 * cvmx_sli_int_sum 1657 * 1658 * SLI_INT_SUM = SLI Interrupt Summary Register 1659 * 1660 * Set when an interrupt condition occurs, write '1' to clear. 1661 */ 1662union cvmx_sli_int_sum 1663{ 1664 uint64_t u64; 1665 struct cvmx_sli_int_sum_s 1666 { 1667#if __BYTE_ORDER == __BIG_ENDIAN 1668 uint64_t reserved_61_63 : 3; 1669 uint64_t ill_pad : 1; /**< Set when a BAR0 address R/W falls into theaddress 1670 range of the Packet-CSR, but for an unused 1671 address. */ 1672 uint64_t reserved_58_59 : 2; 1673 uint64_t sprt1_err : 1; /**< When an error response received on SLI port 1 1674 this bit is set. */ 1675 uint64_t sprt0_err : 1; /**< When an error response received on SLI port 0 1676 this bit is set. */ 1677 uint64_t pins_err : 1; /**< When a read error occurs on a packet instruction 1678 this bit is set. */ 1679 uint64_t pop_err : 1; /**< When a read error occurs on a packet scatter 1680 pointer pair this bit is set. */ 1681 uint64_t pdi_err : 1; /**< When a read error occurs on a packet data read 1682 this bit is set. */ 1683 uint64_t pgl_err : 1; /**< When a read error occurs on a packet gather list 1684 read this bit is set. */ 1685 uint64_t pin_bp : 1; /**< Packet input count has exceeded the WMARK. 1686 See SLI_PKT_IN_BP */ 1687 uint64_t pout_err : 1; /**< Set when PKO sends packet data with the error bit 1688 set. */ 1689 uint64_t psldbof : 1; /**< Packet Scatterlist Doorbell count overflowed. Which 1690 doorbell can be found in DPI_PINT_INFO[PSLDBOF] */ 1691 uint64_t pidbof : 1; /**< Packet Instruction Doorbell count overflowed. Which 1692 doorbell can be found in DPI_PINT_INFO[PIDBOF] */ 1693 uint64_t reserved_38_47 : 10; 1694 uint64_t dtime : 2; /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the 1695 SLI_DMAx_TIM[TIM] timer increments every SLI 1696 clock. 1697 DTIME[x] is set whenever SLI_DMAx_TIM[TIM] > 1698 SLI_DMAx_INT_LEVEL[TIME]. 1699 DTIME[x] is normally cleared by clearing 1700 SLI_DMAx_CNT[CNT] (which also clears 1701 SLI_DMAx_TIM[TIM]). */ 1702 uint64_t dcnt : 2; /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] > 1703 SLI_DMAx_INT_LEVEL[CNT]. 1704 DCNT[x] is normally cleared by decreasing 1705 SLI_DMAx_CNT[CNT]. */ 1706 uint64_t dmafi : 2; /**< DMA set Forced Interrupts. */ 1707 uint64_t reserved_20_31 : 12; 1708 uint64_t mac1_int : 1; /**< Interrupt from MAC1. 1709 See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */ 1710 uint64_t mac0_int : 1; /**< Interrupt from MAC0. 1711 See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */ 1712 uint64_t mio_int1 : 1; /**< Interrupt from MIO for PORT 1. 1713 See CIU_INT33_SUM0, CIU_INT_SUM1 1714 (enabled by CIU_INT33_EN0, CIU_INT33_EN1) */ 1715 uint64_t mio_int0 : 1; /**< Interrupt from MIO for PORT 0. 1716 See CIU_INT32_SUM0, CIU_INT_SUM1 1717 (enabled by CIU_INT32_EN0, CIU_INT32_EN1) */ 1718 uint64_t m1_un_wi : 1; /**< Received Unsupported N-TLP for Window Register 1719 from MAC 1. This occurs when the window registers 1720 are disabeld and a window register access occurs. */ 1721 uint64_t m1_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 1. 1722 This occurs when the BAR 0 address space is 1723 disabeled. */ 1724 uint64_t m1_up_wi : 1; /**< Received Unsupported P-TLP for Window Register 1725 from MAC 1. This occurs when the window registers 1726 are disabeld and a window register access occurs. */ 1727 uint64_t m1_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 1. 1728 This occurs when the BAR 0 address space is 1729 disabeled. */ 1730 uint64_t m0_un_wi : 1; /**< Received Unsupported N-TLP for Window Register 1731 from MAC 0. This occurs when the window registers 1732 are disabeld and a window register access occurs. */ 1733 uint64_t m0_un_b0 : 1; /**< Received Unsupported N-TLP for Bar0 from MAC 0. 1734 This occurs when the BAR 0 address space is 1735 disabeled. */ 1736 uint64_t m0_up_wi : 1; /**< Received Unsupported P-TLP for Window Register 1737 from MAC 0. This occurs when the window registers 1738 are disabeld and a window register access occurs. */ 1739 uint64_t m0_up_b0 : 1; /**< Received Unsupported P-TLP for Bar0 from MAC 0. 1740 This occurs when the BAR 0 address space is 1741 disabeled. */ 1742 uint64_t reserved_6_7 : 2; 1743 uint64_t ptime : 1; /**< Packet Timer has an interrupt. Which rings can 1744 be found in SLI_PKT_TIME_INT. */ 1745 uint64_t pcnt : 1; /**< Packet Counter has an interrupt. Which rings can 1746 be found in SLI_PKT_CNT_INT. */ 1747 uint64_t iob2big : 1; /**< A requested IOBDMA is to large. */ 1748 uint64_t bar0_to : 1; /**< BAR0 R/W to a NCB device did not receive 1749 read-data/commit in 0xffff core clocks. */ 1750 uint64_t reserved_1_1 : 1; 1751 uint64_t rml_to : 1; /**< A read or write transfer did not complete 1752 within 0xffff core clocks. */ 1753#else 1754 uint64_t rml_to : 1; 1755 uint64_t reserved_1_1 : 1; 1756 uint64_t bar0_to : 1; 1757 uint64_t iob2big : 1; 1758 uint64_t pcnt : 1; 1759 uint64_t ptime : 1; 1760 uint64_t reserved_6_7 : 2; 1761 uint64_t m0_up_b0 : 1; 1762 uint64_t m0_up_wi : 1; 1763 uint64_t m0_un_b0 : 1; 1764 uint64_t m0_un_wi : 1; 1765 uint64_t m1_up_b0 : 1; 1766 uint64_t m1_up_wi : 1; 1767 uint64_t m1_un_b0 : 1; 1768 uint64_t m1_un_wi : 1; 1769 uint64_t mio_int0 : 1; 1770 uint64_t mio_int1 : 1; 1771 uint64_t mac0_int : 1; 1772 uint64_t mac1_int : 1; 1773 uint64_t reserved_20_31 : 12; 1774 uint64_t dmafi : 2; 1775 uint64_t dcnt : 2; 1776 uint64_t dtime : 2; 1777 uint64_t reserved_38_47 : 10; 1778 uint64_t pidbof : 1; 1779 uint64_t psldbof : 1; 1780 uint64_t pout_err : 1; 1781 uint64_t pin_bp : 1; 1782 uint64_t pgl_err : 1; 1783 uint64_t pdi_err : 1; 1784 uint64_t pop_err : 1; 1785 uint64_t pins_err : 1; 1786 uint64_t sprt0_err : 1; 1787 uint64_t sprt1_err : 1; 1788 uint64_t reserved_58_59 : 2; 1789 uint64_t ill_pad : 1; 1790 uint64_t reserved_61_63 : 3; 1791#endif 1792 } s; 1793 struct cvmx_sli_int_sum_s cn63xx; 1794 struct cvmx_sli_int_sum_s cn63xxp1; 1795}; 1796typedef union cvmx_sli_int_sum cvmx_sli_int_sum_t; 1797 1798/** 1799 * cvmx_sli_last_win_rdata0 1800 * 1801 * SLI_LAST_WIN_RDATA0 = SLI Last Window Read Data Port0 1802 * 1803 * The data from the last initiated window read. 1804 */ 1805union cvmx_sli_last_win_rdata0 1806{ 1807 uint64_t u64; 1808 struct cvmx_sli_last_win_rdata0_s 1809 { 1810#if __BYTE_ORDER == __BIG_ENDIAN 1811 uint64_t data : 64; /**< Last window read data. */ 1812#else 1813 uint64_t data : 64; 1814#endif 1815 } s; 1816 struct cvmx_sli_last_win_rdata0_s cn63xx; 1817 struct cvmx_sli_last_win_rdata0_s cn63xxp1; 1818}; 1819typedef union cvmx_sli_last_win_rdata0 cvmx_sli_last_win_rdata0_t; 1820 1821/** 1822 * cvmx_sli_last_win_rdata1 1823 * 1824 * SLI_LAST_WIN_RDATA1 = SLI Last Window Read Data Port1 1825 * 1826 * The data from the last initiated window read. 1827 */ 1828union cvmx_sli_last_win_rdata1 1829{ 1830 uint64_t u64; 1831 struct cvmx_sli_last_win_rdata1_s 1832 { 1833#if __BYTE_ORDER == __BIG_ENDIAN 1834 uint64_t data : 64; /**< Last window read data. */ 1835#else 1836 uint64_t data : 64; 1837#endif 1838 } s; 1839 struct cvmx_sli_last_win_rdata1_s cn63xx; 1840 struct cvmx_sli_last_win_rdata1_s cn63xxp1; 1841}; 1842typedef union cvmx_sli_last_win_rdata1 cvmx_sli_last_win_rdata1_t; 1843 1844/** 1845 * cvmx_sli_mac_credit_cnt 1846 * 1847 * SLI_MAC_CREDIT_CNT = SLI MAC Credit Count 1848 * 1849 * Contains the number of credits for the MAC port FIFOs used by the SLI. This value needs to be set BEFORE S2M traffic 1850 * flow starts. A write to this register will cause the credit counts in the SLI for the MAC ports to be reset to the value 1851 * in this register. 1852 */ 1853union cvmx_sli_mac_credit_cnt 1854{ 1855 uint64_t u64; 1856 struct cvmx_sli_mac_credit_cnt_s 1857 { 1858#if __BYTE_ORDER == __BIG_ENDIAN 1859 uint64_t reserved_54_63 : 10; 1860 uint64_t p1_c_d : 1; /**< When set does not allow writing of P1_CCNT. */ 1861 uint64_t p1_n_d : 1; /**< When set does not allow writing of P1_NCNT. */ 1862 uint64_t p1_p_d : 1; /**< When set does not allow writing of P1_PCNT. */ 1863 uint64_t p0_c_d : 1; /**< When set does not allow writing of P0_CCNT. */ 1864 uint64_t p0_n_d : 1; /**< When set does not allow writing of P0_NCNT. */ 1865 uint64_t p0_p_d : 1; /**< When set does not allow writing of P0_PCNT. */ 1866 uint64_t p1_ccnt : 8; /**< Port1 C-TLP FIFO Credits. 1867 Legal values are 0x25 to 0x80. */ 1868 uint64_t p1_ncnt : 8; /**< Port1 N-TLP FIFO Credits. 1869 Legal values are 0x5 to 0x10. */ 1870 uint64_t p1_pcnt : 8; /**< Port1 P-TLP FIFO Credits. 1871 Legal values are 0x25 to 0x80. */ 1872 uint64_t p0_ccnt : 8; /**< Port0 C-TLP FIFO Credits. 1873 Legal values are 0x25 to 0x80. */ 1874 uint64_t p0_ncnt : 8; /**< Port0 N-TLP FIFO Credits. 1875 Legal values are 0x5 to 0x10. */ 1876 uint64_t p0_pcnt : 8; /**< Port0 P-TLP FIFO Credits. 1877 Legal values are 0x25 to 0x80. */ 1878#else 1879 uint64_t p0_pcnt : 8; 1880 uint64_t p0_ncnt : 8; 1881 uint64_t p0_ccnt : 8; 1882 uint64_t p1_pcnt : 8; 1883 uint64_t p1_ncnt : 8; 1884 uint64_t p1_ccnt : 8; 1885 uint64_t p0_p_d : 1; 1886 uint64_t p0_n_d : 1; 1887 uint64_t p0_c_d : 1; 1888 uint64_t p1_p_d : 1; 1889 uint64_t p1_n_d : 1; 1890 uint64_t p1_c_d : 1; 1891 uint64_t reserved_54_63 : 10; 1892#endif 1893 } s; 1894 struct cvmx_sli_mac_credit_cnt_s cn63xx; 1895 struct cvmx_sli_mac_credit_cnt_cn63xxp1 1896 { 1897#if __BYTE_ORDER == __BIG_ENDIAN 1898 uint64_t reserved_48_63 : 16; 1899 uint64_t p1_ccnt : 8; /**< Port1 C-TLP FIFO Credits. 1900 Legal values are 0x25 to 0x80. */ 1901 uint64_t p1_ncnt : 8; /**< Port1 N-TLP FIFO Credits. 1902 Legal values are 0x5 to 0x10. */ 1903 uint64_t p1_pcnt : 8; /**< Port1 P-TLP FIFO Credits. 1904 Legal values are 0x25 to 0x80. */ 1905 uint64_t p0_ccnt : 8; /**< Port0 C-TLP FIFO Credits. 1906 Legal values are 0x25 to 0x80. */ 1907 uint64_t p0_ncnt : 8; /**< Port0 N-TLP FIFO Credits. 1908 Legal values are 0x5 to 0x10. */ 1909 uint64_t p0_pcnt : 8; /**< Port0 P-TLP FIFO Credits. 1910 Legal values are 0x25 to 0x80. */ 1911#else 1912 uint64_t p0_pcnt : 8; 1913 uint64_t p0_ncnt : 8; 1914 uint64_t p0_ccnt : 8; 1915 uint64_t p1_pcnt : 8; 1916 uint64_t p1_ncnt : 8; 1917 uint64_t p1_ccnt : 8; 1918 uint64_t reserved_48_63 : 16; 1919#endif 1920 } cn63xxp1; 1921}; 1922typedef union cvmx_sli_mac_credit_cnt cvmx_sli_mac_credit_cnt_t; 1923 1924/** 1925 * cvmx_sli_mac_number 1926 * 1927 * 0x13DA0 - 0x13DF0 reserved for ports 2 - 7 1928 * 1929 * SLI_MAC_NUMBER = SLI MAC Number 1930 * 1931 * When read from a MAC port it returns the MAC's port number. 1932 * register. 1933 */ 1934union cvmx_sli_mac_number 1935{ 1936 uint64_t u64; 1937 struct cvmx_sli_mac_number_s 1938 { 1939#if __BYTE_ORDER == __BIG_ENDIAN 1940 uint64_t reserved_8_63 : 56; 1941 uint64_t num : 8; /**< The mac number. */ 1942#else 1943 uint64_t num : 8; 1944 uint64_t reserved_8_63 : 56; 1945#endif 1946 } s; 1947 struct cvmx_sli_mac_number_s cn63xx; 1948}; 1949typedef union cvmx_sli_mac_number cvmx_sli_mac_number_t; 1950 1951/** 1952 * cvmx_sli_mem_access_ctl 1953 * 1954 * SLI_MEM_ACCESS_CTL = SLI's Memory Access Control 1955 * 1956 * Contains control for access to the MAC address space. 1957 */ 1958union cvmx_sli_mem_access_ctl 1959{ 1960 uint64_t u64; 1961 struct cvmx_sli_mem_access_ctl_s 1962 { 1963#if __BYTE_ORDER == __BIG_ENDIAN 1964 uint64_t reserved_14_63 : 50; 1965 uint64_t max_word : 4; /**< The maximum number of words to merge into a single 1966 write operation from the PPs to the MAC. Legal 1967 values are 1 to 16, where a '0' is treated as 16. */ 1968 uint64_t timer : 10; /**< When the SLI starts a PP to MAC write it waits 1969 no longer than the value of TIMER in eclks to 1970 merge additional writes from the PPs into 1 1971 large write. The values for this field is 1 to 1972 1024 where a value of '0' is treated as 1024. */ 1973#else 1974 uint64_t timer : 10; 1975 uint64_t max_word : 4; 1976 uint64_t reserved_14_63 : 50; 1977#endif 1978 } s; 1979 struct cvmx_sli_mem_access_ctl_s cn63xx; 1980 struct cvmx_sli_mem_access_ctl_s cn63xxp1; 1981}; 1982typedef union cvmx_sli_mem_access_ctl cvmx_sli_mem_access_ctl_t; 1983 1984/** 1985 * cvmx_sli_mem_access_subid# 1986 * 1987 * // * 1988 * // * 8070 - 80C0 saved for ports 2 through 7 1989 * // * 1990 * // * 1991 * // * 0x80d0 free 1992 * // * 1993 * 1994 * SLI_MEM_ACCESS_SUBIDX = SLI Memory Access SubidX Register 1995 * 1996 * Contains address index and control bits for access to memory from Core PPs. 1997 */ 1998union cvmx_sli_mem_access_subidx 1999{ 2000 uint64_t u64; 2001 struct cvmx_sli_mem_access_subidx_s 2002 { 2003#if __BYTE_ORDER == __BIG_ENDIAN 2004 uint64_t reserved_43_63 : 21; 2005 uint64_t zero : 1; /**< Causes all byte reads to be zero length reads. 2006 Returns to the EXEC a zero for all read data. 2007 This must be zero for sRIO ports. */ 2008 uint64_t port : 3; /**< Physical MAC Port that reads/writes to 2009 this subid are sent to. Must be <= 1, as there are 2010 only two ports present. */ 2011 uint64_t nmerge : 1; /**< When set, no merging is allowed in this window. */ 2012 uint64_t esr : 2; /**< ES<1:0> for reads to this subid. 2013 ES<1:0> is the endian-swap attribute for these MAC 2014 memory space reads. */ 2015 uint64_t esw : 2; /**< ES<1:0> for writes to this subid. 2016 ES<1:0> is the endian-swap attribute for these MAC 2017 memory space writes. */ 2018 uint64_t wtype : 2; /**< ADDRTYPE<1:0> for writes to this subid 2019 For PCIe: 2020 - ADDRTYPE<0> is the relaxed-order attribute 2021 - ADDRTYPE<1> is the no-snoop attribute 2022 For sRIO: 2023 - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE* 2024 entry */ 2025 uint64_t rtype : 2; /**< ADDRTYPE<1:0> for reads to this subid 2026 For PCIe: 2027 - ADDRTYPE<0> is the relaxed-order attribute 2028 - ADDRTYPE<1> is the no-snoop attribute 2029 For sRIO: 2030 - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE* 2031 entry */ 2032 uint64_t ba : 30; /**< Address Bits <63:34> for reads/writes that use 2033 this subid. */ 2034#else 2035 uint64_t ba : 30; 2036 uint64_t rtype : 2; 2037 uint64_t wtype : 2; 2038 uint64_t esw : 2; 2039 uint64_t esr : 2; 2040 uint64_t nmerge : 1; 2041 uint64_t port : 3; 2042 uint64_t zero : 1; 2043 uint64_t reserved_43_63 : 21; 2044#endif 2045 } s; 2046 struct cvmx_sli_mem_access_subidx_s cn63xx; 2047 struct cvmx_sli_mem_access_subidx_s cn63xxp1; 2048}; 2049typedef union cvmx_sli_mem_access_subidx cvmx_sli_mem_access_subidx_t; 2050 2051/** 2052 * cvmx_sli_msi_enb0 2053 * 2054 * SLI_MSI_ENB0 = SLI MSI Enable0 2055 * 2056 * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV0. 2057 */ 2058union cvmx_sli_msi_enb0 2059{ 2060 uint64_t u64; 2061 struct cvmx_sli_msi_enb0_s 2062 { 2063#if __BYTE_ORDER == __BIG_ENDIAN 2064 uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV0. */ 2065#else 2066 uint64_t enb : 64; 2067#endif 2068 } s; 2069 struct cvmx_sli_msi_enb0_s cn63xx; 2070 struct cvmx_sli_msi_enb0_s cn63xxp1; 2071}; 2072typedef union cvmx_sli_msi_enb0 cvmx_sli_msi_enb0_t; 2073 2074/** 2075 * cvmx_sli_msi_enb1 2076 * 2077 * SLI_MSI_ENB1 = SLI MSI Enable1 2078 * 2079 * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV1. 2080 */ 2081union cvmx_sli_msi_enb1 2082{ 2083 uint64_t u64; 2084 struct cvmx_sli_msi_enb1_s 2085 { 2086#if __BYTE_ORDER == __BIG_ENDIAN 2087 uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV1. */ 2088#else 2089 uint64_t enb : 64; 2090#endif 2091 } s; 2092 struct cvmx_sli_msi_enb1_s cn63xx; 2093 struct cvmx_sli_msi_enb1_s cn63xxp1; 2094}; 2095typedef union cvmx_sli_msi_enb1 cvmx_sli_msi_enb1_t; 2096 2097/** 2098 * cvmx_sli_msi_enb2 2099 * 2100 * SLI_MSI_ENB2 = SLI MSI Enable2 2101 * 2102 * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV2. 2103 */ 2104union cvmx_sli_msi_enb2 2105{ 2106 uint64_t u64; 2107 struct cvmx_sli_msi_enb2_s 2108 { 2109#if __BYTE_ORDER == __BIG_ENDIAN 2110 uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV2. */ 2111#else 2112 uint64_t enb : 64; 2113#endif 2114 } s; 2115 struct cvmx_sli_msi_enb2_s cn63xx; 2116 struct cvmx_sli_msi_enb2_s cn63xxp1; 2117}; 2118typedef union cvmx_sli_msi_enb2 cvmx_sli_msi_enb2_t; 2119 2120/** 2121 * cvmx_sli_msi_enb3 2122 * 2123 * SLI_MSI_ENB3 = SLI MSI Enable3 2124 * 2125 * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV3. 2126 */ 2127union cvmx_sli_msi_enb3 2128{ 2129 uint64_t u64; 2130 struct cvmx_sli_msi_enb3_s 2131 { 2132#if __BYTE_ORDER == __BIG_ENDIAN 2133 uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV3. */ 2134#else 2135 uint64_t enb : 64; 2136#endif 2137 } s; 2138 struct cvmx_sli_msi_enb3_s cn63xx; 2139 struct cvmx_sli_msi_enb3_s cn63xxp1; 2140}; 2141typedef union cvmx_sli_msi_enb3 cvmx_sli_msi_enb3_t; 2142 2143/** 2144 * cvmx_sli_msi_rcv0 2145 * 2146 * SLI_MSI_RCV0 = SLI MSI Receive0 2147 * 2148 * Contains bits [63:0] of the 256 bits of MSI interrupts. 2149 */ 2150union cvmx_sli_msi_rcv0 2151{ 2152 uint64_t u64; 2153 struct cvmx_sli_msi_rcv0_s 2154 { 2155#if __BYTE_ORDER == __BIG_ENDIAN 2156 uint64_t intr : 64; /**< Bits 63-0 of the 256 bits of MSI interrupt. */ 2157#else 2158 uint64_t intr : 64; 2159#endif 2160 } s; 2161 struct cvmx_sli_msi_rcv0_s cn63xx; 2162 struct cvmx_sli_msi_rcv0_s cn63xxp1; 2163}; 2164typedef union cvmx_sli_msi_rcv0 cvmx_sli_msi_rcv0_t; 2165 2166/** 2167 * cvmx_sli_msi_rcv1 2168 * 2169 * SLI_MSI_RCV1 = SLI MSI Receive1 2170 * 2171 * Contains bits [127:64] of the 256 bits of MSI interrupts. 2172 */ 2173union cvmx_sli_msi_rcv1 2174{ 2175 uint64_t u64; 2176 struct cvmx_sli_msi_rcv1_s 2177 { 2178#if __BYTE_ORDER == __BIG_ENDIAN 2179 uint64_t intr : 64; /**< Bits 127-64 of the 256 bits of MSI interrupt. */ 2180#else 2181 uint64_t intr : 64; 2182#endif 2183 } s; 2184 struct cvmx_sli_msi_rcv1_s cn63xx; 2185 struct cvmx_sli_msi_rcv1_s cn63xxp1; 2186}; 2187typedef union cvmx_sli_msi_rcv1 cvmx_sli_msi_rcv1_t; 2188 2189/** 2190 * cvmx_sli_msi_rcv2 2191 * 2192 * SLI_MSI_RCV2 = SLI MSI Receive2 2193 * 2194 * Contains bits [191:128] of the 256 bits of MSI interrupts. 2195 */ 2196union cvmx_sli_msi_rcv2 2197{ 2198 uint64_t u64; 2199 struct cvmx_sli_msi_rcv2_s 2200 { 2201#if __BYTE_ORDER == __BIG_ENDIAN 2202 uint64_t intr : 64; /**< Bits 191-128 of the 256 bits of MSI interrupt. */ 2203#else 2204 uint64_t intr : 64; 2205#endif 2206 } s; 2207 struct cvmx_sli_msi_rcv2_s cn63xx; 2208 struct cvmx_sli_msi_rcv2_s cn63xxp1; 2209}; 2210typedef union cvmx_sli_msi_rcv2 cvmx_sli_msi_rcv2_t; 2211 2212/** 2213 * cvmx_sli_msi_rcv3 2214 * 2215 * SLI_MSI_RCV3 = SLI MSI Receive3 2216 * 2217 * Contains bits [255:192] of the 256 bits of MSI interrupts. 2218 */ 2219union cvmx_sli_msi_rcv3 2220{ 2221 uint64_t u64; 2222 struct cvmx_sli_msi_rcv3_s 2223 { 2224#if __BYTE_ORDER == __BIG_ENDIAN 2225 uint64_t intr : 64; /**< Bits 255-192 of the 256 bits of MSI interrupt. */ 2226#else 2227 uint64_t intr : 64; 2228#endif 2229 } s; 2230 struct cvmx_sli_msi_rcv3_s cn63xx; 2231 struct cvmx_sli_msi_rcv3_s cn63xxp1; 2232}; 2233typedef union cvmx_sli_msi_rcv3 cvmx_sli_msi_rcv3_t; 2234 2235/** 2236 * cvmx_sli_msi_rd_map 2237 * 2238 * SLI_MSI_RD_MAP = SLI MSI Read MAP 2239 * 2240 * Used to read the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV registers. 2241 */ 2242union cvmx_sli_msi_rd_map 2243{ 2244 uint64_t u64; 2245 struct cvmx_sli_msi_rd_map_s 2246 { 2247#if __BYTE_ORDER == __BIG_ENDIAN 2248 uint64_t reserved_16_63 : 48; 2249 uint64_t rd_int : 8; /**< The value of the map at the location PREVIOUSLY 2250 written to the MSI_INT field of this register. */ 2251 uint64_t msi_int : 8; /**< Selects the value that would be received when the 2252 SLI_PCIE_MSI_RCV register is written. */ 2253#else 2254 uint64_t msi_int : 8; 2255 uint64_t rd_int : 8; 2256 uint64_t reserved_16_63 : 48; 2257#endif 2258 } s; 2259 struct cvmx_sli_msi_rd_map_s cn63xx; 2260 struct cvmx_sli_msi_rd_map_s cn63xxp1; 2261}; 2262typedef union cvmx_sli_msi_rd_map cvmx_sli_msi_rd_map_t; 2263 2264/** 2265 * cvmx_sli_msi_w1c_enb0 2266 * 2267 * SLI_MSI_W1C_ENB0 = SLI MSI Write 1 To Clear Enable0 2268 * 2269 * Used to clear bits in SLI_MSI_ENB0. 2270 */ 2271union cvmx_sli_msi_w1c_enb0 2272{ 2273 uint64_t u64; 2274 struct cvmx_sli_msi_w1c_enb0_s 2275 { 2276#if __BYTE_ORDER == __BIG_ENDIAN 2277 uint64_t clr : 64; /**< A write of '1' to a vector will clear the 2278 cooresponding bit in SLI_MSI_ENB0. 2279 A read to this address will return 0. */ 2280#else 2281 uint64_t clr : 64; 2282#endif 2283 } s; 2284 struct cvmx_sli_msi_w1c_enb0_s cn63xx; 2285 struct cvmx_sli_msi_w1c_enb0_s cn63xxp1; 2286}; 2287typedef union cvmx_sli_msi_w1c_enb0 cvmx_sli_msi_w1c_enb0_t; 2288 2289/** 2290 * cvmx_sli_msi_w1c_enb1 2291 * 2292 * SLI_MSI_W1C_ENB1 = SLI MSI Write 1 To Clear Enable1 2293 * 2294 * Used to clear bits in SLI_MSI_ENB1. 2295 */ 2296union cvmx_sli_msi_w1c_enb1 2297{ 2298 uint64_t u64; 2299 struct cvmx_sli_msi_w1c_enb1_s 2300 { 2301#if __BYTE_ORDER == __BIG_ENDIAN 2302 uint64_t clr : 64; /**< A write of '1' to a vector will clear the 2303 cooresponding bit in SLI_MSI_ENB1. 2304 A read to this address will return 0. */ 2305#else 2306 uint64_t clr : 64; 2307#endif 2308 } s; 2309 struct cvmx_sli_msi_w1c_enb1_s cn63xx; 2310 struct cvmx_sli_msi_w1c_enb1_s cn63xxp1; 2311}; 2312typedef union cvmx_sli_msi_w1c_enb1 cvmx_sli_msi_w1c_enb1_t; 2313 2314/** 2315 * cvmx_sli_msi_w1c_enb2 2316 * 2317 * SLI_MSI_W1C_ENB2 = SLI MSI Write 1 To Clear Enable2 2318 * 2319 * Used to clear bits in SLI_MSI_ENB2. 2320 */ 2321union cvmx_sli_msi_w1c_enb2 2322{ 2323 uint64_t u64; 2324 struct cvmx_sli_msi_w1c_enb2_s 2325 { 2326#if __BYTE_ORDER == __BIG_ENDIAN 2327 uint64_t clr : 64; /**< A write of '1' to a vector will clear the 2328 cooresponding bit in SLI_MSI_ENB2. 2329 A read to this address will return 0. */ 2330#else 2331 uint64_t clr : 64; 2332#endif 2333 } s; 2334 struct cvmx_sli_msi_w1c_enb2_s cn63xx; 2335 struct cvmx_sli_msi_w1c_enb2_s cn63xxp1; 2336}; 2337typedef union cvmx_sli_msi_w1c_enb2 cvmx_sli_msi_w1c_enb2_t; 2338 2339/** 2340 * cvmx_sli_msi_w1c_enb3 2341 * 2342 * SLI_MSI_W1C_ENB3 = SLI MSI Write 1 To Clear Enable3 2343 * 2344 * Used to clear bits in SLI_MSI_ENB3. 2345 */ 2346union cvmx_sli_msi_w1c_enb3 2347{ 2348 uint64_t u64; 2349 struct cvmx_sli_msi_w1c_enb3_s 2350 { 2351#if __BYTE_ORDER == __BIG_ENDIAN 2352 uint64_t clr : 64; /**< A write of '1' to a vector will clear the 2353 cooresponding bit in SLI_MSI_ENB3. 2354 A read to this address will return 0. */ 2355#else 2356 uint64_t clr : 64; 2357#endif 2358 } s; 2359 struct cvmx_sli_msi_w1c_enb3_s cn63xx; 2360 struct cvmx_sli_msi_w1c_enb3_s cn63xxp1; 2361}; 2362typedef union cvmx_sli_msi_w1c_enb3 cvmx_sli_msi_w1c_enb3_t; 2363 2364/** 2365 * cvmx_sli_msi_w1s_enb0 2366 * 2367 * SLI_MSI_W1S_ENB0 = SLI MSI Write 1 To Set Enable0 2368 * 2369 * Used to set bits in SLI_MSI_ENB0. 2370 */ 2371union cvmx_sli_msi_w1s_enb0 2372{ 2373 uint64_t u64; 2374 struct cvmx_sli_msi_w1s_enb0_s 2375 { 2376#if __BYTE_ORDER == __BIG_ENDIAN 2377 uint64_t set : 64; /**< A write of '1' to a vector will set the 2378 cooresponding bit in SLI_MSI_ENB0. 2379 A read to this address will return 0. */ 2380#else 2381 uint64_t set : 64; 2382#endif 2383 } s; 2384 struct cvmx_sli_msi_w1s_enb0_s cn63xx; 2385 struct cvmx_sli_msi_w1s_enb0_s cn63xxp1; 2386}; 2387typedef union cvmx_sli_msi_w1s_enb0 cvmx_sli_msi_w1s_enb0_t; 2388 2389/** 2390 * cvmx_sli_msi_w1s_enb1 2391 * 2392 * SLI_MSI_W1S_ENB0 = SLI MSI Write 1 To Set Enable1 2393 * 2394 * Used to set bits in SLI_MSI_ENB1. 2395 */ 2396union cvmx_sli_msi_w1s_enb1 2397{ 2398 uint64_t u64; 2399 struct cvmx_sli_msi_w1s_enb1_s 2400 { 2401#if __BYTE_ORDER == __BIG_ENDIAN 2402 uint64_t set : 64; /**< A write of '1' to a vector will set the 2403 cooresponding bit in SLI_MSI_ENB1. 2404 A read to this address will return 0. */ 2405#else 2406 uint64_t set : 64; 2407#endif 2408 } s; 2409 struct cvmx_sli_msi_w1s_enb1_s cn63xx; 2410 struct cvmx_sli_msi_w1s_enb1_s cn63xxp1; 2411}; 2412typedef union cvmx_sli_msi_w1s_enb1 cvmx_sli_msi_w1s_enb1_t; 2413 2414/** 2415 * cvmx_sli_msi_w1s_enb2 2416 * 2417 * SLI_MSI_W1S_ENB2 = SLI MSI Write 1 To Set Enable2 2418 * 2419 * Used to set bits in SLI_MSI_ENB2. 2420 */ 2421union cvmx_sli_msi_w1s_enb2 2422{ 2423 uint64_t u64; 2424 struct cvmx_sli_msi_w1s_enb2_s 2425 { 2426#if __BYTE_ORDER == __BIG_ENDIAN 2427 uint64_t set : 64; /**< A write of '1' to a vector will set the 2428 cooresponding bit in SLI_MSI_ENB2. 2429 A read to this address will return 0. */ 2430#else 2431 uint64_t set : 64; 2432#endif 2433 } s; 2434 struct cvmx_sli_msi_w1s_enb2_s cn63xx; 2435 struct cvmx_sli_msi_w1s_enb2_s cn63xxp1; 2436}; 2437typedef union cvmx_sli_msi_w1s_enb2 cvmx_sli_msi_w1s_enb2_t; 2438 2439/** 2440 * cvmx_sli_msi_w1s_enb3 2441 * 2442 * SLI_MSI_W1S_ENB3 = SLI MSI Write 1 To Set Enable3 2443 * 2444 * Used to set bits in SLI_MSI_ENB3. 2445 */ 2446union cvmx_sli_msi_w1s_enb3 2447{ 2448 uint64_t u64; 2449 struct cvmx_sli_msi_w1s_enb3_s 2450 { 2451#if __BYTE_ORDER == __BIG_ENDIAN 2452 uint64_t set : 64; /**< A write of '1' to a vector will set the 2453 cooresponding bit in SLI_MSI_ENB3. 2454 A read to this address will return 0. */ 2455#else 2456 uint64_t set : 64; 2457#endif 2458 } s; 2459 struct cvmx_sli_msi_w1s_enb3_s cn63xx; 2460 struct cvmx_sli_msi_w1s_enb3_s cn63xxp1; 2461}; 2462typedef union cvmx_sli_msi_w1s_enb3 cvmx_sli_msi_w1s_enb3_t; 2463 2464/** 2465 * cvmx_sli_msi_wr_map 2466 * 2467 * SLI_MSI_WR_MAP = SLI MSI Write MAP 2468 * 2469 * Used to write the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV registers. 2470 */ 2471union cvmx_sli_msi_wr_map 2472{ 2473 uint64_t u64; 2474 struct cvmx_sli_msi_wr_map_s 2475 { 2476#if __BYTE_ORDER == __BIG_ENDIAN 2477 uint64_t reserved_16_63 : 48; 2478 uint64_t ciu_int : 8; /**< Selects which bit in the SLI_MSI_RCV# (0-255) 2479 will be set when the value specified in the 2480 MSI_INT of this register is recevied during a 2481 write to the SLI_PCIE_MSI_RCV register. */ 2482 uint64_t msi_int : 8; /**< Selects the value that would be received when the 2483 SLI_PCIE_MSI_RCV register is written. */ 2484#else 2485 uint64_t msi_int : 8; 2486 uint64_t ciu_int : 8; 2487 uint64_t reserved_16_63 : 48; 2488#endif 2489 } s; 2490 struct cvmx_sli_msi_wr_map_s cn63xx; 2491 struct cvmx_sli_msi_wr_map_s cn63xxp1; 2492}; 2493typedef union cvmx_sli_msi_wr_map cvmx_sli_msi_wr_map_t; 2494 2495/** 2496 * cvmx_sli_pcie_msi_rcv 2497 * 2498 * SLI_PCIE_MSI_RCV = SLI MAC MSI Receive 2499 * 2500 * Register where MSI writes are directed from the MAC. 2501 */ 2502union cvmx_sli_pcie_msi_rcv 2503{ 2504 uint64_t u64; 2505 struct cvmx_sli_pcie_msi_rcv_s 2506 { 2507#if __BYTE_ORDER == __BIG_ENDIAN 2508 uint64_t reserved_8_63 : 56; 2509 uint64_t intr : 8; /**< A write to this register will result in a bit in 2510 one of the SLI_MSI_RCV# registers being set. 2511 Which bit is set is dependent on the previously 2512 written using the SLI_MSI_WR_MAP register or if 2513 not previously written the reset value of the MAP. */ 2514#else 2515 uint64_t intr : 8; 2516 uint64_t reserved_8_63 : 56; 2517#endif 2518 } s; 2519 struct cvmx_sli_pcie_msi_rcv_s cn63xx; 2520 struct cvmx_sli_pcie_msi_rcv_s cn63xxp1; 2521}; 2522typedef union cvmx_sli_pcie_msi_rcv cvmx_sli_pcie_msi_rcv_t; 2523 2524/** 2525 * cvmx_sli_pcie_msi_rcv_b1 2526 * 2527 * SLI_PCIE_MSI_RCV_B1 = SLI MAC MSI Receive Byte 1 2528 * 2529 * Register where MSI writes are directed from the MAC. 2530 * 2531 * Notes: 2532 * This CSR can be used by PCIe and sRIO MACs. 2533 * 2534 */ 2535union cvmx_sli_pcie_msi_rcv_b1 2536{ 2537 uint64_t u64; 2538 struct cvmx_sli_pcie_msi_rcv_b1_s 2539 { 2540#if __BYTE_ORDER == __BIG_ENDIAN 2541 uint64_t reserved_16_63 : 48; 2542 uint64_t intr : 8; /**< A write to this register will result in a bit in 2543 one of the SLI_MSI_RCV# registers being set. 2544 Which bit is set is dependent on the previously 2545 written using the SLI_MSI_WR_MAP register or if 2546 not previously written the reset value of the MAP. */ 2547 uint64_t reserved_0_7 : 8; 2548#else 2549 uint64_t reserved_0_7 : 8; 2550 uint64_t intr : 8; 2551 uint64_t reserved_16_63 : 48; 2552#endif 2553 } s; 2554 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx; 2555 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1; 2556}; 2557typedef union cvmx_sli_pcie_msi_rcv_b1 cvmx_sli_pcie_msi_rcv_b1_t; 2558 2559/** 2560 * cvmx_sli_pcie_msi_rcv_b2 2561 * 2562 * SLI_PCIE_MSI_RCV_B2 = SLI MAC MSI Receive Byte 2 2563 * 2564 * Register where MSI writes are directed from the MAC. 2565 * 2566 * Notes: 2567 * This CSR can be used by PCIe and sRIO MACs. 2568 * 2569 */ 2570union cvmx_sli_pcie_msi_rcv_b2 2571{ 2572 uint64_t u64; 2573 struct cvmx_sli_pcie_msi_rcv_b2_s 2574 { 2575#if __BYTE_ORDER == __BIG_ENDIAN 2576 uint64_t reserved_24_63 : 40; 2577 uint64_t intr : 8; /**< A write to this register will result in a bit in 2578 one of the SLI_MSI_RCV# registers being set. 2579 Which bit is set is dependent on the previously 2580 written using the SLI_MSI_WR_MAP register or if 2581 not previously written the reset value of the MAP. */ 2582 uint64_t reserved_0_15 : 16; 2583#else 2584 uint64_t reserved_0_15 : 16; 2585 uint64_t intr : 8; 2586 uint64_t reserved_24_63 : 40; 2587#endif 2588 } s; 2589 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx; 2590 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1; 2591}; 2592typedef union cvmx_sli_pcie_msi_rcv_b2 cvmx_sli_pcie_msi_rcv_b2_t; 2593 2594/** 2595 * cvmx_sli_pcie_msi_rcv_b3 2596 * 2597 * SLI_PCIE_MSI_RCV_B3 = SLI MAC MSI Receive Byte 3 2598 * 2599 * Register where MSI writes are directed from the MAC. 2600 * 2601 * Notes: 2602 * This CSR can be used by PCIe and sRIO MACs. 2603 * 2604 */ 2605union cvmx_sli_pcie_msi_rcv_b3 2606{ 2607 uint64_t u64; 2608 struct cvmx_sli_pcie_msi_rcv_b3_s 2609 { 2610#if __BYTE_ORDER == __BIG_ENDIAN 2611 uint64_t reserved_32_63 : 32; 2612 uint64_t intr : 8; /**< A write to this register will result in a bit in 2613 one of the SLI_MSI_RCV# registers being set. 2614 Which bit is set is dependent on the previously 2615 written using the SLI_MSI_WR_MAP register or if 2616 not previously written the reset value of the MAP. */ 2617 uint64_t reserved_0_23 : 24; 2618#else 2619 uint64_t reserved_0_23 : 24; 2620 uint64_t intr : 8; 2621 uint64_t reserved_32_63 : 32; 2622#endif 2623 } s; 2624 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx; 2625 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1; 2626}; 2627typedef union cvmx_sli_pcie_msi_rcv_b3 cvmx_sli_pcie_msi_rcv_b3_t; 2628 2629/** 2630 * cvmx_sli_pkt#_cnts 2631 * 2632 * SLI_PKT[0..31]_CNTS = SLI Packet ring# Counts 2633 * 2634 * The counters for output rings. 2635 */ 2636union cvmx_sli_pktx_cnts 2637{ 2638 uint64_t u64; 2639 struct cvmx_sli_pktx_cnts_s 2640 { 2641#if __BYTE_ORDER == __BIG_ENDIAN 2642 uint64_t reserved_54_63 : 10; 2643 uint64_t timer : 22; /**< Timer incremented every 1024 core clocks 2644 when SLI_PKTS#_CNTS[CNT] is non zero. Field 2645 cleared when SLI_PKTS#_CNTS[CNT] goes to 0. 2646 Field is also cleared when SLI_PKT_TIME_INT is 2647 cleared. 2648 The first increment of this count can occur 2649 between 0 to 1023 core clocks. */ 2650 uint64_t cnt : 32; /**< ring counter. This field is incremented as 2651 packets are sent out and decremented in response to 2652 writes to this field. 2653 When SLI_PKT_OUT_BMODE is '0' a value of 1 is 2654 added to the register for each packet, when '1' 2655 and the info-pointer is NOT used the length of the 2656 packet plus 8 is added, when '1' and info-pointer 2657 mode IS used the packet length is added to this 2658 field. */ 2659#else 2660 uint64_t cnt : 32; 2661 uint64_t timer : 22; 2662 uint64_t reserved_54_63 : 10; 2663#endif 2664 } s; 2665 struct cvmx_sli_pktx_cnts_s cn63xx; 2666 struct cvmx_sli_pktx_cnts_s cn63xxp1; 2667}; 2668typedef union cvmx_sli_pktx_cnts cvmx_sli_pktx_cnts_t; 2669 2670/** 2671 * cvmx_sli_pkt#_in_bp 2672 * 2673 * SLI_PKT[0..31]_IN_BP = SLI Packet ring# Input Backpressure 2674 * 2675 * The counters and thresholds for input packets to apply backpressure to processing of the packets. 2676 */ 2677union cvmx_sli_pktx_in_bp 2678{ 2679 uint64_t u64; 2680 struct cvmx_sli_pktx_in_bp_s 2681 { 2682#if __BYTE_ORDER == __BIG_ENDIAN 2683 uint64_t wmark : 32; /**< When CNT is greater than this threshold no more 2684 packets will be processed for this ring. 2685 When writing this field of the SLI_PKT#_IN_BP 2686 register, use a 4-byte write so as to not write 2687 any other field of this register. */ 2688 uint64_t cnt : 32; /**< ring counter. This field is incremented by one 2689 whenever OCTEON receives, buffers, and creates a 2690 work queue entry for a packet that arrives by the 2691 cooresponding input ring. A write to this field 2692 will be subtracted from the field value. 2693 When writing this field of the SLI_PKT#_IN_BP 2694 register, use a 4-byte write so as to not write 2695 any other field of this register. */ 2696#else 2697 uint64_t cnt : 32; 2698 uint64_t wmark : 32; 2699#endif 2700 } s; 2701 struct cvmx_sli_pktx_in_bp_s cn63xx; 2702 struct cvmx_sli_pktx_in_bp_s cn63xxp1; 2703}; 2704typedef union cvmx_sli_pktx_in_bp cvmx_sli_pktx_in_bp_t; 2705 2706/** 2707 * cvmx_sli_pkt#_instr_baddr 2708 * 2709 * SLI_PKT[0..31]_INSTR_BADDR = SLI Packet ring# Instruction Base Address 2710 * 2711 * Start of Instruction for input packets. 2712 */ 2713union cvmx_sli_pktx_instr_baddr 2714{ 2715 uint64_t u64; 2716 struct cvmx_sli_pktx_instr_baddr_s 2717 { 2718#if __BYTE_ORDER == __BIG_ENDIAN 2719 uint64_t addr : 61; /**< Base address for Instructions. */ 2720 uint64_t reserved_0_2 : 3; 2721#else 2722 uint64_t reserved_0_2 : 3; 2723 uint64_t addr : 61; 2724#endif 2725 } s; 2726 struct cvmx_sli_pktx_instr_baddr_s cn63xx; 2727 struct cvmx_sli_pktx_instr_baddr_s cn63xxp1; 2728}; 2729typedef union cvmx_sli_pktx_instr_baddr cvmx_sli_pktx_instr_baddr_t; 2730 2731/** 2732 * cvmx_sli_pkt#_instr_baoff_dbell 2733 * 2734 * SLI_PKT[0..31]_INSTR_BAOFF_DBELL = SLI Packet ring# Instruction Base Address Offset and Doorbell 2735 * 2736 * The doorbell and base address offset for next read. 2737 */ 2738union cvmx_sli_pktx_instr_baoff_dbell 2739{ 2740 uint64_t u64; 2741 struct cvmx_sli_pktx_instr_baoff_dbell_s 2742 { 2743#if __BYTE_ORDER == __BIG_ENDIAN 2744 uint64_t aoff : 32; /**< The offset from the SLI_PKT[0..31]_INSTR_BADDR 2745 where the next instruction will be read. */ 2746 uint64_t dbell : 32; /**< Instruction doorbell count. Writes to this field 2747 will increment the value here. Reads will return 2748 present value. A write of 0xffffffff will set the 2749 DBELL and AOFF fields to '0'. */ 2750#else 2751 uint64_t dbell : 32; 2752 uint64_t aoff : 32; 2753#endif 2754 } s; 2755 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx; 2756 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1; 2757}; 2758typedef union cvmx_sli_pktx_instr_baoff_dbell cvmx_sli_pktx_instr_baoff_dbell_t; 2759 2760/** 2761 * cvmx_sli_pkt#_instr_fifo_rsize 2762 * 2763 * SLI_PKT[0..31]_INSTR_FIFO_RSIZE = SLI Packet ring# Instruction FIFO and Ring Size. 2764 * 2765 * Fifo field and ring size for Instructions. 2766 */ 2767union cvmx_sli_pktx_instr_fifo_rsize 2768{ 2769 uint64_t u64; 2770 struct cvmx_sli_pktx_instr_fifo_rsize_s 2771 { 2772#if __BYTE_ORDER == __BIG_ENDIAN 2773 uint64_t max : 9; /**< Max Fifo Size. */ 2774 uint64_t rrp : 9; /**< Fifo read pointer. */ 2775 uint64_t wrp : 9; /**< Fifo write pointer. */ 2776 uint64_t fcnt : 5; /**< Fifo count. */ 2777 uint64_t rsize : 32; /**< Instruction ring size. */ 2778#else 2779 uint64_t rsize : 32; 2780 uint64_t fcnt : 5; 2781 uint64_t wrp : 9; 2782 uint64_t rrp : 9; 2783 uint64_t max : 9; 2784#endif 2785 } s; 2786 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx; 2787 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1; 2788}; 2789typedef union cvmx_sli_pktx_instr_fifo_rsize cvmx_sli_pktx_instr_fifo_rsize_t; 2790 2791/** 2792 * cvmx_sli_pkt#_instr_header 2793 * 2794 * SLI_PKT[0..31]_INSTR_HEADER = SLI Packet ring# Instruction Header. 2795 * 2796 * VAlues used to build input packet header. 2797 */ 2798union cvmx_sli_pktx_instr_header 2799{ 2800 uint64_t u64; 2801 struct cvmx_sli_pktx_instr_header_s 2802 { 2803#if __BYTE_ORDER == __BIG_ENDIAN 2804 uint64_t reserved_44_63 : 20; 2805 uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */ 2806 uint64_t reserved_38_42 : 5; 2807 uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */ 2808 uint64_t reserved_35_35 : 1; 2809 uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */ 2810 uint64_t reserved_26_27 : 2; 2811 uint64_t rnqos : 1; /**< RNQOS. Used when packet is raw and PBP==0. */ 2812 uint64_t rngrp : 1; /**< RNGRP. Used when packet is raw and PBP==0. */ 2813 uint64_t rntt : 1; /**< RNTT. Used when packet is raw and PBP==0. */ 2814 uint64_t rntag : 1; /**< RNTAG. Used when packet is raw and PBP==0. */ 2815 uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent 2816 as part of the packet data, regardless of the 2817 value of bit [63] of the instruction header. 2818 USE_IHDR must be set whenever PBP is set. */ 2819 uint64_t reserved_16_20 : 5; 2820 uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet 2821 is not raw and PBP is not set. */ 2822 uint64_t reserved_13_13 : 1; 2823 uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet 2824 is not raw and PBP is not set. */ 2825 uint64_t reserved_4_5 : 2; 2826 uint64_t nqos : 1; /**< NQOS. Used when packet is raw and PBP==0. */ 2827 uint64_t ngrp : 1; /**< NGRP. Used when packet is raw and PBP==0. */ 2828 uint64_t ntt : 1; /**< NTT. Used when packet is raw and PBP==0. */ 2829 uint64_t ntag : 1; /**< NTAG. Used when packet is raw and PBP==0. */ 2830#else 2831 uint64_t ntag : 1; 2832 uint64_t ntt : 1; 2833 uint64_t ngrp : 1; 2834 uint64_t nqos : 1; 2835 uint64_t reserved_4_5 : 2; 2836 uint64_t skp_len : 7; 2837 uint64_t reserved_13_13 : 1; 2838 uint64_t par_mode : 2; 2839 uint64_t reserved_16_20 : 5; 2840 uint64_t use_ihdr : 1; 2841 uint64_t rntag : 1; 2842 uint64_t rntt : 1; 2843 uint64_t rngrp : 1; 2844 uint64_t rnqos : 1; 2845 uint64_t reserved_26_27 : 2; 2846 uint64_t rskp_len : 7; 2847 uint64_t reserved_35_35 : 1; 2848 uint64_t rparmode : 2; 2849 uint64_t reserved_38_42 : 5; 2850 uint64_t pbp : 1; 2851 uint64_t reserved_44_63 : 20; 2852#endif 2853 } s; 2854 struct cvmx_sli_pktx_instr_header_s cn63xx; 2855 struct cvmx_sli_pktx_instr_header_s cn63xxp1; 2856}; 2857typedef union cvmx_sli_pktx_instr_header cvmx_sli_pktx_instr_header_t; 2858 2859/** 2860 * cvmx_sli_pkt#_out_size 2861 * 2862 * SLI_PKT[0..31]_OUT_SIZE = SLI Packet Out Size 2863 * 2864 * Contains the BSIZE and ISIZE for output packet ports. 2865 */ 2866union cvmx_sli_pktx_out_size 2867{ 2868 uint64_t u64; 2869 struct cvmx_sli_pktx_out_size_s 2870 { 2871#if __BYTE_ORDER == __BIG_ENDIAN 2872 uint64_t reserved_23_63 : 41; 2873 uint64_t isize : 7; /**< INFO BYTES size (bytes) for ring X. Legal sizes 2874 are 0 to 120. Not used in buffer-pointer-only mode. */ 2875 uint64_t bsize : 16; /**< BUFFER SIZE (bytes) for ring X. */ 2876#else 2877 uint64_t bsize : 16; 2878 uint64_t isize : 7; 2879 uint64_t reserved_23_63 : 41; 2880#endif 2881 } s; 2882 struct cvmx_sli_pktx_out_size_s cn63xx; 2883 struct cvmx_sli_pktx_out_size_s cn63xxp1; 2884}; 2885typedef union cvmx_sli_pktx_out_size cvmx_sli_pktx_out_size_t; 2886 2887/** 2888 * cvmx_sli_pkt#_slist_baddr 2889 * 2890 * SLI_PKT[0..31]_SLIST_BADDR = SLI Packet ring# Scatter List Base Address 2891 * 2892 * Start of Scatter List for output packet pointers - MUST be 16 byte alligned 2893 */ 2894union cvmx_sli_pktx_slist_baddr 2895{ 2896 uint64_t u64; 2897 struct cvmx_sli_pktx_slist_baddr_s 2898 { 2899#if __BYTE_ORDER == __BIG_ENDIAN 2900 uint64_t addr : 60; /**< Base address for scatter list pointers. */ 2901 uint64_t reserved_0_3 : 4; 2902#else 2903 uint64_t reserved_0_3 : 4; 2904 uint64_t addr : 60; 2905#endif 2906 } s; 2907 struct cvmx_sli_pktx_slist_baddr_s cn63xx; 2908 struct cvmx_sli_pktx_slist_baddr_s cn63xxp1; 2909}; 2910typedef union cvmx_sli_pktx_slist_baddr cvmx_sli_pktx_slist_baddr_t; 2911 2912/** 2913 * cvmx_sli_pkt#_slist_baoff_dbell 2914 * 2915 * SLI_PKT[0..31]_SLIST_BAOFF_DBELL = SLI Packet ring# Scatter List Base Address Offset and Doorbell 2916 * 2917 * The doorbell and base address offset for next read. 2918 */ 2919union cvmx_sli_pktx_slist_baoff_dbell 2920{ 2921 uint64_t u64; 2922 struct cvmx_sli_pktx_slist_baoff_dbell_s 2923 { 2924#if __BYTE_ORDER == __BIG_ENDIAN 2925 uint64_t aoff : 32; /**< The offset from the SLI_PKT[0..31]_SLIST_BADDR 2926 where the next SList pointer will be read. 2927 A write of 0xFFFFFFFF to the DBELL field will 2928 clear DBELL and AOFF */ 2929 uint64_t dbell : 32; /**< Scatter list doorbell count. Writes to this field 2930 will increment the value here. Reads will return 2931 present value. The value of this field is 2932 decremented as read operations are ISSUED for 2933 scatter pointers. 2934 A write of 0xFFFFFFFF will clear DBELL and AOFF */ 2935#else 2936 uint64_t dbell : 32; 2937 uint64_t aoff : 32; 2938#endif 2939 } s; 2940 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx; 2941 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1; 2942}; 2943typedef union cvmx_sli_pktx_slist_baoff_dbell cvmx_sli_pktx_slist_baoff_dbell_t; 2944 2945/** 2946 * cvmx_sli_pkt#_slist_fifo_rsize 2947 * 2948 * SLI_PKT[0..31]_SLIST_FIFO_RSIZE = SLI Packet ring# Scatter List FIFO and Ring Size. 2949 * 2950 * The number of scatter pointer pairs in the scatter list. 2951 */ 2952union cvmx_sli_pktx_slist_fifo_rsize 2953{ 2954 uint64_t u64; 2955 struct cvmx_sli_pktx_slist_fifo_rsize_s 2956 { 2957#if __BYTE_ORDER == __BIG_ENDIAN 2958 uint64_t reserved_32_63 : 32; 2959 uint64_t rsize : 32; /**< The number of scatter pointer pairs contained in 2960 the scatter list ring. */ 2961#else 2962 uint64_t rsize : 32; 2963 uint64_t reserved_32_63 : 32; 2964#endif 2965 } s; 2966 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx; 2967 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1; 2968}; 2969typedef union cvmx_sli_pktx_slist_fifo_rsize cvmx_sli_pktx_slist_fifo_rsize_t; 2970 2971/** 2972 * cvmx_sli_pkt_cnt_int 2973 * 2974 * SLI_PKT_CNT_INT = SLI Packet Counter Interrupt 2975 * 2976 * The packets rings that are interrupting because of Packet Counters. 2977 */ 2978union cvmx_sli_pkt_cnt_int 2979{ 2980 uint64_t u64; 2981 struct cvmx_sli_pkt_cnt_int_s 2982 { 2983#if __BYTE_ORDER == __BIG_ENDIAN 2984 uint64_t reserved_32_63 : 32; 2985 uint64_t port : 32; /**< Output ring packet counter interrupt bits 2986 SLI sets PORT<i> whenever 2987 SLI_PKTi_CNTS[CNT] > SLI_PKT_INT_LEVELS[CNT]. 2988 SLI_PKT_CNT_INT_ENB[PORT<i>] is the corresponding 2989 enable. */ 2990#else 2991 uint64_t port : 32; 2992 uint64_t reserved_32_63 : 32; 2993#endif 2994 } s; 2995 struct cvmx_sli_pkt_cnt_int_s cn63xx; 2996 struct cvmx_sli_pkt_cnt_int_s cn63xxp1; 2997}; 2998typedef union cvmx_sli_pkt_cnt_int cvmx_sli_pkt_cnt_int_t; 2999 3000/** 3001 * cvmx_sli_pkt_cnt_int_enb 3002 * 3003 * SLI_PKT_CNT_INT_ENB = SLI Packet Counter Interrupt Enable 3004 * 3005 * Enable for the packets rings that are interrupting because of Packet Counters. 3006 */ 3007union cvmx_sli_pkt_cnt_int_enb 3008{ 3009 uint64_t u64; 3010 struct cvmx_sli_pkt_cnt_int_enb_s 3011 { 3012#if __BYTE_ORDER == __BIG_ENDIAN 3013 uint64_t reserved_32_63 : 32; 3014 uint64_t port : 32; /**< Output ring packet counter interrupt enables 3015 When both PORT<i> and corresponding 3016 SLI_PKT_CNT_INT[PORT<i>] are set, for any i, 3017 then SLI_INT_SUM[PCNT] is set, which can cause 3018 an interrupt. */ 3019#else 3020 uint64_t port : 32; 3021 uint64_t reserved_32_63 : 32; 3022#endif 3023 } s; 3024 struct cvmx_sli_pkt_cnt_int_enb_s cn63xx; 3025 struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1; 3026}; 3027typedef union cvmx_sli_pkt_cnt_int_enb cvmx_sli_pkt_cnt_int_enb_t; 3028 3029/** 3030 * cvmx_sli_pkt_ctl 3031 * 3032 * SLI_PKT_CTL = SLI Packet Control 3033 * 3034 * Control for packets. 3035 */ 3036union cvmx_sli_pkt_ctl 3037{ 3038 uint64_t u64; 3039 struct cvmx_sli_pkt_ctl_s 3040 { 3041#if __BYTE_ORDER == __BIG_ENDIAN 3042 uint64_t reserved_5_63 : 59; 3043 uint64_t ring_en : 1; /**< When '0' forces "relative Q position" received 3044 from PKO to be zero, and replicates the back- 3045 pressure indication for the first ring attached 3046 to a PKO port across all the rings attached to a 3047 PKO port. When '1' backpressure is on a per 3048 port/ring. */ 3049 uint64_t pkt_bp : 4; /**< When set '1' enable the port level backpressure for 3050 PKO ports associated with the bit. */ 3051#else 3052 uint64_t pkt_bp : 4; 3053 uint64_t ring_en : 1; 3054 uint64_t reserved_5_63 : 59; 3055#endif 3056 } s; 3057 struct cvmx_sli_pkt_ctl_s cn63xx; 3058 struct cvmx_sli_pkt_ctl_s cn63xxp1; 3059}; 3060typedef union cvmx_sli_pkt_ctl cvmx_sli_pkt_ctl_t; 3061 3062/** 3063 * cvmx_sli_pkt_data_out_es 3064 * 3065 * SLI_PKT_DATA_OUT_ES = SLI's Packet Data Out Endian Swap 3066 * 3067 * The Endian Swap for writing Data Out. 3068 */ 3069union cvmx_sli_pkt_data_out_es 3070{ 3071 uint64_t u64; 3072 struct cvmx_sli_pkt_data_out_es_s 3073 { 3074#if __BYTE_ORDER == __BIG_ENDIAN 3075 uint64_t es : 64; /**< ES<1:0> or MACADD<63:62> for buffer/info writes. 3076 ES<2i+1:2i> becomes either ES<1:0> or 3077 MACADD<63:62> for writes to buffer/info pair 3078 MAC memory space addresses fetched from packet 3079 output ring i. ES<1:0> if SLI_PKT_DPADDR[DPTR<i>]=1 3080 , else MACADD<63:62>. 3081 In the latter case, ES<1:0> comes from DPTR<63:62>. 3082 ES<1:0> is the endian-swap attribute for these MAC 3083 memory space writes. */ 3084#else 3085 uint64_t es : 64; 3086#endif 3087 } s; 3088 struct cvmx_sli_pkt_data_out_es_s cn63xx; 3089 struct cvmx_sli_pkt_data_out_es_s cn63xxp1; 3090}; 3091typedef union cvmx_sli_pkt_data_out_es cvmx_sli_pkt_data_out_es_t; 3092 3093/** 3094 * cvmx_sli_pkt_data_out_ns 3095 * 3096 * SLI_PKT_DATA_OUT_NS = SLI's Packet Data Out No Snoop 3097 * 3098 * The NS field for the TLP when writing packet data. 3099 */ 3100union cvmx_sli_pkt_data_out_ns 3101{ 3102 uint64_t u64; 3103 struct cvmx_sli_pkt_data_out_ns_s 3104 { 3105#if __BYTE_ORDER == __BIG_ENDIAN 3106 uint64_t reserved_32_63 : 32; 3107 uint64_t nsr : 32; /**< ADDRTYPE<1> or MACADD<61> for buffer/info writes. 3108 NSR<i> becomes either ADDRTYPE<1> or MACADD<61> 3109 for writes to buffer/info pair MAC memory space 3110 addresses fetched from packet output ring i. 3111 ADDRTYPE<1> if SLI_PKT_DPADDR[DPTR<i>]=1, else 3112 MACADD<61>. 3113 In the latter case,ADDRTYPE<1> comes from DPTR<61>. 3114 ADDRTYPE<1> is the no-snoop attribute for PCIe 3115 , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 3116#else 3117 uint64_t nsr : 32; 3118 uint64_t reserved_32_63 : 32; 3119#endif 3120 } s; 3121 struct cvmx_sli_pkt_data_out_ns_s cn63xx; 3122 struct cvmx_sli_pkt_data_out_ns_s cn63xxp1; 3123}; 3124typedef union cvmx_sli_pkt_data_out_ns cvmx_sli_pkt_data_out_ns_t; 3125 3126/** 3127 * cvmx_sli_pkt_data_out_ror 3128 * 3129 * SLI_PKT_DATA_OUT_ROR = SLI's Packet Data Out Relaxed Ordering 3130 * 3131 * The ROR field for the TLP when writing Packet Data. 3132 */ 3133union cvmx_sli_pkt_data_out_ror 3134{ 3135 uint64_t u64; 3136 struct cvmx_sli_pkt_data_out_ror_s 3137 { 3138#if __BYTE_ORDER == __BIG_ENDIAN 3139 uint64_t reserved_32_63 : 32; 3140 uint64_t ror : 32; /**< ADDRTYPE<0> or MACADD<60> for buffer/info writes. 3141 ROR<i> becomes either ADDRTYPE<0> or MACADD<60> 3142 for writes to buffer/info pair MAC memory space 3143 addresses fetched from packet output ring i. 3144 ADDRTYPE<0> if SLI_PKT_DPADDR[DPTR<i>]=1, else 3145 MACADD<60>. 3146 In the latter case,ADDRTYPE<0> comes from DPTR<60>. 3147 ADDRTYPE<0> is the relaxed-order attribute for PCIe 3148 , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 3149#else 3150 uint64_t ror : 32; 3151 uint64_t reserved_32_63 : 32; 3152#endif 3153 } s; 3154 struct cvmx_sli_pkt_data_out_ror_s cn63xx; 3155 struct cvmx_sli_pkt_data_out_ror_s cn63xxp1; 3156}; 3157typedef union cvmx_sli_pkt_data_out_ror cvmx_sli_pkt_data_out_ror_t; 3158 3159/** 3160 * cvmx_sli_pkt_dpaddr 3161 * 3162 * SLI_PKT_DPADDR = SLI's Packet Data Pointer Addr 3163 * 3164 * Used to detemine address and attributes for packet data writes. 3165 */ 3166union cvmx_sli_pkt_dpaddr 3167{ 3168 uint64_t u64; 3169 struct cvmx_sli_pkt_dpaddr_s 3170 { 3171#if __BYTE_ORDER == __BIG_ENDIAN 3172 uint64_t reserved_32_63 : 32; 3173 uint64_t dptr : 32; /**< Determines whether buffer/info pointers are 3174 DPTR format 0 or DPTR format 1. 3175 When DPTR<i>=1, the buffer/info pointers fetched 3176 from packet output ring i are DPTR format 0. 3177 When DPTR<i>=0, the buffer/info pointers fetched 3178 from packet output ring i are DPTR format 1. 3179 (Replace SLI_PKT_INPUT_CONTROL[D_ESR,D_NSR,D_ROR] 3180 in the HRM descriptions of DPTR format 0/1 with 3181 SLI_PKT_DATA_OUT_ES[ES<2i+1:2i>], 3182 SLI_PKT_DATA_OUT_NS[NSR<i>], and 3183 SLI_PKT_DATA_OUT_ROR[ROR<i>], respectively, 3184 though.) */ 3185#else 3186 uint64_t dptr : 32; 3187 uint64_t reserved_32_63 : 32; 3188#endif 3189 } s; 3190 struct cvmx_sli_pkt_dpaddr_s cn63xx; 3191 struct cvmx_sli_pkt_dpaddr_s cn63xxp1; 3192}; 3193typedef union cvmx_sli_pkt_dpaddr cvmx_sli_pkt_dpaddr_t; 3194 3195/** 3196 * cvmx_sli_pkt_in_bp 3197 * 3198 * SLI_PKT_IN_BP = SLI Packet Input Backpressure 3199 * 3200 * Which input rings have backpressure applied. 3201 */ 3202union cvmx_sli_pkt_in_bp 3203{ 3204 uint64_t u64; 3205 struct cvmx_sli_pkt_in_bp_s 3206 { 3207#if __BYTE_ORDER == __BIG_ENDIAN 3208 uint64_t reserved_32_63 : 32; 3209 uint64_t bp : 32; /**< A packet input ring that has its count greater 3210 than its WMARK will have backpressure applied. 3211 Each of the 32 bits coorespond to an input ring. 3212 When '1' that ring has backpressure applied an 3213 will fetch no more instructions, but will process 3214 any previously fetched instructions. */ 3215#else 3216 uint64_t bp : 32; 3217 uint64_t reserved_32_63 : 32; 3218#endif 3219 } s; 3220 struct cvmx_sli_pkt_in_bp_s cn63xx; 3221 struct cvmx_sli_pkt_in_bp_s cn63xxp1; 3222}; 3223typedef union cvmx_sli_pkt_in_bp cvmx_sli_pkt_in_bp_t; 3224 3225/** 3226 * cvmx_sli_pkt_in_done#_cnts 3227 * 3228 * SLI_PKT_IN_DONE[0..31]_CNTS = SLI Instruction Done ring# Counts 3229 * 3230 * Counters for instructions completed on Input rings. 3231 */ 3232union cvmx_sli_pkt_in_donex_cnts 3233{ 3234 uint64_t u64; 3235 struct cvmx_sli_pkt_in_donex_cnts_s 3236 { 3237#if __BYTE_ORDER == __BIG_ENDIAN 3238 uint64_t reserved_32_63 : 32; 3239 uint64_t cnt : 32; /**< This field is incrmented by '1' when an instruction 3240 is completed. This field is incremented as the 3241 last of the data is read from the MAC. */ 3242#else 3243 uint64_t cnt : 32; 3244 uint64_t reserved_32_63 : 32; 3245#endif 3246 } s; 3247 struct cvmx_sli_pkt_in_donex_cnts_s cn63xx; 3248 struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1; 3249}; 3250typedef union cvmx_sli_pkt_in_donex_cnts cvmx_sli_pkt_in_donex_cnts_t; 3251 3252/** 3253 * cvmx_sli_pkt_in_instr_counts 3254 * 3255 * SLI_PKT_IN_INSTR_COUNTS = SLI Packet Input Instrutction Counts 3256 * 3257 * Keeps track of the number of instructions read into the FIFO and Packets sent to IPD. 3258 */ 3259union cvmx_sli_pkt_in_instr_counts 3260{ 3261 uint64_t u64; 3262 struct cvmx_sli_pkt_in_instr_counts_s 3263 { 3264#if __BYTE_ORDER == __BIG_ENDIAN 3265 uint64_t wr_cnt : 32; /**< Shows the number of packets sent to the IPD. */ 3266 uint64_t rd_cnt : 32; /**< Shows the value of instructions that have had reads 3267 issued for them. 3268 to the Packet-ring is in reset. */ 3269#else 3270 uint64_t rd_cnt : 32; 3271 uint64_t wr_cnt : 32; 3272#endif 3273 } s; 3274 struct cvmx_sli_pkt_in_instr_counts_s cn63xx; 3275 struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1; 3276}; 3277typedef union cvmx_sli_pkt_in_instr_counts cvmx_sli_pkt_in_instr_counts_t; 3278 3279/** 3280 * cvmx_sli_pkt_in_pcie_port 3281 * 3282 * SLI_PKT_IN_PCIE_PORT = SLI's Packet In To MAC Port Assignment 3283 * 3284 * Assigns Packet Input rings to MAC ports. 3285 */ 3286union cvmx_sli_pkt_in_pcie_port 3287{ 3288 uint64_t u64; 3289 struct cvmx_sli_pkt_in_pcie_port_s 3290 { 3291#if __BYTE_ORDER == __BIG_ENDIAN 3292 uint64_t pp : 64; /**< The MAC port that the Packet ring number is 3293 assigned. Two bits are used per ring (i.e. ring 0 3294 [1:0], ring 1 [3:2], ....). A value of '0 means 3295 that the Packetring is assign to MAC Port 0, a '1' 3296 MAC Port 1, '2' and '3' are reserved. */ 3297#else 3298 uint64_t pp : 64; 3299#endif 3300 } s; 3301 struct cvmx_sli_pkt_in_pcie_port_s cn63xx; 3302 struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1; 3303}; 3304typedef union cvmx_sli_pkt_in_pcie_port cvmx_sli_pkt_in_pcie_port_t; 3305 3306/** 3307 * cvmx_sli_pkt_input_control 3308 * 3309 * SLI_PKT_INPUT_CONTROL = SLI's Packet Input Control 3310 * 3311 * Control for reads for gather list and instructions. 3312 */ 3313union cvmx_sli_pkt_input_control 3314{ 3315 uint64_t u64; 3316 struct cvmx_sli_pkt_input_control_s 3317 { 3318#if __BYTE_ORDER == __BIG_ENDIAN 3319 uint64_t reserved_23_63 : 41; 3320 uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be 3321 made with a Round Robin arbitration. When '0' 3322 the input packet ring is fixed in priority, 3323 where the lower ring number has higher priority. */ 3324 uint64_t pbp_dhi : 13; /**< PBP_DHI replaces address bits that are used 3325 for parse mode and skip-length when 3326 SLI_PKTi_INSTR_HEADER[PBP]=1. 3327 PBP_DHI becomes either MACADD<63:55> or MACADD<59:51> 3328 for the instruction DPTR reads in this case. 3329 The instruction DPTR reads are called 3330 "First Direct" or "First Indirect" in the HRM. 3331 When PBP=1, if "First Direct" and USE_CSR=0, PBP_DHI 3332 becomes MACADD<59:51>, else MACADD<63:55>. */ 3333 uint64_t d_nsr : 1; /**< ADDRTYPE<1> or MACADD<61> for packet input data 3334 reads. 3335 D_NSR becomes either ADDRTYPE<1> or MACADD<61> 3336 for MAC memory space reads of packet input data 3337 fetched for any packet input ring. 3338 ADDRTYPE<1> if USE_CSR=1, else MACADD<61>. 3339 In the latter case, ADDRTYPE<1> comes from DPTR<61>. 3340 ADDRTYPE<1> is the no-snoop attribute for PCIe 3341 , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 3342 uint64_t d_esr : 2; /**< ES<1:0> or MACADD<63:62> for packet input data 3343 reads. 3344 D_ESR becomes either ES<1:0> or MACADD<63:62> 3345 for MAC memory space reads of packet input data 3346 fetched for any packet input ring. 3347 ES<1:0> if USE_CSR=1, else MACADD<63:62>. 3348 In the latter case, ES<1:0> comes from DPTR<63:62>. 3349 ES<1:0> is the endian-swap attribute for these MAC 3350 memory space reads. */ 3351 uint64_t d_ror : 1; /**< ADDRTYPE<0> or MACADD<60> for packet input data 3352 reads. 3353 D_ROR becomes either ADDRTYPE<0> or MACADD<60> 3354 for MAC memory space reads of packet input data 3355 fetched for any packet input ring. 3356 ADDRTYPE<0> if USE_CSR=1, else MACADD<60>. 3357 In the latter case, ADDRTYPE<0> comes from DPTR<60>. 3358 ADDRTYPE<0> is the relaxed-order attribute for PCIe 3359 , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 3360 uint64_t use_csr : 1; /**< When set '1' the csr value will be used for 3361 ROR, ESR, and NSR. When clear '0' the value in 3362 DPTR will be used. In turn the bits not used for 3363 ROR, ESR, and NSR, will be used for bits [63:60] 3364 of the address used to fetch packet data. */ 3365 uint64_t nsr : 1; /**< ADDRTYPE<1> for packet input instruction reads and 3366 gather list (i.e. DPI component) reads from MAC 3367 memory space. 3368 ADDRTYPE<1> is the no-snoop attribute for PCIe 3369 , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 3370 uint64_t esr : 2; /**< ES<1:0> for packet input instruction reads and 3371 gather list (i.e. DPI component) reads from MAC 3372 memory space. 3373 ES<1:0> is the endian-swap attribute for these MAC 3374 memory space reads. */ 3375 uint64_t ror : 1; /**< ADDRTYPE<0> for packet input instruction reads and 3376 gather list (i.e. DPI component) reads from MAC 3377 memory space. 3378 ADDRTYPE<0> is the relaxed-order attribute for PCIe 3379 , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 3380#else 3381 uint64_t ror : 1; 3382 uint64_t esr : 2; 3383 uint64_t nsr : 1; 3384 uint64_t use_csr : 1; 3385 uint64_t d_ror : 1; 3386 uint64_t d_esr : 2; 3387 uint64_t d_nsr : 1; 3388 uint64_t pbp_dhi : 13; 3389 uint64_t pkt_rr : 1; 3390 uint64_t reserved_23_63 : 41; 3391#endif 3392 } s; 3393 struct cvmx_sli_pkt_input_control_s cn63xx; 3394 struct cvmx_sli_pkt_input_control_s cn63xxp1; 3395}; 3396typedef union cvmx_sli_pkt_input_control cvmx_sli_pkt_input_control_t; 3397 3398/** 3399 * cvmx_sli_pkt_instr_enb 3400 * 3401 * SLI_PKT_INSTR_ENB = SLI's Packet Instruction Enable 3402 * 3403 * Enables the instruction fetch for a Packet-ring. 3404 */ 3405union cvmx_sli_pkt_instr_enb 3406{ 3407 uint64_t u64; 3408 struct cvmx_sli_pkt_instr_enb_s 3409 { 3410#if __BYTE_ORDER == __BIG_ENDIAN 3411 uint64_t reserved_32_63 : 32; 3412 uint64_t enb : 32; /**< When ENB<i>=1, instruction input ring i is enabled. */ 3413#else 3414 uint64_t enb : 32; 3415 uint64_t reserved_32_63 : 32; 3416#endif 3417 } s; 3418 struct cvmx_sli_pkt_instr_enb_s cn63xx; 3419 struct cvmx_sli_pkt_instr_enb_s cn63xxp1; 3420}; 3421typedef union cvmx_sli_pkt_instr_enb cvmx_sli_pkt_instr_enb_t; 3422 3423/** 3424 * cvmx_sli_pkt_instr_rd_size 3425 * 3426 * SLI_PKT_INSTR_RD_SIZE = SLI Instruction Read Size 3427 * 3428 * The number of instruction allowed to be read at one time. 3429 */ 3430union cvmx_sli_pkt_instr_rd_size 3431{ 3432 uint64_t u64; 3433 struct cvmx_sli_pkt_instr_rd_size_s 3434 { 3435#if __BYTE_ORDER == __BIG_ENDIAN 3436 uint64_t rdsize : 64; /**< Number of instructions to be read in one MAC read 3437 request for the 4 ports - 8 rings. Every two bits 3438 (i.e. 1:0, 3:2, 5:4..) are assign to the port/ring 3439 combinations. 3440 - 15:0 PKIPort0,Ring 7..0 31:16 PKIPort1,Ring 7..0 3441 - 47:32 PKIPort2,Ring 7..0 63:48 PKIPort3,Ring 7..0 3442 Two bit value are: 3443 0 - 1 Instruction 3444 1 - 2 Instructions 3445 2 - 3 Instructions 3446 3 - 4 Instructions */ 3447#else 3448 uint64_t rdsize : 64; 3449#endif 3450 } s; 3451 struct cvmx_sli_pkt_instr_rd_size_s cn63xx; 3452 struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1; 3453}; 3454typedef union cvmx_sli_pkt_instr_rd_size cvmx_sli_pkt_instr_rd_size_t; 3455 3456/** 3457 * cvmx_sli_pkt_instr_size 3458 * 3459 * SLI_PKT_INSTR_SIZE = SLI's Packet Instruction Size 3460 * 3461 * Determines if instructions are 64 or 32 byte in size for a Packet-ring. 3462 */ 3463union cvmx_sli_pkt_instr_size 3464{ 3465 uint64_t u64; 3466 struct cvmx_sli_pkt_instr_size_s 3467 { 3468#if __BYTE_ORDER == __BIG_ENDIAN 3469 uint64_t reserved_32_63 : 32; 3470 uint64_t is_64b : 32; /**< When IS_64B<i>=1, instruction input ring i uses 64B 3471 instructions, else 32B instructions. */ 3472#else 3473 uint64_t is_64b : 32; 3474 uint64_t reserved_32_63 : 32; 3475#endif 3476 } s; 3477 struct cvmx_sli_pkt_instr_size_s cn63xx; 3478 struct cvmx_sli_pkt_instr_size_s cn63xxp1; 3479}; 3480typedef union cvmx_sli_pkt_instr_size cvmx_sli_pkt_instr_size_t; 3481 3482/** 3483 * cvmx_sli_pkt_int_levels 3484 * 3485 * 0x90F0 reserved SLI_PKT_PCIE_PORT2 3486 * 3487 * 3488 * SLI_PKT_INT_LEVELS = SLI's Packet Interrupt Levels 3489 * 3490 * Output packet interrupt levels. 3491 */ 3492union cvmx_sli_pkt_int_levels 3493{ 3494 uint64_t u64; 3495 struct cvmx_sli_pkt_int_levels_s 3496 { 3497#if __BYTE_ORDER == __BIG_ENDIAN 3498 uint64_t reserved_54_63 : 10; 3499 uint64_t time : 22; /**< Output ring counter time interrupt threshold 3500 SLI sets SLI_PKT_TIME_INT[PORT<i>] whenever 3501 SLI_PKTi_CNTS[TIMER] > TIME */ 3502 uint64_t cnt : 32; /**< Output ring counter interrupt threshold 3503 SLI sets SLI_PKT_CNT_INT[PORT<i>] whenever 3504 SLI_PKTi_CNTS[CNT] > CNT */ 3505#else 3506 uint64_t cnt : 32; 3507 uint64_t time : 22; 3508 uint64_t reserved_54_63 : 10; 3509#endif 3510 } s; 3511 struct cvmx_sli_pkt_int_levels_s cn63xx; 3512 struct cvmx_sli_pkt_int_levels_s cn63xxp1; 3513}; 3514typedef union cvmx_sli_pkt_int_levels cvmx_sli_pkt_int_levels_t; 3515 3516/** 3517 * cvmx_sli_pkt_iptr 3518 * 3519 * SLI_PKT_IPTR = SLI's Packet Info Poitner 3520 * 3521 * Controls using the Info-Pointer to store length and data. 3522 */ 3523union cvmx_sli_pkt_iptr 3524{ 3525 uint64_t u64; 3526 struct cvmx_sli_pkt_iptr_s 3527 { 3528#if __BYTE_ORDER == __BIG_ENDIAN 3529 uint64_t reserved_32_63 : 32; 3530 uint64_t iptr : 32; /**< When IPTR<i>=1, packet output ring i is in info- 3531 pointer mode, else buffer-pointer-only mode. */ 3532#else 3533 uint64_t iptr : 32; 3534 uint64_t reserved_32_63 : 32; 3535#endif 3536 } s; 3537 struct cvmx_sli_pkt_iptr_s cn63xx; 3538 struct cvmx_sli_pkt_iptr_s cn63xxp1; 3539}; 3540typedef union cvmx_sli_pkt_iptr cvmx_sli_pkt_iptr_t; 3541 3542/** 3543 * cvmx_sli_pkt_out_bmode 3544 * 3545 * SLI_PKT_OUT_BMODE = SLI's Packet Out Byte Mode 3546 * 3547 * Control the updating of the SLI_PKT#_CNT register. 3548 */ 3549union cvmx_sli_pkt_out_bmode 3550{ 3551 uint64_t u64; 3552 struct cvmx_sli_pkt_out_bmode_s 3553 { 3554#if __BYTE_ORDER == __BIG_ENDIAN 3555 uint64_t reserved_32_63 : 32; 3556 uint64_t bmode : 32; /**< Determines whether SLI_PKTi_CNTS[CNT] is a byte or 3557 packet counter. 3558 When BMODE<i>=1, SLI_PKTi_CNTS[CNT] is a byte 3559 counter, else SLI_PKTi_CNTS[CNT] is a packet 3560 counter. */ 3561#else 3562 uint64_t bmode : 32; 3563 uint64_t reserved_32_63 : 32; 3564#endif 3565 } s; 3566 struct cvmx_sli_pkt_out_bmode_s cn63xx; 3567 struct cvmx_sli_pkt_out_bmode_s cn63xxp1; 3568}; 3569typedef union cvmx_sli_pkt_out_bmode cvmx_sli_pkt_out_bmode_t; 3570 3571/** 3572 * cvmx_sli_pkt_out_enb 3573 * 3574 * SLI_PKT_OUT_ENB = SLI's Packet Output Enable 3575 * 3576 * Enables the output packet engines. 3577 */ 3578union cvmx_sli_pkt_out_enb 3579{ 3580 uint64_t u64; 3581 struct cvmx_sli_pkt_out_enb_s 3582 { 3583#if __BYTE_ORDER == __BIG_ENDIAN 3584 uint64_t reserved_32_63 : 32; 3585 uint64_t enb : 32; /**< When ENB<i>=1, packet output ring i is enabled. 3586 If an error occurs on reading pointers for an 3587 output ring, the ring will be disabled by clearing 3588 the bit associated with the ring to '0'. */ 3589#else 3590 uint64_t enb : 32; 3591 uint64_t reserved_32_63 : 32; 3592#endif 3593 } s; 3594 struct cvmx_sli_pkt_out_enb_s cn63xx; 3595 struct cvmx_sli_pkt_out_enb_s cn63xxp1; 3596}; 3597typedef union cvmx_sli_pkt_out_enb cvmx_sli_pkt_out_enb_t; 3598 3599/** 3600 * cvmx_sli_pkt_output_wmark 3601 * 3602 * SLI_PKT_OUTPUT_WMARK = SLI's Packet Output Water Mark 3603 * 3604 * Value that when the SLI_PKT#_SLIST_BAOFF_DBELL[DBELL] value is less then that backpressure for the rings will be applied. 3605 */ 3606union cvmx_sli_pkt_output_wmark 3607{ 3608 uint64_t u64; 3609 struct cvmx_sli_pkt_output_wmark_s 3610 { 3611#if __BYTE_ORDER == __BIG_ENDIAN 3612 uint64_t reserved_32_63 : 32; 3613 uint64_t wmark : 32; /**< Value when DBELL count drops below backpressure 3614 for the ring will be applied to the PKO. */ 3615#else 3616 uint64_t wmark : 32; 3617 uint64_t reserved_32_63 : 32; 3618#endif 3619 } s; 3620 struct cvmx_sli_pkt_output_wmark_s cn63xx; 3621 struct cvmx_sli_pkt_output_wmark_s cn63xxp1; 3622}; 3623typedef union cvmx_sli_pkt_output_wmark cvmx_sli_pkt_output_wmark_t; 3624 3625/** 3626 * cvmx_sli_pkt_pcie_port 3627 * 3628 * SLI_PKT_PCIE_PORT = SLI's Packet To MAC Port Assignment 3629 * 3630 * Assigns Packet Ports to MAC ports. 3631 */ 3632union cvmx_sli_pkt_pcie_port 3633{ 3634 uint64_t u64; 3635 struct cvmx_sli_pkt_pcie_port_s 3636 { 3637#if __BYTE_ORDER == __BIG_ENDIAN 3638 uint64_t pp : 64; /**< The physical MAC port that the output ring uses. 3639 Two bits are used per ring (i.e. ring 0 [1:0], 3640 ring 1 [3:2], ....). A value of '0 means 3641 that the Packetring is assign to MAC Port 0, a '1' 3642 MAC Port 1, '2' and '3' are reserved. */ 3643#else 3644 uint64_t pp : 64; 3645#endif 3646 } s; 3647 struct cvmx_sli_pkt_pcie_port_s cn63xx; 3648 struct cvmx_sli_pkt_pcie_port_s cn63xxp1; 3649}; 3650typedef union cvmx_sli_pkt_pcie_port cvmx_sli_pkt_pcie_port_t; 3651 3652/** 3653 * cvmx_sli_pkt_port_in_rst 3654 * 3655 * 91c0 reserved 3656 * 91d0 reserved 3657 * 91e0 reserved 3658 * 3659 * 3660 * SLI_PKT_PORT_IN_RST = SLI Packet Port In Reset 3661 * 3662 * Vector bits related to ring-port for ones that are reset. 3663 */ 3664union cvmx_sli_pkt_port_in_rst 3665{ 3666 uint64_t u64; 3667 struct cvmx_sli_pkt_port_in_rst_s 3668 { 3669#if __BYTE_ORDER == __BIG_ENDIAN 3670 uint64_t in_rst : 32; /**< When asserted '1' the vector bit cooresponding 3671 to the inbound Packet-ring is in reset. */ 3672 uint64_t out_rst : 32; /**< When asserted '1' the vector bit cooresponding 3673 to the outbound Packet-ring is in reset. */ 3674#else 3675 uint64_t out_rst : 32; 3676 uint64_t in_rst : 32; 3677#endif 3678 } s; 3679 struct cvmx_sli_pkt_port_in_rst_s cn63xx; 3680 struct cvmx_sli_pkt_port_in_rst_s cn63xxp1; 3681}; 3682typedef union cvmx_sli_pkt_port_in_rst cvmx_sli_pkt_port_in_rst_t; 3683 3684/** 3685 * cvmx_sli_pkt_slist_es 3686 * 3687 * SLI_PKT_SLIST_ES = SLI's Packet Scatter List Endian Swap 3688 * 3689 * The Endian Swap for Scatter List Read. 3690 */ 3691union cvmx_sli_pkt_slist_es 3692{ 3693 uint64_t u64; 3694 struct cvmx_sli_pkt_slist_es_s 3695 { 3696#if __BYTE_ORDER == __BIG_ENDIAN 3697 uint64_t es : 64; /**< ES<1:0> for the packet output ring reads that 3698 fetch buffer/info pointer pairs. 3699 ES<2i+1:2i> becomes ES<1:0> in DPI/SLI reads that 3700 fetch buffer/info pairs from packet output ring i 3701 (from address SLI_PKTi_SLIST_BADDR+ in MAC memory 3702 space.) 3703 ES<1:0> is the endian-swap attribute for these MAC 3704 memory space reads. */ 3705#else 3706 uint64_t es : 64; 3707#endif 3708 } s; 3709 struct cvmx_sli_pkt_slist_es_s cn63xx; 3710 struct cvmx_sli_pkt_slist_es_s cn63xxp1; 3711}; 3712typedef union cvmx_sli_pkt_slist_es cvmx_sli_pkt_slist_es_t; 3713 3714/** 3715 * cvmx_sli_pkt_slist_ns 3716 * 3717 * SLI_PKT_SLIST_NS = SLI's Packet Scatter List No Snoop 3718 * 3719 * The NS field for the TLP when fetching Scatter List. 3720 */ 3721union cvmx_sli_pkt_slist_ns 3722{ 3723 uint64_t u64; 3724 struct cvmx_sli_pkt_slist_ns_s 3725 { 3726#if __BYTE_ORDER == __BIG_ENDIAN 3727 uint64_t reserved_32_63 : 32; 3728 uint64_t nsr : 32; /**< ADDRTYPE<1> for the packet output ring reads that 3729 fetch buffer/info pointer pairs. 3730 NSR<i> becomes ADDRTYPE<1> in DPI/SLI reads that 3731 fetch buffer/info pairs from packet output ring i 3732 (from address SLI_PKTi_SLIST_BADDR+ in MAC memory 3733 space.) 3734 ADDRTYPE<1> is the relaxed-order attribute for PCIe 3735 , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 3736#else 3737 uint64_t nsr : 32; 3738 uint64_t reserved_32_63 : 32; 3739#endif 3740 } s; 3741 struct cvmx_sli_pkt_slist_ns_s cn63xx; 3742 struct cvmx_sli_pkt_slist_ns_s cn63xxp1; 3743}; 3744typedef union cvmx_sli_pkt_slist_ns cvmx_sli_pkt_slist_ns_t; 3745 3746/** 3747 * cvmx_sli_pkt_slist_ror 3748 * 3749 * SLI_PKT_SLIST_ROR = SLI's Packet Scatter List Relaxed Ordering 3750 * 3751 * The ROR field for the TLP when fetching Scatter List. 3752 */ 3753union cvmx_sli_pkt_slist_ror 3754{ 3755 uint64_t u64; 3756 struct cvmx_sli_pkt_slist_ror_s 3757 { 3758#if __BYTE_ORDER == __BIG_ENDIAN 3759 uint64_t reserved_32_63 : 32; 3760 uint64_t ror : 32; /**< ADDRTYPE<0> for the packet output ring reads that 3761 fetch buffer/info pointer pairs. 3762 ROR<i> becomes ADDRTYPE<0> in DPI/SLI reads that 3763 fetch buffer/info pairs from packet output ring i 3764 (from address SLI_PKTi_SLIST_BADDR+ in MAC memory 3765 space.) 3766 ADDRTYPE<0> is the relaxed-order attribute for PCIe 3767 , helps select an SRIO*_S2M_TYPE* entry with sRIO. */ 3768#else 3769 uint64_t ror : 32; 3770 uint64_t reserved_32_63 : 32; 3771#endif 3772 } s; 3773 struct cvmx_sli_pkt_slist_ror_s cn63xx; 3774 struct cvmx_sli_pkt_slist_ror_s cn63xxp1; 3775}; 3776typedef union cvmx_sli_pkt_slist_ror cvmx_sli_pkt_slist_ror_t; 3777 3778/** 3779 * cvmx_sli_pkt_time_int 3780 * 3781 * SLI_PKT_TIME_INT = SLI Packet Timer Interrupt 3782 * 3783 * The packets rings that are interrupting because of Packet Timers. 3784 */ 3785union cvmx_sli_pkt_time_int 3786{ 3787 uint64_t u64; 3788 struct cvmx_sli_pkt_time_int_s 3789 { 3790#if __BYTE_ORDER == __BIG_ENDIAN 3791 uint64_t reserved_32_63 : 32; 3792 uint64_t port : 32; /**< Output ring packet timer interrupt bits 3793 SLI sets PORT<i> whenever 3794 SLI_PKTi_CNTS[TIMER] > SLI_PKT_INT_LEVELS[TIME]. 3795 SLI_PKT_TIME_INT_ENB[PORT<i>] is the corresponding 3796 enable. */ 3797#else 3798 uint64_t port : 32; 3799 uint64_t reserved_32_63 : 32; 3800#endif 3801 } s; 3802 struct cvmx_sli_pkt_time_int_s cn63xx; 3803 struct cvmx_sli_pkt_time_int_s cn63xxp1; 3804}; 3805typedef union cvmx_sli_pkt_time_int cvmx_sli_pkt_time_int_t; 3806 3807/** 3808 * cvmx_sli_pkt_time_int_enb 3809 * 3810 * SLI_PKT_TIME_INT_ENB = SLI Packet Timer Interrupt Enable 3811 * 3812 * The packets rings that are interrupting because of Packet Timers. 3813 */ 3814union cvmx_sli_pkt_time_int_enb 3815{ 3816 uint64_t u64; 3817 struct cvmx_sli_pkt_time_int_enb_s 3818 { 3819#if __BYTE_ORDER == __BIG_ENDIAN 3820 uint64_t reserved_32_63 : 32; 3821 uint64_t port : 32; /**< Output ring packet timer interrupt enables 3822 When both PORT<i> and corresponding 3823 SLI_PKT_TIME_INT[PORT<i>] are set, for any i, 3824 then SLI_INT_SUM[PTIME] is set, which can cause 3825 an interrupt. */ 3826#else 3827 uint64_t port : 32; 3828 uint64_t reserved_32_63 : 32; 3829#endif 3830 } s; 3831 struct cvmx_sli_pkt_time_int_enb_s cn63xx; 3832 struct cvmx_sli_pkt_time_int_enb_s cn63xxp1; 3833}; 3834typedef union cvmx_sli_pkt_time_int_enb cvmx_sli_pkt_time_int_enb_t; 3835 3836/** 3837 * cvmx_sli_s2m_port#_ctl 3838 * 3839 * SLI_S2M_PORTX_CTL = SLI's S2M Port 0 Control 3840 * 3841 * Contains control for access from SLI to a MAC port. 3842 * Writes to this register are not ordered with writes/reads to the MAC Memory space. 3843 * To ensure that a write has completed the user must read the register before 3844 * making an access(i.e. MAC memory space) that requires the value of this register to be updated. 3845 */ 3846union cvmx_sli_s2m_portx_ctl 3847{ 3848 uint64_t u64; 3849 struct cvmx_sli_s2m_portx_ctl_s 3850 { 3851#if __BYTE_ORDER == __BIG_ENDIAN 3852 uint64_t reserved_5_63 : 59; 3853 uint64_t wind_d : 1; /**< When set '1' disables access to the Window 3854 Registers from the MAC-Port. */ 3855 uint64_t bar0_d : 1; /**< When set '1' disables access from MAC to 3856 BAR-0 address offsets: Less Than 0x330, 3857 0x3CD0, and greater than 0x3D70. */ 3858 uint64_t mrrs : 3; /**< Max Read Request Size 3859 0 = 128B 3860 1 = 256B 3861 2 = 512B 3862 3 = 1024B 3863 4 = 2048B 3864 5-7 = Reserved 3865 This field should not exceed the desired 3866 max read request size. This field is used to 3867 determine if an IOBDMA is too large. 3868 For a PCIe MAC, this field should not exceed 3869 PCIE*_CFG030[MRRS]. 3870 For a sRIO MAC, this field should indicate a size 3871 of 256B or smaller. */ 3872#else 3873 uint64_t mrrs : 3; 3874 uint64_t bar0_d : 1; 3875 uint64_t wind_d : 1; 3876 uint64_t reserved_5_63 : 59; 3877#endif 3878 } s; 3879 struct cvmx_sli_s2m_portx_ctl_s cn63xx; 3880 struct cvmx_sli_s2m_portx_ctl_s cn63xxp1; 3881}; 3882typedef union cvmx_sli_s2m_portx_ctl cvmx_sli_s2m_portx_ctl_t; 3883 3884/** 3885 * cvmx_sli_scratch_1 3886 * 3887 * SLI_SCRATCH_1 = SLI's Scratch 1 3888 * 3889 * A general purpose 64 bit register for SW use. 3890 */ 3891union cvmx_sli_scratch_1 3892{ 3893 uint64_t u64; 3894 struct cvmx_sli_scratch_1_s 3895 { 3896#if __BYTE_ORDER == __BIG_ENDIAN 3897 uint64_t data : 64; /**< The value in this register is totaly SW dependent. */ 3898#else 3899 uint64_t data : 64; 3900#endif 3901 } s; 3902 struct cvmx_sli_scratch_1_s cn63xx; 3903 struct cvmx_sli_scratch_1_s cn63xxp1; 3904}; 3905typedef union cvmx_sli_scratch_1 cvmx_sli_scratch_1_t; 3906 3907/** 3908 * cvmx_sli_scratch_2 3909 * 3910 * SLI_SCRATCH_2 = SLI's Scratch 2 3911 * 3912 * A general purpose 64 bit register for SW use. 3913 */ 3914union cvmx_sli_scratch_2 3915{ 3916 uint64_t u64; 3917 struct cvmx_sli_scratch_2_s 3918 { 3919#if __BYTE_ORDER == __BIG_ENDIAN 3920 uint64_t data : 64; /**< The value in this register is totaly SW dependent. */ 3921#else 3922 uint64_t data : 64; 3923#endif 3924 } s; 3925 struct cvmx_sli_scratch_2_s cn63xx; 3926 struct cvmx_sli_scratch_2_s cn63xxp1; 3927}; 3928typedef union cvmx_sli_scratch_2 cvmx_sli_scratch_2_t; 3929 3930/** 3931 * cvmx_sli_state1 3932 * 3933 * SLI_STATE1 = SLI State 1 3934 * 3935 * State machines in SLI. For debug. 3936 */ 3937union cvmx_sli_state1 3938{ 3939 uint64_t u64; 3940 struct cvmx_sli_state1_s 3941 { 3942#if __BYTE_ORDER == __BIG_ENDIAN 3943 uint64_t cpl1 : 12; /**< CPL1 State */ 3944 uint64_t cpl0 : 12; /**< CPL0 State */ 3945 uint64_t arb : 1; /**< ARB State */ 3946 uint64_t csr : 39; /**< CSR State */ 3947#else 3948 uint64_t csr : 39; 3949 uint64_t arb : 1; 3950 uint64_t cpl0 : 12; 3951 uint64_t cpl1 : 12; 3952#endif 3953 } s; 3954 struct cvmx_sli_state1_s cn63xx; 3955 struct cvmx_sli_state1_s cn63xxp1; 3956}; 3957typedef union cvmx_sli_state1 cvmx_sli_state1_t; 3958 3959/** 3960 * cvmx_sli_state2 3961 * 3962 * SLI_STATE2 = SLI State 2 3963 * 3964 * State machines in SLI. For debug. 3965 */ 3966union cvmx_sli_state2 3967{ 3968 uint64_t u64; 3969 struct cvmx_sli_state2_s 3970 { 3971#if __BYTE_ORDER == __BIG_ENDIAN 3972 uint64_t reserved_56_63 : 8; 3973 uint64_t nnp1 : 8; /**< NNP1 State */ 3974 uint64_t reserved_47_47 : 1; 3975 uint64_t rac : 1; /**< RAC State */ 3976 uint64_t csm1 : 15; /**< CSM1 State */ 3977 uint64_t csm0 : 15; /**< CSM0 State */ 3978 uint64_t nnp0 : 8; /**< NNP0 State */ 3979 uint64_t nnd : 8; /**< NND State */ 3980#else 3981 uint64_t nnd : 8; 3982 uint64_t nnp0 : 8; 3983 uint64_t csm0 : 15; 3984 uint64_t csm1 : 15; 3985 uint64_t rac : 1; 3986 uint64_t reserved_47_47 : 1; 3987 uint64_t nnp1 : 8; 3988 uint64_t reserved_56_63 : 8; 3989#endif 3990 } s; 3991 struct cvmx_sli_state2_s cn63xx; 3992 struct cvmx_sli_state2_s cn63xxp1; 3993}; 3994typedef union cvmx_sli_state2 cvmx_sli_state2_t; 3995 3996/** 3997 * cvmx_sli_state3 3998 * 3999 * SLI_STATE3 = SLI State 3 4000 * 4001 * State machines in SLI. For debug. 4002 */ 4003union cvmx_sli_state3 4004{ 4005 uint64_t u64; 4006 struct cvmx_sli_state3_s 4007 { 4008#if __BYTE_ORDER == __BIG_ENDIAN 4009 uint64_t reserved_56_63 : 8; 4010 uint64_t psm1 : 15; /**< PSM1 State */ 4011 uint64_t psm0 : 15; /**< PSM0 State */ 4012 uint64_t nsm1 : 13; /**< NSM1 State */ 4013 uint64_t nsm0 : 13; /**< NSM0 State */ 4014#else 4015 uint64_t nsm0 : 13; 4016 uint64_t nsm1 : 13; 4017 uint64_t psm0 : 15; 4018 uint64_t psm1 : 15; 4019 uint64_t reserved_56_63 : 8; 4020#endif 4021 } s; 4022 struct cvmx_sli_state3_s cn63xx; 4023 struct cvmx_sli_state3_s cn63xxp1; 4024}; 4025typedef union cvmx_sli_state3 cvmx_sli_state3_t; 4026 4027/** 4028 * cvmx_sli_win_rd_addr 4029 * 4030 * SLI_WIN_RD_ADDR = SLI Window Read Address Register 4031 * 4032 * The address to be read when the SLI_WIN_RD_DATA register is read. 4033 * This register should NOT be used to read SLI_* registers. 4034 */ 4035union cvmx_sli_win_rd_addr 4036{ 4037 uint64_t u64; 4038 struct cvmx_sli_win_rd_addr_s 4039 { 4040#if __BYTE_ORDER == __BIG_ENDIAN 4041 uint64_t reserved_51_63 : 13; 4042 uint64_t ld_cmd : 2; /**< The load command sent wit hthe read. 4043 0x3 == Load 8-bytes, 0x2 == Load 4-bytes, 4044 0x1 == Load 2-bytes, 0x0 == Load 1-bytes, */ 4045 uint64_t iobit : 1; /**< A 1 or 0 can be written here but will not be used 4046 in address generation. */ 4047 uint64_t rd_addr : 48; /**< The address to be read from. 4048 [47:40] = NCB_ID 4049 [39:0] = Address 4050 When [47:43] == SLI & [42:40] == 0 bits [39:0] are: 4051 [39:32] == x, Not Used 4052 [31:24] == RSL_ID 4053 [23:0] == RSL Register Offset */ 4054#else 4055 uint64_t rd_addr : 48; 4056 uint64_t iobit : 1; 4057 uint64_t ld_cmd : 2; 4058 uint64_t reserved_51_63 : 13; 4059#endif 4060 } s; 4061 struct cvmx_sli_win_rd_addr_s cn63xx; 4062 struct cvmx_sli_win_rd_addr_s cn63xxp1; 4063}; 4064typedef union cvmx_sli_win_rd_addr cvmx_sli_win_rd_addr_t; 4065 4066/** 4067 * cvmx_sli_win_rd_data 4068 * 4069 * SLI_WIN_RD_DATA = SLI Window Read Data Register 4070 * 4071 * Reading this register causes a window read operation to take place. Address read is that contained in the SLI_WIN_RD_ADDR 4072 * register. 4073 */ 4074union cvmx_sli_win_rd_data 4075{ 4076 uint64_t u64; 4077 struct cvmx_sli_win_rd_data_s 4078 { 4079#if __BYTE_ORDER == __BIG_ENDIAN 4080 uint64_t rd_data : 64; /**< The read data. */ 4081#else 4082 uint64_t rd_data : 64; 4083#endif 4084 } s; 4085 struct cvmx_sli_win_rd_data_s cn63xx; 4086 struct cvmx_sli_win_rd_data_s cn63xxp1; 4087}; 4088typedef union cvmx_sli_win_rd_data cvmx_sli_win_rd_data_t; 4089 4090/** 4091 * cvmx_sli_win_wr_addr 4092 * 4093 * Add Lock Register (Set on Read, Clear on write), SW uses to control access to BAR0 space. 4094 * 4095 * Total Address is 16Kb; 0x0000 - 0x3fff, 0x000 - 0x7fe(Reg, every other 8B) 4096 * 4097 * General 5kb; 0x0000 - 0x13ff, 0x000 - 0x27e(Reg-General) 4098 * PktMem 10Kb; 0x1400 - 0x3bff, 0x280 - 0x77e(Reg-General-Packet) 4099 * Rsvd 1Kb; 0x3c00 - 0x3fff, 0x780 - 0x7fe(Reg-NCB Only Mode) 4100 * 4101 * SLI_WIN_WR_ADDR = SLI Window Write Address Register 4102 * 4103 * Contains the address to be writen to when a write operation is started by writing the 4104 * SLI_WIN_WR_DATA register (see below). 4105 * 4106 * This register should NOT be used to write SLI_* registers. 4107 */ 4108union cvmx_sli_win_wr_addr 4109{ 4110 uint64_t u64; 4111 struct cvmx_sli_win_wr_addr_s 4112 { 4113#if __BYTE_ORDER == __BIG_ENDIAN 4114 uint64_t reserved_49_63 : 15; 4115 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4116 read as '0'. */ 4117 uint64_t wr_addr : 45; /**< The address that will be written to when the 4118 SLI_WIN_WR_DATA register is written. 4119 [47:40] = NCB_ID 4120 [39:3] = Address 4121 When [47:43] == SLI & [42:40] == 0 bits [39:0] are: 4122 [39:32] == x, Not Used 4123 [31:24] == RSL_ID 4124 [23:3] == RSL Register Offset */ 4125 uint64_t reserved_0_2 : 3; 4126#else 4127 uint64_t reserved_0_2 : 3; 4128 uint64_t wr_addr : 45; 4129 uint64_t iobit : 1; 4130 uint64_t reserved_49_63 : 15; 4131#endif 4132 } s; 4133 struct cvmx_sli_win_wr_addr_s cn63xx; 4134 struct cvmx_sli_win_wr_addr_s cn63xxp1; 4135}; 4136typedef union cvmx_sli_win_wr_addr cvmx_sli_win_wr_addr_t; 4137 4138/** 4139 * cvmx_sli_win_wr_data 4140 * 4141 * SLI_WIN_WR_DATA = SLI Window Write Data Register 4142 * 4143 * Contains the data to write to the address located in the SLI_WIN_WR_ADDR Register. 4144 * Writing the least-significant-byte of this register will cause a write operation to take place. 4145 */ 4146union cvmx_sli_win_wr_data 4147{ 4148 uint64_t u64; 4149 struct cvmx_sli_win_wr_data_s 4150 { 4151#if __BYTE_ORDER == __BIG_ENDIAN 4152 uint64_t wr_data : 64; /**< The data to be written. Whenever the LSB of this 4153 register is written, the Window Write will take 4154 place. */ 4155#else 4156 uint64_t wr_data : 64; 4157#endif 4158 } s; 4159 struct cvmx_sli_win_wr_data_s cn63xx; 4160 struct cvmx_sli_win_wr_data_s cn63xxp1; 4161}; 4162typedef union cvmx_sli_win_wr_data cvmx_sli_win_wr_data_t; 4163 4164/** 4165 * cvmx_sli_win_wr_mask 4166 * 4167 * SLI_WIN_WR_MASK = SLI Window Write Mask Register 4168 * 4169 * Contains the mask for the data in the SLI_WIN_WR_DATA Register. 4170 */ 4171union cvmx_sli_win_wr_mask 4172{ 4173 uint64_t u64; 4174 struct cvmx_sli_win_wr_mask_s 4175 { 4176#if __BYTE_ORDER == __BIG_ENDIAN 4177 uint64_t reserved_8_63 : 56; 4178 uint64_t wr_mask : 8; /**< The data to be written. When a bit is '1' 4179 the corresponding byte will be written. The values 4180 of this field must be contiguos and for 1, 2, 4, or 4181 8 byte operations and aligned to operation size. 4182 A Value of 0 will produce unpredictable results */ 4183#else 4184 uint64_t wr_mask : 8; 4185 uint64_t reserved_8_63 : 56; 4186#endif 4187 } s; 4188 struct cvmx_sli_win_wr_mask_s cn63xx; 4189 struct cvmx_sli_win_wr_mask_s cn63xxp1; 4190}; 4191typedef union cvmx_sli_win_wr_mask cvmx_sli_win_wr_mask_t; 4192 4193/** 4194 * cvmx_sli_window_ctl 4195 * 4196 * // * 4197 * // * 81e0 - 82d0 Reserved for future subids 4198 * // * 4199 * 4200 * SLI_WINDOW_CTL = SLI's Window Control 4201 * 4202 * Access to register space on the NCB (caused by Window Reads/Writes) will wait for a period of time specified 4203 * by this register before timeing out. Because a Window Access can access the RML, which has a fixed timeout of 0xFFFF 4204 * core clocks, the value of this register should be set to a minimum of 0x200000 to ensure that a timeout to an RML register 4205 * occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from the MAC. 4206 */ 4207union cvmx_sli_window_ctl 4208{ 4209 uint64_t u64; 4210 struct cvmx_sli_window_ctl_s 4211 { 4212#if __BYTE_ORDER == __BIG_ENDIAN 4213 uint64_t reserved_32_63 : 32; 4214 uint64_t time : 32; /**< Time to wait in core clocks for a 4215 BAR0 access to completeon the NCB 4216 before timing out. A value of 0 will cause no 4217 timeouts. A minimum value of 0x200000 should be 4218 used when this register is not set to 0x0. */ 4219#else 4220 uint64_t time : 32; 4221 uint64_t reserved_32_63 : 32; 4222#endif 4223 } s; 4224 struct cvmx_sli_window_ctl_s cn63xx; 4225 struct cvmx_sli_window_ctl_s cn63xxp1; 4226}; 4227typedef union cvmx_sli_window_ctl cvmx_sli_window_ctl_t; 4228 4229#endif 4230