cvmx-pescx-defs.h revision 215990
154359Sroberto/***********************license start*************** 254359Sroberto * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 354359Sroberto * reserved. 454359Sroberto * 554359Sroberto * 654359Sroberto * Redistribution and use in source and binary forms, with or without 754359Sroberto * modification, are permitted provided that the following conditions are 854359Sroberto * met: 954359Sroberto * 1054359Sroberto * * Redistributions of source code must retain the above copyright 1154359Sroberto * notice, this list of conditions and the following disclaimer. 1254359Sroberto * 1354359Sroberto * * Redistributions in binary form must reproduce the above 1454359Sroberto * copyright notice, this list of conditions and the following 1554359Sroberto * disclaimer in the documentation and/or other materials provided 1654359Sroberto * with the distribution. 1754359Sroberto 1854359Sroberto * * Neither the name of Cavium Networks nor the names of 1954359Sroberto * its contributors may be used to endorse or promote products 2054359Sroberto * derived from this software without specific prior written 2154359Sroberto * permission. 2254359Sroberto 2354359Sroberto * This Software, including technical data, may be subject to U.S. export control 2454359Sroberto * laws, including the U.S. Export Administration Act and its associated 2554359Sroberto * regulations, and may be subject to export or import regulations in other 2682498Sroberto * countries. 2782498Sroberto 2882498Sroberto * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 2954359Sroberto * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 3054359Sroberto * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 3154359Sroberto * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 3254359Sroberto * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 3354359Sroberto * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 3454359Sroberto * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 3554359Sroberto * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 3654359Sroberto * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 3754359Sroberto * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 3854359Sroberto ***********************license end**************************************/ 3954359Sroberto 4054359Sroberto 4154359Sroberto/** 4254359Sroberto * cvmx-pescx-defs.h 4354359Sroberto * 4454359Sroberto * Configuration and status register (CSR) type definitions for 4554359Sroberto * Octeon pescx. 4654359Sroberto * 4754359Sroberto * This file is auto generated. Do not edit. 4854359Sroberto * 4954359Sroberto * <hr>$Revision$<hr> 5054359Sroberto * 5154359Sroberto */ 5254359Sroberto#ifndef __CVMX_PESCX_TYPEDEFS_H__ 5354359Sroberto#define __CVMX_PESCX_TYPEDEFS_H__ 5454359Sroberto 5554359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 5654359Srobertostatic inline uint64_t CVMX_PESCX_BIST_STATUS(unsigned long block_id) 5754359Sroberto{ 5854359Sroberto if (!( 5954359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 6054359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 6154359Sroberto cvmx_warn("CVMX_PESCX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 6254359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull; 6354359Sroberto} 6454359Sroberto#else 6554359Sroberto#define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull) 6654359Sroberto#endif 6754359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 6854359Srobertostatic inline uint64_t CVMX_PESCX_BIST_STATUS2(unsigned long block_id) 6954359Sroberto{ 7054359Sroberto if (!( 7154359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 7254359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 7354359Sroberto cvmx_warn("CVMX_PESCX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id); 7454359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull; 7554359Sroberto} 7654359Sroberto#else 7754359Sroberto#define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull) 7854359Sroberto#endif 7954359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 8054359Srobertostatic inline uint64_t CVMX_PESCX_CFG_RD(unsigned long block_id) 8154359Sroberto{ 8254359Sroberto if (!( 8354359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 8454359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 8554359Sroberto cvmx_warn("CVMX_PESCX_CFG_RD(%lu) is invalid on this chip\n", block_id); 8654359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull; 8754359Sroberto} 8854359Sroberto#else 8954359Sroberto#define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull) 9054359Sroberto#endif 9154359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 9254359Srobertostatic inline uint64_t CVMX_PESCX_CFG_WR(unsigned long block_id) 9354359Sroberto{ 9454359Sroberto if (!( 9554359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 9654359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 9754359Sroberto cvmx_warn("CVMX_PESCX_CFG_WR(%lu) is invalid on this chip\n", block_id); 9854359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull; 9954359Sroberto} 10054359Sroberto#else 10154359Sroberto#define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull) 10254359Sroberto#endif 10354359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 10454359Srobertostatic inline uint64_t CVMX_PESCX_CPL_LUT_VALID(unsigned long block_id) 10554359Sroberto{ 10654359Sroberto if (!( 10754359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 10854359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 10954359Sroberto cvmx_warn("CVMX_PESCX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id); 11054359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull; 11154359Sroberto} 11254359Sroberto#else 11354359Sroberto#define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull) 11454359Sroberto#endif 11554359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 11654359Srobertostatic inline uint64_t CVMX_PESCX_CTL_STATUS(unsigned long block_id) 11754359Sroberto{ 11882498Sroberto if (!( 11982498Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 12054359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 12154359Sroberto cvmx_warn("CVMX_PESCX_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 122182007Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull; 12354359Sroberto} 12454359Sroberto#else 12554359Sroberto#define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull) 12654359Sroberto#endif 12754359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 12854359Srobertostatic inline uint64_t CVMX_PESCX_CTL_STATUS2(unsigned long block_id) 12954359Sroberto{ 13054359Sroberto if (!( 13154359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 13254359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 13354359Sroberto cvmx_warn("CVMX_PESCX_CTL_STATUS2(%lu) is invalid on this chip\n", block_id); 13454359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull; 13554359Sroberto} 13654359Sroberto#else 13754359Sroberto#define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull) 13854359Sroberto#endif 13954359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 14054359Srobertostatic inline uint64_t CVMX_PESCX_DBG_INFO(unsigned long block_id) 14154359Sroberto{ 14254359Sroberto if (!( 14354359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 14454359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 14554359Sroberto cvmx_warn("CVMX_PESCX_DBG_INFO(%lu) is invalid on this chip\n", block_id); 14654359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull; 14754359Sroberto} 14854359Sroberto#else 14954359Sroberto#define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull) 15054359Sroberto#endif 15154359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 15254359Srobertostatic inline uint64_t CVMX_PESCX_DBG_INFO_EN(unsigned long block_id) 15354359Sroberto{ 15454359Sroberto if (!( 15554359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 15654359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 15754359Sroberto cvmx_warn("CVMX_PESCX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id); 15854359Sroberto return CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull; 15954359Sroberto} 16054359Sroberto#else 16154359Sroberto#define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull) 16254359Sroberto#endif 16354359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 16454359Srobertostatic inline uint64_t CVMX_PESCX_DIAG_STATUS(unsigned long block_id) 16554359Sroberto{ 16654359Sroberto if (!( 16754359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 16854359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 16954359Sroberto cvmx_warn("CVMX_PESCX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id); 17054359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull; 17154359Sroberto} 17254359Sroberto#else 17354359Sroberto#define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull) 17454359Sroberto#endif 17554359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 17654359Srobertostatic inline uint64_t CVMX_PESCX_P2N_BAR0_START(unsigned long block_id) 17754359Sroberto{ 17854359Sroberto if (!( 17954359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 18054359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 18154359Sroberto cvmx_warn("CVMX_PESCX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id); 18254359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull; 18354359Sroberto} 18454359Sroberto#else 18554359Sroberto#define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull) 18654359Sroberto#endif 18754359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 18854359Srobertostatic inline uint64_t CVMX_PESCX_P2N_BAR1_START(unsigned long block_id) 18954359Sroberto{ 19054359Sroberto if (!( 19154359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 19254359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 19354359Sroberto cvmx_warn("CVMX_PESCX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id); 19454359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull; 19554359Sroberto} 19654359Sroberto#else 19754359Sroberto#define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull) 19854359Sroberto#endif 19954359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 20054359Srobertostatic inline uint64_t CVMX_PESCX_P2N_BAR2_START(unsigned long block_id) 20154359Sroberto{ 20254359Sroberto if (!( 20354359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 20454359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 20554359Sroberto cvmx_warn("CVMX_PESCX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id); 20654359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull; 20754359Sroberto} 20854359Sroberto#else 20954359Sroberto#define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull) 21054359Sroberto#endif 21154359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 21254359Srobertostatic inline uint64_t CVMX_PESCX_P2P_BARX_END(unsigned long offset, unsigned long block_id) 21354359Sroberto{ 21454359Sroberto if (!( 21554359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1)))) || 21654359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))))) 21754359Sroberto cvmx_warn("CVMX_PESCX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id); 21854359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16; 21954359Sroberto} 22054359Sroberto#else 22154359Sroberto#define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16) 22254359Sroberto#endif 22354359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 22454359Srobertostatic inline uint64_t CVMX_PESCX_P2P_BARX_START(unsigned long offset, unsigned long block_id) 22554359Sroberto{ 22654359Sroberto if (!( 22754359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset <= 3)) && ((block_id <= 1)))) || 22854359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset <= 3)) && ((block_id <= 1)))))) 22954359Sroberto cvmx_warn("CVMX_PESCX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id); 23054359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16; 23154359Sroberto} 23254359Sroberto#else 23354359Sroberto#define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16) 23454359Sroberto#endif 23554359Sroberto#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 23654359Srobertostatic inline uint64_t CVMX_PESCX_TLP_CREDITS(unsigned long block_id) 237182007Sroberto{ 23854359Sroberto if (!( 23954359Sroberto (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 24054359Sroberto (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))))) 24154359Sroberto cvmx_warn("CVMX_PESCX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id); 24254359Sroberto return CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull; 24354359Sroberto} 24454359Sroberto#else 24554359Sroberto#define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull) 24654359Sroberto#endif 24754359Sroberto 248182007Sroberto/** 249182007Sroberto * cvmx_pesc#_bist_status 250182007Sroberto * 251182007Sroberto * PESC_BIST_STATUS = PESC Bist Status 252182007Sroberto * 253182007Sroberto * Contains the diffrent interrupt summary bits of the PESC. 254182007Sroberto */ 255182007Srobertounion cvmx_pescx_bist_status 256182007Sroberto{ 257182007Sroberto uint64_t u64; 25854359Sroberto struct cvmx_pescx_bist_status_s 25954359Sroberto { 26054359Sroberto#if __BYTE_ORDER == __BIG_ENDIAN 26154359Sroberto uint64_t reserved_13_63 : 51; 26254359Sroberto uint64_t rqdata5 : 1; /**< Rx Queue Data Memory5. */ 26354359Sroberto uint64_t ctlp_or : 1; /**< C-TLP Order Fifo. */ 26454359Sroberto uint64_t ntlp_or : 1; /**< N-TLP Order Fifo. */ 26554359Sroberto uint64_t ptlp_or : 1; /**< P-TLP Order Fifo. */ 26654359Sroberto uint64_t retry : 1; /**< Retry Buffer. */ 26754359Sroberto uint64_t rqdata0 : 1; /**< Rx Queue Data Memory0. */ 26854359Sroberto uint64_t rqdata1 : 1; /**< Rx Queue Data Memory1. */ 26954359Sroberto uint64_t rqdata2 : 1; /**< Rx Queue Data Memory2. */ 27054359Sroberto uint64_t rqdata3 : 1; /**< Rx Queue Data Memory3. */ 27154359Sroberto uint64_t rqdata4 : 1; /**< Rx Queue Data Memory4. */ 27254359Sroberto uint64_t rqhdr1 : 1; /**< Rx Queue Header1. */ 27354359Sroberto uint64_t rqhdr0 : 1; /**< Rx Queue Header0. */ 27454359Sroberto uint64_t sot : 1; /**< SOT Buffer. */ 275182007Sroberto#else 27654359Sroberto uint64_t sot : 1; 27754359Sroberto uint64_t rqhdr0 : 1; 27854359Sroberto uint64_t rqhdr1 : 1; 27954359Sroberto uint64_t rqdata4 : 1; 28054359Sroberto uint64_t rqdata3 : 1; 28154359Sroberto uint64_t rqdata2 : 1; 28254359Sroberto uint64_t rqdata1 : 1; 28354359Sroberto uint64_t rqdata0 : 1; 28454359Sroberto uint64_t retry : 1; 28554359Sroberto uint64_t ptlp_or : 1; 28654359Sroberto uint64_t ntlp_or : 1; 28754359Sroberto uint64_t ctlp_or : 1; 28854359Sroberto uint64_t rqdata5 : 1; 28954359Sroberto uint64_t reserved_13_63 : 51; 29054359Sroberto#endif 29154359Sroberto } s; 29254359Sroberto struct cvmx_pescx_bist_status_s cn52xx; 29354359Sroberto struct cvmx_pescx_bist_status_cn52xxp1 29454359Sroberto { 29554359Sroberto#if __BYTE_ORDER == __BIG_ENDIAN 29654359Sroberto uint64_t reserved_12_63 : 52; 29754359Sroberto uint64_t ctlp_or : 1; /**< C-TLP Order Fifo. */ 29854359Sroberto uint64_t ntlp_or : 1; /**< N-TLP Order Fifo. */ 29954359Sroberto uint64_t ptlp_or : 1; /**< P-TLP Order Fifo. */ 30054359Sroberto uint64_t retry : 1; /**< Retry Buffer. */ 30154359Sroberto uint64_t rqdata0 : 1; /**< Rx Queue Data Memory0. */ 30254359Sroberto uint64_t rqdata1 : 1; /**< Rx Queue Data Memory1. */ 30354359Sroberto uint64_t rqdata2 : 1; /**< Rx Queue Data Memory2. */ 30454359Sroberto uint64_t rqdata3 : 1; /**< Rx Queue Data Memory3. */ 30554359Sroberto uint64_t rqdata4 : 1; /**< Rx Queue Data Memory4. */ 30654359Sroberto uint64_t rqhdr1 : 1; /**< Rx Queue Header1. */ 30754359Sroberto uint64_t rqhdr0 : 1; /**< Rx Queue Header0. */ 30854359Sroberto uint64_t sot : 1; /**< SOT Buffer. */ 30982498Sroberto#else 31082498Sroberto uint64_t sot : 1; 31182498Sroberto uint64_t rqhdr0 : 1; 31282498Sroberto uint64_t rqhdr1 : 1; 31354359Sroberto uint64_t rqdata4 : 1; 31454359Sroberto uint64_t rqdata3 : 1; 31554359Sroberto uint64_t rqdata2 : 1; 31654359Sroberto uint64_t rqdata1 : 1; 31754359Sroberto uint64_t rqdata0 : 1; 31854359Sroberto uint64_t retry : 1; 31954359Sroberto uint64_t ptlp_or : 1; 32054359Sroberto uint64_t ntlp_or : 1; 32154359Sroberto uint64_t ctlp_or : 1; 32254359Sroberto uint64_t reserved_12_63 : 52; 32354359Sroberto#endif 32454359Sroberto } cn52xxp1; 32554359Sroberto struct cvmx_pescx_bist_status_s cn56xx; 32654359Sroberto struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1; 32754359Sroberto}; 32854359Srobertotypedef union cvmx_pescx_bist_status cvmx_pescx_bist_status_t; 32954359Sroberto 33054359Sroberto/** 33154359Sroberto * cvmx_pesc#_bist_status2 33254359Sroberto * 33354359Sroberto * PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register 33454359Sroberto * 33554359Sroberto * Results from BIST runs of PESC's memories. 33654359Sroberto */ 33754359Srobertounion cvmx_pescx_bist_status2 33854359Sroberto{ 33954359Sroberto uint64_t u64; 34054359Sroberto struct cvmx_pescx_bist_status2_s 34154359Sroberto { 34254359Sroberto#if __BYTE_ORDER == __BIG_ENDIAN 34354359Sroberto uint64_t reserved_14_63 : 50; 34454359Sroberto uint64_t cto_p2e : 1; /**< BIST Status for the cto_p2e_fifo */ 34554359Sroberto uint64_t e2p_cpl : 1; /**< BIST Status for the e2p_cpl_fifo */ 34654359Sroberto uint64_t e2p_n : 1; /**< BIST Status for the e2p_n_fifo */ 34754359Sroberto uint64_t e2p_p : 1; /**< BIST Status for the e2p_p_fifo */ 34854359Sroberto uint64_t e2p_rsl : 1; /**< BIST Status for the e2p_rsl__fifo */ 34954359Sroberto uint64_t dbg_p2e : 1; /**< BIST Status for the dbg_p2e_fifo */ 35054359Sroberto uint64_t peai_p2e : 1; /**< BIST Status for the peai__pesc_fifo */ 35154359Sroberto uint64_t rsl_p2e : 1; /**< BIST Status for the rsl_p2e_fifo */ 35254359Sroberto uint64_t pef_tpf1 : 1; /**< BIST Status for the pef_tlp_p_fifo1 */ 35354359Sroberto uint64_t pef_tpf0 : 1; /**< BIST Status for the pef_tlp_p_fifo0 */ 35454359Sroberto uint64_t pef_tnf : 1; /**< BIST Status for the pef_tlp_n_fifo */ 35554359Sroberto uint64_t pef_tcf1 : 1; /**< BIST Status for the pef_tlp_cpl_fifo1 */ 35654359Sroberto uint64_t pef_tc0 : 1; /**< BIST Status for the pef_tlp_cpl_fifo0 */ 35754359Sroberto uint64_t ppf : 1; /**< BIST Status for the ppf_fifo */ 35854359Sroberto#else 35954359Sroberto uint64_t ppf : 1; 36054359Sroberto uint64_t pef_tc0 : 1; 36154359Sroberto uint64_t pef_tcf1 : 1; 36254359Sroberto uint64_t pef_tnf : 1; 36354359Sroberto uint64_t pef_tpf0 : 1; 36454359Sroberto uint64_t pef_tpf1 : 1; 36554359Sroberto uint64_t rsl_p2e : 1; 36654359Sroberto uint64_t peai_p2e : 1; 36754359Sroberto uint64_t dbg_p2e : 1; 36854359Sroberto uint64_t e2p_rsl : 1; 36954359Sroberto uint64_t e2p_p : 1; 37054359Sroberto uint64_t e2p_n : 1; 37154359Sroberto uint64_t e2p_cpl : 1; 37254359Sroberto uint64_t cto_p2e : 1; 37354359Sroberto uint64_t reserved_14_63 : 50; 37454359Sroberto#endif 37554359Sroberto } s; 37654359Sroberto struct cvmx_pescx_bist_status2_s cn52xx; 37754359Sroberto struct cvmx_pescx_bist_status2_s cn52xxp1; 37854359Sroberto struct cvmx_pescx_bist_status2_s cn56xx; 37954359Sroberto struct cvmx_pescx_bist_status2_s cn56xxp1; 38054359Sroberto}; 38154359Srobertotypedef union cvmx_pescx_bist_status2 cvmx_pescx_bist_status2_t; 38254359Sroberto 38354359Sroberto/** 38454359Sroberto * cvmx_pesc#_cfg_rd 38554359Sroberto * 38654359Sroberto * PESC_CFG_RD = PESC Configuration Read 38754359Sroberto * 38854359Sroberto * Allows read access to the configuration in the PCIe Core. 38954359Sroberto */ 39054359Srobertounion cvmx_pescx_cfg_rd 39154359Sroberto{ 39254359Sroberto uint64_t u64; 39354359Sroberto struct cvmx_pescx_cfg_rd_s 39454359Sroberto { 39554359Sroberto#if __BYTE_ORDER == __BIG_ENDIAN 39654359Sroberto uint64_t data : 32; /**< Data. */ 39754359Sroberto uint64_t addr : 32; /**< Address to read. A write to this register 39854359Sroberto starts a read operation. */ 39954359Sroberto#else 40054359Sroberto uint64_t addr : 32; 40154359Sroberto uint64_t data : 32; 40254359Sroberto#endif 40354359Sroberto } s; 40454359Sroberto struct cvmx_pescx_cfg_rd_s cn52xx; 40554359Sroberto struct cvmx_pescx_cfg_rd_s cn52xxp1; 40654359Sroberto struct cvmx_pescx_cfg_rd_s cn56xx; 40754359Sroberto struct cvmx_pescx_cfg_rd_s cn56xxp1; 40854359Sroberto}; 40954359Srobertotypedef union cvmx_pescx_cfg_rd cvmx_pescx_cfg_rd_t; 41054359Sroberto 41154359Sroberto/** 41254359Sroberto * cvmx_pesc#_cfg_wr 41354359Sroberto * 41454359Sroberto * PESC_CFG_WR = PESC Configuration Write 41554359Sroberto * 41654359Sroberto * Allows write access to the configuration in the PCIe Core. 41754359Sroberto */ 41854359Srobertounion cvmx_pescx_cfg_wr 41954359Sroberto{ 42054359Sroberto uint64_t u64; 42154359Sroberto struct cvmx_pescx_cfg_wr_s 42254359Sroberto { 42354359Sroberto#if __BYTE_ORDER == __BIG_ENDIAN 42454359Sroberto uint64_t data : 32; /**< Data to write. A write to this register starts 42554359Sroberto a write operation. */ 42654359Sroberto uint64_t addr : 32; /**< Address to write. A write to this register starts 42754359Sroberto a write operation. */ 42854359Sroberto#else 42954359Sroberto uint64_t addr : 32; 43054359Sroberto uint64_t data : 32; 43154359Sroberto#endif 43254359Sroberto } s; 43354359Sroberto struct cvmx_pescx_cfg_wr_s cn52xx; 43454359Sroberto struct cvmx_pescx_cfg_wr_s cn52xxp1; 43554359Sroberto struct cvmx_pescx_cfg_wr_s cn56xx; 43654359Sroberto struct cvmx_pescx_cfg_wr_s cn56xxp1; 43754359Sroberto}; 43854359Srobertotypedef union cvmx_pescx_cfg_wr cvmx_pescx_cfg_wr_t; 43954359Sroberto 44054359Sroberto/** 44154359Sroberto * cvmx_pesc#_cpl_lut_valid 44254359Sroberto * 44382498Sroberto * PESC_CPL_LUT_VALID = PESC Cmpletion Lookup Table Valid 44454359Sroberto * 44554359Sroberto * Bit set for outstanding tag read. 44654359Sroberto */ 44754359Srobertounion cvmx_pescx_cpl_lut_valid 44854359Sroberto{ 44954359Sroberto uint64_t u64; 45054359Sroberto struct cvmx_pescx_cpl_lut_valid_s 45154359Sroberto { 45254359Sroberto#if __BYTE_ORDER == __BIG_ENDIAN 45354359Sroberto uint64_t reserved_32_63 : 32; 45454359Sroberto uint64_t tag : 32; /**< Bit vector set cooresponds to an outstanding tag 45554359Sroberto expecting a completion. */ 45682498Sroberto#else 45754359Sroberto uint64_t tag : 32; 45854359Sroberto uint64_t reserved_32_63 : 32; 45982498Sroberto#endif 46054359Sroberto } s; 46154359Sroberto struct cvmx_pescx_cpl_lut_valid_s cn52xx; 46254359Sroberto struct cvmx_pescx_cpl_lut_valid_s cn52xxp1; 46354359Sroberto struct cvmx_pescx_cpl_lut_valid_s cn56xx; 46454359Sroberto struct cvmx_pescx_cpl_lut_valid_s cn56xxp1; 46554359Sroberto}; 46654359Srobertotypedef union cvmx_pescx_cpl_lut_valid cvmx_pescx_cpl_lut_valid_t; 46754359Sroberto 46854359Sroberto/** 46954359Sroberto * cvmx_pesc#_ctl_status 47054359Sroberto * 47154359Sroberto * PESC_CTL_STATUS = PESC Control Status 47282498Sroberto * 47354359Sroberto * General control and status of the PESC. 47454359Sroberto */ 47554359Srobertounion cvmx_pescx_ctl_status 47654359Sroberto{ 47754359Sroberto uint64_t u64; 47854359Sroberto struct cvmx_pescx_ctl_status_s 47954359Sroberto { 48054359Sroberto#if __BYTE_ORDER == __BIG_ENDIAN 48154359Sroberto uint64_t reserved_28_63 : 36; 48254359Sroberto uint64_t dnum : 5; /**< Primary bus device number. */ 48354359Sroberto uint64_t pbus : 8; /**< Primary bus number. */ 48454359Sroberto uint64_t qlm_cfg : 2; /**< The QLM configuration pad bits. */ 48554359Sroberto uint64_t lane_swp : 1; /**< Lane Swap. For PEDC1, when 0 NO LANE SWAP when '1' 48654359Sroberto enables LANE SWAP. THis bit has no effect on PEDC0. 48754359Sroberto This bit should be set before enabling PEDC1. */ 48854359Sroberto uint64_t pm_xtoff : 1; /**< When WRITTEN with a '1' a single cycle pulse is 48954359Sroberto to the PCIe core pm_xmt_turnoff port. RC mode. */ 49054359Sroberto uint64_t pm_xpme : 1; /**< When WRITTEN with a '1' a single cycle pulse is 49154359Sroberto to the PCIe core pm_xmt_pme port. EP mode. */ 49254359Sroberto uint64_t ob_p_cmd : 1; /**< When WRITTEN with a '1' a single cycle pulse is 49354359Sroberto to the PCIe core outband_pwrup_cmd port. EP mode. */ 49454359Sroberto uint64_t reserved_7_8 : 2; 49554359Sroberto uint64_t nf_ecrc : 1; /**< Do not forward peer-to-peer ECRC TLPs. */ 49654359Sroberto uint64_t dly_one : 1; /**< When set the output client state machines will 49754359Sroberto wait one cycle before starting a new TLP out. */ 49854359Sroberto uint64_t lnk_enb : 1; /**< When set '1' the link is enabled when '0' the 49954359Sroberto link is disabled. This bit only is active when in 50054359Sroberto RC mode. */ 50154359Sroberto uint64_t ro_ctlp : 1; /**< When set '1' C-TLPs that have the RO bit set will 50254359Sroberto not wait for P-TLPs that normaly would be sent 50354359Sroberto first. */ 50454359Sroberto uint64_t reserved_2_2 : 1; 50554359Sroberto uint64_t inv_ecrc : 1; /**< When '1' causes the LSB of the ECRC to be inverted. */ 50654359Sroberto uint64_t inv_lcrc : 1; /**< When '1' causes the LSB of the LCRC to be inverted. */ 50754359Sroberto#else 50854359Sroberto uint64_t inv_lcrc : 1; 50954359Sroberto uint64_t inv_ecrc : 1; 51054359Sroberto uint64_t reserved_2_2 : 1; 51154359Sroberto uint64_t ro_ctlp : 1; 51254359Sroberto uint64_t lnk_enb : 1; 51354359Sroberto uint64_t dly_one : 1; 51454359Sroberto uint64_t nf_ecrc : 1; 51554359Sroberto uint64_t reserved_7_8 : 2; 51654359Sroberto uint64_t ob_p_cmd : 1; 51754359Sroberto uint64_t pm_xpme : 1; 51854359Sroberto uint64_t pm_xtoff : 1; 51954359Sroberto uint64_t lane_swp : 1; 52054359Sroberto uint64_t qlm_cfg : 2; 52154359Sroberto uint64_t pbus : 8; 52254359Sroberto uint64_t dnum : 5; 52354359Sroberto uint64_t reserved_28_63 : 36; 52454359Sroberto#endif 52554359Sroberto } s; 52654359Sroberto struct cvmx_pescx_ctl_status_s cn52xx; 52754359Sroberto struct cvmx_pescx_ctl_status_s cn52xxp1; 52854359Sroberto struct cvmx_pescx_ctl_status_cn56xx 52954359Sroberto { 53054359Sroberto#if __BYTE_ORDER == __BIG_ENDIAN 53154359Sroberto uint64_t reserved_28_63 : 36; 53254359Sroberto uint64_t dnum : 5; /**< Primary bus device number. */ 53354359Sroberto uint64_t pbus : 8; /**< Primary bus number. */ 53454359Sroberto uint64_t qlm_cfg : 2; /**< The QLM configuration pad bits. */ 53554359Sroberto uint64_t reserved_12_12 : 1; 53654359Sroberto uint64_t pm_xtoff : 1; /**< When WRITTEN with a '1' a single cycle pulse is 53754359Sroberto to the PCIe core pm_xmt_turnoff port. RC mode. */ 53854359Sroberto uint64_t pm_xpme : 1; /**< When WRITTEN with a '1' a single cycle pulse is 53954359Sroberto to the PCIe core pm_xmt_pme port. EP mode. */ 54054359Sroberto uint64_t ob_p_cmd : 1; /**< When WRITTEN with a '1' a single cycle pulse is 54154359Sroberto to the PCIe core outband_pwrup_cmd port. EP mode. */ 54254359Sroberto uint64_t reserved_7_8 : 2; 54354359Sroberto uint64_t nf_ecrc : 1; /**< Do not forward peer-to-peer ECRC TLPs. */ 54454359Sroberto uint64_t dly_one : 1; /**< When set the output client state machines will 54554359Sroberto wait one cycle before starting a new TLP out. */ 54654359Sroberto uint64_t lnk_enb : 1; /**< When set '1' the link is enabled when '0' the 54754359Sroberto link is disabled. This bit only is active when in 54854359Sroberto RC mode. */ 54954359Sroberto uint64_t ro_ctlp : 1; /**< When set '1' C-TLPs that have the RO bit set will 55054359Sroberto not wait for P-TLPs that normaly would be sent 55154359Sroberto first. */ 55254359Sroberto uint64_t reserved_2_2 : 1; 55354359Sroberto uint64_t inv_ecrc : 1; /**< When '1' causes the LSB of the ECRC to be inverted. */ 55454359Sroberto uint64_t inv_lcrc : 1; /**< When '1' causes the LSB of the LCRC to be inverted. */ 55554359Sroberto#else 55654359Sroberto uint64_t inv_lcrc : 1; 55754359Sroberto uint64_t inv_ecrc : 1; 55854359Sroberto uint64_t reserved_2_2 : 1; 55954359Sroberto uint64_t ro_ctlp : 1; 56054359Sroberto uint64_t lnk_enb : 1; 56154359Sroberto uint64_t dly_one : 1; 56254359Sroberto uint64_t nf_ecrc : 1; 56354359Sroberto uint64_t reserved_7_8 : 2; 56454359Sroberto uint64_t ob_p_cmd : 1; 56554359Sroberto uint64_t pm_xpme : 1; 56654359Sroberto uint64_t pm_xtoff : 1; 56754359Sroberto uint64_t reserved_12_12 : 1; 56854359Sroberto uint64_t qlm_cfg : 2; 56954359Sroberto uint64_t pbus : 8; 57054359Sroberto uint64_t dnum : 5; 57154359Sroberto uint64_t reserved_28_63 : 36; 57254359Sroberto#endif 57354359Sroberto } cn56xx; 57454359Sroberto struct cvmx_pescx_ctl_status_cn56xx cn56xxp1; 57554359Sroberto}; 57654359Srobertotypedef union cvmx_pescx_ctl_status cvmx_pescx_ctl_status_t; 57754359Sroberto 57854359Sroberto/** 57954359Sroberto * cvmx_pesc#_ctl_status2 58054359Sroberto * 58154359Sroberto * Below are in PESC 58254359Sroberto * 58354359Sroberto * PESC(0..1)_BIST_STATUS2 = PESC BIST Status Register 58454359Sroberto * 58554359Sroberto * Results from BIST runs of PESC's memories. 58654359Sroberto */ 58754359Srobertounion cvmx_pescx_ctl_status2 58854359Sroberto{ 58954359Sroberto uint64_t u64; 59054359Sroberto struct cvmx_pescx_ctl_status2_s 59154359Sroberto { 59254359Sroberto#if __BYTE_ORDER == __BIG_ENDIAN 59354359Sroberto uint64_t reserved_2_63 : 62; 59454359Sroberto uint64_t pclk_run : 1; /**< When the pce_clk is running this bit will be '1'. 59554359Sroberto Writing a '1' to this location will cause the 59654359Sroberto bit to be cleared, but if the pce_clk is running 59754359Sroberto this bit will be re-set. */ 59854359Sroberto uint64_t pcierst : 1; /**< Set to '1' when PCIe is in reset. */ 59954359Sroberto#else 60054359Sroberto uint64_t pcierst : 1; 60154359Sroberto uint64_t pclk_run : 1; 60254359Sroberto uint64_t reserved_2_63 : 62; 60354359Sroberto#endif 60454359Sroberto } s; 60554359Sroberto struct cvmx_pescx_ctl_status2_s cn52xx; 60654359Sroberto struct cvmx_pescx_ctl_status2_cn52xxp1 60754359Sroberto { 60854359Sroberto#if __BYTE_ORDER == __BIG_ENDIAN 60954359Sroberto uint64_t reserved_1_63 : 63; 61054359Sroberto uint64_t pcierst : 1; /**< Set to '1' when PCIe is in reset. */ 61154359Sroberto#else 61254359Sroberto uint64_t pcierst : 1; 61354359Sroberto uint64_t reserved_1_63 : 63; 61454359Sroberto#endif 61554359Sroberto } cn52xxp1; 61654359Sroberto struct cvmx_pescx_ctl_status2_s cn56xx; 61754359Sroberto struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1; 61854359Sroberto}; 61954359Srobertotypedef union cvmx_pescx_ctl_status2 cvmx_pescx_ctl_status2_t; 62054359Sroberto 62154359Sroberto/** 62254359Sroberto * cvmx_pesc#_dbg_info 62354359Sroberto * 62454359Sroberto * PESC(0..1)_DBG_INFO = PESC Debug Information 62554359Sroberto * 62654359Sroberto * General debug info. 62754359Sroberto */ 62854359Srobertounion cvmx_pescx_dbg_info 62954359Sroberto{ 63054359Sroberto uint64_t u64; 63154359Sroberto struct cvmx_pescx_dbg_info_s 63254359Sroberto { 63354359Sroberto#if __BYTE_ORDER == __BIG_ENDIAN 63454359Sroberto uint64_t reserved_31_63 : 33; 63554359Sroberto uint64_t ecrc_e : 1; /**< Received a ECRC error. 63654359Sroberto radm_ecrc_err */ 63754359Sroberto uint64_t rawwpp : 1; /**< Received a write with poisoned payload 63854359Sroberto radm_rcvd_wreq_poisoned */ 63954359Sroberto uint64_t racpp : 1; /**< Received a completion with poisoned payload 64054359Sroberto radm_rcvd_cpl_poisoned */ 64154359Sroberto uint64_t ramtlp : 1; /**< Received a malformed TLP 64254359Sroberto radm_mlf_tlp_err */ 64354359Sroberto uint64_t rarwdns : 1; /**< Recieved a request which device does not support 64454359Sroberto radm_rcvd_ur_req */ 64554359Sroberto uint64_t caar : 1; /**< Completer aborted a request 64654359Sroberto radm_rcvd_ca_req 64754359Sroberto This bit will never be set because Octeon does 64854359Sroberto not generate Completer Aborts. */ 64954359Sroberto uint64_t racca : 1; /**< Received a completion with CA status 65054359Sroberto radm_rcvd_cpl_ca */ 65154359Sroberto uint64_t racur : 1; /**< Received a completion with UR status 65254359Sroberto radm_rcvd_cpl_ur */ 65354359Sroberto uint64_t rauc : 1; /**< Received an unexpected completion 65454359Sroberto radm_unexp_cpl_err */ 65554359Sroberto uint64_t rqo : 1; /**< Receive queue overflow. Normally happens only when 65654359Sroberto flow control advertisements are ignored 65754359Sroberto radm_qoverflow */ 65854359Sroberto uint64_t fcuv : 1; /**< Flow Control Update Violation (opt. checks) 65954359Sroberto int_xadm_fc_prot_err */ 66054359Sroberto uint64_t rpe : 1; /**< When the PHY reports 8B/10B decode error 66154359Sroberto (RxStatus = 3b100) or disparity error 66254359Sroberto (RxStatus = 3b111), the signal rmlh_rcvd_err will 66354359Sroberto be asserted. 66454359Sroberto rmlh_rcvd_err */ 66554359Sroberto uint64_t fcpvwt : 1; /**< Flow Control Protocol Violation (Watchdog Timer) 66654359Sroberto rtlh_fc_prot_err */ 66754359Sroberto uint64_t dpeoosd : 1; /**< DLLP protocol error (out of sequence DLLP) 66854359Sroberto rdlh_prot_err */ 66954359Sroberto uint64_t rtwdle : 1; /**< Received TLP with DataLink Layer Error 67054359Sroberto rdlh_bad_tlp_err */ 67154359Sroberto uint64_t rdwdle : 1; /**< Received DLLP with DataLink Layer Error 67254359Sroberto rdlh_bad_dllp_err */ 67354359Sroberto uint64_t mre : 1; /**< Max Retries Exceeded 67454359Sroberto xdlh_replay_num_rlover_err */ 67554359Sroberto uint64_t rte : 1; /**< Replay Timer Expired 67654359Sroberto xdlh_replay_timeout_err 67754359Sroberto This bit is set when the REPLAY_TIMER expires in 67854359Sroberto the PCIE core. The probability of this bit being 67954359Sroberto set will increase with the traffic load. */ 68054359Sroberto uint64_t acto : 1; /**< A Completion Timeout Occured 68154359Sroberto pedc_radm_cpl_timeout */ 68254359Sroberto uint64_t rvdm : 1; /**< Received Vendor-Defined Message 68354359Sroberto pedc_radm_vendor_msg */ 68454359Sroberto uint64_t rumep : 1; /**< Received Unlock Message (EP Mode Only) 68554359Sroberto pedc_radm_msg_unlock */ 68654359Sroberto uint64_t rptamrc : 1; /**< Received PME Turnoff Acknowledge Message 68754359Sroberto (RC Mode only) 68854359Sroberto pedc_radm_pm_to_ack */ 68954359Sroberto uint64_t rpmerc : 1; /**< Received PME Message (RC Mode only) 69054359Sroberto pedc_radm_pm_pme */ 69154359Sroberto uint64_t rfemrc : 1; /**< Received Fatal Error Message (RC Mode only) 69254359Sroberto pedc_radm_fatal_err 69354359Sroberto Bit set when a message with ERR_FATAL is set. */ 69454359Sroberto uint64_t rnfemrc : 1; /**< Received Non-Fatal Error Message (RC Mode only) 69554359Sroberto pedc_radm_nonfatal_err */ 69654359Sroberto uint64_t rcemrc : 1; /**< Received Correctable Error Message (RC Mode only) 69754359Sroberto pedc_radm_correctable_err */ 69854359Sroberto uint64_t rpoison : 1; /**< Received Poisoned TLP 69954359Sroberto pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv */ 70054359Sroberto uint64_t recrce : 1; /**< Received ECRC Error 70154359Sroberto pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot */ 70254359Sroberto uint64_t rtlplle : 1; /**< Received TLP has link layer error 70354359Sroberto pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot */ 70454359Sroberto uint64_t rtlpmal : 1; /**< Received TLP is malformed or a message. 70554359Sroberto pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot 70654359Sroberto If the core receives a MSG (or Vendor Message) 70754359Sroberto this bit will be set. */ 70854359Sroberto uint64_t spoison : 1; /**< Poisoned TLP sent 70954359Sroberto peai__client0_tlp_ep & peai__client0_tlp_hv */ 71054359Sroberto#else 71154359Sroberto uint64_t spoison : 1; 71254359Sroberto uint64_t rtlpmal : 1; 71354359Sroberto uint64_t rtlplle : 1; 71454359Sroberto uint64_t recrce : 1; 71554359Sroberto uint64_t rpoison : 1; 71654359Sroberto uint64_t rcemrc : 1; 71754359Sroberto uint64_t rnfemrc : 1; 71854359Sroberto uint64_t rfemrc : 1; 71954359Sroberto uint64_t rpmerc : 1; 72054359Sroberto uint64_t rptamrc : 1; 72154359Sroberto uint64_t rumep : 1; 72254359Sroberto uint64_t rvdm : 1; 723132451Sroberto uint64_t acto : 1; 72454359Sroberto uint64_t rte : 1; 72554359Sroberto uint64_t mre : 1; 72654359Sroberto uint64_t rdwdle : 1; 72754359Sroberto uint64_t rtwdle : 1; 72854359Sroberto uint64_t dpeoosd : 1; 72954359Sroberto uint64_t fcpvwt : 1; 73054359Sroberto uint64_t rpe : 1; 73154359Sroberto uint64_t fcuv : 1; 73254359Sroberto uint64_t rqo : 1; 73354359Sroberto uint64_t rauc : 1; 73454359Sroberto uint64_t racur : 1; 73554359Sroberto uint64_t racca : 1; 73654359Sroberto uint64_t caar : 1; 73754359Sroberto uint64_t rarwdns : 1; 73854359Sroberto uint64_t ramtlp : 1; 73954359Sroberto uint64_t racpp : 1; 74054359Sroberto uint64_t rawwpp : 1; 74154359Sroberto uint64_t ecrc_e : 1; 74254359Sroberto uint64_t reserved_31_63 : 33; 74354359Sroberto#endif 74454359Sroberto } s; 74554359Sroberto struct cvmx_pescx_dbg_info_s cn52xx; 74654359Sroberto struct cvmx_pescx_dbg_info_s cn52xxp1; 74754359Sroberto struct cvmx_pescx_dbg_info_s cn56xx; 74854359Sroberto struct cvmx_pescx_dbg_info_s cn56xxp1; 74954359Sroberto}; 75054359Srobertotypedef union cvmx_pescx_dbg_info cvmx_pescx_dbg_info_t; 75154359Sroberto 75254359Sroberto/** 75354359Sroberto * cvmx_pesc#_dbg_info_en 75454359Sroberto * 75554359Sroberto * PESC(0..1)_DBG_INFO_EN = PESC Debug Information Enable 75654359Sroberto * 75754359Sroberto * Allows PESC_DBG_INFO to generate interrupts when cooresponding enable bit is set. 75854359Sroberto */ 75954359Srobertounion cvmx_pescx_dbg_info_en 76054359Sroberto{ 76154359Sroberto uint64_t u64; 76254359Sroberto struct cvmx_pescx_dbg_info_en_s 76354359Sroberto { 76454359Sroberto#if __BYTE_ORDER == __BIG_ENDIAN 76554359Sroberto uint64_t reserved_31_63 : 33; 76654359Sroberto uint64_t ecrc_e : 1; /**< Allows PESC_DBG_INFO[30] to generate an interrupt. */ 76754359Sroberto uint64_t rawwpp : 1; /**< Allows PESC_DBG_INFO[29] to generate an interrupt. */ 76854359Sroberto uint64_t racpp : 1; /**< Allows PESC_DBG_INFO[28] to generate an interrupt. */ 76954359Sroberto uint64_t ramtlp : 1; /**< Allows PESC_DBG_INFO[27] to generate an interrupt. */ 77054359Sroberto uint64_t rarwdns : 1; /**< Allows PESC_DBG_INFO[26] to generate an interrupt. */ 77154359Sroberto uint64_t caar : 1; /**< Allows PESC_DBG_INFO[25] to generate an interrupt. */ 77254359Sroberto uint64_t racca : 1; /**< Allows PESC_DBG_INFO[24] to generate an interrupt. */ 77354359Sroberto uint64_t racur : 1; /**< Allows PESC_DBG_INFO[23] to generate an interrupt. */ 77454359Sroberto uint64_t rauc : 1; /**< Allows PESC_DBG_INFO[22] to generate an interrupt. */ 77554359Sroberto uint64_t rqo : 1; /**< Allows PESC_DBG_INFO[21] to generate an interrupt. */ 77654359Sroberto uint64_t fcuv : 1; /**< Allows PESC_DBG_INFO[20] to generate an interrupt. */ 77754359Sroberto uint64_t rpe : 1; /**< Allows PESC_DBG_INFO[19] to generate an interrupt. */ 77854359Sroberto uint64_t fcpvwt : 1; /**< Allows PESC_DBG_INFO[18] to generate an interrupt. */ 77954359Sroberto uint64_t dpeoosd : 1; /**< Allows PESC_DBG_INFO[17] to generate an interrupt. */ 78054359Sroberto uint64_t rtwdle : 1; /**< Allows PESC_DBG_INFO[16] to generate an interrupt. */ 78154359Sroberto uint64_t rdwdle : 1; /**< Allows PESC_DBG_INFO[15] to generate an interrupt. */ 78254359Sroberto uint64_t mre : 1; /**< Allows PESC_DBG_INFO[14] to generate an interrupt. */ 78354359Sroberto uint64_t rte : 1; /**< Allows PESC_DBG_INFO[13] to generate an interrupt. */ 78454359Sroberto uint64_t acto : 1; /**< Allows PESC_DBG_INFO[12] to generate an interrupt. */ 78554359Sroberto uint64_t rvdm : 1; /**< Allows PESC_DBG_INFO[11] to generate an interrupt. */ 78654359Sroberto uint64_t rumep : 1; /**< Allows PESC_DBG_INFO[10] to generate an interrupt. */ 78754359Sroberto uint64_t rptamrc : 1; /**< Allows PESC_DBG_INFO[9] to generate an interrupt. */ 78854359Sroberto uint64_t rpmerc : 1; /**< Allows PESC_DBG_INFO[8] to generate an interrupt. */ 78954359Sroberto uint64_t rfemrc : 1; /**< Allows PESC_DBG_INFO[7] to generate an interrupt. */ 79054359Sroberto uint64_t rnfemrc : 1; /**< Allows PESC_DBG_INFO[6] to generate an interrupt. */ 79154359Sroberto uint64_t rcemrc : 1; /**< Allows PESC_DBG_INFO[5] to generate an interrupt. */ 79254359Sroberto uint64_t rpoison : 1; /**< Allows PESC_DBG_INFO[4] to generate an interrupt. */ 79354359Sroberto uint64_t recrce : 1; /**< Allows PESC_DBG_INFO[3] to generate an interrupt. */ 79454359Sroberto uint64_t rtlplle : 1; /**< Allows PESC_DBG_INFO[2] to generate an interrupt. */ 79554359Sroberto uint64_t rtlpmal : 1; /**< Allows PESC_DBG_INFO[1] to generate an interrupt. */ 79654359Sroberto uint64_t spoison : 1; /**< Allows PESC_DBG_INFO[0] to generate an interrupt. */ 79754359Sroberto#else 79854359Sroberto uint64_t spoison : 1; 79954359Sroberto uint64_t rtlpmal : 1; 80054359Sroberto uint64_t rtlplle : 1; 80154359Sroberto uint64_t recrce : 1; 80254359Sroberto uint64_t rpoison : 1; 80354359Sroberto uint64_t rcemrc : 1; 80454359Sroberto uint64_t rnfemrc : 1; 80554359Sroberto uint64_t rfemrc : 1; 80654359Sroberto uint64_t rpmerc : 1; 80754359Sroberto uint64_t rptamrc : 1; 80854359Sroberto uint64_t rumep : 1; 80954359Sroberto uint64_t rvdm : 1; 81054359Sroberto uint64_t acto : 1; 81154359Sroberto uint64_t rte : 1; 81254359Sroberto uint64_t mre : 1; 81354359Sroberto uint64_t rdwdle : 1; 81454359Sroberto uint64_t rtwdle : 1; 81554359Sroberto uint64_t dpeoosd : 1; 81654359Sroberto uint64_t fcpvwt : 1; 81754359Sroberto uint64_t rpe : 1; 81854359Sroberto uint64_t fcuv : 1; 81954359Sroberto uint64_t rqo : 1; 82054359Sroberto uint64_t rauc : 1; 82154359Sroberto uint64_t racur : 1; 82254359Sroberto uint64_t racca : 1; 82354359Sroberto uint64_t caar : 1; 82454359Sroberto uint64_t rarwdns : 1; 825132451Sroberto uint64_t ramtlp : 1; 82654359Sroberto uint64_t racpp : 1; 82754359Sroberto uint64_t rawwpp : 1; 82854359Sroberto uint64_t ecrc_e : 1; 82954359Sroberto uint64_t reserved_31_63 : 33; 83054359Sroberto#endif 83154359Sroberto } s; 83254359Sroberto struct cvmx_pescx_dbg_info_en_s cn52xx; 83354359Sroberto struct cvmx_pescx_dbg_info_en_s cn52xxp1; 83454359Sroberto struct cvmx_pescx_dbg_info_en_s cn56xx; 83554359Sroberto struct cvmx_pescx_dbg_info_en_s cn56xxp1; 83654359Sroberto}; 83754359Srobertotypedef union cvmx_pescx_dbg_info_en cvmx_pescx_dbg_info_en_t; 83854359Sroberto 83954359Sroberto/** 84054359Sroberto * cvmx_pesc#_diag_status 84154359Sroberto * 84254359Sroberto * PESC_DIAG_STATUS = PESC Diagnostic Status 84354359Sroberto * 84454359Sroberto * Selection control for the cores diagnostic bus. 84554359Sroberto */ 84654359Srobertounion cvmx_pescx_diag_status 84754359Sroberto{ 84854359Sroberto uint64_t u64; 84954359Sroberto struct cvmx_pescx_diag_status_s 85054359Sroberto { 85154359Sroberto#if __BYTE_ORDER == __BIG_ENDIAN 85254359Sroberto uint64_t reserved_4_63 : 60; 85354359Sroberto uint64_t pm_dst : 1; /**< Current power management DSTATE. */ 85454359Sroberto uint64_t pm_stat : 1; /**< Power Management Status. */ 85554359Sroberto uint64_t pm_en : 1; /**< Power Management Event Enable. */ 85654359Sroberto uint64_t aux_en : 1; /**< Auxilary Power Enable. */ 85754359Sroberto#else 85854359Sroberto uint64_t aux_en : 1; 85954359Sroberto uint64_t pm_en : 1; 86054359Sroberto uint64_t pm_stat : 1; 86154359Sroberto uint64_t pm_dst : 1; 86254359Sroberto uint64_t reserved_4_63 : 60; 86354359Sroberto#endif 86454359Sroberto } s; 86554359Sroberto struct cvmx_pescx_diag_status_s cn52xx; 86654359Sroberto struct cvmx_pescx_diag_status_s cn52xxp1; 86754359Sroberto struct cvmx_pescx_diag_status_s cn56xx; 86854359Sroberto struct cvmx_pescx_diag_status_s cn56xxp1; 86954359Sroberto}; 87054359Srobertotypedef union cvmx_pescx_diag_status cvmx_pescx_diag_status_t; 87154359Sroberto 87254359Sroberto/** 87354359Sroberto * cvmx_pesc#_p2n_bar0_start 87454359Sroberto * 87554359Sroberto * PESC_P2N_BAR0_START = PESC PCIe to Npei BAR0 Start 87654359Sroberto * 87754359Sroberto * The starting address for addresses to forwarded to the NPEI in RC Mode. 878 */ 879union cvmx_pescx_p2n_bar0_start 880{ 881 uint64_t u64; 882 struct cvmx_pescx_p2n_bar0_start_s 883 { 884#if __BYTE_ORDER == __BIG_ENDIAN 885 uint64_t addr : 50; /**< The starting address of the 16KB address space that 886 is the BAR0 address space. */ 887 uint64_t reserved_0_13 : 14; 888#else 889 uint64_t reserved_0_13 : 14; 890 uint64_t addr : 50; 891#endif 892 } s; 893 struct cvmx_pescx_p2n_bar0_start_s cn52xx; 894 struct cvmx_pescx_p2n_bar0_start_s cn52xxp1; 895 struct cvmx_pescx_p2n_bar0_start_s cn56xx; 896 struct cvmx_pescx_p2n_bar0_start_s cn56xxp1; 897}; 898typedef union cvmx_pescx_p2n_bar0_start cvmx_pescx_p2n_bar0_start_t; 899 900/** 901 * cvmx_pesc#_p2n_bar1_start 902 * 903 * PESC_P2N_BAR1_START = PESC PCIe to Npei BAR1 Start 904 * 905 * The starting address for addresses to forwarded to the NPEI in RC Mode. 906 */ 907union cvmx_pescx_p2n_bar1_start 908{ 909 uint64_t u64; 910 struct cvmx_pescx_p2n_bar1_start_s 911 { 912#if __BYTE_ORDER == __BIG_ENDIAN 913 uint64_t addr : 38; /**< The starting address of the 64KB address space 914 that is the BAR1 address space. */ 915 uint64_t reserved_0_25 : 26; 916#else 917 uint64_t reserved_0_25 : 26; 918 uint64_t addr : 38; 919#endif 920 } s; 921 struct cvmx_pescx_p2n_bar1_start_s cn52xx; 922 struct cvmx_pescx_p2n_bar1_start_s cn52xxp1; 923 struct cvmx_pescx_p2n_bar1_start_s cn56xx; 924 struct cvmx_pescx_p2n_bar1_start_s cn56xxp1; 925}; 926typedef union cvmx_pescx_p2n_bar1_start cvmx_pescx_p2n_bar1_start_t; 927 928/** 929 * cvmx_pesc#_p2n_bar2_start 930 * 931 * PESC_P2N_BAR2_START = PESC PCIe to Npei BAR2 Start 932 * 933 * The starting address for addresses to forwarded to the NPEI in RC Mode. 934 */ 935union cvmx_pescx_p2n_bar2_start 936{ 937 uint64_t u64; 938 struct cvmx_pescx_p2n_bar2_start_s 939 { 940#if __BYTE_ORDER == __BIG_ENDIAN 941 uint64_t addr : 25; /**< The starting address of the 2^39 address space 942 that is the BAR2 address space. */ 943 uint64_t reserved_0_38 : 39; 944#else 945 uint64_t reserved_0_38 : 39; 946 uint64_t addr : 25; 947#endif 948 } s; 949 struct cvmx_pescx_p2n_bar2_start_s cn52xx; 950 struct cvmx_pescx_p2n_bar2_start_s cn52xxp1; 951 struct cvmx_pescx_p2n_bar2_start_s cn56xx; 952 struct cvmx_pescx_p2n_bar2_start_s cn56xxp1; 953}; 954typedef union cvmx_pescx_p2n_bar2_start cvmx_pescx_p2n_bar2_start_t; 955 956/** 957 * cvmx_pesc#_p2p_bar#_end 958 * 959 * PESC_P2P_BAR#_END = PESC Peer-To-Peer BAR0 End 960 * 961 * The ending address for addresses to forwarded to the PCIe peer port. 962 */ 963union cvmx_pescx_p2p_barx_end 964{ 965 uint64_t u64; 966 struct cvmx_pescx_p2p_barx_end_s 967 { 968#if __BYTE_ORDER == __BIG_ENDIAN 969 uint64_t addr : 52; /**< The ending address of the address window created 970 this field and the PESC_P2P_BAR0_START[63:12] 971 field. The full 64-bits of address are created by: 972 [ADDR[63:12], 12'b0]. */ 973 uint64_t reserved_0_11 : 12; 974#else 975 uint64_t reserved_0_11 : 12; 976 uint64_t addr : 52; 977#endif 978 } s; 979 struct cvmx_pescx_p2p_barx_end_s cn52xx; 980 struct cvmx_pescx_p2p_barx_end_s cn52xxp1; 981 struct cvmx_pescx_p2p_barx_end_s cn56xx; 982 struct cvmx_pescx_p2p_barx_end_s cn56xxp1; 983}; 984typedef union cvmx_pescx_p2p_barx_end cvmx_pescx_p2p_barx_end_t; 985 986/** 987 * cvmx_pesc#_p2p_bar#_start 988 * 989 * PESC_P2P_BAR#_START = PESC Peer-To-Peer BAR0 Start 990 * 991 * The starting address and enable for addresses to forwarded to the PCIe peer port. 992 */ 993union cvmx_pescx_p2p_barx_start 994{ 995 uint64_t u64; 996 struct cvmx_pescx_p2p_barx_start_s 997 { 998#if __BYTE_ORDER == __BIG_ENDIAN 999 uint64_t addr : 52; /**< The starting address of the address window created 1000 this field and the PESC_P2P_BAR0_END[63:12] field. 1001 The full 64-bits of address are created by: 1002 [ADDR[63:12], 12'b0]. */ 1003 uint64_t reserved_0_11 : 12; 1004#else 1005 uint64_t reserved_0_11 : 12; 1006 uint64_t addr : 52; 1007#endif 1008 } s; 1009 struct cvmx_pescx_p2p_barx_start_s cn52xx; 1010 struct cvmx_pescx_p2p_barx_start_s cn52xxp1; 1011 struct cvmx_pescx_p2p_barx_start_s cn56xx; 1012 struct cvmx_pescx_p2p_barx_start_s cn56xxp1; 1013}; 1014typedef union cvmx_pescx_p2p_barx_start cvmx_pescx_p2p_barx_start_t; 1015 1016/** 1017 * cvmx_pesc#_tlp_credits 1018 * 1019 * PESC_TLP_CREDITS = PESC TLP Credits 1020 * 1021 * Specifies the number of credits the PESC for use in moving TLPs. When this register is written the credit values are 1022 * reset to the register value. A write to this register should take place BEFORE traffic flow starts. 1023 */ 1024union cvmx_pescx_tlp_credits 1025{ 1026 uint64_t u64; 1027 struct cvmx_pescx_tlp_credits_s 1028 { 1029#if __BYTE_ORDER == __BIG_ENDIAN 1030 uint64_t reserved_0_63 : 64; 1031#else 1032 uint64_t reserved_0_63 : 64; 1033#endif 1034 } s; 1035 struct cvmx_pescx_tlp_credits_cn52xx 1036 { 1037#if __BYTE_ORDER == __BIG_ENDIAN 1038 uint64_t reserved_56_63 : 8; 1039 uint64_t peai_ppf : 8; /**< TLP credits for Completion TLPs in the Peer. 1040 Legal values are 0x24 to 0x80. */ 1041 uint64_t pesc_cpl : 8; /**< TLP credits for Completion TLPs in the Peer. 1042 Legal values are 0x24 to 0x80. */ 1043 uint64_t pesc_np : 8; /**< TLP credits for Non-Posted TLPs in the Peer. 1044 Legal values are 0x4 to 0x10. */ 1045 uint64_t pesc_p : 8; /**< TLP credits for Posted TLPs in the Peer. 1046 Legal values are 0x24 to 0x80. */ 1047 uint64_t npei_cpl : 8; /**< TLP credits for Completion TLPs in the NPEI. 1048 Legal values are 0x24 to 0x80. */ 1049 uint64_t npei_np : 8; /**< TLP credits for Non-Posted TLPs in the NPEI. 1050 Legal values are 0x4 to 0x10. */ 1051 uint64_t npei_p : 8; /**< TLP credits for Posted TLPs in the NPEI. 1052 Legal values are 0x24 to 0x80. */ 1053#else 1054 uint64_t npei_p : 8; 1055 uint64_t npei_np : 8; 1056 uint64_t npei_cpl : 8; 1057 uint64_t pesc_p : 8; 1058 uint64_t pesc_np : 8; 1059 uint64_t pesc_cpl : 8; 1060 uint64_t peai_ppf : 8; 1061 uint64_t reserved_56_63 : 8; 1062#endif 1063 } cn52xx; 1064 struct cvmx_pescx_tlp_credits_cn52xxp1 1065 { 1066#if __BYTE_ORDER == __BIG_ENDIAN 1067 uint64_t reserved_38_63 : 26; 1068 uint64_t peai_ppf : 8; /**< TLP credits in core clk pre-buffer that holds TLPs 1069 being sent from PCIe Core to NPEI or PEER. */ 1070 uint64_t pesc_cpl : 5; /**< TLP credits for Completion TLPs in the Peer. */ 1071 uint64_t pesc_np : 5; /**< TLP credits for Non-Posted TLPs in the Peer. */ 1072 uint64_t pesc_p : 5; /**< TLP credits for Posted TLPs in the Peer. */ 1073 uint64_t npei_cpl : 5; /**< TLP credits for Completion TLPs in the NPEI. */ 1074 uint64_t npei_np : 5; /**< TLP credits for Non-Posted TLPs in the NPEI. */ 1075 uint64_t npei_p : 5; /**< TLP credits for Posted TLPs in the NPEI. */ 1076#else 1077 uint64_t npei_p : 5; 1078 uint64_t npei_np : 5; 1079 uint64_t npei_cpl : 5; 1080 uint64_t pesc_p : 5; 1081 uint64_t pesc_np : 5; 1082 uint64_t pesc_cpl : 5; 1083 uint64_t peai_ppf : 8; 1084 uint64_t reserved_38_63 : 26; 1085#endif 1086 } cn52xxp1; 1087 struct cvmx_pescx_tlp_credits_cn52xx cn56xx; 1088 struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1; 1089}; 1090typedef union cvmx_pescx_tlp_credits cvmx_pescx_tlp_credits_t; 1091 1092#endif 1093