cvmx-higig.h revision 210284
1210284Sjmallett/***********************license start*************** 2210284Sjmallett * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3210284Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6210284Sjmallett * Redistribution and use in source and binary forms, with or without 7210284Sjmallett * modification, are permitted provided that the following conditions are 8210284Sjmallett * met: 9210284Sjmallett * 10210284Sjmallett * * Redistributions of source code must retain the above copyright 11210284Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13210284Sjmallett * * Redistributions in binary form must reproduce the above 14210284Sjmallett * copyright notice, this list of conditions and the following 15210284Sjmallett * disclaimer in the documentation and/or other materials provided 16210284Sjmallett * with the distribution. 17210284Sjmallett * 18210284Sjmallett * * Neither the name of Cavium Networks nor the names of 19210284Sjmallett * its contributors may be used to endorse or promote products 20210284Sjmallett * derived from this software without specific prior written 21210284Sjmallett * permission. 22210284Sjmallett * 23210284Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24210284Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25210284Sjmallett * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26210284Sjmallett * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27210284Sjmallett * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28210284Sjmallett * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29210284Sjmallett * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30210284Sjmallett * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31210284Sjmallett * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32210284Sjmallett * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33210284Sjmallett * 34210284Sjmallett * 35210284Sjmallett * For any questions regarding licensing please contact marketing@caviumnetworks.com 36210284Sjmallett * 37210284Sjmallett ***********************license end**************************************/ 38210284Sjmallett 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett/** 45210284Sjmallett * @file 46210284Sjmallett * 47210284Sjmallett * Functions and typedefs for using Octeon in HiGig/HiGig+/HiGig2 mode over 48210284Sjmallett * XAUI. 49210284Sjmallett * 50210284Sjmallett * <hr>$Revision: 41586 $<hr> 51210284Sjmallett */ 52210284Sjmallett 53210284Sjmallett#ifndef __CVMX_HIGIG_H__ 54210284Sjmallett#define __CVMX_HIGIG_H__ 55210284Sjmallett#include "cvmx-wqe.h" 56210284Sjmallett 57210284Sjmallett#ifdef __cplusplus 58210284Sjmallettextern "C" { 59210284Sjmallett#endif 60210284Sjmallett 61210284Sjmalletttypedef struct 62210284Sjmallett{ 63210284Sjmallett union 64210284Sjmallett { 65210284Sjmallett uint32_t u32; 66210284Sjmallett struct 67210284Sjmallett { 68210284Sjmallett uint32_t start : 8; /**< 8-bits of Preamble indicating start of frame */ 69210284Sjmallett uint32_t dst_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of 70210284Sjmallett DST_MODID (bits 4:0 are in Byte 7 and bit 5 is in Byte 9). ). For HGI field 71210284Sjmallett value of b'01' this field should be b'1'. For all other values of HGI it is don't 72210284Sjmallett care. */ 73210284Sjmallett uint32_t src_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of 74210284Sjmallett SRC_MODID (bits 4:0 are in Byte 4 and bit 5 is in Byte 9). For HGI field 75210284Sjmallett value of b'01' this field should be b'0'. For all other values of HGI it is don't 76210284Sjmallett care. */ 77210284Sjmallett uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension 78210284Sjmallett to the standard 12-bytes of XGS HiGig header. Each unit represents 4 79210284Sjmallett bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110' 80210284Sjmallett and b'111' are reserved. For HGI field value of b'01' this field should be 81210284Sjmallett b'01'. For all other values of HGI it is don't care. */ 82210284Sjmallett uint32_t cng_high : 1; /**< Congestion Bit High flag */ 83210284Sjmallett uint32_t hgi : 2; /**< HiGig interface format indicator 84210284Sjmallett 00 = Reserved 85210284Sjmallett 01 = Pure preamble - IEEE standard framing of 10GE 86210284Sjmallett 10 = XGS header - framing based on XGS family definition In this 87210284Sjmallett format, the default length of the header is 12 bytes and additional 88210284Sjmallett bytes are indicated by the HDR_EXT_LEN field 89210284Sjmallett 11 = Reserved */ 90210284Sjmallett uint32_t vid_high : 8; /**< 8-bits of the VLAN tag information */ 91210284Sjmallett uint32_t vid_low : 8; /**< 8 bits LSB of the VLAN tag information */ 92210284Sjmallett } s; 93210284Sjmallett } dw0; 94210284Sjmallett union 95210284Sjmallett { 96210284Sjmallett uint32_t u32; 97210284Sjmallett struct 98210284Sjmallett { 99210284Sjmallett uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet 100210284Sjmallett 000 = Control frames used for CPU to CPU communications 101210284Sjmallett 001 = Unicast packet with destination resolved; The packet can be 102210284Sjmallett either Layer 2 unicast packet or L3 unicast packet that was 103210284Sjmallett routed in the ingress chip. 104210284Sjmallett 010 = Broadcast or unknown Unicast packet or unknown multicast, 105210284Sjmallett destined to all members of the VLAN 106210284Sjmallett 011 = L2 Multicast packet, destined to all ports of the group indicated 107210284Sjmallett in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields 108210284Sjmallett 100 = IP Multicast packet, destined to all ports of the group indicated 109210284Sjmallett in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields 110210284Sjmallett 101 = Reserved 111210284Sjmallett 110 = Reserved 112210284Sjmallett 111 = Reserved */ 113210284Sjmallett uint32_t src_modid_low : 5; /**< Bits 4:0 of Module ID of the source module on which the packet ingress (bit 114210284Sjmallett 5 is in Byte 9 and bit 6 Is in Byte 1) */ 115210284Sjmallett uint32_t src_port_tgid : 6; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed 116210284Sjmallett on, else it represents the physical port the packet ingressed on. */ 117210284Sjmallett uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered 118210284Sjmallett multicast (unknown L2 multicast and IPMC) packets. This field is used 119210284Sjmallett when OPCODE is 011 or 100 Semantics of PFM bits are as follows; 120210284Sjmallett For registered L2 multicast packets: 121210284Sjmallett PFM= 0 � Flood to VLAN 122210284Sjmallett PFM= 1 or 2 � Send to group members in the L2MC table 123210284Sjmallett For unregistered L2 multicast packets: 124210284Sjmallett PFM= 0 or 1 � Flood to VLAN 125210284Sjmallett PFM= 2 � Drop the packet */ 126210284Sjmallett uint32_t priority : 3; /**< This is the internal priority of the packet. This internal priority will go through 127210284Sjmallett COS_SEL mapping registers to map to the actual MMU queues. */ 128210284Sjmallett uint32_t dst_port : 5; /**< Port number of destination port on which the packet needs to egress. */ 129210284Sjmallett uint32_t dst_modid_low : 5; /**< Bits [4-: 0] of Module ID of the destination port on which the packet needs to egress. */ 130210284Sjmallett uint32_t cng_low : 1; /**< Semantics of CNG_HIGH and CNG_LOW are as follows: The following 131210284Sjmallett encodings are to make it backward compatible: 132210284Sjmallett {CNG_HIGH, CNG_LOW] - COLOR 133210284Sjmallett [0, 0] � Packet is green 134210284Sjmallett [0, 1] � Packet is red 135210284Sjmallett [1, 1] � Packet is yellow 136210284Sjmallett [1, 0] � Undefined */ 137210284Sjmallett uint32_t header_type : 2; /**< Indicates the format of the next 4 bytes of the XGS HiGig header 138210284Sjmallett 00 = Overlay 1 (default) 139210284Sjmallett 01 = Overlay 2 (Classification Tag) 140210284Sjmallett 10 = Reserved 141210284Sjmallett 11 = Reserved */ 142210284Sjmallett } s; 143210284Sjmallett } dw1; 144210284Sjmallett union 145210284Sjmallett { 146210284Sjmallett uint32_t u32; 147210284Sjmallett struct 148210284Sjmallett { 149210284Sjmallett uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the 150210284Sjmallett packet was switched and only needs to be mirrored. */ 151210284Sjmallett uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and 152210284Sjmallett may still need to be switched. */ 153210284Sjmallett uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only 154210284Sjmallett needs to be mirrored. */ 155210284Sjmallett uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally 156210284Sjmallett ingressed the system. */ 157210284Sjmallett uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The 158210284Sjmallett DO_NOT_LEARN bit is overlaid on the second bit of this field. */ 159210284Sjmallett uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk 160210284Sjmallett group. */ 161210284Sjmallett uint32_t vc_label_16_19 : 4; /**< VC Label: Bits 19:16 of VC label: HiGig+ added field */ 162210284Sjmallett uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+ 163210284Sjmallett added field. */ 164210284Sjmallett uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */ 165210284Sjmallett uint32_t dst_modid_5 : 1; /**< Destination Module ID: Bit 5 of Dst_ModID (bits 4:0 are in byte 7 and bit 6 166210284Sjmallett is in byte 1) */ 167210284Sjmallett uint32_t src_modid_5 : 1; /**< Source Module ID: Bit 5 of Src_ModID (bits 4:0 are in byte 4 and bit 6 is in 168210284Sjmallett byte 1) */ 169210284Sjmallett uint32_t vc_label_0_15 : 16;/**< VC Label: Bits 15:0 of VC label: HiGig+ added field */ 170210284Sjmallett } o1; 171210284Sjmallett struct 172210284Sjmallett { 173210284Sjmallett uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */ 174210284Sjmallett uint32_t reserved_0_15 : 16; 175210284Sjmallett 176210284Sjmallett } o2; 177210284Sjmallett } dw2; 178210284Sjmallett} cvmx_higig_header_t; 179210284Sjmallett 180210284Sjmallett 181210284Sjmallett/** 182210284Sjmallett * Initialize the HiGig aspects of a XAUI interface. This function 183210284Sjmallett * should be called before the cvmx-helper generic init. 184210284Sjmallett * 185210284Sjmallett * @param interface Interface to initialize HiGig on (0-1) 186210284Sjmallett * @param enable_higig2 187210284Sjmallett * Non zero to enable HiGig2 support. Zero to support HiGig 188210284Sjmallett * and HiGig+. 189210284Sjmallett * 190210284Sjmallett * @return Zero on success, negative on failure 191210284Sjmallett */ 192210284Sjmallettstatic inline int cvmx_higig_initialize(int interface, int enable_higig2) 193210284Sjmallett{ 194210284Sjmallett cvmx_pip_prt_cfgx_t pip_prt_cfg; 195210284Sjmallett cvmx_gmxx_rxx_udd_skp_t gmx_rx_udd_skp; 196210284Sjmallett cvmx_gmxx_txx_min_pkt_t gmx_tx_min_pkt; 197210284Sjmallett cvmx_gmxx_txx_append_t gmx_tx_append; 198210284Sjmallett cvmx_gmxx_tx_ifg_t gmx_tx_ifg; 199210284Sjmallett cvmx_gmxx_tx_ovr_bp_t gmx_tx_ovr_bp; 200210284Sjmallett cvmx_gmxx_rxx_frm_ctl_t gmx_rx_frm_ctl; 201210284Sjmallett cvmx_gmxx_tx_xaui_ctl_t gmx_tx_xaui_ctl; 202210284Sjmallett int i; 203210284Sjmallett int header_size = (enable_higig2) ? 16 : 12; 204210284Sjmallett 205210284Sjmallett /* Setup PIP to handle HiGig */ 206210284Sjmallett pip_prt_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(interface*16)); 207210284Sjmallett pip_prt_cfg.s.dsa_en = 0; 208210284Sjmallett pip_prt_cfg.s.higig_en = 1; 209210284Sjmallett pip_prt_cfg.s.hg_qos = 1; 210210284Sjmallett pip_prt_cfg.s.skip = header_size; 211210284Sjmallett cvmx_write_csr(CVMX_PIP_PRT_CFGX(interface*16), pip_prt_cfg.u64); 212210284Sjmallett 213210284Sjmallett /* Setup some sample QoS defaults. These can be changed later */ 214210284Sjmallett for (i=0; i<64; i++) 215210284Sjmallett { 216210284Sjmallett cvmx_pip_hg_pri_qos_t pip_hg_pri_qos; 217210284Sjmallett pip_hg_pri_qos.u64 = 0; 218210284Sjmallett pip_hg_pri_qos.s.up_qos = 1; 219210284Sjmallett pip_hg_pri_qos.s.pri = i; 220210284Sjmallett pip_hg_pri_qos.s.qos = i&7; 221210284Sjmallett cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64); 222210284Sjmallett } 223210284Sjmallett 224210284Sjmallett /* Setup GMX RX to treat the HiGig header as user data to ignore */ 225210284Sjmallett gmx_rx_udd_skp.u64 = cvmx_read_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface)); 226210284Sjmallett gmx_rx_udd_skp.s.len = header_size; 227210284Sjmallett gmx_rx_udd_skp.s.fcssel = 0; 228210284Sjmallett cvmx_write_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface), gmx_rx_udd_skp.u64); 229210284Sjmallett 230210284Sjmallett /* Disable GMX preamble checking */ 231210284Sjmallett gmx_rx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface)); 232210284Sjmallett gmx_rx_frm_ctl.s.pre_chk = 0; 233210284Sjmallett cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface), gmx_rx_frm_ctl.u64); 234210284Sjmallett 235210284Sjmallett /* Setup GMX TX to pad properly min sized packets */ 236210284Sjmallett gmx_tx_min_pkt.u64 = cvmx_read_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface)); 237210284Sjmallett gmx_tx_min_pkt.s.min_size = 59 + header_size; 238210284Sjmallett cvmx_write_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface), gmx_tx_min_pkt.u64); 239210284Sjmallett 240210284Sjmallett /* Setup GMX TX to not add a preamble */ 241210284Sjmallett gmx_tx_append.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface)); 242210284Sjmallett gmx_tx_append.s.preamble = 0; 243210284Sjmallett cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmx_tx_append.u64); 244210284Sjmallett 245210284Sjmallett /* Reduce the inter frame gap to 8 bytes */ 246210284Sjmallett gmx_tx_ifg.u64 = cvmx_read_csr(CVMX_GMXX_TX_IFG(interface)); 247210284Sjmallett gmx_tx_ifg.s.ifg1 = 4; 248210284Sjmallett gmx_tx_ifg.s.ifg2 = 4; 249210284Sjmallett cvmx_write_csr(CVMX_GMXX_TX_IFG(interface), gmx_tx_ifg.u64); 250210284Sjmallett 251210284Sjmallett /* Disable GMX backpressure */ 252210284Sjmallett gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); 253210284Sjmallett gmx_tx_ovr_bp.s.bp = 0; 254210284Sjmallett gmx_tx_ovr_bp.s.en = 0xf; 255210284Sjmallett gmx_tx_ovr_bp.s.ign_full = 0xf; 256210284Sjmallett cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64); 257210284Sjmallett 258210284Sjmallett if (enable_higig2) 259210284Sjmallett { 260210284Sjmallett /* Enable HiGig2 support and forwarding of virtual port backpressure 261210284Sjmallett to PKO */ 262210284Sjmallett cvmx_gmxx_hg2_control_t gmx_hg2_control; 263210284Sjmallett gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); 264210284Sjmallett gmx_hg2_control.s.hg2rx_en = 1; 265210284Sjmallett gmx_hg2_control.s.hg2tx_en = 1; 266210284Sjmallett gmx_hg2_control.s.logl_en = 0xffff; 267210284Sjmallett gmx_hg2_control.s.phys_en = 1; 268210284Sjmallett cvmx_write_csr(CVMX_GMXX_HG2_CONTROL(interface), gmx_hg2_control.u64); 269210284Sjmallett } 270210284Sjmallett 271210284Sjmallett /* Enable HiGig */ 272210284Sjmallett gmx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); 273210284Sjmallett gmx_tx_xaui_ctl.s.hg_en = 1; 274210284Sjmallett cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmx_tx_xaui_ctl.u64); 275210284Sjmallett 276210284Sjmallett return 0; 277210284Sjmallett} 278210284Sjmallett 279210284Sjmallett#ifdef __cplusplus 280210284Sjmallett} 281210284Sjmallett#endif 282210284Sjmallett 283210284Sjmallett#endif // __CVMX_HIGIG_H__ 284