cvmx-core.c revision 210284 
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38
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41
42
43
44/**
45 * @file
46 *
47 * Module to support operations on core such as TLB config, etc.
48 *
49 * <hr>$Revision: 41586 $<hr>
50 *
51 */
52
53#include "cvmx-config.h"
54#include "cvmx.h"
55#include "cvmx-core.h"
56
57
58/**
59 * Adds a wired TLB entry, and returns the index of the entry added.
60 * Parameters are written to TLB registers without further processing.
61 *
62 * @param hi     HI register value
63 * @param lo0    lo0 register value
64 * @param lo1    lo1 register value
65 * @param page_mask   pagemask register value
66 *
67 * @return Success: TLB index used (0-31) or (0-63) for OCTEON Plus
68 *         Failure: -1
69 */
70int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask)
71{
72    uint32_t index;
73    uint32_t index_limit = 31;
74
75    if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
76    {
77        index_limit=63;
78    }
79
80    CVMX_MF_TLB_WIRED(index);
81    if (index >= index_limit)
82    {
83        return(-1);
84    }
85    CVMX_MT_ENTRY_HIGH(hi);
86    CVMX_MT_ENTRY_LO_0(lo0);
87    CVMX_MT_ENTRY_LO_1(lo1);
88    CVMX_MT_PAGEMASK(page_mask);
89    CVMX_MT_TLB_INDEX(index);
90    CVMX_MT_TLB_WIRED(index + 1);
91    CVMX_EHB;
92    CVMX_TLBWI;
93    CVMX_EHB;
94    return(index);
95}
96
97
98
99/**
100 * Adds a fixed (wired) TLB mapping.  Returns TLB index used or -1 on error.
101 * This is a wrapper around cvmx_core_add_wired_tlb_entry()
102 *
103 * @param vaddr      Virtual address to map
104 * @param page0_addr page 0 physical address, with low 3 bits representing the DIRTY, VALID, and GLOBAL bits
105 * @param page1_addr page1 physical address, with low 3 bits representing the DIRTY, VALID, and GLOBAL bits
106 * @param page_mask  page mask.
107 *
108 * @return Success: TLB index used (0-31)
109 *         Failure: -1
110 */
111int cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask)
112{
113
114    if ((vaddr & (page_mask | 0x7ff))
115        || ((page0_addr & ~0x7ULL) & ((page_mask | 0x7ff) >> 1))
116        || ((page1_addr & ~0x7ULL) & ((page_mask | 0x7ff) >> 1)))
117    {
118        cvmx_dprintf("Error adding tlb mapping: invalid address alignment at vaddr: 0x%llx\n", (unsigned long long)vaddr);
119        return(-1);
120    }
121
122
123    return(cvmx_core_add_wired_tlb_entry(vaddr,
124                                         (page0_addr >> 6) | (page0_addr & 0x7),
125                                         (page1_addr >> 6) | (page1_addr & 0x7),
126                                         page_mask));
127
128}
129/**
130 * Adds a fixed (wired) TLB mapping.  Returns TLB index used or -1 on error.
131 * Assumes both pages are valid.  Use cvmx_core_add_fixed_tlb_mapping_bits for more control.
132 * This is a wrapper around cvmx_core_add_wired_tlb_entry()
133 *
134 * @param vaddr      Virtual address to map
135 * @param page0_addr page 0 physical address
136 * @param page1_addr page1 physical address
137 * @param page_mask  page mask.
138 *
139 * @return Success: TLB index used (0-31)
140 *         Failure: -1
141 */
142int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask)
143{
144
145    return(cvmx_core_add_fixed_tlb_mapping_bits(vaddr, page0_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page1_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page_mask));
146
147}
148