1250003Sadrian/* 2250003Sadrian * Copyright (c) 2013 Qualcomm Atheros, Inc. 3250003Sadrian * 4250003Sadrian * Permission to use, copy, modify, and/or distribute this software for any 5250003Sadrian * purpose with or without fee is hereby granted, provided that the above 6250003Sadrian * copyright notice and this permission notice appear in all copies. 7250003Sadrian * 8250003Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9250003Sadrian * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10250003Sadrian * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11250003Sadrian * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12250003Sadrian * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13250003Sadrian * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14250003Sadrian * PERFORMANCE OF THIS SOFTWARE. 15250003Sadrian */ 16250003Sadrian 17250003Sadrian#ifndef _ATH_AR9300_EEP_H_ 18250003Sadrian#define _ATH_AR9300_EEP_H_ 19250003Sadrian 20250003Sadrian#include "opt_ah.h" 21250003Sadrian 22250003Sadrian#include "ah.h" 23250003Sadrian 24250003Sadrian#if defined(WIN32) || defined(WIN64) 25250003Sadrian#pragma pack (push, ar9300, 1) 26250003Sadrian#endif 27250003Sadrian 28250008Sadrian/* FreeBSD extras - should be in ah_eeprom.h ? */ 29250008Sadrian#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 30250008Sadrian#define AR_EEPROM_EEPCAP_AES_DIS 0x0002 31250008Sadrian#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 32250008Sadrian#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 33250008Sadrian#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 34250008Sadrian#define AR_EEPROM_EEPCAP_MAXQCU_S 4 35250008Sadrian#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 36250008Sadrian#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 37250008Sadrian#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 38250003Sadrian 39250008Sadrian 40250003Sadrian#define MSTATE 100 41250003Sadrian#define MOUTPUT 2048 42250003Sadrian#define MDEFAULT 15 43250003Sadrian#define MVALUE 100 44250003Sadrian 45250003Sadrianenum CompressAlgorithm 46250003Sadrian{ 47250003Sadrian _compress_none = 0, 48250003Sadrian _compress_lzma, 49250003Sadrian _compress_pairs, 50250003Sadrian _compress_block, 51250003Sadrian _compress4, 52250003Sadrian _compress5, 53250003Sadrian _compress6, 54250003Sadrian _compress7, 55250003Sadrian}; 56250003Sadrian 57250003Sadrian 58250003Sadrianenum 59250003Sadrian{ 60250003Sadrian calibration_data_none = 0, 61250003Sadrian calibration_data_dram, 62250003Sadrian calibration_data_flash, 63250003Sadrian calibration_data_eeprom, 64250003Sadrian calibration_data_otp, 65250003Sadrian#ifdef ATH_CAL_NAND_FLASH 66250003Sadrian calibration_data_nand, 67250003Sadrian#endif 68250003Sadrian CalibrationDataDontLoad, 69250003Sadrian}; 70250003Sadrian#define HOST_CALDATA_SIZE (16*1024) 71250003Sadrian 72250003Sadrian// 73250003Sadrian// DO NOT CHANGE THE DEFINTIONS OF THESE SYMBOLS. 74250003Sadrian// Add additional definitions to the end. 75250003Sadrian// Yes, the first one is 2. Do not use 0 or 1. 76250003Sadrian// 77250003Sadrianenum Ar9300EepromTemplate 78250003Sadrian{ 79250003Sadrian ar9300_eeprom_template_generic = 2, 80250003Sadrian ar9300_eeprom_template_hb112 = 3, 81250003Sadrian ar9300_eeprom_template_hb116 = 4, 82250003Sadrian ar9300_eeprom_template_xb112 = 5, 83250003Sadrian ar9300_eeprom_template_xb113 = 6, 84250003Sadrian ar9300_eeprom_template_xb114 = 7, 85250003Sadrian ar9300_eeprom_template_tb417 = 8, 86250003Sadrian ar9300_eeprom_template_ap111 = 9, 87250003Sadrian ar9300_eeprom_template_ap121 = 10, 88250003Sadrian ar9300_eeprom_template_hornet_generic = 11, 89250003Sadrian ar9300_eeprom_template_wasp_2 = 12, 90250003Sadrian ar9300_eeprom_template_wasp_k31 = 13, 91250003Sadrian ar9300_eeprom_template_osprey_k31 = 14, 92250003Sadrian ar9300_eeprom_template_aphrodite = 15 93250003Sadrian}; 94250003Sadrian 95250003Sadrian#define ar9300_eeprom_template_default ar9300_eeprom_template_generic 96250003Sadrian#define Ar9300EepromFormatDefault 2 97250003Sadrian 98250003Sadrian#define reference_current 0 99250003Sadrian#define compression_header_length 4 100250003Sadrian#define compression_checksum_length 2 101250003Sadrian 102250003Sadrian#define OSPREY_EEP_VER 0xD000 103250003Sadrian#define OSPREY_EEP_VER_MINOR_MASK 0xFFF 104250003Sadrian#define OSPREY_EEP_MINOR_VER_1 0x1 105250003Sadrian#define OSPREY_EEP_MINOR_VER OSPREY_EEP_MINOR_VER_1 106250003Sadrian 107250003Sadrian// 16-bit offset location start of calibration struct 108250003Sadrian#define OSPREY_EEP_START_LOC 256 109250003Sadrian#define OSPREY_NUM_5G_CAL_PIERS 8 110250003Sadrian#define OSPREY_NUM_2G_CAL_PIERS 3 111250003Sadrian#define OSPREY_NUM_5G_20_TARGET_POWERS 8 112250003Sadrian#define OSPREY_NUM_5G_40_TARGET_POWERS 8 113250003Sadrian#define OSPREY_NUM_2G_CCK_TARGET_POWERS 2 114250003Sadrian#define OSPREY_NUM_2G_20_TARGET_POWERS 3 115250003Sadrian#define OSPREY_NUM_2G_40_TARGET_POWERS 3 116250003Sadrian//#define OSPREY_NUM_CTLS 21 117250003Sadrian#define OSPREY_NUM_CTLS_5G 9 118250003Sadrian#define OSPREY_NUM_CTLS_2G 12 119250003Sadrian#define OSPREY_CTL_MODE_M 0xF 120250003Sadrian#define OSPREY_NUM_BAND_EDGES_5G 8 121250003Sadrian#define OSPREY_NUM_BAND_EDGES_2G 4 122250003Sadrian#define OSPREY_NUM_PD_GAINS 4 123250003Sadrian#define OSPREY_PD_GAINS_IN_MASK 4 124250003Sadrian#define OSPREY_PD_GAIN_ICEPTS 5 125250003Sadrian#define OSPREY_EEPROM_MODAL_SPURS 5 126250003Sadrian#define OSPREY_MAX_RATE_POWER 63 127250003Sadrian#define OSPREY_NUM_PDADC_VALUES 128 128250003Sadrian#define OSPREY_NUM_RATES 16 129250003Sadrian#define OSPREY_BCHAN_UNUSED 0xFF 130250003Sadrian#define OSPREY_MAX_PWR_RANGE_IN_HALF_DB 64 131250003Sadrian#define OSPREY_OPFLAGS_11A 0x01 132250003Sadrian#define OSPREY_OPFLAGS_11G 0x02 133250003Sadrian#define OSPREY_OPFLAGS_5G_HT40 0x04 134250003Sadrian#define OSPREY_OPFLAGS_2G_HT40 0x08 135250003Sadrian#define OSPREY_OPFLAGS_5G_HT20 0x10 136250003Sadrian#define OSPREY_OPFLAGS_2G_HT20 0x20 137250003Sadrian#define OSPREY_EEPMISC_BIG_ENDIAN 0x01 138250003Sadrian#define OSPREY_EEPMISC_WOW 0x02 139250003Sadrian#define OSPREY_CUSTOMER_DATA_SIZE 20 140250003Sadrian 141250003Sadrian#define FREQ2FBIN(x,y) \ 142250003Sadrian (((y) == HAL_FREQ_BAND_2GHZ) ? ((x) - 2300) : (((x) - 4800) / 5)) 143250003Sadrian#define FBIN2FREQ(x,y) \ 144250003Sadrian (((y) == HAL_FREQ_BAND_2GHZ) ? (2300 + x) : (4800 + 5 * x)) 145250003Sadrian#define OSPREY_MAX_CHAINS 3 146250003Sadrian#define OSPREY_ANT_16S 25 147250003Sadrian#define OSPREY_FUTURE_MODAL_SZ 6 148250003Sadrian 149250003Sadrian#define OSPREY_NUM_ANT_CHAIN_FIELDS 7 150250003Sadrian#define OSPREY_NUM_ANT_COMMON_FIELDS 4 151250003Sadrian#define OSPREY_SIZE_ANT_CHAIN_FIELD 3 152250003Sadrian#define OSPREY_SIZE_ANT_COMMON_FIELD 4 153250003Sadrian#define OSPREY_ANT_CHAIN_MASK 0x7 154250003Sadrian#define OSPREY_ANT_COMMON_MASK 0xf 155250003Sadrian#define OSPREY_CHAIN_0_IDX 0 156250003Sadrian#define OSPREY_CHAIN_1_IDX 1 157250003Sadrian#define OSPREY_CHAIN_2_IDX 2 158250003Sadrian#define OSPREY_1_CHAINMASK 1 159250003Sadrian#define OSPREY_2LOHI_CHAINMASK 5 160250003Sadrian#define OSPREY_2LOMID_CHAINMASK 3 161250003Sadrian#define OSPREY_3_CHAINMASK 7 162250003Sadrian 163250003Sadrian#define AR928X_NUM_ANT_CHAIN_FIELDS 6 164250003Sadrian#define AR928X_SIZE_ANT_CHAIN_FIELD 2 165250003Sadrian#define AR928X_ANT_CHAIN_MASK 0x3 166250003Sadrian 167250003Sadrian/* Delta from which to start power to pdadc table */ 168250003Sadrian/* This offset is used in both open loop and closed loop power control 169250003Sadrian * schemes. In open loop power control, it is not really needed, but for 170250003Sadrian * the "sake of consistency" it was kept. 171250003Sadrian * For certain AP designs, this value is overwritten by the value in the flag 172250003Sadrian * "pwrTableOffset" just before writing the pdadc vs pwr into the chip registers. 173250003Sadrian */ 174250003Sadrian#define OSPREY_PWR_TABLE_OFFSET 0 175250003Sadrian 176250003Sadrian//enable flags for voltage and temp compensation 177250003Sadrian#define ENABLE_TEMP_COMPENSATION 0x01 178250003Sadrian#define ENABLE_VOLT_COMPENSATION 0x02 179250003Sadrian 180250003Sadrian#define FLASH_BASE_CALDATA_OFFSET 0x1000 181250003Sadrian#define AR9300_EEPROM_SIZE 16*1024 // byte addressable 182250003Sadrian#define FIXED_CCA_THRESHOLD 15 183250003Sadrian 184250003Sadriantypedef struct eepFlags { 185250003Sadrian u_int8_t op_flags; 186250003Sadrian u_int8_t eepMisc; 187250003Sadrian} __packed EEP_FLAGS; 188250003Sadrian 189250003Sadriantypedef enum targetPowerHTRates { 190250003Sadrian HT_TARGET_RATE_0_8_16, 191250003Sadrian HT_TARGET_RATE_1_3_9_11_17_19, 192250003Sadrian HT_TARGET_RATE_4, 193250003Sadrian HT_TARGET_RATE_5, 194250003Sadrian HT_TARGET_RATE_6, 195250003Sadrian HT_TARGET_RATE_7, 196250003Sadrian HT_TARGET_RATE_12, 197250003Sadrian HT_TARGET_RATE_13, 198250003Sadrian HT_TARGET_RATE_14, 199250003Sadrian HT_TARGET_RATE_15, 200250003Sadrian HT_TARGET_RATE_20, 201250003Sadrian HT_TARGET_RATE_21, 202250003Sadrian HT_TARGET_RATE_22, 203250003Sadrian HT_TARGET_RATE_23 204250003Sadrian}TARGET_POWER_HT_RATES; 205250003Sadrian 206250003Sadrianconst static int mapRate2Index[24]= 207250003Sadrian{ 208250003Sadrian 0,1,1,1,2, 209250003Sadrian 3,4,5,0,1, 210250003Sadrian 1,1,6,7,8, 211250003Sadrian 9,0,1,1,1, 212250003Sadrian 10,11,12,13 213250003Sadrian}; 214250003Sadrian 215250003Sadriantypedef enum targetPowerLegacyRates { 216250003Sadrian LEGACY_TARGET_RATE_6_24, 217250003Sadrian LEGACY_TARGET_RATE_36, 218250003Sadrian LEGACY_TARGET_RATE_48, 219250003Sadrian LEGACY_TARGET_RATE_54 220250003Sadrian}TARGET_POWER_LEGACY_RATES; 221250003Sadrian 222250003Sadriantypedef enum targetPowerCckRates { 223250003Sadrian LEGACY_TARGET_RATE_1L_5L, 224250003Sadrian LEGACY_TARGET_RATE_5S, 225250003Sadrian LEGACY_TARGET_RATE_11L, 226250003Sadrian LEGACY_TARGET_RATE_11S 227250003Sadrian}TARGET_POWER_CCK_RATES; 228250003Sadrian 229250003Sadrian#define MAX_MODAL_RESERVED 11 230250003Sadrian#define MAX_MODAL_FUTURE 5 231250003Sadrian#define MAX_BASE_EXTENSION_FUTURE 2 232250003Sadrian#define MAX_TEMP_SLOPE 8 233250003Sadrian#define OSPREY_CHECKSUM_LOCATION (OSPREY_EEP_START_LOC + 1) 234250003Sadrian 235250003Sadriantypedef struct osprey_BaseEepHeader { 236250003Sadrian u_int16_t reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 237250003Sadrian u_int8_t txrx_mask; //4 bits tx and 4 bits rx 238250003Sadrian EEP_FLAGS op_cap_flags; 239250003Sadrian u_int8_t rf_silent; 240250003Sadrian u_int8_t blue_tooth_options; 241250003Sadrian u_int8_t device_cap; 242250003Sadrian u_int8_t device_type; // takes lower byte in eeprom location 243250003Sadrian int8_t pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 244250003Sadrian u_int8_t params_for_tuning_caps[2]; //placeholder, get more details from Don 245250003Sadrian u_int8_t feature_enable; //bit0 - enable tx temp comp 246250003Sadrian //bit1 - enable tx volt comp 247250003Sadrian //bit2 - enable fastClock - default to 1 248250003Sadrian //bit3 - enable doubling - default to 1 249250003Sadrian //bit4 - enable internal regulator - default to 1 250250003Sadrian //bit5 - enable paprd - default to 0 251250003Sadrian //bit6 - enable TuningCaps - default to 0 252250003Sadrian //bit7 - enable tx_frame_to_xpa_on - default to 0 253250003Sadrian u_int8_t misc_configuration; //misc flags: bit0 - turn down drivestrength 254250003Sadrian // bit 1:2 - 0=don't force, 1=force to thermometer 0, 2=force to thermometer 1, 3=force to thermometer 2 255250003Sadrian // bit 3 - reduce chain mask from 0x7 to 0x3 on 2 stream rates 256250003Sadrian // bit 4 - enable quick drop 257250003Sadrian // bit 5 - enable 8 temp slop 258250003Sadrian // bit 6; enable xLNA_bias_strength 259250003Sadrian // bit 7; enable rf_gain_cap 260250003Sadrian u_int8_t eeprom_write_enable_gpio; 261250003Sadrian u_int8_t wlan_disable_gpio; 262250003Sadrian u_int8_t wlan_led_gpio; 263250003Sadrian u_int8_t rx_band_select_gpio; 264250003Sadrian u_int8_t txrxgain; 265250003Sadrian u_int32_t swreg; // SW controlled internal regulator fields 266250003Sadrian} __packed OSPREY_BASE_EEP_HEADER; 267250003Sadrian 268250003Sadriantypedef struct osprey_BaseExtension_1 { 269250003Sadrian u_int8_t ant_div_control; 270250003Sadrian u_int8_t future[MAX_BASE_EXTENSION_FUTURE]; 271250003Sadrian u_int8_t misc_enable; 272250003Sadrian int8_t tempslopextension[MAX_TEMP_SLOPE]; 273250003Sadrian int8_t quick_drop_low; 274250003Sadrian int8_t quick_drop_high; 275250003Sadrian} __packed OSPREY_BASE_EXTENSION_1; 276250003Sadrian 277250003Sadriantypedef struct osprey_BaseExtension_2 { 278250003Sadrian int8_t temp_slope_low; 279250003Sadrian int8_t temp_slope_high; 280250003Sadrian u_int8_t xatten1_db_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 281250003Sadrian u_int8_t xatten1_margin_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 282250003Sadrian u_int8_t xatten1_db_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 283250003Sadrian u_int8_t xatten1_margin_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 284250003Sadrian} __packed OSPREY_BASE_EXTENSION_2; 285250003Sadrian 286250003Sadriantypedef struct spurChanStruct { 287250003Sadrian u_int16_t spur_chan; 288250003Sadrian u_int8_t spurRangeLow; 289250003Sadrian u_int8_t spurRangeHigh; 290250003Sadrian} __packed SPUR_CHAN; 291250003Sadrian 292250003Sadrian//Note the order of the fields in this structure has been optimized to put all fields likely to change together 293250003Sadriantypedef struct ospreyModalEepHeader { 294250003Sadrian u_int32_t ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 295250003Sadrian u_int32_t ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 296250003Sadrian u_int16_t ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 297250003Sadrian u_int8_t xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 298250003Sadrian u_int8_t xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 299250003Sadrian int8_t temp_slope; 300250003Sadrian int8_t voltSlope; 301250003Sadrian u_int8_t spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 302250003Sadrian int8_t noise_floor_thresh_ch[OSPREY_MAX_CHAINS];// 3 //Check if the register is per chain 303250003Sadrian u_int8_t reserved[MAX_MODAL_RESERVED]; 304250003Sadrian int8_t quick_drop; 305250003Sadrian u_int8_t xpa_bias_lvl; // 1 306250003Sadrian u_int8_t tx_frame_to_data_start; // 1 307250003Sadrian u_int8_t tx_frame_to_pa_on; // 1 308250003Sadrian u_int8_t txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 309250003Sadrian int8_t antenna_gain; // 1 310250003Sadrian u_int8_t switchSettling; // 1 311250003Sadrian int8_t adcDesiredSize; // 1 312250003Sadrian u_int8_t tx_end_to_xpa_off; // 1 313250003Sadrian u_int8_t txEndToRxOn; // 1 314250003Sadrian u_int8_t tx_frame_to_xpa_on; // 1 315250003Sadrian u_int8_t thresh62; // 1 316250003Sadrian u_int32_t paprd_rate_mask_ht20; 317250003Sadrian u_int32_t paprd_rate_mask_ht40; 318250003Sadrian u_int16_t switchcomspdt; 319250003Sadrian u_int8_t xLNA_bias_strength; // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 320250003Sadrian u_int8_t rf_gain_cap; 321250003Sadrian u_int8_t tx_gain_cap; // bit0:4 txgain cap, txgain index for max_txgain + 20 (10dBm higher than max txgain) 322250003Sadrian u_int8_t futureModal[MAX_MODAL_FUTURE]; 323250003Sadrian // last 12 bytes stolen and moved to newly created base extension structure 324250003Sadrian} __packed OSPREY_MODAL_EEP_HEADER; // == 100 B 325250003Sadrian 326250003Sadriantypedef struct ospCalDataPerFreqOpLoop { 327250003Sadrian int8_t ref_power; /* */ 328250003Sadrian u_int8_t volt_meas; /* pdadc voltage at power measurement */ 329250003Sadrian u_int8_t temp_meas; /* pcdac used for power measurement */ 330250003Sadrian int8_t rx_noisefloor_cal; /*range is -60 to -127 create a mapping equation 1db resolution */ 331250003Sadrian int8_t rx_noisefloor_power; /*range is same as noisefloor */ 332250003Sadrian u_int8_t rxTempMeas; /*temp measured when noisefloor cal was performed */ 333250003Sadrian} __packed OSP_CAL_DATA_PER_FREQ_OP_LOOP; 334250003Sadrian 335250003Sadriantypedef struct CalTargetPowerLegacy { 336250003Sadrian u_int8_t t_pow2x[4]; 337250003Sadrian} __packed CAL_TARGET_POWER_LEG; 338250003Sadrian 339250003Sadriantypedef struct ospCalTargetPowerHt { 340250003Sadrian u_int8_t t_pow2x[14]; 341250003Sadrian} __packed OSP_CAL_TARGET_POWER_HT; 342250003Sadrian 343250003Sadrian#if AH_BYTE_ORDER == AH_BIG_ENDIAN 344250003Sadriantypedef struct CalCtlEdgePwr { 345250003Sadrian u_int8_t flag :2, 346250003Sadrian t_power :6; 347250003Sadrian} __packed CAL_CTL_EDGE_PWR; 348250003Sadrian#else 349250003Sadriantypedef struct CalCtlEdgePwr { 350250003Sadrian u_int8_t t_power :6, 351250003Sadrian flag :2; 352250003Sadrian} __packed CAL_CTL_EDGE_PWR; 353250003Sadrian#endif 354250003Sadrian 355250003Sadriantypedef struct ospCalCtlData_5G { 356250003Sadrian CAL_CTL_EDGE_PWR ctl_edges[OSPREY_NUM_BAND_EDGES_5G]; 357250003Sadrian} __packed OSP_CAL_CTL_DATA_5G; 358250003Sadrian 359250003Sadriantypedef struct ospCalCtlData_2G { 360250003Sadrian CAL_CTL_EDGE_PWR ctl_edges[OSPREY_NUM_BAND_EDGES_2G]; 361250003Sadrian} __packed OSP_CAL_CTL_DATA_2G; 362250003Sadrian 363250003Sadriantypedef struct ospreyEeprom { 364250003Sadrian u_int8_t eeprom_version; 365250003Sadrian u_int8_t template_version; 366250003Sadrian u_int8_t mac_addr[6]; 367250003Sadrian u_int8_t custData[OSPREY_CUSTOMER_DATA_SIZE]; 368250003Sadrian 369250003Sadrian OSPREY_BASE_EEP_HEADER base_eep_header; 370250003Sadrian 371250003Sadrian OSPREY_MODAL_EEP_HEADER modal_header_2g; 372250003Sadrian OSPREY_BASE_EXTENSION_1 base_ext1; 373250003Sadrian u_int8_t cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]; 374250003Sadrian OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]; 375250003Sadrian u_int8_t cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 376250003Sadrian u_int8_t cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS]; 377250003Sadrian u_int8_t cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]; 378250003Sadrian u_int8_t cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]; 379250003Sadrian CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 380250003Sadrian CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]; 381250003Sadrian OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]; 382250003Sadrian OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]; 383250003Sadrian u_int8_t ctl_index_2g[OSPREY_NUM_CTLS_2G]; 384250003Sadrian u_int8_t ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 385250003Sadrian OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; 386250003Sadrian 387250003Sadrian OSPREY_MODAL_EEP_HEADER modal_header_5g; 388250003Sadrian OSPREY_BASE_EXTENSION_2 base_ext2; 389250003Sadrian u_int8_t cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]; 390250003Sadrian OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]; 391250003Sadrian u_int8_t cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]; 392250003Sadrian u_int8_t cal_target_freqbin_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]; 393250003Sadrian u_int8_t cal_target_freqbin_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]; 394250003Sadrian CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]; 395250003Sadrian OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]; 396250003Sadrian OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]; 397250003Sadrian u_int8_t ctl_index_5g[OSPREY_NUM_CTLS_5G]; 398250003Sadrian u_int8_t ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 399250003Sadrian OSP_CAL_CTL_DATA_5G ctl_power_data_5g[OSPREY_NUM_CTLS_5G]; 400250003Sadrian} __packed ar9300_eeprom_t; 401250003Sadrian 402250003Sadrian 403250003Sadrian/* 404250003Sadrian** SWAP Functions 405250003Sadrian** used to read EEPROM data, which is apparently stored in little 406250003Sadrian** endian form. We have included both forms of the swap functions, 407250003Sadrian** one for big endian and one for little endian. The indices of the 408250003Sadrian** array elements are the differences 409250003Sadrian*/ 410250003Sadrian#if AH_BYTE_ORDER == AH_BIG_ENDIAN 411250003Sadrian 412250003Sadrian#define AR9300_EEPROM_MAGIC 0x5aa5 413250003Sadrian#define SWAP16(_x) ( (u_int16_t)( (((const u_int8_t *)(&_x))[0] ) |\ 414250003Sadrian ( ( (const u_int8_t *)( &_x ) )[1]<< 8) ) ) 415250003Sadrian 416250003Sadrian#define SWAP32(_x) ((u_int32_t)( \ 417250003Sadrian (((const u_int8_t *)(&_x))[0]) | \ 418250003Sadrian (((const u_int8_t *)(&_x))[1]<< 8) | \ 419250003Sadrian (((const u_int8_t *)(&_x))[2]<<16) | \ 420250003Sadrian (((const u_int8_t *)(&_x))[3]<<24))) 421250003Sadrian 422250003Sadrian#else // AH_BYTE_ORDER 423250003Sadrian 424250003Sadrian#define AR9300_EEPROM_MAGIC 0xa55a 425250003Sadrian#define SWAP16(_x) ( (u_int16_t)( (((const u_int8_t *)(&_x))[1] ) |\ 426250003Sadrian ( ( (const u_int8_t *)( &_x ) )[0]<< 8) ) ) 427250003Sadrian 428250003Sadrian#define SWAP32(_x) ((u_int32_t)( \ 429250003Sadrian (((const u_int8_t *)(&_x))[3]) | \ 430250003Sadrian (((const u_int8_t *)(&_x))[2]<< 8) | \ 431250003Sadrian (((const u_int8_t *)(&_x))[1]<<16) | \ 432250003Sadrian (((const u_int8_t *)(&_x))[0]<<24))) 433250003Sadrian 434250003Sadrian#endif // AH_BYTE_ORDER 435250003Sadrian 436250003Sadrian// OTP registers for OSPREY 437250003Sadrian 438250003Sadrian#define AR_GPIO_IN_OUT 0x4048 // GPIO input / output register 439250003Sadrian#define OTP_MEM_START_ADDRESS 0x14000 440250003Sadrian#define OTP_STATUS0_OTP_SM_BUSY 0x00015f18 441250003Sadrian#define OTP_STATUS1_EFUSE_READ_DATA 0x00015f1c 442250003Sadrian 443250003Sadrian#define OTP_LDO_CONTROL_ENABLE 0x00015f24 444250003Sadrian#define OTP_LDO_STATUS_POWER_ON 0x00015f2c 445250003Sadrian#define OTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00015f00 446250003Sadrian// OTP register for Jupiter 447250003Sadrian#define GLB_OTP_LDO_CONTROL_ENABLE 0x00020020 448250003Sadrian#define GLB_OTP_LDO_STATUS_POWER_ON 0x00020028 449250003Sadrian#define OTP_PGENB_SETUP_HOLD_TIME_DELAY 0x15f34 450250003Sadrian 451250003Sadrian// OTP register for Jupiter BT 452250003Sadrian#define BTOTP_MEM_START_ADDRESS 0x64000 453250003Sadrian#define BTOTP_STATUS0_OTP_SM_BUSY 0x00065f18 454250003Sadrian#define BTOTP_STATUS1_EFUSE_READ_DATA 0x00065f1c 455250003Sadrian#define BTOTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00065f00 456250003Sadrian#define BTOTP_INTF2 0x00065f08 457250003Sadrian#define BTOTP_PGENB_SETUP_HOLD_TIME_DELAY 0x65f34 458250003Sadrian#define BT_RESET_CTL 0x44000 459250003Sadrian#define BT_CLOCK_CONTROL 0x44028 460250003Sadrian 461250003Sadrian 462250003Sadrian// OTP register for WASP 463250003Sadrian#define OTP_MEM_START_ADDRESS_WASP 0x00030000 464250003Sadrian#define OTP_STATUS0_OTP_SM_BUSY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1018) 465250003Sadrian#define OTP_STATUS1_EFUSE_READ_DATA_WASP (OTP_MEM_START_ADDRESS_WASP + 0x101C) 466250003Sadrian#define OTP_LDO_CONTROL_ENABLE_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1024) 467250003Sadrian#define OTP_LDO_STATUS_POWER_ON_WASP (OTP_MEM_START_ADDRESS_WASP + 0x102C) 468250003Sadrian#define OTP_INTF0_EFUSE_WR_ENABLE_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1000) 469250003Sadrian// Below control the access timing of OTP read/write 470250003Sadrian#define OTP_PG_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1008) 471250003Sadrian#define OTP_RD_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x100C) 472250003Sadrian#define OTP_VDDQ_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1030) 473250003Sadrian#define OTP_PGENB_SETUP_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1034) 474250003Sadrian#define OTP_STROBE_PULSE_INTERVAL_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1038) 475250003Sadrian#define OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x103C) 476250003Sadrian 477250003Sadrian#define AR9300_EEPROM_MAGIC_OFFSET 0x0 478250003Sadrian/* reg_off = 4 * (eep_off) */ 479250003Sadrian#define AR9300_EEPROM_S 2 480250003Sadrian#define AR9300_EEPROM_OFFSET 0x2000 481250003Sadrian#ifdef AR9100 482250003Sadrian#define AR9300_EEPROM_START_ADDR 0x1fff1000 483250003Sadrian#else 484250003Sadrian#define AR9300_EEPROM_START_ADDR 0x503f1200 485250003Sadrian#endif 486250003Sadrian#define AR9300_FLASH_CAL_START_OFFSET 0x1000 487250003Sadrian#define AR9300_EEPROM_MAX 0xae0 488250003Sadrian#define IS_EEP_MINOR_V3(_ahp) (ar9300_eeprom_get((_ahp), EEP_MINOR_REV) >= AR9300_EEP_MINOR_VER_3) 489250003Sadrian 490250003Sadrian#define ar9300_get_ntxchains(_txchainmask) \ 491250003Sadrian (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 492250003Sadrian 493250003Sadrian/* RF silent fields in \ */ 494250003Sadrian#define EEP_RFSILENT_ENABLED 0x0001 /* bit 0: enabled/disabled */ 495250003Sadrian#define EEP_RFSILENT_ENABLED_S 0 /* bit 0: enabled/disabled */ 496250003Sadrian#define EEP_RFSILENT_POLARITY 0x0002 /* bit 1: polarity */ 497250003Sadrian#define EEP_RFSILENT_POLARITY_S 1 /* bit 1: polarity */ 498250003Sadrian#define EEP_RFSILENT_GPIO_SEL 0x00fc /* bits 2..7: gpio PIN */ 499250003Sadrian#define EEP_RFSILENT_GPIO_SEL_S 2 /* bits 2..7: gpio PIN */ 500250003Sadrian#define AR9300_EEP_VER 0xE 501250003Sadrian#define AR9300_BCHAN_UNUSED 0xFF 502250003Sadrian#define AR9300_MAX_RATE_POWER 63 503250003Sadrian 504250003Sadriantypedef enum { 505250003Sadrian CALDATA_AUTO=0, 506250003Sadrian CALDATA_EEPROM, 507250003Sadrian CALDATA_FLASH, 508250003Sadrian CALDATA_OTP 509250003Sadrian} CALDATA_TYPE; 510250003Sadrian 511250003Sadriantypedef enum { 512250003Sadrian EEP_NFTHRESH_5, 513250003Sadrian EEP_NFTHRESH_2, 514250003Sadrian EEP_MAC_MSW, 515250003Sadrian EEP_MAC_MID, 516250003Sadrian EEP_MAC_LSW, 517250003Sadrian EEP_REG_0, 518250003Sadrian EEP_REG_1, 519250003Sadrian EEP_OP_CAP, 520250003Sadrian EEP_OP_MODE, 521250003Sadrian EEP_RF_SILENT, 522250003Sadrian EEP_OB_5, 523250003Sadrian EEP_DB_5, 524250003Sadrian EEP_OB_2, 525250003Sadrian EEP_DB_2, 526250003Sadrian EEP_MINOR_REV, 527250003Sadrian EEP_TX_MASK, 528250003Sadrian EEP_RX_MASK, 529250003Sadrian EEP_FSTCLK_5G, 530250003Sadrian EEP_RXGAIN_TYPE, 531250003Sadrian EEP_OL_PWRCTRL, 532250003Sadrian EEP_TXGAIN_TYPE, 533250003Sadrian EEP_RC_CHAIN_MASK, 534250003Sadrian EEP_DAC_HPWR_5G, 535250003Sadrian EEP_FRAC_N_5G, 536250003Sadrian EEP_DEV_TYPE, 537250003Sadrian EEP_TEMPSENSE_SLOPE, 538250003Sadrian EEP_TEMPSENSE_SLOPE_PAL_ON, 539250003Sadrian EEP_PWR_TABLE_OFFSET, 540250003Sadrian EEP_DRIVE_STRENGTH, 541250003Sadrian EEP_INTERNAL_REGULATOR, 542250003Sadrian EEP_SWREG, 543250003Sadrian EEP_PAPRD_ENABLED, 544250003Sadrian EEP_ANTDIV_control, 545250003Sadrian EEP_CHAIN_MASK_REDUCE, 546250003Sadrian} EEPROM_PARAM; 547250003Sadrian 548250003Sadrian#define AR9300_RATES_OFDM_OFFSET 0 549250003Sadrian#define AR9300_RATES_CCK_OFFSET 4 550250003Sadrian#define AR9300_RATES_HT20_OFFSET 8 551250003Sadrian#define AR9300_RATES_HT40_OFFSET 22 552250003Sadriantypedef enum ar9300_Rates { 553250003Sadrian ALL_TARGET_LEGACY_6_24, 554250003Sadrian ALL_TARGET_LEGACY_36, 555250003Sadrian ALL_TARGET_LEGACY_48, 556250003Sadrian ALL_TARGET_LEGACY_54, 557250003Sadrian ALL_TARGET_LEGACY_1L_5L, 558250003Sadrian ALL_TARGET_LEGACY_5S, 559250003Sadrian ALL_TARGET_LEGACY_11L, 560250003Sadrian ALL_TARGET_LEGACY_11S, 561250003Sadrian ALL_TARGET_HT20_0_8_16, 562250003Sadrian ALL_TARGET_HT20_1_3_9_11_17_19, 563250003Sadrian ALL_TARGET_HT20_4, 564250003Sadrian ALL_TARGET_HT20_5, 565250003Sadrian ALL_TARGET_HT20_6, 566250003Sadrian ALL_TARGET_HT20_7, 567250003Sadrian ALL_TARGET_HT20_12, 568250003Sadrian ALL_TARGET_HT20_13, 569250003Sadrian ALL_TARGET_HT20_14, 570250003Sadrian ALL_TARGET_HT20_15, 571250003Sadrian ALL_TARGET_HT20_20, 572250003Sadrian ALL_TARGET_HT20_21, 573250003Sadrian ALL_TARGET_HT20_22, 574250003Sadrian ALL_TARGET_HT20_23, 575250003Sadrian ALL_TARGET_HT40_0_8_16, 576250003Sadrian ALL_TARGET_HT40_1_3_9_11_17_19, 577250003Sadrian ALL_TARGET_HT40_4, 578250003Sadrian ALL_TARGET_HT40_5, 579250003Sadrian ALL_TARGET_HT40_6, 580250003Sadrian ALL_TARGET_HT40_7, 581250003Sadrian ALL_TARGET_HT40_12, 582250003Sadrian ALL_TARGET_HT40_13, 583250003Sadrian ALL_TARGET_HT40_14, 584250003Sadrian ALL_TARGET_HT40_15, 585250003Sadrian ALL_TARGET_HT40_20, 586250003Sadrian ALL_TARGET_HT40_21, 587250003Sadrian ALL_TARGET_HT40_22, 588250003Sadrian ALL_TARGET_HT40_23, 589250003Sadrian ar9300_rate_size 590250003Sadrian} AR9300_RATES; 591250003Sadrian 592250003Sadrian 593250003Sadrian/************************************************************************** 594250003Sadrian * fbin2freq 595250003Sadrian * 596250003Sadrian * Get channel value from binary representation held in eeprom 597250003Sadrian * RETURNS: the frequency in MHz 598250003Sadrian */ 599250003Sadrianstatic inline u_int16_t 600250003Sadrianfbin2freq(u_int8_t fbin, HAL_BOOL is_2ghz) 601250003Sadrian{ 602250003Sadrian /* 603250003Sadrian * Reserved value 0xFF provides an empty definition both as 604250003Sadrian * an fbin and as a frequency - do not convert 605250003Sadrian */ 606250003Sadrian if (fbin == AR9300_BCHAN_UNUSED) 607250003Sadrian { 608250003Sadrian return fbin; 609250003Sadrian } 610250003Sadrian 611250003Sadrian return (u_int16_t)((is_2ghz) ? (2300 + fbin) : (4800 + 5 * fbin)); 612250003Sadrian} 613250003Sadrian 614250003Sadrianextern int CompressionHeaderUnpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor); 615250003Sadrianextern void Ar9300EepromFormatConvert(ar9300_eeprom_t *mptr); 616250003Sadrianextern HAL_BOOL ar9300_eeprom_restore(struct ath_hal *ah); 617250003Sadrianextern int ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr, int /*msize*/); 618250003Sadrianextern int ar9300_eeprom_base_address(struct ath_hal *ah); 619250003Sadrianextern int ar9300_eeprom_volatile(struct ath_hal *ah); 620250003Sadrianextern int ar9300_eeprom_low_limit(struct ath_hal *ah); 621250003Sadrianextern u_int16_t ar9300_compression_checksum(u_int8_t *data, int dsize); 622250003Sadrianextern int ar9300_compression_header_unpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor); 623250003Sadrian 624250003Sadrianextern u_int16_t ar9300_eeprom_struct_size(void); 625250003Sadrianextern ar9300_eeprom_t *ar9300EepromStructInit(int default_index); 626250003Sadrianextern ar9300_eeprom_t *ar9300EepromStructGet(void); 627250003Sadrianextern ar9300_eeprom_t *ar9300_eeprom_struct_default(int default_index); 628250003Sadrianextern ar9300_eeprom_t *ar9300_eeprom_struct_default_find_by_id(int ver); 629250003Sadrianextern int ar9300_eeprom_struct_default_many(void); 630250003Sadrianextern int ar9300EepromUpdateCalPier(int pierIdx, int freq, int chain, 631250003Sadrian int pwrCorrection, int volt_meas, int temp_meas); 632250003Sadrianextern int ar9300_power_control_override(struct ath_hal *ah, int frequency, int *correction, int *voltage, int *temperature); 633250003Sadrian 634250003Sadrianextern void ar9300EepromDisplayCalData(int for2GHz); 635250003Sadrianextern void ar9300EepromDisplayAll(void); 636250003Sadrianextern void ar9300_set_target_power_from_eeprom(struct ath_hal *ah, u_int16_t freq, 637250003Sadrian u_int8_t *target_power_val_t2); 638250003Sadrianextern HAL_BOOL ar9300_eeprom_set_power_per_rate_table(struct ath_hal *ah, 639250003Sadrian ar9300_eeprom_t *p_eep_data, 640250008Sadrian const struct ieee80211_channel *chan, 641250003Sadrian u_int8_t *p_pwr_array, 642250003Sadrian u_int16_t cfg_ctl, 643250003Sadrian u_int16_t antenna_reduction, 644250003Sadrian u_int16_t twice_max_regulatory_power, 645250003Sadrian u_int16_t power_limit, 646250003Sadrian u_int8_t chainmask); 647250003Sadrianextern int ar9300_transmit_power_reg_write(struct ath_hal *ah, u_int8_t *p_pwr_array); 648250003Sadrian 649250003Sadrianextern u_int8_t ar9300_eeprom_get_legacy_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); 650250003Sadrianextern u_int8_t ar9300_eeprom_get_ht20_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); 651250003Sadrianextern u_int8_t ar9300_eeprom_get_ht40_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); 652250003Sadrianextern u_int8_t ar9300_eeprom_get_cck_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq); 653250003Sadrianextern HAL_BOOL ar9300_internal_regulator_apply(struct ath_hal *ah); 654250003Sadrianextern HAL_BOOL ar9300_drive_strength_apply(struct ath_hal *ah); 655250003Sadrianextern HAL_BOOL ar9300_attenuation_apply(struct ath_hal *ah, u_int16_t channel); 656250003Sadrianextern int32_t ar9300_thermometer_get(struct ath_hal *ah); 657250003Sadrianextern HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah); 658250003Sadrianextern HAL_BOOL ar9300_xpa_timing_control_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 659250003Sadrianextern HAL_BOOL ar9300_x_lNA_bias_strength_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 660250003Sadrian 661250003Sadrianextern int32_t ar9300MacAdressGet(u_int8_t *mac); 662250003Sadrianextern int32_t ar9300CustomerDataGet(u_int8_t *data, int32_t len); 663250003Sadrianextern int32_t ar9300ReconfigDriveStrengthGet(void); 664250003Sadrianextern int32_t ar9300EnableTempCompensationGet(void); 665250003Sadrianextern int32_t ar9300EnableVoltCompensationGet(void); 666250003Sadrianextern int32_t ar9300FastClockEnableGet(void); 667250003Sadrianextern int32_t ar9300EnableDoublingGet(void); 668250003Sadrian 669250003Sadrianextern u_int16_t *ar9300_regulatory_domain_get(struct ath_hal *ah); 670250003Sadrianextern int32_t ar9300_eeprom_write_enable_gpio_get(struct ath_hal *ah); 671250003Sadrianextern int32_t ar9300_wlan_led_gpio_get(struct ath_hal *ah); 672250003Sadrianextern int32_t ar9300_wlan_disable_gpio_get(struct ath_hal *ah); 673250003Sadrianextern int32_t ar9300_rx_band_select_gpio_get(struct ath_hal *ah); 674250003Sadrianextern int32_t ar9300_rx_gain_index_get(struct ath_hal *ah); 675250003Sadrianextern int32_t ar9300_tx_gain_index_get(struct ath_hal *ah); 676250003Sadrianextern int32_t ar9300_xpa_bias_level_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 677250003Sadrianextern HAL_BOOL ar9300_xpa_bias_level_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 678250003Sadrianextern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 679250003Sadrianextern u_int32_t ar9300_ant_ctrl_common2_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 680250003Sadrianextern u_int16_t ar9300_ant_ctrl_chain_get(struct ath_hal *ah, int chain, HAL_BOOL is_2ghz); 681250003Sadrianextern HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 682250003Sadrian/* since valid noise floor values are negative, returns 1 on error */ 683250003Sadrianextern int32_t ar9300_noise_floor_cal_or_power_get( 684250003Sadrian struct ath_hal *ah, int32_t frequency, int32_t ichain, HAL_BOOL use_cal); 685250003Sadrian#define ar9300NoiseFloorGet(ah, frequency, ichain) \ 686250003Sadrian ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 1/*use_cal*/) 687250003Sadrian#define ar9300NoiseFloorPowerGet(ah, frequency, ichain) \ 688250003Sadrian ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 0/*use_cal*/) 689250003Sadrianextern void ar9300_eeprom_template_preference(int32_t value); 690250003Sadrianextern int32_t ar9300_eeprom_template_install(struct ath_hal *ah, int32_t value); 691250003Sadrianextern void ar9300_calibration_data_set(struct ath_hal *ah, int32_t source); 692250003Sadrianextern int32_t ar9300_calibration_data_get(struct ath_hal *ah); 693250003Sadrianextern int32_t ar9300_calibration_data_address_get(struct ath_hal *ah); 694250003Sadrianextern void ar9300_calibration_data_address_set(struct ath_hal *ah, int32_t source); 695250003Sadrianextern HAL_BOOL ar9300_calibration_data_read_flash(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 696250003Sadrianextern HAL_BOOL ar9300_calibration_data_read_eeprom(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 697250003Sadrianextern HAL_BOOL ar9300_calibration_data_read_otp(struct ath_hal *ah, long address, u_int8_t *buffer, int many, HAL_BOOL is_wifi); 698250003Sadrianextern HAL_BOOL ar9300_calibration_data_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 699250003Sadrianextern int32_t ar9300_eeprom_size(struct ath_hal *ah); 700250003Sadrianextern int32_t ar9300_otp_size(struct ath_hal *ah); 701250003Sadrianextern HAL_BOOL ar9300_calibration_data_read_array(struct ath_hal *ah, int address, u_int8_t *buffer, int many); 702250003Sadrian 703250003Sadrian 704250003Sadrian 705250003Sadrian#if defined(WIN32) || defined(WIN64) 706250003Sadrian#pragma pack (pop, ar9300) 707250003Sadrian#endif 708250003Sadrian 709250003Sadrian#endif /* _ATH_AR9300_EEP_H_ */ 710