ar9300_radio.c revision 250008
1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "opt_ah.h" 18 19#include "ah.h" 20#include "ah_internal.h" 21 22#include "ar9300/ar9300.h" 23#include "ar9300/ar9300reg.h" 24#include "ar9300/ar9300phy.h" 25 26/* chansel table, used by Hornet and Poseidon */ 27static const u_int32_t ar9300_chansel_xtal_25M[] = { 28 0x101479e, /* Freq 2412 - (128 << 17) + 83870 */ 29 0x101d027, /* Freq 2417 - (128 << 17) + 118823 */ 30 0x10258af, /* Freq 2422 - (129 << 17) + 22703 */ 31 0x102e138, /* Freq 2427 - (129 << 17) + 57656 */ 32 0x10369c0, /* Freq 2432 - (129 << 17) + 92608 */ 33 0x103f249, /* Freq 2437 - (129 << 17) + 127561 */ 34 0x1047ad1, /* Freq 2442 - (130 << 17) + 31441 */ 35 0x105035a, /* Freq 2447 - (130 << 17) + 66394 */ 36 0x1058be2, /* Freq 2452 - (130 << 17) + 101346 */ 37 0x106146b, /* Freq 2457 - (131 << 17) + 5227 */ 38 0x1069cf3, /* Freq 2462 - (131 << 17) + 40179 */ 39 0x107257c, /* Freq 2467 - (131 << 17) + 75132 */ 40 0x107ae04, /* Freq 2472 - (131 << 17) + 110084 */ 41 0x108f5b2, /* Freq 2484 - (132 << 17) + 62898 */ 42}; 43 44static const u_int32_t ar9300_chansel_xtal_40M[] = { 45 0xa0ccbe, /* Freq 2412 - (80 << 17) + 52414 */ 46 0xa12213, /* Freq 2417 - (80 << 17) + 74259 */ 47 0xa17769, /* Freq 2422 - (80 << 17) + 96105 */ 48 0xa1ccbe, /* Freq 2427 - (80 << 17) + 117950 */ 49 0xa22213, /* Freq 2432 - (81 << 17) + 8723 */ 50 0xa27769, /* Freq 2437 - (81 << 17) + 30569 */ 51 0xa2ccbe, /* Freq 2442 - (81 << 17) + 52414 */ 52 0xa32213, /* Freq 2447 - (81 << 17) + 74259 */ 53 0xa37769, /* Freq 2452 - (81 << 17) + 96105 */ 54 0xa3ccbe, /* Freq 2457 - (81 << 17) + 117950 */ 55 0xa42213, /* Freq 2462 - (82 << 17) + 8723 */ 56 0xa47769, /* Freq 2467 - (82 << 17) + 30569 */ 57 0xa4ccbe, /* Freq 2472 - (82 << 17) + 52414 */ 58 0xa5998b, /* Freq 2484 - (82 << 17) + 104843 */ 59}; 60 61 62/* 63 * Take the MHz channel value and set the Channel value 64 * 65 * ASSUMES: Writes enabled to analog bus 66 * 67 * Actual Expression, 68 * 69 * For 2GHz channel, 70 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 71 * (freq_ref = 40MHz) 72 * 73 * For 5GHz channel, 74 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) 75 * (freq_ref = 40MHz/(24>>amode_ref_sel)) 76 * 77 * For 5GHz channels which are 5MHz spaced, 78 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) 79 * (freq_ref = 40MHz) 80 */ 81static HAL_BOOL 82ar9300_set_channel(struct ath_hal *ah, struct ieee80211_channel *chan) 83{ 84 u_int16_t b_mode, frac_mode = 0, a_mode_ref_sel = 0; 85 u_int32_t freq, channel_sel, reg32; 86 u_int8_t clk_25mhz = AH9300(ah)->clk_25mhz; 87 CHAN_CENTERS centers; 88 int load_synth_channel; 89#ifdef AH_DEBUG 90 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 91#endif 92 93#ifdef AH_DEBUG 94 OS_MARK(ah, AH_MARK_SETCHANNEL, ichan->channel); 95#endif 96 97 ar9300_get_channel_centers(ah, chan, ¢ers); 98 freq = centers.synth_center; 99 100 101 if (freq < 4800) { /* 2 GHz, fractional mode */ 102 b_mode = 1; /* 2 GHz */ 103 104 if (AR_SREV_HORNET(ah)) { 105 /* 106 * XXX TODO: this should call ieee80211_mhz2ieee which will 107 * take care of the up/down conversion and GSM mapping. 108 * However, the HAL _can't_ call that, so we'll need to 109 * introduce it in ah_osdep or something. 110 */ 111#if 0 112 u_int32_t ichan = 113 ieee80211_mhz2ieee(ah, chan->ic_freq, chan->ic_flags); 114 HALASSERT(ichan > 0 && ichan <= 14); 115 if (clk_25mhz) { 116 channel_sel = ar9300_chansel_xtal_25M[ichan - 1]; 117 } else { 118 channel_sel = ar9300_chansel_xtal_40M[ichan - 1]; 119 } 120#else 121 ath_hal_printf(ah, "%s: unimplemented, implement!\n", __func__); 122 return AH_FALSE; 123#endif 124 } else if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) { 125 u_int32_t channel_frac; 126 /* 127 * freq_ref = (40 / (refdiva >> a_mode_ref_sel)); 128 * (where refdiva = 1 and amoderefsel = 0) 129 * ndiv = ((chan_mhz * 4) / 3) / freq_ref; 130 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 131 */ 132 channel_sel = (freq * 4) / 120; 133 channel_frac = (((freq * 4) % 120) * 0x20000) / 120; 134 channel_sel = (channel_sel << 17) | (channel_frac); 135 } else if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) { 136 u_int32_t channel_frac; 137 if (clk_25mhz) { 138 /* 139 * freq_ref = (50 / (refdiva >> a_mode_ref_sel)); 140 * (where refdiva = 1 and amoderefsel = 0) 141 * ndiv = ((chan_mhz * 4) / 3) / freq_ref; 142 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 143 */ 144 if (AR_SREV_SCORPION(ah)) { 145 /* Doubler is off for Scorpion */ 146 channel_sel = (freq * 4) / 75; 147 channel_frac = (((freq * 4) % 75) * 0x20000) / 75; 148 } else { 149 channel_sel = (freq * 2) / 75; 150 channel_frac = (((freq * 2) % 75) * 0x20000) / 75; 151 } 152 } else { 153 /* 154 * freq_ref = (50 / (refdiva >> a_mode_ref_sel)); 155 * (where refdiva = 1 and amoderefsel = 0) 156 * ndiv = ((chan_mhz * 4) / 3) / freq_ref; 157 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 158 */ 159 if (AR_SREV_SCORPION(ah)) { 160 /* Doubler is off for Scorpion */ 161 channel_sel = (freq * 4) / 120; 162 channel_frac = (((freq * 4) % 120) * 0x20000) / 120; 163 } else { 164 channel_sel = (freq * 2) / 120; 165 channel_frac = (((freq * 2) % 120) * 0x20000) / 120; 166 } 167 } 168 channel_sel = (channel_sel << 17) | (channel_frac); 169 } else { 170 channel_sel = CHANSEL_2G(freq); 171 } 172 } else { 173 b_mode = 0; /* 5 GHz */ 174 if ((AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) && clk_25mhz){ 175 u_int32_t channel_frac; 176 /* 177 * freq_ref = (50 / (refdiva >> amoderefsel)); 178 * (refdiva = 1, amoderefsel = 0) 179 * ndiv = ((chan_mhz * 2) / 3) / freq_ref; 180 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 181 */ 182 channel_sel = freq / 75 ; 183 channel_frac = ((freq % 75) * 0x20000) / 75; 184 channel_sel = (channel_sel << 17) | (channel_frac); 185 } else { 186 channel_sel = CHANSEL_5G(freq); 187 /* Doubler is ON, so, divide channel_sel by 2. */ 188 channel_sel >>= 1; 189 } 190 } 191 192 193 /* Enable fractional mode for all channels */ 194 frac_mode = 1; 195 a_mode_ref_sel = 0; 196 load_synth_channel = 0; 197 198 reg32 = (b_mode << 29); 199 OS_REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 200 201 /* Enable Long shift Select for Synthesizer */ 202 OS_REG_RMW_FIELD(ah, 203 AR_PHY_65NM_CH0_SYNTH4, AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); 204 205 /* program synth. setting */ 206 reg32 = 207 (channel_sel << 2) | 208 (a_mode_ref_sel << 28) | 209 (frac_mode << 30) | 210 (load_synth_channel << 31); 211 if (IEEE80211_IS_CHAN_QUARTER(chan)) { 212 reg32 += CHANSEL_5G_DOT5MHZ; 213 } 214 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 215 /* Toggle Load Synth channel bit */ 216 load_synth_channel = 1; 217 reg32 |= load_synth_channel << 31; 218 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 219 220 221 AH_PRIVATE(ah)->ah_curchan = chan; 222 223 return AH_TRUE; 224} 225 226 227#if 0 228static HAL_BOOL 229ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans, 230 u_int32_t nchans) 231{ 232 int i; 233 234 for (i = 0; i < nchans; i++) { 235 chans[i].max_tx_power = AR9300_MAX_RATE_POWER; 236 chans[i].min_tx_power = AR9300_MAX_RATE_POWER; 237 } 238 return AH_TRUE; 239} 240#endif 241 242/* XXX FreeBSD */ 243static HAL_BOOL 244ar9300_get_chip_power_limits(struct ath_hal *ah, 245 struct ieee80211_channel *chan) 246{ 247 /* XXX ? */ 248 chan->ic_minpower = 0; 249 chan->ic_maxpower = AR9300_MAX_RATE_POWER; 250 251 return AH_TRUE; 252} 253 254HAL_BOOL 255ar9300_rf_attach(struct ath_hal *ah, HAL_STATUS *status) 256{ 257 struct ath_hal_9300 *ahp = AH9300(ah); 258 259 ahp->ah_rf_hal.set_channel = ar9300_set_channel; 260 ahp->ah_rf_hal.get_chip_power_lim = ar9300_get_chip_power_limits; 261 262 *status = HAL_OK; 263 264 return AH_TRUE; 265} 266