vybrid.dtsi revision 266251
1/*- 2 * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/sys/boot/fdt/dts/arm/vybrid.dtsi 262614 2014-02-28 18:29:09Z imp $ 27 */ 28 29/ { 30 model = "Freescale Vybrid Family"; 31 compatible = "freescale,vybrid", "fsl,mvf"; 32 #address-cells = <1>; 33 #size-cells = <1>; 34 35 interrupt-parent = <&GIC>; 36 37 aliases { 38 soc = &SOC; 39 serial0 = &serial0; 40 serial1 = &serial1; 41 sai0 = &sai0; 42 sai1 = &sai1; 43 sai2 = &sai2; 44 sai3 = &sai3; 45 esai = &esai; 46 adc0 = &adc0; 47 adc1 = &adc1; 48 edma0 = &edma0; 49 edma1 = &edma1; 50 src = &SRC; 51 }; 52 53 SOC: vybrid { 54 #address-cells = <1>; 55 #size-cells = <1>; 56 compatible = "simple-bus"; 57 ranges; 58 bus-frequency = <0>; 59 60 SRC: src@4006E000 { 61 compatible = "fsl,mvf600-src"; 62 reg = <0x4006E000 0x100>; 63 }; 64 65 mscm@40001000 { 66 compatible = "fsl,mvf600-mscm"; 67 reg = <0x40001000 0x1000>; 68 }; 69 70 GIC: interrupt-controller@01c81000 { 71 compatible = "arm,gic"; 72 reg = <0x40003000 0x1000>, /* Distributor Registers */ 73 <0x40002100 0x100>; /* CPU Interface Registers */ 74 interrupt-controller; 75 #interrupt-cells = <1>; 76 }; 77 78 anadig@40050000 { 79 compatible = "fsl,mvf600-anadig"; 80 reg = <0x40050000 0x300>; 81 }; 82 83 ccm@4006b000 { 84 compatible = "fsl,mvf600-ccm"; 85 reg = <0x4006b000 0x1000>; 86 clock_names = "pll4"; 87 }; 88 89 mp_tmr@40002100 { 90 compatible = "arm,mpcore-timers"; 91 clock-frequency = <133000000>; 92 #address-cells = <1>; 93 #size-cells = <0>; 94 reg = < 0x40002200 0x100 >, /* Global Timer Registers */ 95 < 0x40002600 0x100 >; /* Private Timer Registers */ 96 interrupts = < 27 29 >; 97 interrupt-parent = < &GIC >; 98 }; 99 100 dmamux@40024000 { 101 compatible = "fsl,mvf600-dmamux"; 102 reg = <0x40024000 0x100>, 103 <0x40025000 0x100>, 104 <0x400A1000 0x100>, 105 <0x400A2000 0x100>; 106 }; 107 108 edma0: edma@40018000 { 109 compatible = "fsl,mvf600-edma"; 110 reg = <0x40018000 0x1000>, 111 <0x40019000 0x1000>; /* TCD */ 112 interrupts = < 40 41 >; 113 interrupt-parent = <&GIC>; 114 device-id = < 0 >; 115 status = "disabled"; 116 }; 117 118 edma1: edma@40098000 { 119 compatible = "fsl,mvf600-edma"; 120 reg = <0x40098000 0x1000>, 121 <0x40099000 0x1000>; /* TCD */ 122 interrupts = < 42 43 >; 123 interrupt-parent = <&GIC>; 124 device-id = < 1 >; 125 status = "disabled"; 126 }; 127 128 pit@40037000 { 129 compatible = "fsl,mvf600-pit"; 130 reg = <0x40037000 0x1000>; 131 interrupts = < 71 >; 132 interrupt-parent = <&GIC>; 133 clock-frequency = < 24000000 >; 134 }; 135 136 lptmr@40040000 { 137 compatible = "fsl,mvf600-lptmr"; 138 reg = <0x40040000 0x1000>; 139 interrupts = < 72 >; 140 interrupt-parent = <&GIC>; 141 clock-frequency = < 24000000 >; 142 }; 143 144 iomuxc@40048000 { 145 compatible = "fsl,mvf600-iomuxc"; 146 reg = <0x40048000 0x1000>; 147 }; 148 149 gpio@400FF000 { 150 compatible = "fsl,mvf600-gpio"; 151 reg = <0x400FF000 0x200>; 152 #gpio-cells = <3>; 153 gpio-controller; 154 interrupts = < 139 140 141 142 143 >; 155 interrupt-parent = <&GIC>; 156 }; 157 158 nand@400E0000 { 159 #address-cells = <1>; 160 #size-cells = <1>; 161 compatible = "fsl,mvf600-nand"; 162 reg = <0x400E0000 0x10000>; 163 interrupts = < 115 >; 164 interrupt-parent = <&GIC>; 165 clock_names = "nand"; 166 status = "disabled"; 167 168 partition@40000 { 169 reg = <0x40000 0x200000>; /* 2MB */ 170 label = "u-boot"; 171 read-only; 172 }; 173 174 partition@240000 { 175 reg = <0x240000 0x200000>; /* 2MB */ 176 label = "test"; 177 }; 178 179 partition@440000 { 180 reg = <0x440000 0xa00000>; /* 10MB */ 181 label = "kernel"; 182 }; 183 184 partition@e40000 { 185 reg = <0xe40000 0x1e000000>; /* 480MB */ 186 label = "root"; 187 }; 188 }; 189 190 sdhci0: sdhci@400B1000 { 191 compatible = "fsl,mvf600-sdhci"; 192 reg = <0x400B1000 0x1000>; 193 interrupts = < 59 >; 194 interrupt-parent = <&GIC>; 195 clock-frequency = <50000000>; 196 status = "disabled"; 197 clock_names = "esdhc0"; 198 }; 199 200 sdhci1: sdhci@400B2000 { 201 compatible = "fsl,mvf600-sdhci"; 202 reg = <0x400B2000 0x1000>; 203 interrupts = < 60 >; 204 interrupt-parent = <&GIC>; 205 clock-frequency = <50000000>; 206 status = "disabled"; 207 clock_names = "esdhc1"; 208 iomux_config = < 14 0x500060 209 15 0x500060 210 16 0x500060 211 17 0x500060 212 18 0x500060 213 19 0x500060 >; 214 }; 215 216 serial0: serial@40027000 { 217 compatible = "fsl,mvf600-uart"; 218 reg = <0x40027000 0x1000>; 219 interrupts = <93>; 220 interrupt-parent = <&GIC>; 221 current-speed = <115200>; 222 clock-frequency = < 24000000 >; 223 status = "disabled"; 224 }; 225 226 serial1: serial@40028000 { 227 compatible = "fsl,mvf600-uart"; 228 reg = <0x40028000 0x1000>; 229 interrupts = <94>; 230 interrupt-parent = <&GIC>; 231 current-speed = <115200>; 232 clock-frequency = < 24000000 >; 233 status = "disabled"; 234 }; 235 236 usb@40034000 { 237 compatible = "fsl,mvf600-usb-ehci", "usb-ehci"; 238 reg = < 0x40034000 0x1000 >, /* ehci */ 239 < 0x40035000 0x1000 >, /* usbc */ 240 < 0x40050800 0x100 >; /* phy */ 241 interrupts = < 107 >; 242 interrupt-parent = <&GIC>; 243 iomux_config = < 134 0x0001be 244 7 0x200060 >; 245 }; 246 247 usb@400b4000 { 248 compatible = "fsl,mvf600-usb-ehci", "usb-ehci"; 249 reg = < 0x400b4000 0x1000 >, /* ehci */ 250 < 0x400b5000 0x1000 >, /* usbc */ 251 < 0x40050C00 0x100 >; /* phy */ 252 interrupts = < 108 >; 253 interrupt-parent = <&GIC>; 254 iomux_config = < 134 0x0001be 255 7 0x200060 >; 256 }; 257 258 fec0: ethernet@400D0000 { 259 compatible = "fsl,mvf600-fec"; 260 reg = <0x400D0000 0x1000>; 261 interrupts = < 110 >; 262 interrupt-parent = <&GIC>; 263 phy-mode = "rmii"; 264 phy-disable-preamble; 265 status = "disabled"; 266 clock_names = "enet"; 267 iomux_config = < 45 0x100061 268 46 0x100061 269 47 0x100061 270 48 0x100060 271 49 0x100060 272 50 0x100060 273 51 0x100060 274 52 0x100060 275 53 0x100060 >; 276 }; 277 278 fec1: ethernet@400D1000 { 279 compatible = "fsl,mvf600-fec"; 280 reg = <0x400D1000 0x1000>; 281 interrupts = < 111 >; 282 interrupt-parent = <&GIC>; 283 phy-mode = "rmii"; 284 phy-disable-preamble; 285 status = "disabled"; 286 clock_names = "enet"; 287 iomux_config = < 54 0x103192 288 55 0x103193 289 56 0x103191 290 57 0x103191 291 58 0x103191 292 59 0x103191 293 60 0x103192 294 61 0x103192 295 62 0x103192 >; 296 }; 297 298 sai0: sai@4002F000 { 299 compatible = "fsl,mvf600-sai"; 300 reg = <0x4002F000 0x1000>; 301 interrupts = < 116 >; 302 interrupt-parent = <&GIC>; 303 status = "disabled"; 304 }; 305 306 sai1: sai@40030000 { 307 compatible = "fsl,mvf600-sai"; 308 reg = <0x40030000 0x1000>; 309 interrupts = < 117 >; 310 interrupt-parent = <&GIC>; 311 status = "disabled"; 312 }; 313 314 sai2: sai@40031000 { 315 compatible = "fsl,mvf600-sai"; 316 reg = <0x40031000 0x1000>; 317 interrupts = < 118 >; 318 interrupt-parent = <&GIC>; 319 status = "disabled"; 320 }; 321 322 sai3: sai@40032000 { 323 compatible = "fsl,mvf600-sai"; 324 reg = <0x40032000 0x1000>; 325 interrupts = < 119 >; 326 interrupt-parent = <&GIC>; 327 status = "disabled"; 328 edma-controller = <&edma1>; 329 edma-src-receive = < 8 >; 330 edma-src-transmit = < 9 >; 331 edma-mux-group = < 1 >; 332 clock_names = "sai3", "cko1"; 333 iomux_config = < 16 0x200060 334 19 0x200060 335 21 0x200060 336 40 0x400061 >; /* CKO1 */ 337 }; 338 339 esai: esai@40062000 { 340 compatible = "fsl,mvf600-esai"; 341 reg = <0x40062000 0x1000>; 342 interrupts = < 120 >; 343 interrupt-parent = <&GIC>; 344 status = "disabled"; 345 clock_names = "esai"; 346 iomux_config = < 45 0x400061 347 46 0x400061 348 47 0x400061 349 48 0x400060 350 49 0x400060 351 50 0x400060 352 51 0x400060 353 52 0x400060 354 78 0x3038df 355 40 0x400061 >; 356 }; 357 358 spi0: spi@4002C000 { 359 compatible = "fsl,mvf600-spi"; 360 reg = <0x4002C000 0x1000>; 361 interrupts = < 99 >; 362 interrupt-parent = <&GIC>; 363 status = "disabled"; 364 iomux_config = < 40 0x100061 365 41 0x100061 366 42 0x100060 367 43 0x100060 368 44 0x100061 >; 369 }; 370 371 spi1: spi@4002D000 { 372 compatible = "fsl,mvf600-spi"; 373 reg = <0x4002D000 0x1000>; 374 interrupts = < 100 >; 375 interrupt-parent = <&GIC>; 376 status = "disabled"; 377 }; 378 379 spi2: spi@400AC000 { 380 compatible = "fsl,mvf600-spi"; 381 reg = <0x400AC000 0x1000>; 382 interrupts = < 101 >; 383 interrupt-parent = <&GIC>; 384 status = "disabled"; 385 }; 386 387 spi3: spi@400AD000 { 388 compatible = "fsl,mvf600-spi"; 389 reg = <0x400AD000 0x1000>; 390 interrupts = < 102 >; 391 interrupt-parent = <&GIC>; 392 status = "disabled"; 393 }; 394 395 i2c0: i2c@40066000 { 396 compatible = "fsl,mvf600-i2c"; 397 reg = <0x40066000 0x1000>; 398 interrupts = < 103 >; 399 interrupt-parent = <&GIC>; 400 status = "disabled"; 401 clock_names = "ipg"; 402 iomux_config = < 36 0x2034d3 403 37 0x2034d3 404 207 0x1 405 208 0x1 >; 406 }; 407 408 i2c1: i2c@40067000 { 409 compatible = "fsl,mvf600-i2c"; 410 reg = <0x40067000 0x1000>; 411 interrupts = < 104 >; 412 interrupt-parent = <&GIC>; 413 status = "disabled"; 414 }; 415 416 i2c2: i2c@400E6000 { 417 compatible = "fsl,mvf600-i2c"; 418 reg = <0x400E6000 0x1000>; 419 interrupts = < 105 >; 420 interrupt-parent = <&GIC>; 421 status = "disabled"; 422 }; 423 424 i2c3: i2c@400E7000 { 425 compatible = "fsl,mvf600-i2c"; 426 reg = <0x400E7000 0x1000>; 427 interrupts = < 106 >; 428 interrupt-parent = <&GIC>; 429 status = "disabled"; 430 }; 431 432 adc0: adc@4003B000 { 433 compatible = "fsl,mvf600-adc"; 434 reg = <0x4003B000 0x1000>; 435 interrupts = < 85 >; 436 interrupt-parent = <&GIC>; 437 status = "disabled"; 438 }; 439 440 adc1: adc@400BB000 { 441 compatible = "fsl,mvf600-adc"; 442 reg = <0x400BB000 0x1000>; 443 interrupts = < 86 >; 444 interrupt-parent = <&GIC>; 445 status = "disabled"; 446 }; 447 448 tcon0: tcon@4003D000 { 449 compatible = "fsl,mvf600-tcon"; 450 reg = <0x4003D000 0x1000>; 451 status = "disabled"; 452 }; 453 454 dcu0: dcu4@40058000 { 455 compatible = "fsl,mvf600-dcu4"; 456 reg = <0x40058000 0x7000>; 457 interrupts = < 62 >; 458 interrupt-parent = <&GIC>; 459 status = "disabled"; 460 clock_names = "dcu0"; 461 iomux_config = < 105 0x100044 462 106 0x100044 463 107 0x100060 464 108 0x100060 465 109 0x100060 466 110 0x100060 467 111 0x100060 468 112 0x100060 469 113 0x100060 470 114 0x100060 471 115 0x100060 472 116 0x100060 473 117 0x100060 474 118 0x100060 475 119 0x100060 476 120 0x100060 477 121 0x100060 478 122 0x100060 479 123 0x100060 480 124 0x100060 481 125 0x100060 482 126 0x100060 483 127 0x100060 484 128 0x100060 485 129 0x100060 486 130 0x100060 487 131 0x100060 488 132 0x100060 489 133 0x100060 >; 490 }; 491 }; 492}; 493