1258057Sbr/*- 2261406Sbr * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com> 3258057Sbr * All rights reserved. 4258057Sbr * 5258057Sbr * Redistribution and use in source and binary forms, with or without 6258057Sbr * modification, are permitted provided that the following conditions 7258057Sbr * are met: 8258057Sbr * 1. Redistributions of source code must retain the above copyright 9258057Sbr * notice, this list of conditions and the following disclaimer. 10258057Sbr * 2. Redistributions in binary form must reproduce the above copyright 11258057Sbr * notice, this list of conditions and the following disclaimer in the 12258057Sbr * documentation and/or other materials provided with the distribution. 13258057Sbr * 14258057Sbr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15258057Sbr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16258057Sbr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17258057Sbr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18258057Sbr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19258057Sbr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20258057Sbr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21258057Sbr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22258057Sbr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23258057Sbr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24258057Sbr * SUCH DAMAGE. 25258057Sbr * 26258057Sbr * $FreeBSD: releng/10.3/sys/boot/fdt/dts/arm/vybrid.dtsi 266274 2014-05-16 23:27:18Z ian $ 27258057Sbr */ 28258057Sbr 29258057Sbr/ { 30258057Sbr model = "Freescale Vybrid Family"; 31261406Sbr compatible = "freescale,vybrid", "fsl,mvf"; 32258057Sbr #address-cells = <1>; 33258057Sbr #size-cells = <1>; 34258057Sbr 35258057Sbr interrupt-parent = <&GIC>; 36258057Sbr 37258057Sbr aliases { 38258057Sbr soc = &SOC; 39258057Sbr serial0 = &serial0; 40258057Sbr serial1 = &serial1; 41261406Sbr sai0 = &sai0; 42261406Sbr sai1 = &sai1; 43261406Sbr sai2 = &sai2; 44261406Sbr sai3 = &sai3; 45261406Sbr esai = &esai; 46261406Sbr adc0 = &adc0; 47261406Sbr adc1 = &adc1; 48261406Sbr edma0 = &edma0; 49261406Sbr edma1 = &edma1; 50258057Sbr src = &SRC; 51258057Sbr }; 52258057Sbr 53258057Sbr SOC: vybrid { 54258057Sbr #address-cells = <1>; 55258057Sbr #size-cells = <1>; 56258057Sbr compatible = "simple-bus"; 57258057Sbr ranges; 58258057Sbr bus-frequency = <0>; 59258057Sbr 60258057Sbr SRC: src@4006E000 { 61258057Sbr compatible = "fsl,mvf600-src"; 62258057Sbr reg = <0x4006E000 0x100>; 63258057Sbr }; 64258057Sbr 65258057Sbr mscm@40001000 { 66258057Sbr compatible = "fsl,mvf600-mscm"; 67258057Sbr reg = <0x40001000 0x1000>; 68258057Sbr }; 69258057Sbr 70258057Sbr GIC: interrupt-controller@01c81000 { 71258057Sbr compatible = "arm,gic"; 72258057Sbr reg = <0x40003000 0x1000>, /* Distributor Registers */ 73258057Sbr <0x40002100 0x100>; /* CPU Interface Registers */ 74258057Sbr interrupt-controller; 75258057Sbr #interrupt-cells = <1>; 76258057Sbr }; 77258057Sbr 78258057Sbr anadig@40050000 { 79258057Sbr compatible = "fsl,mvf600-anadig"; 80258057Sbr reg = <0x40050000 0x300>; 81258057Sbr }; 82258057Sbr 83258057Sbr ccm@4006b000 { 84258057Sbr compatible = "fsl,mvf600-ccm"; 85258057Sbr reg = <0x4006b000 0x1000>; 86261406Sbr clock_names = "pll4"; 87258057Sbr }; 88258057Sbr 89258057Sbr mp_tmr@40002100 { 90258057Sbr compatible = "arm,mpcore-timers"; 91258057Sbr clock-frequency = <133000000>; 92258057Sbr #address-cells = <1>; 93258057Sbr #size-cells = <0>; 94258057Sbr reg = < 0x40002200 0x100 >, /* Global Timer Registers */ 95258057Sbr < 0x40002600 0x100 >; /* Private Timer Registers */ 96258057Sbr interrupts = < 27 29 >; 97258057Sbr interrupt-parent = < &GIC >; 98258057Sbr }; 99258057Sbr 100261406Sbr dmamux@40024000 { 101261406Sbr compatible = "fsl,mvf600-dmamux"; 102261406Sbr reg = <0x40024000 0x100>, 103261406Sbr <0x40025000 0x100>, 104261406Sbr <0x400A1000 0x100>, 105261406Sbr <0x400A2000 0x100>; 106261406Sbr }; 107261406Sbr 108261406Sbr edma0: edma@40018000 { 109261406Sbr compatible = "fsl,mvf600-edma"; 110261406Sbr reg = <0x40018000 0x1000>, 111261406Sbr <0x40019000 0x1000>; /* TCD */ 112261406Sbr interrupts = < 40 41 >; 113261406Sbr interrupt-parent = <&GIC>; 114261639Sbr device-id = < 0 >; 115261406Sbr status = "disabled"; 116261406Sbr }; 117261406Sbr 118261406Sbr edma1: edma@40098000 { 119261406Sbr compatible = "fsl,mvf600-edma"; 120261406Sbr reg = <0x40098000 0x1000>, 121261406Sbr <0x40099000 0x1000>; /* TCD */ 122261406Sbr interrupts = < 42 43 >; 123261406Sbr interrupt-parent = <&GIC>; 124261639Sbr device-id = < 1 >; 125261406Sbr status = "disabled"; 126261406Sbr }; 127261406Sbr 128258057Sbr pit@40037000 { 129258057Sbr compatible = "fsl,mvf600-pit"; 130258057Sbr reg = <0x40037000 0x1000>; 131258057Sbr interrupts = < 71 >; 132258057Sbr interrupt-parent = <&GIC>; 133258057Sbr clock-frequency = < 24000000 >; 134258057Sbr }; 135258057Sbr 136258057Sbr lptmr@40040000 { 137258057Sbr compatible = "fsl,mvf600-lptmr"; 138258057Sbr reg = <0x40040000 0x1000>; 139258057Sbr interrupts = < 72 >; 140258057Sbr interrupt-parent = <&GIC>; 141258057Sbr clock-frequency = < 24000000 >; 142258057Sbr }; 143258057Sbr 144258057Sbr iomuxc@40048000 { 145258057Sbr compatible = "fsl,mvf600-iomuxc"; 146258057Sbr reg = <0x40048000 0x1000>; 147258057Sbr }; 148258057Sbr 149266274Sian port@40049000 { 150266274Sian compatible = "fsl,mvf600-port"; 151266274Sian reg = <0x40049000 0x5000>; 152266274Sian interrupts = < 139 140 141 142 143 >; 153266274Sian interrupt-parent = <&GIC>; 154266274Sian }; 155266274Sian 156258057Sbr gpio@400FF000 { 157258057Sbr compatible = "fsl,mvf600-gpio"; 158258057Sbr reg = <0x400FF000 0x200>; 159258057Sbr #gpio-cells = <3>; 160258057Sbr gpio-controller; 161258057Sbr }; 162258057Sbr 163258057Sbr nand@400E0000 { 164258057Sbr #address-cells = <1>; 165258057Sbr #size-cells = <1>; 166258057Sbr compatible = "fsl,mvf600-nand"; 167258057Sbr reg = <0x400E0000 0x10000>; 168258057Sbr interrupts = < 115 >; 169258057Sbr interrupt-parent = <&GIC>; 170261406Sbr clock_names = "nand"; 171261406Sbr status = "disabled"; 172258057Sbr 173258057Sbr partition@40000 { 174258057Sbr reg = <0x40000 0x200000>; /* 2MB */ 175258057Sbr label = "u-boot"; 176258057Sbr read-only; 177258057Sbr }; 178258057Sbr 179258057Sbr partition@240000 { 180258057Sbr reg = <0x240000 0x200000>; /* 2MB */ 181258057Sbr label = "test"; 182258057Sbr }; 183258057Sbr 184258057Sbr partition@440000 { 185258057Sbr reg = <0x440000 0xa00000>; /* 10MB */ 186258057Sbr label = "kernel"; 187258057Sbr }; 188258057Sbr 189258057Sbr partition@e40000 { 190258057Sbr reg = <0xe40000 0x1e000000>; /* 480MB */ 191258057Sbr label = "root"; 192258057Sbr }; 193258057Sbr }; 194258057Sbr 195258057Sbr sdhci0: sdhci@400B1000 { 196258057Sbr compatible = "fsl,mvf600-sdhci"; 197258057Sbr reg = <0x400B1000 0x1000>; 198258057Sbr interrupts = < 59 >; 199258057Sbr interrupt-parent = <&GIC>; 200258057Sbr clock-frequency = <50000000>; 201261406Sbr status = "disabled"; 202261406Sbr clock_names = "esdhc0"; 203258057Sbr }; 204258057Sbr 205258057Sbr sdhci1: sdhci@400B2000 { 206258057Sbr compatible = "fsl,mvf600-sdhci"; 207258057Sbr reg = <0x400B2000 0x1000>; 208258057Sbr interrupts = < 60 >; 209258057Sbr interrupt-parent = <&GIC>; 210258057Sbr clock-frequency = <50000000>; 211261406Sbr status = "disabled"; 212261406Sbr clock_names = "esdhc1"; 213262483Sbr iomux_config = < 14 0x500060 214262483Sbr 15 0x500060 215262483Sbr 16 0x500060 216262483Sbr 17 0x500060 217262483Sbr 18 0x500060 218262483Sbr 19 0x500060 >; 219258057Sbr }; 220258057Sbr 221258057Sbr serial0: serial@40027000 { 222258057Sbr compatible = "fsl,mvf600-uart"; 223258057Sbr reg = <0x40027000 0x1000>; 224258057Sbr interrupts = <93>; 225258057Sbr interrupt-parent = <&GIC>; 226258057Sbr current-speed = <115200>; 227258057Sbr clock-frequency = < 24000000 >; 228261406Sbr status = "disabled"; 229258057Sbr }; 230258057Sbr 231258057Sbr serial1: serial@40028000 { 232258057Sbr compatible = "fsl,mvf600-uart"; 233258057Sbr reg = <0x40028000 0x1000>; 234258057Sbr interrupts = <94>; 235258057Sbr interrupt-parent = <&GIC>; 236258057Sbr current-speed = <115200>; 237258057Sbr clock-frequency = < 24000000 >; 238261406Sbr status = "disabled"; 239258057Sbr }; 240258057Sbr 241258057Sbr usb@40034000 { 242258057Sbr compatible = "fsl,mvf600-usb-ehci", "usb-ehci"; 243258057Sbr reg = < 0x40034000 0x1000 >, /* ehci */ 244258057Sbr < 0x40035000 0x1000 >, /* usbc */ 245258057Sbr < 0x40050800 0x100 >; /* phy */ 246258057Sbr interrupts = < 107 >; 247258057Sbr interrupt-parent = <&GIC>; 248262483Sbr iomux_config = < 134 0x0001be 249262483Sbr 7 0x200060 >; 250258057Sbr }; 251258057Sbr 252258057Sbr usb@400b4000 { 253258057Sbr compatible = "fsl,mvf600-usb-ehci", "usb-ehci"; 254258057Sbr reg = < 0x400b4000 0x1000 >, /* ehci */ 255258057Sbr < 0x400b5000 0x1000 >, /* usbc */ 256258057Sbr < 0x40050C00 0x100 >; /* phy */ 257258057Sbr interrupts = < 108 >; 258258057Sbr interrupt-parent = <&GIC>; 259262483Sbr iomux_config = < 134 0x0001be 260262483Sbr 7 0x200060 >; 261258057Sbr }; 262258057Sbr 263258057Sbr fec0: ethernet@400D0000 { 264258057Sbr compatible = "fsl,mvf600-fec"; 265258057Sbr reg = <0x400D0000 0x1000>; 266258057Sbr interrupts = < 110 >; 267258057Sbr interrupt-parent = <&GIC>; 268258057Sbr phy-mode = "rmii"; 269258057Sbr phy-disable-preamble; 270261406Sbr status = "disabled"; 271261406Sbr clock_names = "enet"; 272262483Sbr iomux_config = < 45 0x100061 273262483Sbr 46 0x100061 274262483Sbr 47 0x100061 275262483Sbr 48 0x100060 276262483Sbr 49 0x100060 277262483Sbr 50 0x100060 278262483Sbr 51 0x100060 279262483Sbr 52 0x100060 280262483Sbr 53 0x100060 >; 281258057Sbr }; 282258057Sbr 283258057Sbr fec1: ethernet@400D1000 { 284258057Sbr compatible = "fsl,mvf600-fec"; 285258057Sbr reg = <0x400D1000 0x1000>; 286258057Sbr interrupts = < 111 >; 287258057Sbr interrupt-parent = <&GIC>; 288258057Sbr phy-mode = "rmii"; 289258057Sbr phy-disable-preamble; 290261406Sbr status = "disabled"; 291261406Sbr clock_names = "enet"; 292262483Sbr iomux_config = < 54 0x103192 293262483Sbr 55 0x103193 294262483Sbr 56 0x103191 295262483Sbr 57 0x103191 296262483Sbr 58 0x103191 297262483Sbr 59 0x103191 298262483Sbr 60 0x103192 299262483Sbr 61 0x103192 300262483Sbr 62 0x103192 >; 301258057Sbr }; 302258057Sbr 303261406Sbr sai0: sai@4002F000 { 304261406Sbr compatible = "fsl,mvf600-sai"; 305261406Sbr reg = <0x4002F000 0x1000>; 306261406Sbr interrupts = < 116 >; 307261406Sbr interrupt-parent = <&GIC>; 308261406Sbr status = "disabled"; 309261406Sbr }; 310261406Sbr 311261406Sbr sai1: sai@40030000 { 312261406Sbr compatible = "fsl,mvf600-sai"; 313261406Sbr reg = <0x40030000 0x1000>; 314261406Sbr interrupts = < 117 >; 315261406Sbr interrupt-parent = <&GIC>; 316261406Sbr status = "disabled"; 317261406Sbr }; 318261406Sbr 319261406Sbr sai2: sai@40031000 { 320261406Sbr compatible = "fsl,mvf600-sai"; 321261406Sbr reg = <0x40031000 0x1000>; 322261406Sbr interrupts = < 118 >; 323261406Sbr interrupt-parent = <&GIC>; 324261406Sbr status = "disabled"; 325261406Sbr }; 326261406Sbr 327261406Sbr sai3: sai@40032000 { 328261406Sbr compatible = "fsl,mvf600-sai"; 329261406Sbr reg = <0x40032000 0x1000>; 330261406Sbr interrupts = < 119 >; 331261406Sbr interrupt-parent = <&GIC>; 332261406Sbr status = "disabled"; 333261639Sbr edma-controller = <&edma1>; 334261982Sbr edma-src-receive = < 8 >; 335261982Sbr edma-src-transmit = < 9 >; 336261982Sbr edma-mux-group = < 1 >; 337261406Sbr clock_names = "sai3", "cko1"; 338262483Sbr iomux_config = < 16 0x200060 339262483Sbr 19 0x200060 340262483Sbr 21 0x200060 341262483Sbr 40 0x400061 >; /* CKO1 */ 342261406Sbr }; 343261406Sbr 344261406Sbr esai: esai@40062000 { 345261406Sbr compatible = "fsl,mvf600-esai"; 346261406Sbr reg = <0x40062000 0x1000>; 347261406Sbr interrupts = < 120 >; 348261406Sbr interrupt-parent = <&GIC>; 349261406Sbr status = "disabled"; 350261406Sbr clock_names = "esai"; 351262483Sbr iomux_config = < 45 0x400061 352262483Sbr 46 0x400061 353262483Sbr 47 0x400061 354262483Sbr 48 0x400060 355262483Sbr 49 0x400060 356262483Sbr 50 0x400060 357262483Sbr 51 0x400060 358262483Sbr 52 0x400060 359262483Sbr 78 0x3038df 360262483Sbr 40 0x400061 >; 361261406Sbr }; 362261406Sbr 363261406Sbr spi0: spi@4002C000 { 364261406Sbr compatible = "fsl,mvf600-spi"; 365261406Sbr reg = <0x4002C000 0x1000>; 366261406Sbr interrupts = < 99 >; 367261406Sbr interrupt-parent = <&GIC>; 368261406Sbr status = "disabled"; 369262483Sbr iomux_config = < 40 0x100061 370262483Sbr 41 0x100061 371262483Sbr 42 0x100060 372262483Sbr 43 0x100060 373262483Sbr 44 0x100061 >; 374261406Sbr }; 375261406Sbr 376261406Sbr spi1: spi@4002D000 { 377261406Sbr compatible = "fsl,mvf600-spi"; 378261406Sbr reg = <0x4002D000 0x1000>; 379261406Sbr interrupts = < 100 >; 380261406Sbr interrupt-parent = <&GIC>; 381261406Sbr status = "disabled"; 382261406Sbr }; 383261406Sbr 384261406Sbr spi2: spi@400AC000 { 385261406Sbr compatible = "fsl,mvf600-spi"; 386261406Sbr reg = <0x400AC000 0x1000>; 387261406Sbr interrupts = < 101 >; 388261406Sbr interrupt-parent = <&GIC>; 389261406Sbr status = "disabled"; 390261406Sbr }; 391261406Sbr 392261406Sbr spi3: spi@400AD000 { 393261406Sbr compatible = "fsl,mvf600-spi"; 394261406Sbr reg = <0x400AD000 0x1000>; 395261406Sbr interrupts = < 102 >; 396261406Sbr interrupt-parent = <&GIC>; 397261406Sbr status = "disabled"; 398261406Sbr }; 399261406Sbr 400262483Sbr i2c0: i2c@40066000 { 401262483Sbr compatible = "fsl,mvf600-i2c"; 402262483Sbr reg = <0x40066000 0x1000>; 403262483Sbr interrupts = < 103 >; 404262483Sbr interrupt-parent = <&GIC>; 405262483Sbr status = "disabled"; 406262483Sbr clock_names = "ipg"; 407262483Sbr iomux_config = < 36 0x2034d3 408262483Sbr 37 0x2034d3 409262483Sbr 207 0x1 410262483Sbr 208 0x1 >; 411262483Sbr }; 412262483Sbr 413262483Sbr i2c1: i2c@40067000 { 414262483Sbr compatible = "fsl,mvf600-i2c"; 415262483Sbr reg = <0x40067000 0x1000>; 416262483Sbr interrupts = < 104 >; 417262483Sbr interrupt-parent = <&GIC>; 418262483Sbr status = "disabled"; 419262483Sbr }; 420262483Sbr 421262483Sbr i2c2: i2c@400E6000 { 422262483Sbr compatible = "fsl,mvf600-i2c"; 423262483Sbr reg = <0x400E6000 0x1000>; 424262483Sbr interrupts = < 105 >; 425262483Sbr interrupt-parent = <&GIC>; 426262483Sbr status = "disabled"; 427262483Sbr }; 428262483Sbr 429262483Sbr i2c3: i2c@400E7000 { 430262483Sbr compatible = "fsl,mvf600-i2c"; 431262483Sbr reg = <0x400E7000 0x1000>; 432262483Sbr interrupts = < 106 >; 433262483Sbr interrupt-parent = <&GIC>; 434262483Sbr status = "disabled"; 435262483Sbr }; 436262483Sbr 437261406Sbr adc0: adc@4003B000 { 438261406Sbr compatible = "fsl,mvf600-adc"; 439261406Sbr reg = <0x4003B000 0x1000>; 440261406Sbr interrupts = < 85 >; 441261406Sbr interrupt-parent = <&GIC>; 442261406Sbr status = "disabled"; 443261406Sbr }; 444261406Sbr 445261406Sbr adc1: adc@400BB000 { 446261406Sbr compatible = "fsl,mvf600-adc"; 447261406Sbr reg = <0x400BB000 0x1000>; 448261406Sbr interrupts = < 86 >; 449261406Sbr interrupt-parent = <&GIC>; 450261406Sbr status = "disabled"; 451261406Sbr }; 452261406Sbr 453261406Sbr tcon0: tcon@4003D000 { 454261406Sbr compatible = "fsl,mvf600-tcon"; 455261406Sbr reg = <0x4003D000 0x1000>; 456261406Sbr status = "disabled"; 457261406Sbr }; 458261406Sbr 459261406Sbr dcu0: dcu4@40058000 { 460261406Sbr compatible = "fsl,mvf600-dcu4"; 461261406Sbr reg = <0x40058000 0x7000>; 462261406Sbr interrupts = < 62 >; 463261406Sbr interrupt-parent = <&GIC>; 464261406Sbr status = "disabled"; 465261406Sbr clock_names = "dcu0"; 466262483Sbr iomux_config = < 105 0x100044 467262483Sbr 106 0x100044 468262483Sbr 107 0x100060 469262483Sbr 108 0x100060 470262483Sbr 109 0x100060 471262483Sbr 110 0x100060 472262483Sbr 111 0x100060 473262483Sbr 112 0x100060 474262483Sbr 113 0x100060 475262483Sbr 114 0x100060 476262483Sbr 115 0x100060 477262483Sbr 116 0x100060 478262483Sbr 117 0x100060 479262483Sbr 118 0x100060 480262483Sbr 119 0x100060 481262483Sbr 120 0x100060 482262483Sbr 121 0x100060 483262483Sbr 122 0x100060 484262483Sbr 123 0x100060 485262483Sbr 124 0x100060 486262483Sbr 125 0x100060 487262483Sbr 126 0x100060 488262483Sbr 127 0x100060 489262483Sbr 128 0x100060 490262483Sbr 129 0x100060 491262483Sbr 130 0x100060 492262483Sbr 131 0x100060 493262483Sbr 132 0x100060 494262483Sbr 133 0x100060 >; 495261406Sbr }; 496258057Sbr }; 497258057Sbr}; 498