sheevaplug.dts revision 235609
1/*
2 * Copyright (c) 2010 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Semihalf under sponsorship from
6 * the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * Marvell SheevaPlug Device Tree Source.
30 *
31 * $FreeBSD: head/sys/boot/fdt/dts/sheevaplug.dts 235609 2012-05-18 14:41:14Z gber $
32 */
33
34/dts-v1/;
35
36/ {
37	model = "mrvl,SheevaPlug";
38	compatible = "SheevaPlug";
39	#address-cells = <1>;
40	#size-cells = <1>;
41
42	aliases {
43		ethernet0 = &enet0;
44		mpp = &MPP;
45		serial0 = &serial0;
46		serial1 = &serial1;
47		soc = &SOC;
48		sram = &SRAM;
49	};
50
51	cpus {
52		#address-cells = <1>;
53		#size-cells = <0>;
54
55		cpu@0 {
56			device_type = "cpu";
57			compatible = "ARM,88FR131";
58			reg = <0x0>;
59			d-cache-line-size = <32>;	// 32 bytes
60			i-cache-line-size = <32>;	// 32 bytes
61			d-cache-size = <0x4000>;	// L1, 16K
62			i-cache-size = <0x4000>;	// L1, 16K
63			timebase-frequency = <0>;
64			bus-frequency = <0>;
65			clock-frequency = <0>;
66		};
67	};
68
69	memory {
70		device_type = "memory";
71		reg = <0x0 0x20000000>;		// 512M at 0x0
72	};
73
74	localbus@0 {
75		#address-cells = <2>;
76		#size-cells = <1>;
77		compatible = "mrvl,lbc";
78		bank-count = <3>;
79
80		/* This reflects CPU decode windows setup. */
81		ranges = <0x0 0x2f 0xf9300000 0x00100000>;
82
83		nand@0,0 {
84			#address-cells = <1>;
85			#size-cells = <1>;
86			compatible = "mrvl,nfc";
87			reg = <0x0 0x0 0x00100000>;
88			bank-width = <2>;
89			device-width = <1>;
90
91
92		};
93	};
94
95	SOC: soc88f6281@f1000000 {
96		#address-cells = <1>;
97		#size-cells = <1>;
98		compatible = "simple-bus";
99		ranges = <0x0 0xf1000000 0x00100000>;
100		bus-frequency = <0>;
101
102		PIC: pic@20200 {
103			interrupt-controller;
104			#address-cells = <0>;
105			#interrupt-cells = <1>;
106			reg = <0x20200 0x3c>;
107			compatible = "mrvl,pic";
108		};
109
110		timer@20300 {
111			compatible = "mrvl,timer";
112			reg = <0x20300 0x30>;
113			interrupts = <1>;
114			interrupt-parent = <&PIC>;
115			mrvl,has-wdt;
116		};
117
118		MPP: mpp@10000 {
119			#pin-cells = <2>;
120			compatible = "mrvl,mpp";
121			reg = <0x10000 0x34>;
122			pin-count = <50>;
123			pin-map = <
124				0  1		/* MPP[0]:  NF_IO[2] */
125				1  1		/* MPP[1]:  NF_IO[3] */
126				2  1		/* MPP[2]:  NF_IO[4] */
127				3  1		/* MPP[3]:  NF_IO[5] */
128				4  1		/* MPP[4]:  NF_IO[6] */
129				5  1		/* MPP[5]:  NF_IO[7] */
130				6  1		/* MPP[6]:  SYSRST_OUTn */
131				8  2		/* MPP[8]:  UA0_RTS */
132				9  2		/* MPP[9]:  UA0_CTS */
133				10 3		/* MPP[10]: UA0_TXD */
134				11 3		/* MPP[11]: UA0_RXD */
135				12 1		/* MPP[12]: SD_CLK */
136				13 1		/* MPP[13]: SD_CMD */
137				14 1		/* MPP[14]: SD_D[0] */
138				15 1		/* MPP[15]: SD_D[1] */
139				16 1		/* MPP[16]: SD_D[2] */
140				17 1		/* MPP[17]: SD_D[3] */
141				18 1		/* MPP[18]: NF_IO[0] */
142				19 1		/* MPP[19]: NF_IO[1] */
143				29 1 >;		/* MPP[29]: TSMP[9] */
144		};
145
146		GPIO: gpio@10100 {
147			#gpio-cells = <3>;
148			compatible = "mrvl,gpio";
149			reg = <0x10100 0x20>;
150			gpio-controller;
151			interrupts = <35 36 37 38 39 40 41>;
152			interrupt-parent = <&PIC>;
153		};
154
155		rtc@10300 {
156			compatible = "mrvl,rtc";
157			reg = <0x10300 0x08>;
158		};
159
160		twsi@11000 {
161			#address-cells = <1>;
162			#size-cells = <0>;
163			compatible = "mrvl,twsi";
164			reg = <0x11000 0x20>;
165			interrupts = <43>;
166			interrupt-parent = <&PIC>;
167		};
168
169		enet0: ethernet@72000 {
170			#address-cells = <1>;
171			#size-cells = <1>;
172			model = "V2";
173			compatible = "mrvl,ge";
174			reg = <0x72000 0x2000>;
175			ranges = <0x0 0x72000 0x2000>;
176			local-mac-address = [ 00 00 00 00 00 00 ];
177			interrupts = <12 13 14 11 46>;
178			interrupt-parent = <&PIC>;
179			phy-handle = <&phy0>;
180
181			mdio@0 {
182				#address-cells = <1>;
183				#size-cells = <0>;
184				compatible = "mrvl,mdio";
185
186				phy0: ethernet-phy@0 {
187					reg = <0x0>;
188				};
189			};
190		};
191
192		serial0: serial@12000 {
193			compatible = "ns16550";
194			reg = <0x12000 0x20>;
195			reg-shift = <2>;
196			clock-frequency = <0>;
197			interrupts = <33>;
198			interrupt-parent = <&PIC>;
199		};
200
201		serial1: serial@12100 {
202			compatible = "ns16550";
203			reg = <0x12100 0x20>;
204			reg-shift = <2>;
205			clock-frequency = <0>;
206			interrupts = <34>;
207			interrupt-parent = <&PIC>;
208		};
209
210		crypto@30000 {
211			compatible = "mrvl,cesa";
212			reg = <0x30000 0x10000>;
213			interrupts = <22>;
214			interrupt-parent = <&PIC>;
215
216			sram-handle = <&SRAM>;
217		};
218
219		usb@50000 {
220			compatible = "mrvl,usb-ehci", "usb-ehci";
221			reg = <0x50000 0x1000>;
222			interrupts = <48 19>;
223			interrupt-parent = <&PIC>;
224		};
225
226		xor@60000 {
227			compatible = "mrvl,xor";
228			reg = <0x60000 0x1000>;
229			interrupts = <5 6 7 8>;
230			interrupt-parent = <&PIC>;
231		};
232	};
233
234	SRAM: sram@fd000000 {
235		compatible = "mrvl,cesa-sram";
236		reg = <0xfd000000 0x00100000>;
237	};
238
239	chosen {
240		stdin = "serial0";
241		stdout = "serial0";
242	};
243};
244