s3c24x0reg.h revision 205354
1/* $NetBSD: s3c24x0reg.h,v 1.7 2004/02/12 03:52:46 bsh Exp $ */ 2 3/*- 4 * Copyright (c) 2003 Genetec corporation All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec corporation may not be used to endorse 16 * or promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm/s3c2xx0/s3c24x0reg.h 205354 2010-03-20 03:39:35Z imp $ 32 */ 33 34 35/* 36 * Samsung S3C2410X/2400 processor is ARM920T based integrated CPU 37 * 38 * Reference: 39 * S3C2410X User's Manual 40 * S3C2400 User's Manual 41 */ 42#ifndef _ARM_S3C2XX0_S3C24X0REG_H_ 43#define _ARM_S3C2XX0_S3C24X0REG_H_ 44 45/* common definitions for S3C2800, S3C2410 and S3C2440 */ 46#include <arm/s3c2xx0/s3c2xx0reg.h> 47 48/* 49 * Map the device registers into kernel space 50 */ 51#define S3C24X0_DEV_START 0x48000000 52#define S3C24X0_DEV_STOP 0x60000000 53#define S3C24X0_DEV_VA_OFFSET 0xD0000000 54#define S3C24X0_DEV_VA_SIZE (S3C24X0_DEV_STOP - S3C24X0_DEV_START) 55#define S3C24X0_DEV_PA_TO_VA(x) (x - S3C24X0_DEV_START + S3C24X0_DEV_VA_OFFSET) 56 57/* 58 * Physical address of integrated peripherals 59 */ 60#define S3C24X0_MEMCTL_PA_BASE 0x48000000 /* memory controller */ 61#define S3C24X0_MEMCTL_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_MEMCTL_PA_BASE) 62#define S3C24X0_USBHC_PA_BASE 0x49000000 /* USB Host controller */ 63#define S3C24X0_USBHC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_USBHC_PA_BASE) 64#define S3C24X0_INTCTL_PA_BASE 0x4a000000 /* Interrupt controller */ 65#define S3C24X0_INTCTL_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_INTCTL_PA_BASE) 66#define S3C24X0_INTCTL_SIZE 0x20 67#define S3C24X0_DMAC_PA_BASE 0x4b000000 68#define S3C24X0_DMAC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_DMAC_PA_BASE) 69#define S3C24X0_DMAC_SIZE 0xe4 70#define S3C24X0_CLKMAN_PA_BASE 0x4c000000 /* clock & power management */ 71#define S3C24X0_CLKMAN_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_CLKMAN_PA_BASE) 72#define S3C24X0_LCDC_PA_BASE 0x4d000000 /* LCD controller */ 73#define S3C24X0_LCDC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_LCDC_PA_BASE) 74#define S3C24X0_LCDC_SIZE 0x64 75#define S3C24X0_NANDFC_PA_BASE 0x4e000000 /* NAND Flash controller */ 76#define S3C24X0_NANDFC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_NANDFC_PA_BASE) 77#define S3C24X0_UART0_PA_BASE 0x50000000 78#define S3C24X0_UART0_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_UART0_PA_BASE) 79#define S3C24X0_UART_PA_BASE(n) (S3C24X0_UART0_PA_BASE+0x4000*(n)) 80#define S3C24X0_UART_BASE(n) S3C24X0_DEV_PA_TO_VA(S3C24X0_UART_PA_BASE(n)) 81#define S3C24X0_TIMER_PA_BASE 0x51000000 82#define S3C24X0_TIMER_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_TIMER_PA_BASE) 83#define S3C24X0_USBDC_PA_BASE 0x5200140 84#define S3C24X0_USBDC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_USBDC_PA_BASE) 85#define S3C24X0_USBDC_SIZE 0x130 86#define S3C24X0_WDT_PA_BASE 0x53000000 87#define S3C24X0_WDT_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_WDT_PA_BASE) 88#define S3C24X0_IIC_PA_BASE 0x54000000 89#define S3C24X0_IIC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_IIC_PA_BASE) 90#define S3C24X0_IIS_PA_BASE 0x55000000 91#define S3C24X0_IIS_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_IIS_PA_BASE) 92#define S3C24X0_GPIO_PA_BASE 0x56000000 93#define S3C24X0_GPIO_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_GPIO_PA_BASE) 94#define S3C24X0_ADC_PA_BASE 0x58000000 95#define S3C24X0_ADC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_ADC_PA_BASE) 96#define S3C24X0_SPI0_PA_BASE 0x59000000 97#define S3C24X0_SPI0_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_SPI0_PA_BASE) 98#define S3C24X0_SPI1_PA_BASE 0x59000020 99#define S3C24X0_SPI1_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_SPI1_PA_BASE) 100#define S3C24X0_SDI_PA_BASE 0x5a000000 /* SD Interface */ 101#define S3C24X0_SDI_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_SDI_PA_BASE) 102 103#define S3C24X0_REG_BASE 0x48000000 104#define S3C24X0_REG_SIZE 0x13000000 105 106/* Memory controller */ 107#define MEMCTL_BWSCON 0x00 /* Bus width and wait status */ 108#define BWSCON_DW0_SHIFT 1 /* bank0 is odd */ 109#define BWSCON_BANK_SHIFT(n) (4*(n)) /* for bank 1..7 */ 110#define BWSCON_DW_MASK 0x03 111#define BWSCON_DW_8 0 112#define BWSCON_DW_16 1 113#define BWSCON_DW_32 2 114#define BWSCON_WS 0x04 /* WAIT enable for the bank */ 115#define BWSCON_ST 0x08 /* SRAM use UB/LB for the bank */ 116 117#define MEMCTL_BANKCON0 0x04 /* Boot ROM control */ 118#define MEMCTL_BANKCON(n) (0x04+4*(n)) /* BANKn control */ 119#define BANKCON_MT_SHIFT 15 120#define BANKCON_MT_ROM (0<<BANKCON_MT_SHIFT) 121#define BANKCON_MT_DRAM (3<<BANKCON_MT_SHIFT) 122#define BANKCON_TACS_SHIFT 13 /* address set-up time to nGCS */ 123#define BANKCON_TCOS_SHIFT 11 /* CS set-up to nOE */ 124#define BANKCON_TACC_SHIFT 8 /* CS set-up to nOE */ 125#define BANKCON_TOCH_SHIFT 6 /* CS hold time from OE */ 126#define BANKCON_TCAH_SHIFT 4 /* address hold time from OE */ 127#define BANKCON_TACP_SHIFT 2 /* page mode access cycle */ 128#define BANKCON_TACP_2 (0<<BANKCON_TACP_SHIFT) 129#define BANKCON_TACP_3 (1<<BANKCON_TACP_SHIFT) 130#define BANKCON_TACP_4 (2<<BANKCON_TACP_SHIFT) 131#define BANKCON_TACP_6 (3<<BANKCON_TACP_SHIFT) 132#define BANKCON_PMC_4 (1<<0) 133#define BANKCON_PMC_8 (2<<0) 134#define BANKCON_PMC_16 (3<<0) 135#define BANKCON_TRCD_SHIFT 2 /* RAS to CAS delay */ 136#define BANKCON_TRCD_2 (0<<2) 137#define BANKCON_TRCD_3 (1<<2) 138#define BANKCON_TRCD_4 (2<<2) 139#define BANKCON_SCAN_8 (0<<0) /* Column address number */ 140#define BANKCON_SCAN_9 (1<<0) 141#define BANKCON_SCAN_10 (2<<0) 142#define MEMCTL_REFRESH 0x24 /* DRAM?SDRAM Refresh */ 143#define REFRESH_REFEN (1<<23) 144#define REFRESH_TREFMD (1<<22) /* 1=self refresh */ 145#define REFRESH_TRP_2 (0<<20) 146#define REFRESH_TRP_3 (1<<20) 147#define REFRESH_TRP_4 (2<<20) 148#define REFRESH_TRC_4 (0<<18) 149#define REFRESH_TRC_5 (1<<18) 150#define REFRESH_TRC_6 (2<<18) 151#define REFRESH_TRC_7 (3<<18) 152#define REFRESH_COUNTER_MASK 0x3ff 153#define MEMCTL_BANKSIZE 0x28 /* Flexible Bank size */ 154#define MEMCTL_MRSRB6 0x2c /* SDRAM Mode register */ 155#define MEMCTL_MRSRB7 0x30 156#define MRSR_CL_SHIFT 4 /* CAS Latency */ 157 158#define S3C24X0_MEMCTL_SIZE 0x34 159 160/* USB Host controller */ 161#define S3C24X0_USBHC_SIZE 0x5c 162 163/* Interrupt controller */ 164#define INTCTL_PRIORITY 0x0c /* IRQ Priority control */ 165#define INTCTL_INTPND 0x10 /* Interrupt request status */ 166#define INTCTL_INTOFFSET 0x14 /* Interrupt request source */ 167#define INTCTL_SUBSRCPND 0x18 /* sub source pending */ 168#define INTCTL_INTSUBMSK 0x1c /* sub mask */ 169 170/* Interrupt source */ 171#define S3C24X0_INT_ADCTC 31 /* ADC (and TC for 2410) */ 172#define S3C24X0_INT_RTC 30 /* RTC alarm */ 173#define S3C24X0_INT_SPI1 29 /* SPI 1 */ 174#define S3C24X0_INT_UART0 28 /* UART0 */ 175#define S3C24X0_INT_IIC 27 176#define S3C24X0_INT_USBH 26 /* USB Host */ 177#define S3C24X0_INT_USBD 25 /* USB Device */ 178#define S3C24X0_INT_UART1 23 /* UART0 (2410 only) */ 179#define S3C24X0_INT_SPI0 22 /* SPI 0 */ 180#define S3C24X0_INT_SDI 21 181#define S3C24X0_INT_DMA3 20 182#define S3C24X0_INT_DMA2 19 183#define S3C24X0_INT_DMA1 18 184#define S3C24X0_INT_DMA0 17 185#define S3C24X0_INT_LCD 16 186 187#define S3C24X0_INT_UART2 15 /* UART2 int (2410) */ 188#define S3C24X0_INT_TIMER4 14 189#define S3C24X0_INT_TIMER3 13 190#define S3C24X0_INT_TIMER2 12 191#define S3C24X0_INT_TIMER1 11 192#define S3C24X0_INT_TIMER0 10 193#define S3C24X0_INT_TIMER(n) (10+(n)) /* timer interrupt [4:0] */ 194#define S3C24X0_INT_WDT 9 /* Watch dog timer */ 195#define S3C24X0_INT_TICK 8 196#define S3C24X0_INT_BFLT 7 /* Battery fault */ 197#define S3C24X0_INT_8_23 5 /* Ext int 8..23 */ 198#define S3C24X0_INT_4_7 4 /* Ext int 4..7 */ 199#define S3C24X0_INT_EXT(n) (n) /* External interrupt [3:0] for 24{1,4}0 */ 200 201/* 24{1,4}0 has more than 32 interrupt sources. These are sub-sources 202 * that are OR-ed into main interrupt sources, and controlled via 203 * SUBSRCPND and SUBSRCMSK registers */ 204#define S3C24X0_SUBIRQ_MIN 32 205 206/* cascaded to INT_ADCTC */ 207#define S3C24X0_INT_ADC (S3C24X0_SUBIRQ_MIN+10) /* AD converter */ 208#define S3C24X0_INT_TC (S3C24X0_SUBIRQ_MIN+9) /* Touch screen */ 209/* cascaded to INT_UART2 */ 210#define S3C24X0_INT_ERR2 (S3C24X0_SUBIRQ_MIN+8) /* UART2 Error */ 211#define S3C24X0_INT_TXD2 (S3C24X0_SUBIRQ_MIN+7) /* UART2 Tx */ 212#define S3C24X0_INT_RXD2 (S3C24X0_SUBIRQ_MIN+6) /* UART2 Rx */ 213/* cascaded to INT_UART1 */ 214#define S3C24X0_INT_ERR1 (S3C24X0_SUBIRQ_MIN+5) /* UART1 Error */ 215#define S3C24X0_INT_TXD1 (S3C24X0_SUBIRQ_MIN+4) /* UART1 Tx */ 216#define S3C24X0_INT_RXD1 (S3C24X0_SUBIRQ_MIN+3) /* UART1 Rx */ 217/* cascaded to INT_UART0 */ 218#define S3C24X0_INT_ERR0 (S3C24X0_SUBIRQ_MIN+2) /* UART0 Error */ 219#define S3C24X0_INT_TXD0 (S3C24X0_SUBIRQ_MIN+1) /* UART0 Tx */ 220#define S3C24X0_INT_RXD0 (S3C24X0_SUBIRQ_MIN+0) /* UART0 Rx */ 221 222/* DMA controller */ 223/* XXX */ 224 225/* Clock & power manager */ 226#define CLKMAN_LOCKTIME 0x00 /* PLL lock time */ 227#define CLKMAN_MPLLCON 0x04 /* MPLL control */ 228#define CLKMAN_UPLLCON 0x08 /* UPLL control */ 229#define PLLCON_MDIV_SHIFT 12 230#define PLLCON_MDIV_MASK (0xff<<PLLCON_MDIV_SHIFT) 231#define PLLCON_PDIV_SHIFT 4 232#define PLLCON_PDIV_MASK (0x3f<<PLLCON_PDIV_SHIFT) 233#define PLLCON_SDIV_SHIFT 0 234#define PLLCON_SDIV_MASK (0x03<<PLLCON_SDIV_SHIFT) 235#define CLKMAN_CLKCON 0x0c 236#define CLKCON_SPI (1<<18) 237#define CLKCON_IIS (1<<17) 238#define CLKCON_IIC (1<<16) 239#define CLKCON_ADC (1<<15) 240#define CLKCON_RTC (1<<14) 241#define CLKCON_GPIO (1<<13) 242#define CLKCON_UART2 (1<<12) 243#define CLKCON_UART1 (1<<11) 244#define CLKCON_UART0 (1<<10) /* PCLK to UART0 */ 245#define CLKCON_SDI (1<<9) 246#define CLKCON_TIMER (1<<8) /* PCLK to TIMER */ 247#define CLKCON_USBD (1<<7) /* PCLK to USB device controller */ 248#define CLKCON_USBH (1<<6) /* PCLK to USB host controller */ 249#define CLKCON_LCDC (1<<5) /* PCLK to LCD controller */ 250#define CLKCON_NANDFC (1<<4) /* PCLK to NAND Flash controller */ 251#define CLKCON_IDLE (1<<2) /* 1=transition to IDLE mode */ 252#define CLKMAN_CLKSLOW 0x10 253#define CLKMAN_CLKDIVN 0x14 254#define CLKDIVN_PDIVN (1<<0) /* pclk=hclk/2 */ 255 256#define CLKMAN_CLKSLOW 0x10 /* slow clock controll */ 257#define CLKSLOW_UCLK (1<<7) /* 1=UPLL off */ 258#define CLKSLOW_MPLL (1<<5) /* 1=PLL off */ 259#define CLKSLOW_SLOW (1<<4) /* 1: Enable SLOW mode */ 260#define CLKSLOW_VAL_MASK 0x0f /* divider value for slow clock */ 261 262#define CLKMAN_CLKDIVN 0x14 /* Software reset control */ 263#define CLKDIVN_PDIVN (1<<0) 264 265#define S3C24X0_CLKMAN_SIZE 0x18 266 267/* LCD controller */ 268#define LCDC_LCDCON1 0x00 /* control 1 */ 269#define LCDCON1_ENVID (1<<0) /* enable video */ 270#define LCDCON1_BPPMODE_SHIFT 1 271#define LCDCON1_BPPMODE_MASK (0x0f<<LCDCON1_BPPMODE_SHIFT) 272#define LCDCON1_BPPMODE_STN1 (0x0<<LCDCON1_BPPMODE_SHIFT) 273#define LCDCON1_BPPMODE_STN2 (0x1<<LCDCON1_BPPMODE_SHIFT) 274#define LCDCON1_BPPMODE_STN4 (0x2<<LCDCON1_BPPMODE_SHIFT) 275#define LCDCON1_BPPMODE_STN8 (0x3<<LCDCON1_BPPMODE_SHIFT) 276#define LCDCON1_BPPMODE_STN12 (0x4<<LCDCON1_BPPMODE_SHIFT) 277#define LCDCON1_BPPMODE_TFT1 (0x8<<LCDCON1_BPPMODE_SHIFT) 278#define LCDCON1_BPPMODE_TFT2 (0x9<<LCDCON1_BPPMODE_SHIFT) 279#define LCDCON1_BPPMODE_TFT4 (0xa<<LCDCON1_BPPMODE_SHIFT) 280#define LCDCON1_BPPMODE_TFT8 (0xb<<LCDCON1_BPPMODE_SHIFT) 281#define LCDCON1_BPPMODE_TFT16 (0xc<<LCDCON1_BPPMODE_SHIFT) 282#define LCDCON1_BPPMODE_TFT24 (0xd<<LCDCON1_BPPMODE_SHIFT) 283#define LCDCON1_BPPMODE_TFTX (0x8<<LCDCON1_BPPMODE_SHIFT) 284 285#define LCDCON1_PNRMODE_SHIFT 5 286#define LCDCON1_PNRMODE_MASK (0x3<<LCDCON1_PNRMODE_SHIFT) 287#define LCDCON1_PNRMODE_DUALSTN4 (0x0<<LCDCON1_PNRMODE_SHIFT) 288#define LCDCON1_PNRMODE_SINGLESTN4 (0x1<<LCDCON1_PNRMODE_SHIFT) 289#define LCDCON1_PNRMODE_SINGLESTN8 (0x2<<LCDCON1_PNRMODE_SHIFT) 290#define LCDCON1_PNRMODE_TFT (0x3<<LCDCON1_PNRMODE_SHIFT) 291 292#define LCDCON1_MMODE (1<<7) /* VM toggle rate */ 293#define LCDCON1_CLKVAL_SHIFT 8 294#define LCDCON1_CLKVAL_MASK (0x3ff<<LCDCON1_CLKVAL_SHIFT) 295#define LCDCON1_LINCNT_SHIFT 18 296#define LCDCON1_LINCNT_MASK (0x3ff<<LCDCON1_LINCNT_SHIFT) 297 298#define LCDC_LCDCON2 0x04 /* control 2 */ 299#define LCDCON2_VPSW_SHIFT 0 /* TFT Vsync pulse width */ 300#define LCDCON2_VPSW_MASK (0x3f<<LCDCON2_VPSW_SHIFT) 301#define LCDCON2_VFPD_SHIFT 6 /* TFT V front porch */ 302#define LCDCON2_VFPD_MASK (0xff<<LCDCON2_VFPD_SHIFT) 303#define LCDCON2_LINEVAL_SHIFT 14 /* Vertical size */ 304#define LCDCON2_LINEVAL_MASK (0x3ff<<LCDCON2_LINEVAL_SHIFT) 305#define LCDCON2_VBPD_SHIFT 24 /* TFT V back porch */ 306#define LCDCON2_VBPD_MASK (0xff<<LCDCON2_VBPD_SHIFT) 307 308#define LCDC_LCDCON3 0x08 /* control 2 */ 309#define LCDCON3_HFPD_SHIFT 0 /* TFT H front porch */ 310#define LCDCON3_HFPD_MASK (0xff<<LCDCON3_VPFD_SHIFT) 311#define LCDCON3_LINEBLANK_SHIFT 0 /* STN H blank time */ 312#define LCDCON3_LINEBLANK_MASK (0xff<<LCDCON3_LINEBLANK_SHIFT) 313#define LCDCON3_HOZVAL_SHIFT 8 /* Horizontal size */ 314#define LCDCON3_HOZVAL_MASK (0x7ff<<LCDCON3_HOZVAL_SHIFT) 315#define LCDCON3_HBPD_SHIFT 19 /* TFT H back porch */ 316#define LCDCON3_HBPD_MASK (0x7f<<LCDCON3_HPBD_SHIFT) 317#define LCDCON3_WDLY_SHIFT 19 /* STN vline delay */ 318#define LCDCON3_WDLY_MASK (0x03<<LCDCON3_WDLY_SHIFT) 319#define LCDCON3_WDLY_16 (0x00<<LCDCON3_WDLY_SHIFT) 320#define LCDCON3_WDLY_32 (0x01<<LCDCON3_WDLY_SHIFT) 321#define LCDCON3_WDLY_64 (0x02<<LCDCON3_WDLY_SHIFT) 322#define LCDCON3_WDLY_128 (0x03<<LCDCON3_WDLY_SHIFT) 323 324#define LCDC_LCDCON4 0x0c /* control 4 */ 325#define LCDCON4_HPSW_SHIFT 0 /* TFT Hsync pulse width */ 326#define LCDCON4_HPSW_MASK (0xff<<LCDCON4_HPSW_SHIFT) 327#define LCDCON4_WLH_SHIFT 0 /* STN VLINE high width */ 328#define LCDCON4_WLH_MASK (0x03<<LCDCON4_WLH_SHIFT) 329#define LCDCON4_WLH_16 (0x00<<LCDCON4_WLH_SHIFT) 330#define LCDCON4_WLH_32 (0x01<<LCDCON4_WLH_SHIFT) 331#define LCDCON4_WLH_64 (0x02<<LCDCON4_WLH_SHIFT) 332#define LCDCON4_WLH_128 (0x03<<LCDCON4_WLH_SHIFT) 333 334#define LCDCON4_MVAL_SHIFT 8 /* STN VM toggle rate */ 335#define LCDCON4_MVAL_MASK (0xff<<LCDCON4_MVAL_SHIFT) 336 337#define LCDC_LCDCON5 0x10 /* control 5 */ 338#define LCDCON5_HWSWP (1<<0) /* half-word swap */ 339#define LCDCON5_BSWP (1<<1) /* byte swap */ 340#define LCDCON5_ENLEND (1<<2) /* TFT: enable LEND signal */ 341#define LCDCON5_PWREN (1<<3) /* enable PWREN signale */ 342#define LCDCON5_INVLEND (1<<4) /* TFT: LEND signal polarity */ 343#define LCDCON5_INVPWREN (1<<5) /* PWREN signal polarity */ 344#define LCDCON5_INVVDEN (1<<6) /* VDEN signal polarity */ 345#define LCDCON5_INVVD (1<<7) /* video data signal polarity */ 346#define LCDCON5_INVVFRAME (1<<8) /* VFRAME/VSYNC signal polarity */ 347#define LCDCON5_INVVLINE (1<<9) /* VLINE/HSYNC signal polarity */ 348#define LCDCON5_INVVCLK (1<<10) /* VCLK signal polarity */ 349#define LCDCON5_INVVCLK_RISING LCDCON5_INVVCLK 350#define LCDCON5_INVVCLK_FALLING 0 351#define LCDCON5_FRM565 (1<<11) /* RGB:565 format*/ 352#define LCDCON5_FRM555I 0 /* RGBI:5551 format */ 353#define LCDCON5_BPP24BL (1<<12) /* bit order for bpp24 */ 354 355#define LCDCON5_HSTATUS_SHIFT 17 /* TFT: horizontal status */ 356#define LCDCON5_HSTATUS_MASK (0x03<<LCDCON5_HSTATUS_SHIFT) 357#define LCDCON5_HSTATUS_HSYNC (0x00<<LCDCON5_HSTATUS_SHIFT) 358#define LCDCON5_HSTATUS_BACKP (0x01<<LCDCON5_HSTATUS_SHIFT) 359#define LCDCON5_HSTATUS_ACTIVE (0x02<<LCDCON5_HSTATUS_SHIFT) 360#define LCDCON5_HSTATUS_FRONTP (0x03<<LCDCON5_HSTATUS_SHIFT) 361 362#define LCDCON5_VSTATUS_SHIFT 19 /* TFT: vertical status */ 363#define LCDCON5_VSTATUS_MASK (0x03<<LCDCON5_VSTATUS_SHIFT) 364#define LCDCON5_VSTATUS_HSYNC (0x00<<LCDCON5_VSTATUS_SHIFT) 365#define LCDCON5_VSTATUS_BACKP (0x01<<LCDCON5_VSTATUS_SHIFT) 366#define LCDCON5_VSTATUS_ACTIVE (0x02<<LCDCON5_VSTATUS_SHIFT) 367#define LCDCON5_VSTATUS_FRONTP (0x03<<LCDCON5_VSTATUS_SHIFT) 368 369#define LCDC_LCDSADDR1 0x14 /* frame buffer start address */ 370#define LCDC_LCDSADDR2 0x18 371#define LCDC_LCDSADDR3 0x1c 372#define LCDSADDR3_OFFSIZE_SHIFT 11 373#define LCDSADDR3_PAGEWIDTH_SHIFT 0 374 375#define LCDC_REDLUT 0x20 /* STN: red lookup table */ 376#define LCDC_GREENLUT 0x24 /* STN: green lookup table */ 377#define LCDC_BLUELUT 0x28 /* STN: blue lookup table */ 378#define LCDC_DITHMODE 0x4c /* STN: dithering mode */ 379 380#define LCDC_TPAL 0x50 /* TFT: temporary palette */ 381#define TPAL_TPALEN (1<<24) 382#define TPAL_RED_SHIFT 16 383#define TPAL_GREEN_SHIFT 8 384#define TPAL_BLUE_SHIFT 0 385 386#define LCDC_LCDINTPND 0x54 387#define LCDC_LCDSRCPND 0x58 388#define LCDC_LCDINTMSK 0x5c 389#define LCDINT_FICNT (1<<0) /* FIFO trigger interrupt pending */ 390#define LCDINT_FRSYN (1<<1) /* frame sync interrupt pending */ 391#define LCDINT_FIWSEL (1<<2) /* FIFO trigger level: 1=8 words, 0=4 words*/ 392 393#define LCDC_LPCSEL 0x60 /* LPC3600 mode */ 394#define LPCSEL_LPC_EN (1<<0) /* enable LPC3600 mode */ 395#define LPCSEL_RES_SEL (1<<1) /* 1=240x320 0=320x240 */ 396#define LPCSEL_MODE_SEL (1<<2) 397#define LPCSEL_CPV_SEL (1<<3) 398 399 400#define LCDC_PALETTE 0x0400 401#define LCDC_PALETTE_SIZE 0x0400 402 403/* NAND Flash controller */ 404#define NANDFC_NFCONF 0x00 /* Configuration */ 405/* NANDFC_NFSTAT */ 406#define NFSTAT_READY (1<<0) /* NAND flash memory ready/busy status */ 407 408 409/* MMC/SD */ 410#define SDI_CON 0x00 411#define CON_BYTEORDER (1<<4) 412#define CON_SDIO_INTR (1<<3) 413#define CON_READWAIT_EN (1<<2) 414#define CON_CLOCK_EN (1<<0) 415#define SDI_PRE 0x04 416#define SDI_CARG 0x08 417#define SDI_CCON 0x0c 418#define CCON_ABORDCMD (1<<12) /* Abort SDIO CMD12/52 */ 419#define CCON_WITHDATA (1<<11) /* CMD with data */ 420#define CCON_LONGRSP (1<<10) /* 136 bit response */ 421#define CCON_WAITRSP (1<<9) /* Host waits for response */ 422#define CCON_CMD_START (1<<8) 423#define CCON_CMDINDEX_MASK (0x7F) /* Command number index */ 424#define SDI_CSTA 0x10 425#define CSTA_RSPCRCFAIL (1<<12) 426#define CSTA_CMDSENT (1<<11) 427#define CSTA_CMDTOUT (1<<10) 428#define CSTA_RSPFIN (1<<9) 429/* All the bits to be cleared */ 430#define CSTA_ALL_CLEAR (CSTA_RSPCRCFAIL | CSTA_CMDSENT | \ 431 CSTA_CMDTOUT | CSTA_RSPFIN) 432#define CSTA_ERROR (CSTA_RSPCRCFAIL | CSTA_CMDTOUT) 433#define CSTA_CMDON (1<<8) 434#define SDI_RSP0 0x14 435#define SDI_RSP1 0x18 436#define SDI_RSP2 0x1c 437#define SDI_RSP3 0x20 438#define SDI_DTIMER 0x24 439#define SDI_BSIZE 0x28 440#define SDI_DCON 0x2c 441#define DCON_PRDTYPE (1<<21) 442#define DCON_TARSP (1<<20) /* Transmit after response */ 443#define DCON_RACMD (1<<19) /* Receive after command */ 444#define DCON_BACMD (1<<18) /* Busy after command */ 445#define DCON_BLKMODE (1<<17) /* Stream/Block mode */ 446#define DCON_WIDEBUS (1<<16) /* Standard/Wide bus */ 447#define DCON_ENDMA (1<<15) /* DMA Enable */ 448/* Determine the direction of the data transfer */ 449#define DCON_DATA_READY (0<<12) /* No transfer */ 450#define DCON_ONLYBUST (1<<12) /* Check if busy */ 451#define DCON_DATA_RECEIVE (2<<12) /* Receive data from SD */ 452#define DCON_DATA_TRANSMIT (3<<12) /* Send data to SD */ 453#define DCON_BLKNUM_MASK (0x7FF) /* Block number */ 454#define SDI_DCNT 0x30 455#define SDI_DSTA 0x34 456#define SDI_FSTA 0x38 457#define FSTA_TX_AVAIL (1<<13) 458#define FSTA_RX_AVAIL (1<<12) 459#define FSTA_TX_FIFO_HALF_FULL (1<<11) 460#define FSTA_TX_FIFO_EMPTY (1<<10) 461#define FSTA_RX_FIFO_LAST_DATA (1<<9) 462#define FSTA_RX_FIFO_FULL (1<<8) 463#define FSTA_RX_FIFO_HALF_FULL (1<<7) 464#define FSTA_FIFO_COUNT_MSK (0x7F) 465 466/* Timer */ 467#define TIMER_TCFG0 0x00 /* Timer configuration */ 468#define TIMER_TCFG1 0x04 469#define TCFG1_MUX_SHIFT(n) (4*(n)) 470#define TCFG1_MUX_MASK(n) (0x0f << TCFG1_MUX_SHIFT(n)) 471#define TCFG1_MUX_DIV2 0 472#define TCFG1_MUX_DIV4 1 473#define TCFG1_MUX_DIV8 2 474#define TCFG1_MUX_DIV16 3 475#define TCFG1_MUX_EXT 4 476#define TIMER_TCON 0x08 /* control */ 477#define TCON_SHIFT(n) (4 * ((n)==0 ? 0 : (n)+1)) 478#define TCON_START(n) (1 << TCON_SHIFT(n)) 479#define TCON_MANUALUPDATE(n) (1 << (TCON_SHIFT(n) + 1)) 480#define TCON_INVERTER(n) (1 << (TCON_SHIFT(n) + 2)) 481#define __TCON_AUTORELOAD(n) (1 << (TCON_SHIFT(n) + 3)) /* n=0..3 */ 482#define TCON_AUTORELOAD4 (1<<22) /* stupid hardware design */ 483#define TCON_AUTORELOAD(n) \ 484 ((n)==4 ? TCON_AUTORELOAD4 : __TCON_AUTORELOAD(n)) 485#define TCON_MASK(n) (0x0f << TCON_SHIFT(n)) 486#define TIMER_TCNTB(n) (0x0c+0x0c*(n)) /* count buffer */ 487#define TIMER_TCMPB(n) (0x10+0x0c*(n)) /* compare buffer */ 488#define __TIMER_TCNTO(n) (0x14+0x0c*(n)) /* count observation */ 489#define TIMER_TCNTO4 0x40 490#define TIMER_TCNTO(n) ((n)==4 ? TIMER_TCNTO4 : __TIMER_TCNTO(n)) 491 492#define S3C24X0_TIMER_SIZE 0x44 493 494/* UART */ 495/* diffs to s3c2800 */ 496/* SSCOM_UMCON */ 497#define UMCON_AFC (1<<4) /* auto flow control */ 498/* SSCOM_UMSTAT */ 499#define UMSTAT_DCTS (1<<2) /* CTS change */ 500/* SSCOM_UMSTAT */ 501#define ULCON_IR (1<<6) 502#define ULCON_PARITY_SHIFT 3 503 504#define S3C24X0_UART_SIZE 0x2c 505 506/* USB device */ 507/* XXX */ 508 509/* Watch dog timer */ 510#define WDT_WTCON 0x00 /* WDT mode */ 511#define WTCON_PRESCALE_SHIFT 8 512#define WTCON_PRESCALE (0xff<<WTCON_PRESCALE_SHIFT) 513#define WTCON_ENABLE (1<<5) 514#define WTCON_CLKSEL (3<<3) 515#define WTCON_CLKSEL_16 (0<<3) 516#define WTCON_CLKSEL_32 (1<<3) 517#define WTCON_CLKSEL_64 (2<<3) 518#define WTCON_CLKSEL_128 (3<<3) 519#define WTCON_ENINT (1<<2) 520#define WTCON_ENRST (1<<0) 521 522#define WTCON_WDTSTOP 0 523 524#define WDT_WTDAT 0x04 /* timer data */ 525#define WDT_WTCNT 0x08 /* timer count */ 526 527#define S3C24X0_WDT_SIZE 0x0c 528 529/* IIC */ 530#define S3C24X0_IIC_SIZE 0x0c 531 532 533/* IIS */ 534#define S3C24X0_IIS_SIZE 0x14 535 536/* GPIO */ 537#define GPIO_PACON 0x00 /* port A configuration */ 538#define GPIO_PADAT 0x04 /* port A data */ 539 540#define GPIO_PBCON 0x10 541/* These are only used on port B-H on 2410 & B-H,J on 2440 */ 542#define PCON_INPUT 0 /* Input port */ 543#define PCON_OUTPUT 1 /* Output port */ 544#define PCON_ALTFUN 2 /* Alternate function */ 545#define PCON_ALTFUN2 3 /* Alternate function */ 546#define GPIO_PBDAT 0x14 547/* This is different between 2440 and 2442 (pull up vs pull down): */ 548#define GPIO_PBUP 0x18 /* 2410 & 2440 */ 549#define GPIO_PBDOWN 0x18 /* 2442 */ 550 551#define GPIO_PCCON 0x20 552#define GPIO_PCDAT 0x24 553#define GPIO_PCUP 0x28 /* 2410 & 2440 */ 554#define GPIO_PCDOWN 0x28 /* 2442 */ 555 556#define GPIO_PDCON 0x30 557#define GPIO_PDDAT 0x34 558#define GPIO_PDUP 0x38 /* 2410 & 2440 */ 559#define GPIO_PDDOWN 0x38 /* 2442 */ 560 561#define GPIO_PECON 0x40 562#define PECON_INPUT(x) (0<<((x)*2)) /* Pin is used for input */ 563#define PECON_OUTPUT(x) (1<<((x)*2)) /* Pin is used for output */ 564#define PECON_FUNC_A(x) (2<<((x)*2)) /* Pin is used for function 'A' */ 565#define PECON_FUNC_B(x) (3<<((x)*2)) /* Pin is used for function 'B' */ 566#define PECON_MASK(x) (3<<((x)*2)) 567#define GPIO_PEDAT 0x44 568#define GPIO_PEUP 0x48 /* 2410 & 2440 */ 569#define GPIO_PEDOWN 0x48 /* 2442 */ 570#define PEUD_ENABLE(x) (~(1<<(x))) /* Enable the pull Up/Down */ 571#define PEUD_DISABLE(x) (1<<(x)) /* Disable the pull Up/Down */ 572 573#define GPIO_PFCON 0x50 574#define GPIO_PFDAT 0x54 575#define GPIO_PFUP 0x58 /* 2410 & 2440 */ 576#define GPIO_PFDOWN 0x58 /* 2442 */ 577 578#define GPIO_PGCON 0x60 579#define GPIO_PGDAT 0x64 580#define GPIO_PGUP 0x68 /* 2410 & 2440 */ 581#define GPIO_PGDOWN 0x68 /* 2442 */ 582 583#define GPIO_PHCON 0x70 584#define GPIO_PHDAT 0x74 585#define GPIO_PHUP 0x78 /* 2410 & 2440 */ 586#define GPIO_PHDOWN 0x78 /* 2442 */ 587 588#define GPIO_MISCCR 0x80 /* miscellaneous control */ 589#define GPIO_DCLKCON 0x84 /* DCLK 0/1 */ 590#define GPIO_EXTINT(n) (0x88+4*(n)) /* external int control 0/1/2 */ 591#define GPIO_EINTFLT(n) (0x94+4*(n)) /* external int filter control 0..3 */ 592#define EXTINTR_LOW 0x00 593#define EXTINTR_HIGH 0x01 594#define EXTINTR_FALLING 0x02 595#define EXTINTR_RISING 0x04 596#define EXTINTR_BOTH 0x06 597#define GPIO_EINTMASK 0xa4 598#define GPIO_EINTPEND 0xa8 599#define GPIO_GSTATUS0 0xac /* external pin status */ 600#define GPIO_GSTATUS1 0xb0 /* Chip ID */ 601#define CHIPID_S3C2410A 0x32410002 602#define CHIPID_S3C2440A 0x32440001 603#define CHIPID_S3C2442B 0x32440AAB 604#define GPIO_GSTATUS2 0xb4 /* Reset status */ 605#define GPIO_GSTATUS3 0xb8 606#define GPIO_GSTATUS4 0xbc 607 608#define GPIO_SET_FUNC(v,port,func) \ 609 (((v) & ~(3<<(2*(port))))|((func)<<(2*(port)))) 610 611/* ADC */ 612#define ADC_ADCCON 0x00 613#define ADCCON_ENABLE_START (1<<0) 614#define ADCCON_READ_START (1<<1) 615#define ADCCON_STDBM (1<<2) 616#define ADCCON_SEL_MUX_SHIFT 3 617#define ADCCON_SEL_MUX_MASK (0x7<<ADCCON_SEL_MUX_SHIFT) 618#define ADCCON_PRSCVL_SHIFT 6 619#define ADCCON_PRSCVL_MASK (0xff<<ADCCON_PRSCVL_SHIFT) 620#define ADCCON_PRSCEN (1<<14) 621#define ADCCON_ECFLG (1<<15) 622 623#define ADC_ADCTSC 0x04 624#define ADCTSC_XY_PST 0x03 625#define ADCTSC_AUTO_PST (1<<2) 626#define ADCTSC_PULL_UP (1<<3) 627#define ADCTSC_XP_SEN (1<<4) 628#define ADCTSC_XM_SEN (1<<5) 629#define ADCTSC_YP_SEN (1<<6) 630#define ADCTSC_YM_SEN (1<<7) 631#define ADC_ADCDLY 0x08 632#define ADC_ADCDAT0 0x0c 633#define ADC_ADCDAT1 0x10 634 635#define ADCDAT_DATAMASK 0x3ff 636 637/* RTC */ /* XXX */ 638 639/* SPI */ 640#define S3C24X0_SPI_SIZE 0x20 641 642#define SPI_SPCON 0x00 643#define SPCON_TAGD (1<<0) /* Tx auto garbage */ 644#define SPCON_CPHA (1<<1) 645#define SPCON_CPOL (1<<2) 646#define SPCON_IDLELOW_RISING (0|0) 647#define SPCON_IDLELOW_FALLING (0|SPCON_CPHA) 648#define SPCON_IDLEHIGH_FALLING (SPCON_CPOL|0) 649#define SPCON_IDLEHIGH_RISING (SPCON_CPOL|SPCON_CPHA) 650#define SPCON_MSTR (1<<3) 651#define SPCON_ENSCK (1<<4) 652#define SPCON_SMOD_SHIFT 5 653#define SPCON_SMOD_MASK (0x03<<SPCON_SMOD_SHIFT) 654#define SPCON_SMOD_POLL (0x00<<SPCON_SMOD_SHIFT) 655#define SPCON_SMOD_INT (0x01<<SPCON_SMOD_SHIFT) 656#define SPCON_SMOD_DMA (0x02<<SPCON_SMOD_SHIFT) 657 658#define SPI_SPSTA 0x04 /* status register */ 659#define SPSTA_REDY (1<<0) /* ready */ 660#define SPSTA_MULF (1<<1) /* multi master error */ 661#define SPSTA_DCOL (1<<2) /* Data collision error */ 662 663#define SPI_SPPIN 0x08 664#define SPPIN_KEEP (1<<0) 665#define SPPIN_ENMUL (1<<2) /* multi master error detect */ 666 667#define SPI_SPPRE 0x0c /* prescaler */ 668#define SPI_SPTDAT 0x10 /* tx data */ 669#define SPI_SPRDAT 0x14 /* rx data */ 670 671 672#endif /* _ARM_S3C2XX0_S3C24X0REG_H_ */ 673