1205354Simp/* $NetBSD: s3c24x0reg.h,v 1.7 2004/02/12 03:52:46 bsh Exp $ */ 2205354Simp 3205354Simp/*- 4205354Simp * Copyright (c) 2003 Genetec corporation All rights reserved. 5205354Simp * Written by Hiroyuki Bessho for Genetec corporation. 6205354Simp * 7205354Simp * Redistribution and use in source and binary forms, with or without 8205354Simp * modification, are permitted provided that the following conditions 9205354Simp * are met: 10205354Simp * 1. Redistributions of source code must retain the above copyright 11205354Simp * notice, this list of conditions and the following disclaimer. 12205354Simp * 2. Redistributions in binary form must reproduce the above copyright 13205354Simp * notice, this list of conditions and the following disclaimer in the 14205354Simp * documentation and/or other materials provided with the distribution. 15205354Simp * 3. The name of Genetec corporation may not be used to endorse 16205354Simp * or promote products derived from this software without specific prior 17205354Simp * written permission. 18205354Simp * 19205354Simp * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20205354Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21205354Simp * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22205354Simp * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23205354Simp * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24205354Simp * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25205354Simp * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26205354Simp * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27205354Simp * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28205354Simp * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29205354Simp * POSSIBILITY OF SUCH DAMAGE. 30205354Simp * 31205354Simp * $FreeBSD: releng/10.3/sys/arm/samsung/s3c2xx0/s3c24x0reg.h 272103 2014-09-25 11:38:26Z gavin $ 32205354Simp */ 33205354Simp 34205354Simp 35205354Simp/* 36205354Simp * Samsung S3C2410X/2400 processor is ARM920T based integrated CPU 37205354Simp * 38205354Simp * Reference: 39236990Simp * S3C2410X User's Manual 40205354Simp * S3C2400 User's Manual 41205354Simp */ 42205354Simp#ifndef _ARM_S3C2XX0_S3C24X0REG_H_ 43205354Simp#define _ARM_S3C2XX0_S3C24X0REG_H_ 44205354Simp 45205354Simp/* common definitions for S3C2800, S3C2410 and S3C2440 */ 46272103Sgavin#include <arm/samsung/s3c2xx0/s3c2xx0reg.h> 47205354Simp 48205354Simp/* 49210396Sandrew * Map the device registers into kernel space. 50210396Sandrew * 51210396Sandrew * As most devices use less than 1 page of memory reduce 52210396Sandrew * the distance between allocations by right shifting 53210396Sandrew * S3C24X0_DEV_SHIFT bits. Because the UART takes 3*0x4000 54210396Sandrew * bytes the upper limit on S3C24X0_DEV_SHIFT is 4. 55210396Sandrew * TODO: Fix the UART code so we can increase this value. 56205354Simp */ 57205354Simp#define S3C24X0_DEV_START 0x48000000 58205354Simp#define S3C24X0_DEV_STOP 0x60000000 59210396Sandrew#define S3C24X0_DEV_VA_OFFSET 0xD8000000 60210396Sandrew#define S3C24X0_DEV_SHIFT 4 61210396Sandrew#define S3C24X0_DEV_PA_SIZE (S3C24X0_DEV_STOP - S3C24X0_DEV_START) 62210396Sandrew#define S3C24X0_DEV_VA_SIZE (S3C24X0_DEV_PA_SIZE >> S3C24X0_DEV_SHIFT) 63210396Sandrew#define S3C24X0_DEV_PA_TO_VA(x) ((x >> S3C24X0_DEV_SHIFT) - S3C24X0_DEV_START + S3C24X0_DEV_VA_OFFSET) 64205354Simp 65205354Simp/* 66205354Simp * Physical address of integrated peripherals 67205354Simp */ 68205354Simp#define S3C24X0_MEMCTL_PA_BASE 0x48000000 /* memory controller */ 69205354Simp#define S3C24X0_MEMCTL_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_MEMCTL_PA_BASE) 70205354Simp#define S3C24X0_USBHC_PA_BASE 0x49000000 /* USB Host controller */ 71205354Simp#define S3C24X0_USBHC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_USBHC_PA_BASE) 72205354Simp#define S3C24X0_INTCTL_PA_BASE 0x4a000000 /* Interrupt controller */ 73205354Simp#define S3C24X0_INTCTL_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_INTCTL_PA_BASE) 74205354Simp#define S3C24X0_INTCTL_SIZE 0x20 75205354Simp#define S3C24X0_DMAC_PA_BASE 0x4b000000 76205354Simp#define S3C24X0_DMAC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_DMAC_PA_BASE) 77205354Simp#define S3C24X0_DMAC_SIZE 0xe4 78205354Simp#define S3C24X0_CLKMAN_PA_BASE 0x4c000000 /* clock & power management */ 79205354Simp#define S3C24X0_CLKMAN_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_CLKMAN_PA_BASE) 80205354Simp#define S3C24X0_LCDC_PA_BASE 0x4d000000 /* LCD controller */ 81205354Simp#define S3C24X0_LCDC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_LCDC_PA_BASE) 82205354Simp#define S3C24X0_LCDC_SIZE 0x64 83205354Simp#define S3C24X0_NANDFC_PA_BASE 0x4e000000 /* NAND Flash controller */ 84205354Simp#define S3C24X0_NANDFC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_NANDFC_PA_BASE) 85205354Simp#define S3C24X0_UART0_PA_BASE 0x50000000 86205354Simp#define S3C24X0_UART0_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_UART0_PA_BASE) 87205354Simp#define S3C24X0_UART_PA_BASE(n) (S3C24X0_UART0_PA_BASE+0x4000*(n)) 88210396Sandrew#define S3C24X0_UART_BASE(n) (S3C24X0_UART0_BASE+0x4000*(n)) 89205354Simp#define S3C24X0_TIMER_PA_BASE 0x51000000 90205354Simp#define S3C24X0_TIMER_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_TIMER_PA_BASE) 91205354Simp#define S3C24X0_USBDC_PA_BASE 0x5200140 92205354Simp#define S3C24X0_USBDC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_USBDC_PA_BASE) 93205354Simp#define S3C24X0_USBDC_SIZE 0x130 94205354Simp#define S3C24X0_WDT_PA_BASE 0x53000000 95205354Simp#define S3C24X0_WDT_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_WDT_PA_BASE) 96205354Simp#define S3C24X0_IIC_PA_BASE 0x54000000 97205354Simp#define S3C24X0_IIC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_IIC_PA_BASE) 98205354Simp#define S3C24X0_IIS_PA_BASE 0x55000000 99205354Simp#define S3C24X0_IIS_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_IIS_PA_BASE) 100205354Simp#define S3C24X0_GPIO_PA_BASE 0x56000000 101205354Simp#define S3C24X0_GPIO_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_GPIO_PA_BASE) 102210397Sandrew#define S3C24X0_RTC_PA_BASE 0x57000000 103210397Sandrew#define S3C24X0_RTC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_RTC_PA_BASE) 104210397Sandrew#define S3C24X0_RTC_SIZE 0x8C 105205354Simp#define S3C24X0_ADC_PA_BASE 0x58000000 106205354Simp#define S3C24X0_ADC_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_ADC_PA_BASE) 107205354Simp#define S3C24X0_SPI0_PA_BASE 0x59000000 108205354Simp#define S3C24X0_SPI0_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_SPI0_PA_BASE) 109205354Simp#define S3C24X0_SPI1_PA_BASE 0x59000020 110205354Simp#define S3C24X0_SPI1_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_SPI1_PA_BASE) 111205354Simp#define S3C24X0_SDI_PA_BASE 0x5a000000 /* SD Interface */ 112205354Simp#define S3C24X0_SDI_BASE S3C24X0_DEV_PA_TO_VA(S3C24X0_SDI_PA_BASE) 113205354Simp 114205354Simp#define S3C24X0_REG_BASE 0x48000000 115205354Simp#define S3C24X0_REG_SIZE 0x13000000 116205354Simp 117205354Simp/* Memory controller */ 118205354Simp#define MEMCTL_BWSCON 0x00 /* Bus width and wait status */ 119205354Simp#define BWSCON_DW0_SHIFT 1 /* bank0 is odd */ 120205354Simp#define BWSCON_BANK_SHIFT(n) (4*(n)) /* for bank 1..7 */ 121205354Simp#define BWSCON_DW_MASK 0x03 122205354Simp#define BWSCON_DW_8 0 123205354Simp#define BWSCON_DW_16 1 124205354Simp#define BWSCON_DW_32 2 125205354Simp#define BWSCON_WS 0x04 /* WAIT enable for the bank */ 126205354Simp#define BWSCON_ST 0x08 /* SRAM use UB/LB for the bank */ 127205354Simp 128205354Simp#define MEMCTL_BANKCON0 0x04 /* Boot ROM control */ 129205354Simp#define MEMCTL_BANKCON(n) (0x04+4*(n)) /* BANKn control */ 130205354Simp#define BANKCON_MT_SHIFT 15 131205354Simp#define BANKCON_MT_ROM (0<<BANKCON_MT_SHIFT) 132205354Simp#define BANKCON_MT_DRAM (3<<BANKCON_MT_SHIFT) 133205354Simp#define BANKCON_TACS_SHIFT 13 /* address set-up time to nGCS */ 134205354Simp#define BANKCON_TCOS_SHIFT 11 /* CS set-up to nOE */ 135205354Simp#define BANKCON_TACC_SHIFT 8 /* CS set-up to nOE */ 136205354Simp#define BANKCON_TOCH_SHIFT 6 /* CS hold time from OE */ 137205354Simp#define BANKCON_TCAH_SHIFT 4 /* address hold time from OE */ 138205354Simp#define BANKCON_TACP_SHIFT 2 /* page mode access cycle */ 139205354Simp#define BANKCON_TACP_2 (0<<BANKCON_TACP_SHIFT) 140205354Simp#define BANKCON_TACP_3 (1<<BANKCON_TACP_SHIFT) 141205354Simp#define BANKCON_TACP_4 (2<<BANKCON_TACP_SHIFT) 142205354Simp#define BANKCON_TACP_6 (3<<BANKCON_TACP_SHIFT) 143205354Simp#define BANKCON_PMC_4 (1<<0) 144205354Simp#define BANKCON_PMC_8 (2<<0) 145205354Simp#define BANKCON_PMC_16 (3<<0) 146205354Simp#define BANKCON_TRCD_SHIFT 2 /* RAS to CAS delay */ 147205354Simp#define BANKCON_TRCD_2 (0<<2) 148205354Simp#define BANKCON_TRCD_3 (1<<2) 149205354Simp#define BANKCON_TRCD_4 (2<<2) 150205354Simp#define BANKCON_SCAN_8 (0<<0) /* Column address number */ 151205354Simp#define BANKCON_SCAN_9 (1<<0) 152205354Simp#define BANKCON_SCAN_10 (2<<0) 153205354Simp#define MEMCTL_REFRESH 0x24 /* DRAM?SDRAM Refresh */ 154205354Simp#define REFRESH_REFEN (1<<23) 155205354Simp#define REFRESH_TREFMD (1<<22) /* 1=self refresh */ 156205354Simp#define REFRESH_TRP_2 (0<<20) 157205354Simp#define REFRESH_TRP_3 (1<<20) 158205354Simp#define REFRESH_TRP_4 (2<<20) 159205354Simp#define REFRESH_TRC_4 (0<<18) 160205354Simp#define REFRESH_TRC_5 (1<<18) 161205354Simp#define REFRESH_TRC_6 (2<<18) 162205354Simp#define REFRESH_TRC_7 (3<<18) 163205354Simp#define REFRESH_COUNTER_MASK 0x3ff 164205354Simp#define MEMCTL_BANKSIZE 0x28 /* Flexible Bank size */ 165205354Simp#define MEMCTL_MRSRB6 0x2c /* SDRAM Mode register */ 166205354Simp#define MEMCTL_MRSRB7 0x30 167205354Simp#define MRSR_CL_SHIFT 4 /* CAS Latency */ 168205354Simp 169205354Simp#define S3C24X0_MEMCTL_SIZE 0x34 170205354Simp 171205354Simp/* USB Host controller */ 172205354Simp#define S3C24X0_USBHC_SIZE 0x5c 173205354Simp 174205354Simp/* Interrupt controller */ 175205354Simp#define INTCTL_PRIORITY 0x0c /* IRQ Priority control */ 176205354Simp#define INTCTL_INTPND 0x10 /* Interrupt request status */ 177205354Simp#define INTCTL_INTOFFSET 0x14 /* Interrupt request source */ 178205354Simp#define INTCTL_SUBSRCPND 0x18 /* sub source pending */ 179205354Simp#define INTCTL_INTSUBMSK 0x1c /* sub mask */ 180205354Simp 181205354Simp/* Interrupt source */ 182205354Simp#define S3C24X0_INT_ADCTC 31 /* ADC (and TC for 2410) */ 183205354Simp#define S3C24X0_INT_RTC 30 /* RTC alarm */ 184205354Simp#define S3C24X0_INT_SPI1 29 /* SPI 1 */ 185205354Simp#define S3C24X0_INT_UART0 28 /* UART0 */ 186205354Simp#define S3C24X0_INT_IIC 27 187205354Simp#define S3C24X0_INT_USBH 26 /* USB Host */ 188205354Simp#define S3C24X0_INT_USBD 25 /* USB Device */ 189205354Simp#define S3C24X0_INT_UART1 23 /* UART0 (2410 only) */ 190205354Simp#define S3C24X0_INT_SPI0 22 /* SPI 0 */ 191205354Simp#define S3C24X0_INT_SDI 21 192205354Simp#define S3C24X0_INT_DMA3 20 193205354Simp#define S3C24X0_INT_DMA2 19 194205354Simp#define S3C24X0_INT_DMA1 18 195205354Simp#define S3C24X0_INT_DMA0 17 196205354Simp#define S3C24X0_INT_LCD 16 197205354Simp 198205354Simp#define S3C24X0_INT_UART2 15 /* UART2 int (2410) */ 199205354Simp#define S3C24X0_INT_TIMER4 14 200205354Simp#define S3C24X0_INT_TIMER3 13 201205354Simp#define S3C24X0_INT_TIMER2 12 202205354Simp#define S3C24X0_INT_TIMER1 11 203205354Simp#define S3C24X0_INT_TIMER0 10 204205354Simp#define S3C24X0_INT_TIMER(n) (10+(n)) /* timer interrupt [4:0] */ 205205354Simp#define S3C24X0_INT_WDT 9 /* Watch dog timer */ 206205354Simp#define S3C24X0_INT_TICK 8 207205354Simp#define S3C24X0_INT_BFLT 7 /* Battery fault */ 208205354Simp#define S3C24X0_INT_8_23 5 /* Ext int 8..23 */ 209205354Simp#define S3C24X0_INT_4_7 4 /* Ext int 4..7 */ 210210458Sandrew#define S3C24X0_INT_3 3 211210458Sandrew#define S3C24X0_INT_2 2 212210458Sandrew#define S3C24X0_INT_1 1 213210458Sandrew#define S3C24X0_INT_0 0 214205354Simp 215205354Simp/* 24{1,4}0 has more than 32 interrupt sources. These are sub-sources 216205354Simp * that are OR-ed into main interrupt sources, and controlled via 217205354Simp * SUBSRCPND and SUBSRCMSK registers */ 218205354Simp#define S3C24X0_SUBIRQ_MIN 32 219205354Simp 220205354Simp/* cascaded to INT_ADCTC */ 221205354Simp#define S3C24X0_INT_ADC (S3C24X0_SUBIRQ_MIN+10) /* AD converter */ 222205354Simp#define S3C24X0_INT_TC (S3C24X0_SUBIRQ_MIN+9) /* Touch screen */ 223205354Simp/* cascaded to INT_UART2 */ 224205354Simp#define S3C24X0_INT_ERR2 (S3C24X0_SUBIRQ_MIN+8) /* UART2 Error */ 225205354Simp#define S3C24X0_INT_TXD2 (S3C24X0_SUBIRQ_MIN+7) /* UART2 Tx */ 226205354Simp#define S3C24X0_INT_RXD2 (S3C24X0_SUBIRQ_MIN+6) /* UART2 Rx */ 227205354Simp/* cascaded to INT_UART1 */ 228205354Simp#define S3C24X0_INT_ERR1 (S3C24X0_SUBIRQ_MIN+5) /* UART1 Error */ 229205354Simp#define S3C24X0_INT_TXD1 (S3C24X0_SUBIRQ_MIN+4) /* UART1 Tx */ 230205354Simp#define S3C24X0_INT_RXD1 (S3C24X0_SUBIRQ_MIN+3) /* UART1 Rx */ 231205354Simp/* cascaded to INT_UART0 */ 232205354Simp#define S3C24X0_INT_ERR0 (S3C24X0_SUBIRQ_MIN+2) /* UART0 Error */ 233205354Simp#define S3C24X0_INT_TXD0 (S3C24X0_SUBIRQ_MIN+1) /* UART0 Tx */ 234205354Simp#define S3C24X0_INT_RXD0 (S3C24X0_SUBIRQ_MIN+0) /* UART0 Rx */ 235205354Simp 236210458Sandrew/* 237210458Sandrew * Support for external interrupts. We use values from 48 238210458Sandrew * to allow new CPU's to allocate new subirq's. 239210458Sandrew */ 240210458Sandrew#define S3C24X0_EXTIRQ_MIN 48 241210458Sandrew#define S3C24X0_EXTIRQ_COUNT 24 242210458Sandrew#define S3C24X0_EXTIRQ_MAX (S3C24X0_EXTIRQ_MIN + S3C24X0_EXTIRQ_COUNT - 1) 243210458Sandrew#define S3C24X0_INT_EXT(n) (S3C24X0_EXTIRQ_MIN + (n)) 244210458Sandrew 245205354Simp/* DMA controller */ 246205354Simp/* XXX */ 247205354Simp 248205354Simp/* Clock & power manager */ 249205354Simp#define CLKMAN_LOCKTIME 0x00 /* PLL lock time */ 250205354Simp#define CLKMAN_MPLLCON 0x04 /* MPLL control */ 251205354Simp#define CLKMAN_UPLLCON 0x08 /* UPLL control */ 252205354Simp#define PLLCON_MDIV_SHIFT 12 253205354Simp#define PLLCON_MDIV_MASK (0xff<<PLLCON_MDIV_SHIFT) 254205354Simp#define PLLCON_PDIV_SHIFT 4 255205354Simp#define PLLCON_PDIV_MASK (0x3f<<PLLCON_PDIV_SHIFT) 256205354Simp#define PLLCON_SDIV_SHIFT 0 257205354Simp#define PLLCON_SDIV_MASK (0x03<<PLLCON_SDIV_SHIFT) 258205354Simp#define CLKMAN_CLKCON 0x0c 259205354Simp#define CLKCON_SPI (1<<18) 260205354Simp#define CLKCON_IIS (1<<17) 261205354Simp#define CLKCON_IIC (1<<16) 262205354Simp#define CLKCON_ADC (1<<15) 263205354Simp#define CLKCON_RTC (1<<14) 264205354Simp#define CLKCON_GPIO (1<<13) 265205354Simp#define CLKCON_UART2 (1<<12) 266205354Simp#define CLKCON_UART1 (1<<11) 267205354Simp#define CLKCON_UART0 (1<<10) /* PCLK to UART0 */ 268205354Simp#define CLKCON_SDI (1<<9) 269205354Simp#define CLKCON_TIMER (1<<8) /* PCLK to TIMER */ 270205354Simp#define CLKCON_USBD (1<<7) /* PCLK to USB device controller */ 271205354Simp#define CLKCON_USBH (1<<6) /* PCLK to USB host controller */ 272205354Simp#define CLKCON_LCDC (1<<5) /* PCLK to LCD controller */ 273205354Simp#define CLKCON_NANDFC (1<<4) /* PCLK to NAND Flash controller */ 274205354Simp#define CLKCON_IDLE (1<<2) /* 1=transition to IDLE mode */ 275205354Simp#define CLKMAN_CLKSLOW 0x10 276205354Simp#define CLKMAN_CLKDIVN 0x14 277205354Simp#define CLKDIVN_PDIVN (1<<0) /* pclk=hclk/2 */ 278205354Simp 279205354Simp#define CLKMAN_CLKSLOW 0x10 /* slow clock controll */ 280205354Simp#define CLKSLOW_UCLK (1<<7) /* 1=UPLL off */ 281205354Simp#define CLKSLOW_MPLL (1<<5) /* 1=PLL off */ 282205354Simp#define CLKSLOW_SLOW (1<<4) /* 1: Enable SLOW mode */ 283205354Simp#define CLKSLOW_VAL_MASK 0x0f /* divider value for slow clock */ 284205354Simp 285205354Simp#define CLKMAN_CLKDIVN 0x14 /* Software reset control */ 286205354Simp#define CLKDIVN_PDIVN (1<<0) 287205354Simp 288205354Simp#define S3C24X0_CLKMAN_SIZE 0x18 289205354Simp 290205354Simp/* LCD controller */ 291205354Simp#define LCDC_LCDCON1 0x00 /* control 1 */ 292205354Simp#define LCDCON1_ENVID (1<<0) /* enable video */ 293205354Simp#define LCDCON1_BPPMODE_SHIFT 1 294205354Simp#define LCDCON1_BPPMODE_MASK (0x0f<<LCDCON1_BPPMODE_SHIFT) 295205354Simp#define LCDCON1_BPPMODE_STN1 (0x0<<LCDCON1_BPPMODE_SHIFT) 296205354Simp#define LCDCON1_BPPMODE_STN2 (0x1<<LCDCON1_BPPMODE_SHIFT) 297205354Simp#define LCDCON1_BPPMODE_STN4 (0x2<<LCDCON1_BPPMODE_SHIFT) 298205354Simp#define LCDCON1_BPPMODE_STN8 (0x3<<LCDCON1_BPPMODE_SHIFT) 299205354Simp#define LCDCON1_BPPMODE_STN12 (0x4<<LCDCON1_BPPMODE_SHIFT) 300205354Simp#define LCDCON1_BPPMODE_TFT1 (0x8<<LCDCON1_BPPMODE_SHIFT) 301205354Simp#define LCDCON1_BPPMODE_TFT2 (0x9<<LCDCON1_BPPMODE_SHIFT) 302205354Simp#define LCDCON1_BPPMODE_TFT4 (0xa<<LCDCON1_BPPMODE_SHIFT) 303205354Simp#define LCDCON1_BPPMODE_TFT8 (0xb<<LCDCON1_BPPMODE_SHIFT) 304205354Simp#define LCDCON1_BPPMODE_TFT16 (0xc<<LCDCON1_BPPMODE_SHIFT) 305205354Simp#define LCDCON1_BPPMODE_TFT24 (0xd<<LCDCON1_BPPMODE_SHIFT) 306205354Simp#define LCDCON1_BPPMODE_TFTX (0x8<<LCDCON1_BPPMODE_SHIFT) 307205354Simp 308205354Simp#define LCDCON1_PNRMODE_SHIFT 5 309205354Simp#define LCDCON1_PNRMODE_MASK (0x3<<LCDCON1_PNRMODE_SHIFT) 310205354Simp#define LCDCON1_PNRMODE_DUALSTN4 (0x0<<LCDCON1_PNRMODE_SHIFT) 311205354Simp#define LCDCON1_PNRMODE_SINGLESTN4 (0x1<<LCDCON1_PNRMODE_SHIFT) 312205354Simp#define LCDCON1_PNRMODE_SINGLESTN8 (0x2<<LCDCON1_PNRMODE_SHIFT) 313205354Simp#define LCDCON1_PNRMODE_TFT (0x3<<LCDCON1_PNRMODE_SHIFT) 314205354Simp 315205354Simp#define LCDCON1_MMODE (1<<7) /* VM toggle rate */ 316205354Simp#define LCDCON1_CLKVAL_SHIFT 8 317205354Simp#define LCDCON1_CLKVAL_MASK (0x3ff<<LCDCON1_CLKVAL_SHIFT) 318205354Simp#define LCDCON1_LINCNT_SHIFT 18 319205354Simp#define LCDCON1_LINCNT_MASK (0x3ff<<LCDCON1_LINCNT_SHIFT) 320205354Simp 321205354Simp#define LCDC_LCDCON2 0x04 /* control 2 */ 322205354Simp#define LCDCON2_VPSW_SHIFT 0 /* TFT Vsync pulse width */ 323205354Simp#define LCDCON2_VPSW_MASK (0x3f<<LCDCON2_VPSW_SHIFT) 324205354Simp#define LCDCON2_VFPD_SHIFT 6 /* TFT V front porch */ 325205354Simp#define LCDCON2_VFPD_MASK (0xff<<LCDCON2_VFPD_SHIFT) 326205354Simp#define LCDCON2_LINEVAL_SHIFT 14 /* Vertical size */ 327205354Simp#define LCDCON2_LINEVAL_MASK (0x3ff<<LCDCON2_LINEVAL_SHIFT) 328205354Simp#define LCDCON2_VBPD_SHIFT 24 /* TFT V back porch */ 329205354Simp#define LCDCON2_VBPD_MASK (0xff<<LCDCON2_VBPD_SHIFT) 330205354Simp 331205354Simp#define LCDC_LCDCON3 0x08 /* control 2 */ 332205354Simp#define LCDCON3_HFPD_SHIFT 0 /* TFT H front porch */ 333205354Simp#define LCDCON3_HFPD_MASK (0xff<<LCDCON3_VPFD_SHIFT) 334205354Simp#define LCDCON3_LINEBLANK_SHIFT 0 /* STN H blank time */ 335205354Simp#define LCDCON3_LINEBLANK_MASK (0xff<<LCDCON3_LINEBLANK_SHIFT) 336205354Simp#define LCDCON3_HOZVAL_SHIFT 8 /* Horizontal size */ 337205354Simp#define LCDCON3_HOZVAL_MASK (0x7ff<<LCDCON3_HOZVAL_SHIFT) 338205354Simp#define LCDCON3_HBPD_SHIFT 19 /* TFT H back porch */ 339205354Simp#define LCDCON3_HBPD_MASK (0x7f<<LCDCON3_HPBD_SHIFT) 340205354Simp#define LCDCON3_WDLY_SHIFT 19 /* STN vline delay */ 341205354Simp#define LCDCON3_WDLY_MASK (0x03<<LCDCON3_WDLY_SHIFT) 342205354Simp#define LCDCON3_WDLY_16 (0x00<<LCDCON3_WDLY_SHIFT) 343205354Simp#define LCDCON3_WDLY_32 (0x01<<LCDCON3_WDLY_SHIFT) 344205354Simp#define LCDCON3_WDLY_64 (0x02<<LCDCON3_WDLY_SHIFT) 345205354Simp#define LCDCON3_WDLY_128 (0x03<<LCDCON3_WDLY_SHIFT) 346205354Simp 347205354Simp#define LCDC_LCDCON4 0x0c /* control 4 */ 348205354Simp#define LCDCON4_HPSW_SHIFT 0 /* TFT Hsync pulse width */ 349205354Simp#define LCDCON4_HPSW_MASK (0xff<<LCDCON4_HPSW_SHIFT) 350205354Simp#define LCDCON4_WLH_SHIFT 0 /* STN VLINE high width */ 351205354Simp#define LCDCON4_WLH_MASK (0x03<<LCDCON4_WLH_SHIFT) 352205354Simp#define LCDCON4_WLH_16 (0x00<<LCDCON4_WLH_SHIFT) 353205354Simp#define LCDCON4_WLH_32 (0x01<<LCDCON4_WLH_SHIFT) 354205354Simp#define LCDCON4_WLH_64 (0x02<<LCDCON4_WLH_SHIFT) 355205354Simp#define LCDCON4_WLH_128 (0x03<<LCDCON4_WLH_SHIFT) 356205354Simp 357205354Simp#define LCDCON4_MVAL_SHIFT 8 /* STN VM toggle rate */ 358205354Simp#define LCDCON4_MVAL_MASK (0xff<<LCDCON4_MVAL_SHIFT) 359205354Simp 360205354Simp#define LCDC_LCDCON5 0x10 /* control 5 */ 361205354Simp#define LCDCON5_HWSWP (1<<0) /* half-word swap */ 362205354Simp#define LCDCON5_BSWP (1<<1) /* byte swap */ 363205354Simp#define LCDCON5_ENLEND (1<<2) /* TFT: enable LEND signal */ 364205354Simp#define LCDCON5_PWREN (1<<3) /* enable PWREN signale */ 365205354Simp#define LCDCON5_INVLEND (1<<4) /* TFT: LEND signal polarity */ 366205354Simp#define LCDCON5_INVPWREN (1<<5) /* PWREN signal polarity */ 367205354Simp#define LCDCON5_INVVDEN (1<<6) /* VDEN signal polarity */ 368205354Simp#define LCDCON5_INVVD (1<<7) /* video data signal polarity */ 369205354Simp#define LCDCON5_INVVFRAME (1<<8) /* VFRAME/VSYNC signal polarity */ 370205354Simp#define LCDCON5_INVVLINE (1<<9) /* VLINE/HSYNC signal polarity */ 371205354Simp#define LCDCON5_INVVCLK (1<<10) /* VCLK signal polarity */ 372205354Simp#define LCDCON5_INVVCLK_RISING LCDCON5_INVVCLK 373205354Simp#define LCDCON5_INVVCLK_FALLING 0 374205354Simp#define LCDCON5_FRM565 (1<<11) /* RGB:565 format*/ 375205354Simp#define LCDCON5_FRM555I 0 /* RGBI:5551 format */ 376205354Simp#define LCDCON5_BPP24BL (1<<12) /* bit order for bpp24 */ 377205354Simp 378205354Simp#define LCDCON5_HSTATUS_SHIFT 17 /* TFT: horizontal status */ 379205354Simp#define LCDCON5_HSTATUS_MASK (0x03<<LCDCON5_HSTATUS_SHIFT) 380205354Simp#define LCDCON5_HSTATUS_HSYNC (0x00<<LCDCON5_HSTATUS_SHIFT) 381205354Simp#define LCDCON5_HSTATUS_BACKP (0x01<<LCDCON5_HSTATUS_SHIFT) 382205354Simp#define LCDCON5_HSTATUS_ACTIVE (0x02<<LCDCON5_HSTATUS_SHIFT) 383205354Simp#define LCDCON5_HSTATUS_FRONTP (0x03<<LCDCON5_HSTATUS_SHIFT) 384205354Simp 385205354Simp#define LCDCON5_VSTATUS_SHIFT 19 /* TFT: vertical status */ 386205354Simp#define LCDCON5_VSTATUS_MASK (0x03<<LCDCON5_VSTATUS_SHIFT) 387205354Simp#define LCDCON5_VSTATUS_HSYNC (0x00<<LCDCON5_VSTATUS_SHIFT) 388205354Simp#define LCDCON5_VSTATUS_BACKP (0x01<<LCDCON5_VSTATUS_SHIFT) 389205354Simp#define LCDCON5_VSTATUS_ACTIVE (0x02<<LCDCON5_VSTATUS_SHIFT) 390205354Simp#define LCDCON5_VSTATUS_FRONTP (0x03<<LCDCON5_VSTATUS_SHIFT) 391205354Simp 392205354Simp#define LCDC_LCDSADDR1 0x14 /* frame buffer start address */ 393205354Simp#define LCDC_LCDSADDR2 0x18 394205354Simp#define LCDC_LCDSADDR3 0x1c 395205354Simp#define LCDSADDR3_OFFSIZE_SHIFT 11 396205354Simp#define LCDSADDR3_PAGEWIDTH_SHIFT 0 397205354Simp 398205354Simp#define LCDC_REDLUT 0x20 /* STN: red lookup table */ 399205354Simp#define LCDC_GREENLUT 0x24 /* STN: green lookup table */ 400205354Simp#define LCDC_BLUELUT 0x28 /* STN: blue lookup table */ 401205354Simp#define LCDC_DITHMODE 0x4c /* STN: dithering mode */ 402205354Simp 403205354Simp#define LCDC_TPAL 0x50 /* TFT: temporary palette */ 404205354Simp#define TPAL_TPALEN (1<<24) 405205354Simp#define TPAL_RED_SHIFT 16 406205354Simp#define TPAL_GREEN_SHIFT 8 407205354Simp#define TPAL_BLUE_SHIFT 0 408205354Simp 409205354Simp#define LCDC_LCDINTPND 0x54 410205354Simp#define LCDC_LCDSRCPND 0x58 411205354Simp#define LCDC_LCDINTMSK 0x5c 412205354Simp#define LCDINT_FICNT (1<<0) /* FIFO trigger interrupt pending */ 413205354Simp#define LCDINT_FRSYN (1<<1) /* frame sync interrupt pending */ 414205354Simp#define LCDINT_FIWSEL (1<<2) /* FIFO trigger level: 1=8 words, 0=4 words*/ 415205354Simp 416205354Simp#define LCDC_LPCSEL 0x60 /* LPC3600 mode */ 417205354Simp#define LPCSEL_LPC_EN (1<<0) /* enable LPC3600 mode */ 418205354Simp#define LPCSEL_RES_SEL (1<<1) /* 1=240x320 0=320x240 */ 419205354Simp#define LPCSEL_MODE_SEL (1<<2) 420205354Simp#define LPCSEL_CPV_SEL (1<<3) 421205354Simp 422205354Simp 423205354Simp#define LCDC_PALETTE 0x0400 424205354Simp#define LCDC_PALETTE_SIZE 0x0400 425205354Simp 426205354Simp/* NAND Flash controller */ 427205354Simp#define NANDFC_NFCONF 0x00 /* Configuration */ 428205354Simp/* NANDFC_NFSTAT */ 429205354Simp#define NFSTAT_READY (1<<0) /* NAND flash memory ready/busy status */ 430205354Simp 431205354Simp 432205354Simp/* MMC/SD */ 433205354Simp#define SDI_CON 0x00 434205354Simp#define CON_BYTEORDER (1<<4) 435205354Simp#define CON_SDIO_INTR (1<<3) 436205354Simp#define CON_READWAIT_EN (1<<2) 437205354Simp#define CON_CLOCK_EN (1<<0) 438205354Simp#define SDI_PRE 0x04 439205354Simp#define SDI_CARG 0x08 440205354Simp#define SDI_CCON 0x0c 441205354Simp#define CCON_ABORDCMD (1<<12) /* Abort SDIO CMD12/52 */ 442205354Simp#define CCON_WITHDATA (1<<11) /* CMD with data */ 443205354Simp#define CCON_LONGRSP (1<<10) /* 136 bit response */ 444205354Simp#define CCON_WAITRSP (1<<9) /* Host waits for response */ 445205354Simp#define CCON_CMD_START (1<<8) 446205354Simp#define CCON_CMDINDEX_MASK (0x7F) /* Command number index */ 447205354Simp#define SDI_CSTA 0x10 448205354Simp#define CSTA_RSPCRCFAIL (1<<12) 449205354Simp#define CSTA_CMDSENT (1<<11) 450205354Simp#define CSTA_CMDTOUT (1<<10) 451205354Simp#define CSTA_RSPFIN (1<<9) 452205354Simp/* All the bits to be cleared */ 453205354Simp#define CSTA_ALL_CLEAR (CSTA_RSPCRCFAIL | CSTA_CMDSENT | \ 454205354Simp CSTA_CMDTOUT | CSTA_RSPFIN) 455205354Simp#define CSTA_ERROR (CSTA_RSPCRCFAIL | CSTA_CMDTOUT) 456205354Simp#define CSTA_CMDON (1<<8) 457205354Simp#define SDI_RSP0 0x14 458205354Simp#define SDI_RSP1 0x18 459205354Simp#define SDI_RSP2 0x1c 460205354Simp#define SDI_RSP3 0x20 461205354Simp#define SDI_DTIMER 0x24 462205354Simp#define SDI_BSIZE 0x28 463205354Simp#define SDI_DCON 0x2c 464205354Simp#define DCON_PRDTYPE (1<<21) 465205354Simp#define DCON_TARSP (1<<20) /* Transmit after response */ 466205354Simp#define DCON_RACMD (1<<19) /* Receive after command */ 467205354Simp#define DCON_BACMD (1<<18) /* Busy after command */ 468205354Simp#define DCON_BLKMODE (1<<17) /* Stream/Block mode */ 469205354Simp#define DCON_WIDEBUS (1<<16) /* Standard/Wide bus */ 470205354Simp#define DCON_ENDMA (1<<15) /* DMA Enable */ 471205354Simp/* Determine the direction of the data transfer */ 472205354Simp#define DCON_DATA_READY (0<<12) /* No transfer */ 473205354Simp#define DCON_ONLYBUST (1<<12) /* Check if busy */ 474205354Simp#define DCON_DATA_RECEIVE (2<<12) /* Receive data from SD */ 475205354Simp#define DCON_DATA_TRANSMIT (3<<12) /* Send data to SD */ 476205354Simp#define DCON_BLKNUM_MASK (0x7FF) /* Block number */ 477205354Simp#define SDI_DCNT 0x30 478205354Simp#define SDI_DSTA 0x34 479205354Simp#define SDI_FSTA 0x38 480205354Simp#define FSTA_TX_AVAIL (1<<13) 481205354Simp#define FSTA_RX_AVAIL (1<<12) 482205354Simp#define FSTA_TX_FIFO_HALF_FULL (1<<11) 483205354Simp#define FSTA_TX_FIFO_EMPTY (1<<10) 484205354Simp#define FSTA_RX_FIFO_LAST_DATA (1<<9) 485205354Simp#define FSTA_RX_FIFO_FULL (1<<8) 486205354Simp#define FSTA_RX_FIFO_HALF_FULL (1<<7) 487205354Simp#define FSTA_FIFO_COUNT_MSK (0x7F) 488205354Simp 489205354Simp/* Timer */ 490205354Simp#define TIMER_TCFG0 0x00 /* Timer configuration */ 491205354Simp#define TIMER_TCFG1 0x04 492205354Simp#define TCFG1_MUX_SHIFT(n) (4*(n)) 493205354Simp#define TCFG1_MUX_MASK(n) (0x0f << TCFG1_MUX_SHIFT(n)) 494205354Simp#define TCFG1_MUX_DIV2 0 495205354Simp#define TCFG1_MUX_DIV4 1 496205354Simp#define TCFG1_MUX_DIV8 2 497205354Simp#define TCFG1_MUX_DIV16 3 498205354Simp#define TCFG1_MUX_EXT 4 499205354Simp#define TIMER_TCON 0x08 /* control */ 500205354Simp#define TCON_SHIFT(n) (4 * ((n)==0 ? 0 : (n)+1)) 501205354Simp#define TCON_START(n) (1 << TCON_SHIFT(n)) 502205354Simp#define TCON_MANUALUPDATE(n) (1 << (TCON_SHIFT(n) + 1)) 503205354Simp#define TCON_INVERTER(n) (1 << (TCON_SHIFT(n) + 2)) 504205354Simp#define __TCON_AUTORELOAD(n) (1 << (TCON_SHIFT(n) + 3)) /* n=0..3 */ 505205354Simp#define TCON_AUTORELOAD4 (1<<22) /* stupid hardware design */ 506205354Simp#define TCON_AUTORELOAD(n) \ 507205354Simp ((n)==4 ? TCON_AUTORELOAD4 : __TCON_AUTORELOAD(n)) 508205354Simp#define TCON_MASK(n) (0x0f << TCON_SHIFT(n)) 509205354Simp#define TIMER_TCNTB(n) (0x0c+0x0c*(n)) /* count buffer */ 510205354Simp#define TIMER_TCMPB(n) (0x10+0x0c*(n)) /* compare buffer */ 511205354Simp#define __TIMER_TCNTO(n) (0x14+0x0c*(n)) /* count observation */ 512205354Simp#define TIMER_TCNTO4 0x40 513205354Simp#define TIMER_TCNTO(n) ((n)==4 ? TIMER_TCNTO4 : __TIMER_TCNTO(n)) 514205354Simp 515205354Simp#define S3C24X0_TIMER_SIZE 0x44 516205354Simp 517205354Simp/* UART */ 518205354Simp/* diffs to s3c2800 */ 519205354Simp/* SSCOM_UMCON */ 520205354Simp#define UMCON_AFC (1<<4) /* auto flow control */ 521205354Simp/* SSCOM_UMSTAT */ 522205354Simp#define UMSTAT_DCTS (1<<2) /* CTS change */ 523205354Simp/* SSCOM_UMSTAT */ 524205354Simp#define ULCON_IR (1<<6) 525205354Simp#define ULCON_PARITY_SHIFT 3 526205354Simp 527205354Simp#define S3C24X0_UART_SIZE 0x2c 528205354Simp 529205354Simp/* USB device */ 530205354Simp/* XXX */ 531205354Simp 532205354Simp/* Watch dog timer */ 533205354Simp#define WDT_WTCON 0x00 /* WDT mode */ 534205354Simp#define WTCON_PRESCALE_SHIFT 8 535205354Simp#define WTCON_PRESCALE (0xff<<WTCON_PRESCALE_SHIFT) 536205354Simp#define WTCON_ENABLE (1<<5) 537205354Simp#define WTCON_CLKSEL (3<<3) 538205354Simp#define WTCON_CLKSEL_16 (0<<3) 539205354Simp#define WTCON_CLKSEL_32 (1<<3) 540205354Simp#define WTCON_CLKSEL_64 (2<<3) 541205354Simp#define WTCON_CLKSEL_128 (3<<3) 542205354Simp#define WTCON_ENINT (1<<2) 543205354Simp#define WTCON_ENRST (1<<0) 544205354Simp 545205354Simp#define WTCON_WDTSTOP 0 546205354Simp 547205354Simp#define WDT_WTDAT 0x04 /* timer data */ 548205354Simp#define WDT_WTCNT 0x08 /* timer count */ 549205354Simp 550205354Simp#define S3C24X0_WDT_SIZE 0x0c 551205354Simp 552205354Simp/* IIC */ 553205354Simp#define S3C24X0_IIC_SIZE 0x0c 554205354Simp 555205354Simp 556205354Simp/* IIS */ 557205354Simp#define S3C24X0_IIS_SIZE 0x14 558205354Simp 559205354Simp/* GPIO */ 560205354Simp#define GPIO_PACON 0x00 /* port A configuration */ 561205354Simp#define GPIO_PADAT 0x04 /* port A data */ 562205354Simp 563205354Simp#define GPIO_PBCON 0x10 564205354Simp/* These are only used on port B-H on 2410 & B-H,J on 2440 */ 565205354Simp#define PCON_INPUT 0 /* Input port */ 566205354Simp#define PCON_OUTPUT 1 /* Output port */ 567205354Simp#define PCON_ALTFUN 2 /* Alternate function */ 568205354Simp#define PCON_ALTFUN2 3 /* Alternate function */ 569205354Simp#define GPIO_PBDAT 0x14 570205354Simp/* This is different between 2440 and 2442 (pull up vs pull down): */ 571205354Simp#define GPIO_PBUP 0x18 /* 2410 & 2440 */ 572205354Simp#define GPIO_PBDOWN 0x18 /* 2442 */ 573205354Simp 574205354Simp#define GPIO_PCCON 0x20 575205354Simp#define GPIO_PCDAT 0x24 576205354Simp#define GPIO_PCUP 0x28 /* 2410 & 2440 */ 577205354Simp#define GPIO_PCDOWN 0x28 /* 2442 */ 578205354Simp 579205354Simp#define GPIO_PDCON 0x30 580205354Simp#define GPIO_PDDAT 0x34 581205354Simp#define GPIO_PDUP 0x38 /* 2410 & 2440 */ 582205354Simp#define GPIO_PDDOWN 0x38 /* 2442 */ 583205354Simp 584205354Simp#define GPIO_PECON 0x40 585205354Simp#define PECON_INPUT(x) (0<<((x)*2)) /* Pin is used for input */ 586205354Simp#define PECON_OUTPUT(x) (1<<((x)*2)) /* Pin is used for output */ 587205354Simp#define PECON_FUNC_A(x) (2<<((x)*2)) /* Pin is used for function 'A' */ 588205354Simp#define PECON_FUNC_B(x) (3<<((x)*2)) /* Pin is used for function 'B' */ 589205354Simp#define PECON_MASK(x) (3<<((x)*2)) 590205354Simp#define GPIO_PEDAT 0x44 591205354Simp#define GPIO_PEUP 0x48 /* 2410 & 2440 */ 592205354Simp#define GPIO_PEDOWN 0x48 /* 2442 */ 593205354Simp#define PEUD_ENABLE(x) (~(1<<(x))) /* Enable the pull Up/Down */ 594205354Simp#define PEUD_DISABLE(x) (1<<(x)) /* Disable the pull Up/Down */ 595205354Simp 596205354Simp#define GPIO_PFCON 0x50 597205354Simp#define GPIO_PFDAT 0x54 598205354Simp#define GPIO_PFUP 0x58 /* 2410 & 2440 */ 599205354Simp#define GPIO_PFDOWN 0x58 /* 2442 */ 600205354Simp 601205354Simp#define GPIO_PGCON 0x60 602205354Simp#define GPIO_PGDAT 0x64 603205354Simp#define GPIO_PGUP 0x68 /* 2410 & 2440 */ 604205354Simp#define GPIO_PGDOWN 0x68 /* 2442 */ 605205354Simp 606205354Simp#define GPIO_PHCON 0x70 607205354Simp#define GPIO_PHDAT 0x74 608205354Simp#define GPIO_PHUP 0x78 /* 2410 & 2440 */ 609205354Simp#define GPIO_PHDOWN 0x78 /* 2442 */ 610205354Simp 611205354Simp#define GPIO_MISCCR 0x80 /* miscellaneous control */ 612205354Simp#define GPIO_DCLKCON 0x84 /* DCLK 0/1 */ 613205354Simp#define GPIO_EXTINT(n) (0x88+4*(n)) /* external int control 0/1/2 */ 614205354Simp#define GPIO_EINTFLT(n) (0x94+4*(n)) /* external int filter control 0..3 */ 615205354Simp#define EXTINTR_LOW 0x00 616205354Simp#define EXTINTR_HIGH 0x01 617205354Simp#define EXTINTR_FALLING 0x02 618205354Simp#define EXTINTR_RISING 0x04 619205354Simp#define EXTINTR_BOTH 0x06 620205354Simp#define GPIO_EINTMASK 0xa4 621205354Simp#define GPIO_EINTPEND 0xa8 622205354Simp#define GPIO_GSTATUS0 0xac /* external pin status */ 623205354Simp#define GPIO_GSTATUS1 0xb0 /* Chip ID */ 624205354Simp#define CHIPID_S3C2410A 0x32410002 625205354Simp#define CHIPID_S3C2440A 0x32440001 626205354Simp#define CHIPID_S3C2442B 0x32440AAB 627205354Simp#define GPIO_GSTATUS2 0xb4 /* Reset status */ 628205354Simp#define GPIO_GSTATUS3 0xb8 629205354Simp#define GPIO_GSTATUS4 0xbc 630205354Simp 631205354Simp#define GPIO_SET_FUNC(v,port,func) \ 632205354Simp (((v) & ~(3<<(2*(port))))|((func)<<(2*(port)))) 633205354Simp 634205354Simp/* ADC */ 635205354Simp#define ADC_ADCCON 0x00 636205354Simp#define ADCCON_ENABLE_START (1<<0) 637205354Simp#define ADCCON_READ_START (1<<1) 638205354Simp#define ADCCON_STDBM (1<<2) 639205354Simp#define ADCCON_SEL_MUX_SHIFT 3 640205354Simp#define ADCCON_SEL_MUX_MASK (0x7<<ADCCON_SEL_MUX_SHIFT) 641205354Simp#define ADCCON_PRSCVL_SHIFT 6 642205354Simp#define ADCCON_PRSCVL_MASK (0xff<<ADCCON_PRSCVL_SHIFT) 643205354Simp#define ADCCON_PRSCEN (1<<14) 644205354Simp#define ADCCON_ECFLG (1<<15) 645205354Simp 646205354Simp#define ADC_ADCTSC 0x04 647205354Simp#define ADCTSC_XY_PST 0x03 648205354Simp#define ADCTSC_AUTO_PST (1<<2) 649205354Simp#define ADCTSC_PULL_UP (1<<3) 650205354Simp#define ADCTSC_XP_SEN (1<<4) 651205354Simp#define ADCTSC_XM_SEN (1<<5) 652205354Simp#define ADCTSC_YP_SEN (1<<6) 653205354Simp#define ADCTSC_YM_SEN (1<<7) 654205354Simp#define ADC_ADCDLY 0x08 655205354Simp#define ADC_ADCDAT0 0x0c 656205354Simp#define ADC_ADCDAT1 0x10 657205354Simp 658205354Simp#define ADCDAT_DATAMASK 0x3ff 659205354Simp 660210397Sandrew/* RTC */ 661210397Sandrew#define RTC_RTCCON 0x40 662210397Sandrew#define RTCCON_RTCEN (1<<0) 663210397Sandrew#define RTCCON_CLKSEL (1<<1) 664210397Sandrew#define RTCCON_CNTSEL (1<<2) 665210397Sandrew#define RTCCON_CLKRST (1<<3) 666210397Sandrew#define RTC_TICNT0 0x44 667210397Sandrew/* TICNT1 on 2440 */ 668210397Sandrew#define RTC_RTCALM 0x50 669210397Sandrew#define RTC_ALMSEC 0x54 670210397Sandrew#define RTC_ALMMIN 0x58 671210397Sandrew#define RTC_ALMHOUR 0x5C 672210397Sandrew#define RTC_ALMDATE 0x60 673210397Sandrew#define RTC_ALMMON 0x64 674210397Sandrew#define RTC_ALMYEAR 0x68 675210397Sandrew/* RTCRST on 2410 */ 676210397Sandrew#define RTC_BCDSEC 0x70 677210397Sandrew#define RTC_BCDMIN 0x74 678210397Sandrew#define RTC_BCDHOUR 0x78 679210397Sandrew#define RTC_BCDDATE 0x7C 680210397Sandrew#define RTC_BCDDAY 0x80 681210397Sandrew#define RTC_BCDMON 0x84 682210397Sandrew#define RTC_BCDYEAR 0x88 683205354Simp 684210397Sandrew 685205354Simp/* SPI */ 686205354Simp#define S3C24X0_SPI_SIZE 0x20 687205354Simp 688205354Simp#define SPI_SPCON 0x00 689205354Simp#define SPCON_TAGD (1<<0) /* Tx auto garbage */ 690205354Simp#define SPCON_CPHA (1<<1) 691205354Simp#define SPCON_CPOL (1<<2) 692205354Simp#define SPCON_IDLELOW_RISING (0|0) 693205354Simp#define SPCON_IDLELOW_FALLING (0|SPCON_CPHA) 694236990Simp#define SPCON_IDLEHIGH_FALLING (SPCON_CPOL|0) 695205354Simp#define SPCON_IDLEHIGH_RISING (SPCON_CPOL|SPCON_CPHA) 696205354Simp#define SPCON_MSTR (1<<3) 697205354Simp#define SPCON_ENSCK (1<<4) 698205354Simp#define SPCON_SMOD_SHIFT 5 699205354Simp#define SPCON_SMOD_MASK (0x03<<SPCON_SMOD_SHIFT) 700205354Simp#define SPCON_SMOD_POLL (0x00<<SPCON_SMOD_SHIFT) 701205354Simp#define SPCON_SMOD_INT (0x01<<SPCON_SMOD_SHIFT) 702205354Simp#define SPCON_SMOD_DMA (0x02<<SPCON_SMOD_SHIFT) 703205354Simp 704205354Simp#define SPI_SPSTA 0x04 /* status register */ 705205354Simp#define SPSTA_REDY (1<<0) /* ready */ 706205354Simp#define SPSTA_MULF (1<<1) /* multi master error */ 707205354Simp#define SPSTA_DCOL (1<<2) /* Data collision error */ 708205354Simp 709205354Simp#define SPI_SPPIN 0x08 710205354Simp#define SPPIN_KEEP (1<<0) 711205354Simp#define SPPIN_ENMUL (1<<2) /* multi master error detect */ 712205354Simp 713205354Simp#define SPI_SPPRE 0x0c /* prescaler */ 714205354Simp#define SPI_SPTDAT 0x10 /* tx data */ 715205354Simp#define SPI_SPRDAT 0x14 /* rx data */ 716205354Simp 717205354Simp 718205354Simp#endif /* _ARM_S3C2XX0_S3C24X0REG_H_ */ 719