1205354Simp/* $NetBSD: s3c2410reg.h,v 1.6 2004/02/12 03:52:46 bsh Exp $ */ 2205354Simp 3205354Simp/*- 4205354Simp * Copyright (c) 2003, 2004 Genetec corporation. All rights reserved. 5205354Simp * Written by Hiroyuki Bessho for Genetec corporation. 6205354Simp * 7205354Simp * Redistribution and use in source and binary forms, with or without 8205354Simp * modification, are permitted provided that the following conditions 9205354Simp * are met: 10205354Simp * 1. Redistributions of source code must retain the above copyright 11205354Simp * notice, this list of conditions and the following disclaimer. 12205354Simp * 2. Redistributions in binary form must reproduce the above copyright 13205354Simp * notice, this list of conditions and the following disclaimer in the 14205354Simp * documentation and/or other materials provided with the distribution. 15205354Simp * 3. The name of Genetec corporation may not be used to endorse 16205354Simp * or promote products derived from this software without specific prior 17205354Simp * written permission. 18205354Simp * 19205354Simp * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 20205354Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21205354Simp * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22205354Simp * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 23205354Simp * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24205354Simp * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25205354Simp * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26205354Simp * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27205354Simp * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28205354Simp * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29205354Simp * POSSIBILITY OF SUCH DAMAGE. 30205354Simp * 31205354Simp * $FreeBSD: releng/10.3/sys/arm/samsung/s3c2xx0/s3c2410reg.h 272103 2014-09-25 11:38:26Z gavin $ 32205354Simp */ 33205354Simp 34205354Simp 35205354Simp/* 36205354Simp * Samsung S3C2410X processor is ARM920T based integrated CPU 37205354Simp * 38205354Simp * Reference: 39236990Simp * S3C2410X User's Manual 40205354Simp */ 41205354Simp#ifndef _ARM_S3C2XX0_S3C2410REG_H_ 42205354Simp#define _ARM_S3C2XX0_S3C2410REG_H_ 43205354Simp 44205354Simp/* common definitions for S3C2410 and S3C2440 */ 45272103Sgavin#include <arm/samsung/s3c2xx0/s3c24x0reg.h> 46205354Simp 47205354Simp/* 48205354Simp * Memory Map 49205354Simp */ 50205354Simp#define S3C2410_BANK_SIZE 0x08000000 51205354Simp#define S3C2410_BANK_START(n) (S3C2410_BANK_SIZE*(n)) 52205354Simp#define S3C2410_SDRAM_START S3C2410_BANK_START(6) 53205354Simp 54205354Simp 55205354Simp/* interrupt control */ 56205354Simp#define S3C2410_SUBIRQ_MAX (S3C24X0_SUBIRQ_MIN+10) 57205354Simp 58205354Simp/* Clock control */ 59205354Simp/* CLKMAN_CLKCON */ 60205354Simp#define S3C2410_CLKCON_SM (1<<0) /* 1=transition to SPECIAL mode */ 61205354Simp/* CLKMAN_CLKDIVN */ 62205354Simp#define S3C2410_CLKDIVN_HDIVN (1<<1) /* hclk=fclk/2 */ 63205354Simp 64205354Simp/* NAND Flash controller */ 65205354Simp#define S3C2410_NANDFC_SIZE 0x18 66205354Simp/* NANDFC_NFCONF */ 67205354Simp#define S3C2410_NFCONF_ENABLE (1<<15) /* NAND controller enabled */ 68205354Simp#define S3C2410_NFCONF_ECC (1<<12) /* Initialize ECC decoder/encoder */ 69205354Simp#define S3C2410_NFCONF_FCE (1<<11) /* Flash chip enabled */ 70205354Simp#define S3C2410_NFCONF_TACLS (7<<8) /* CLE and ALE duration */ 71205354Simp#define S3C2410_NFCONF_TWRPH0 (7<<4) /* TWRPH0 duration */ 72205354Simp#define S3C2410_NFCONF_TWRPH1 (7<<0) /* TWRPH1 duration */ 73205354Simp#define S3C2410_NANDFC_NFCMD 0x04 /* command */ 74205354Simp#define S3C2410_NANDFC_NFADDR 0x08 /* address */ 75205354Simp#define S3C2410_NANDFC_NFDATA 0x0c /* data */ 76205354Simp#define S3C2410_NANDFC_NFSTAT 0x10 /* operation status */ 77205354Simp#define S3C2410_NANDFC_NFECC 0x14 /* ecc */ 78205354Simp 79205354Simp/* MMC/SD */ 80205354Simp/* SDI_CON */ 81205354Simp#define S3C2410_CON_FIFO_RESET (1<<1) 82205354Simp 83205354Simp/* GPIO */ 84205354Simp#define S3C2410_GPIO_SIZE 0xb4 85205354Simp 86205354Simp/* SD interface */ 87205354Simp#define S3C2410_SDI_SIZE 0x44 88205354Simp#define DCON_STOP (1<<14) /* Force the transfer to stop */ 89205354Simp#define S3C2410_SDI_DAT 0x3c 90205354Simp#define S3C2410_SDI_IMSK 0x40 /* Interrupt mask */ 91205354Simp#define S3C2410_SDI_IMASK_ALL 0x3ffdf 92205354Simp 93205354Simp/* ADC */ 94205354Simp#define S3C2410_ADC_SIZE 0x14 95205354Simp 96205354Simp#endif /* _ARM_S3C2XX0_S3C2410REG_H_ */ 97