mvreg.h revision 251371
1201360Srdivacky/*- 2201360Srdivacky * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3201360Srdivacky * All rights reserved. 4201360Srdivacky * 5201360Srdivacky * Developed by Semihalf. 6201360Srdivacky * 7201360Srdivacky * Redistribution and use in source and binary forms, with or without 8201360Srdivacky * modification, are permitted provided that the following conditions 9201360Srdivacky * are met: 10201360Srdivacky * 1. Redistributions of source code must retain the above copyright 11201360Srdivacky * notice, this list of conditions and the following disclaimer. 12201360Srdivacky * 2. Redistributions in binary form must reproduce the above copyright 13201360Srdivacky * notice, this list of conditions and the following disclaimer in the 14201360Srdivacky * documentation and/or other materials provided with the distribution. 15201360Srdivacky * 3. Neither the name of MARVELL nor the names of contributors 16201360Srdivacky * may be used to endorse or promote products derived from this software 17201360Srdivacky * without specific prior written permission. 18201360Srdivacky * 19201360Srdivacky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20201360Srdivacky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21218893Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22201360Srdivacky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23201360Srdivacky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24201360Srdivacky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25201360Srdivacky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26201360Srdivacky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27201360Srdivacky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28201360Srdivacky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29201360Srdivacky * SUCH DAMAGE. 30201360Srdivacky * 31201360Srdivacky * $FreeBSD: head/sys/arm/mv/mvreg.h 251371 2013-06-04 09:33:03Z gber $ 32201360Srdivacky */ 33201360Srdivacky 34201360Srdivacky#ifndef _MVREG_H_ 35201360Srdivacky#define _MVREG_H_ 36201360Srdivacky 37201360Srdivacky#if defined(SOC_MV_DISCOVERY) 38201360Srdivacky#define IRQ_CAUSE_ERROR 0x0 39201360Srdivacky#define IRQ_CAUSE 0x4 40201360Srdivacky#define IRQ_CAUSE_HI 0x8 41201360Srdivacky#define IRQ_MASK_ERROR 0xC 42201360Srdivacky#define IRQ_MASK 0x10 43201360Srdivacky#define IRQ_MASK_HI 0x14 44201360Srdivacky#define IRQ_CAUSE_SELECT 0x18 45201360Srdivacky#define FIQ_MASK_ERROR 0x1C 46201360Srdivacky#define FIQ_MASK 0x20 47201360Srdivacky#define FIQ_MASK_HI 0x24 48201360Srdivacky#define FIQ_CAUSE_SELECT 0x28 49201360Srdivacky#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C 50201360Srdivacky#define ENDPOINT_IRQ_MASK(n) 0x30 51201360Srdivacky#define ENDPOINT_IRQ_MASK_HI(n) 0x34 52201360Srdivacky#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 53201360Srdivacky#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY) 54201360Srdivacky#define IRQ_CAUSE 0x0 55201360Srdivacky#define IRQ_MASK 0x4 56201360Srdivacky#define FIQ_MASK 0x8 57201360Srdivacky#define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4) 58201360Srdivacky#define IRQ_CAUSE_HI (-1) /* Fake defines for unified */ 59201360Srdivacky#define IRQ_MASK_HI (-1) /* interrupt controller code */ 60201360Srdivacky#define FIQ_MASK_HI (-1) 61201360Srdivacky#define ENDPOINT_IRQ_MASK_HI(n) (-1) 62201360Srdivacky#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 63201360Srdivacky#define IRQ_CAUSE_ERROR (-1) 64201360Srdivacky#define IRQ_MASK_ERROR (-1) 65201360Srdivacky#elif defined (SOC_MV_ARMADAXP) 66201360Srdivacky#define IRQ_CAUSE 0x18 67201360Srdivacky#define IRQ_MASK 0x30 68201360Srdivacky#else /* !SOC_MV_DISCOVERY && !SOC_MV_LOKIPLUS */ 69201360Srdivacky#define IRQ_CAUSE 0x0 70201360Srdivacky#define IRQ_MASK 0x4 71201360Srdivacky#define FIQ_MASK 0x8 72201360Srdivacky#define ENDPOINT_IRQ_MASK(n) 0xC 73201360Srdivacky#define IRQ_CAUSE_HI 0x10 74201360Srdivacky#define IRQ_MASK_HI 0x14 75201360Srdivacky#define FIQ_MASK_HI 0x18 76201360Srdivacky#define ENDPOINT_IRQ_MASK_HI(n) 0x1C 77201360Srdivacky#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 78201360Srdivacky#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 79201360Srdivacky#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 80201360Srdivacky#endif 81201360Srdivacky 82201360Srdivacky#if defined(SOC_MV_FREY) 83201360Srdivacky#define BRIDGE_IRQ_CAUSE 0x118 84201360Srdivacky#define IRQ_TIMER0 0x00000002 85201360Srdivacky#define IRQ_TIMER1 0x00000004 86201360Srdivacky#define IRQ_TIMER_WD 0x00000008 87201360Srdivacky 88201360Srdivacky#define BRIDGE_IRQ_MASK 0x11c 89201360Srdivacky#define IRQ_TIMER0_MASK 0x00000002 90201360Srdivacky#define IRQ_TIMER1_MASK 0x00000004 91201360Srdivacky#define IRQ_TIMER_WD_MASK 0x00000008 92201360Srdivacky#elif defined(SOC_MV_ARMADAXP) 93201360Srdivacky#define BRIDGE_IRQ_CAUSE 0x68 94201360Srdivacky#define IRQ_TIMER0 0x00000001 95201360Srdivacky#define IRQ_TIMER1 0x00000002 96201360Srdivacky#define IRQ_TIMER_WD 0x00000004 97201360Srdivacky#else 98201360Srdivacky#define BRIDGE_IRQ_CAUSE 0x10 99201360Srdivacky#define IRQ_CPU_SELF 0x00000001 100201360Srdivacky#define IRQ_TIMER0 0x00000002 101201360Srdivacky#define IRQ_TIMER1 0x00000004 102201360Srdivacky#define IRQ_TIMER_WD 0x00000008 103201360Srdivacky 104201360Srdivacky#define BRIDGE_IRQ_MASK 0x14 105201360Srdivacky#define IRQ_CPU_MASK 0x00000001 106201360Srdivacky#define IRQ_TIMER0_MASK 0x00000002 107201360Srdivacky#define IRQ_TIMER1_MASK 0x00000004 108201360Srdivacky#define IRQ_TIMER_WD_MASK 0x00000008 109201360Srdivacky#endif 110201360Srdivacky 111201360Srdivacky#if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY) 112201360Srdivacky#define IRQ_CPU_SELF_CLR IRQ_CPU_SELF 113201360Srdivacky#define IRQ_TIMER0_CLR IRQ_TIMER0 114201360Srdivacky#define IRQ_TIMER1_CLR IRQ_TIMER1 115201360Srdivacky#define IRQ_TIMER_WD_CLR IRQ_TIMER_WD 116201360Srdivacky#else 117201360Srdivacky#define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) 118201360Srdivacky#define IRQ_TIMER0_CLR (~IRQ_TIMER0) 119201360Srdivacky#define IRQ_TIMER1_CLR (~IRQ_TIMER1) 120201360Srdivacky#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 121201360Srdivacky#endif 122201360Srdivacky 123201360Srdivacky/* 124201360Srdivacky * System reset 125201360Srdivacky */ 126201360Srdivacky#if defined(SOC_MV_ARMADAXP) 127201360Srdivacky#define RSTOUTn_MASK 0x60 128201360Srdivacky#define SYSTEM_SOFT_RESET 0x64 129201360Srdivacky#define WD_RSTOUTn_MASK 0x4 130201360Srdivacky#define WD_GLOBAL_MASK 0x00000100 131201360Srdivacky#define WD_CPU0_MASK 0x00000001 132201360Srdivacky#define SOFT_RST_OUT_EN 0x00000001 133201360Srdivacky#define SYS_SOFT_RST 0x00000001 134201360Srdivacky#else 135201360Srdivacky#define RSTOUTn_MASK 0x8 136201360Srdivacky#define WD_RST_OUT_EN 0x00000002 137201360Srdivacky#define SOFT_RST_OUT_EN 0x00000004 138201360Srdivacky#define SYSTEM_SOFT_RESET 0xc 139201360Srdivacky#define SYS_SOFT_RST 0x00000001 140201360Srdivacky#endif 141201360Srdivacky 142201360Srdivacky/* 143201360Srdivacky * Power Control 144201360Srdivacky */ 145201360Srdivacky#define CPU_PM_CTRL 0x1C 146201360Srdivacky#define CPU_PM_CTRL_NONE 0 147201360Srdivacky#define CPU_PM_CTRL_ALL ~0x0 148201360Srdivacky 149201360Srdivacky#if defined(SOC_MV_KIRKWOOD) 150201360Srdivacky#define CPU_PM_CTRL_GE0 (1 << 0) 151201360Srdivacky#define CPU_PM_CTRL_PEX0_PHY (1 << 1) 152201360Srdivacky#define CPU_PM_CTRL_PEX0 (1 << 2) 153201360Srdivacky#define CPU_PM_CTRL_USB0 (1 << 3) 154201360Srdivacky#define CPU_PM_CTRL_SDIO (1 << 4) 155201360Srdivacky#define CPU_PM_CTRL_TSU (1 << 5) 156201360Srdivacky#define CPU_PM_CTRL_DUNIT (1 << 6) 157201360Srdivacky#define CPU_PM_CTRL_RUNIT (1 << 7) 158201360Srdivacky#define CPU_PM_CTRL_XOR0 (1 << 8) 159201360Srdivacky#define CPU_PM_CTRL_AUDIO (1 << 9) 160201360Srdivacky#define CPU_PM_CTRL_SATA0 (1 << 14) 161201360Srdivacky#define CPU_PM_CTRL_SATA1 (1 << 15) 162201360Srdivacky#define CPU_PM_CTRL_XOR1 (1 << 16) 163201360Srdivacky#define CPU_PM_CTRL_CRYPTO (1 << 17) 164201360Srdivacky#define CPU_PM_CTRL_GE1 (1 << 19) 165201360Srdivacky#define CPU_PM_CTRL_TDM (1 << 20) 166201360Srdivacky#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1) 167201360Srdivacky#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0) 168201360Srdivacky#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 169201360Srdivacky#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 170201360Srdivacky (1 - (u))) 171201360Srdivacky#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 172201360Srdivacky#elif defined(SOC_MV_DISCOVERY) 173201360Srdivacky#define CPU_PM_CTRL_GE0 (1 << 1) 174201360Srdivacky#define CPU_PM_CTRL_GE1 (1 << 2) 175201360Srdivacky#define CPU_PM_CTRL_PEX00 (1 << 5) 176201360Srdivacky#define CPU_PM_CTRL_PEX01 (1 << 6) 177201360Srdivacky#define CPU_PM_CTRL_PEX02 (1 << 7) 178201360Srdivacky#define CPU_PM_CTRL_PEX03 (1 << 8) 179201360Srdivacky#define CPU_PM_CTRL_PEX10 (1 << 9) 180201360Srdivacky#define CPU_PM_CTRL_PEX11 (1 << 10) 181201360Srdivacky#define CPU_PM_CTRL_PEX12 (1 << 11) 182201360Srdivacky#define CPU_PM_CTRL_PEX13 (1 << 12) 183201360Srdivacky#define CPU_PM_CTRL_SATA0_PHY (1 << 13) 184201360Srdivacky#define CPU_PM_CTRL_SATA0 (1 << 14) 185201360Srdivacky#define CPU_PM_CTRL_SATA1_PHY (1 << 15) 186201360Srdivacky#define CPU_PM_CTRL_SATA1 (1 << 16) 187201360Srdivacky#define CPU_PM_CTRL_USB0 (1 << 17) 188201360Srdivacky#define CPU_PM_CTRL_USB1 (1 << 18) 189201360Srdivacky#define CPU_PM_CTRL_USB2 (1 << 19) 190201360Srdivacky#define CPU_PM_CTRL_IDMA (1 << 20) 191201360Srdivacky#define CPU_PM_CTRL_XOR (1 << 21) 192201360Srdivacky#define CPU_PM_CTRL_CRYPTO (1 << 22) 193201360Srdivacky#define CPU_PM_CTRL_DEVICE (1 << 23) 194201360Srdivacky#define CPU_PM_CTRL_USB(u) (1 << (17 + (u))) 195201360Srdivacky#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) 196201360Srdivacky#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ 197201360Srdivacky (1 - (u))) 198#else 199#define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) 200#define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) 201#define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) 202#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 203#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 204#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 205#endif 206 207/* 208 * Timers 209 */ 210#define CPU_TIMERS_BASE 0x300 211#define CPU_TIMER_CONTROL 0x0 212#define CPU_TIMER0_EN 0x00000001 213#define CPU_TIMER0_AUTO 0x00000002 214#define CPU_TIMER1_EN 0x00000004 215#define CPU_TIMER1_AUTO 0x00000008 216#define CPU_TIMER_WD_EN 0x00000010 217#define CPU_TIMER_WD_AUTO 0x00000020 218/* 25MHz mode is Armada XP - specific */ 219#define CPU_TIMER_WD_25MHZ_EN 0x00000400 220#define CPU_TIMER0_25MHZ_EN 0x00000800 221#define CPU_TIMER1_25MHZ_EN 0x00001000 222#define CPU_TIMER0_REL 0x10 223#define CPU_TIMER0 0x14 224 225/* 226 * SATA 227 */ 228#define SATA_CHAN_NUM 2 229 230#define EDMA_REGISTERS_OFFSET 0x2000 231#define EDMA_REGISTERS_SIZE 0x2000 232#define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ 233 ((ch) * EDMA_REGISTERS_SIZE)) 234 235/* SATAHC registers */ 236#define SATA_CR 0x000 /* Configuration Reg. */ 237#define SATA_CR_NODMABS (1 << 8) 238#define SATA_CR_NOEDMABS (1 << 9) 239#define SATA_CR_NOPRDPBS (1 << 10) 240#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 241 242/* Interrupt Coalescing Threshold Reg. */ 243#define SATA_ICTR 0x00C 244#define SATA_ICTR_MAX ((1 << 8) - 1) 245 246/* Interrupt Time Threshold Reg. */ 247#define SATA_ITTR 0x010 248#define SATA_ITTR_MAX ((1 << 24) - 1) 249 250#define SATA_ICR 0x014 /* Interrupt Cause Reg. */ 251#define SATA_ICR_DMADONE(ch) (1 << (ch)) 252#define SATA_ICR_COAL (1 << 4) 253#define SATA_ICR_DEV(ch) (1 << (8 + ch)) 254 255#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 256#define SATA_MICR_ERR(ch) (1 << (2 * ch)) 257#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 258#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) 259#define SATA_MICR_COAL (1 << 8) 260 261#define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ 262 263/* Shadow registers */ 264#define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) 265#define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) 266 267/* SATA registers */ 268#define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) 269#define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) 270#define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) 271#define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) 272 273/* EDMA registers */ 274#define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) 275#define SATA_EDMA_CFG_QL128 (1 << 19) 276#define SATA_EDMA_CFG_HQCACHE (1 << 22) 277 278#define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) 279 280#define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) 281#define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) 282#define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) 283#define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) 284#define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) 285#define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) 286#define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) 287 288#define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) 289#define SATA_EDMA_CMD_ENABLE (1 << 0) 290#define SATA_EDMA_CMD_DISABLE (1 << 1) 291#define SATA_EDMA_CMD_RESET (1 << 2) 292 293#define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) 294#define SATA_EDMA_STATUS_IDLE (1 << 7) 295 296/* Offset to extract input slot from REQIPR register */ 297#define SATA_EDMA_REQIS_OFS 5 298 299/* Offset to extract input slot from RESOPR register */ 300#define SATA_EDMA_RESOS_OFS 3 301 302/* 303 * GPIO 304 */ 305#define GPIO_DATA_OUT 0x00 306#define GPIO_DATA_OUT_EN_CTRL 0x04 307#define GPIO_BLINK_EN 0x08 308#define GPIO_DATA_IN_POLAR 0x0c 309#define GPIO_DATA_IN 0x10 310#define GPIO_INT_CAUSE 0x14 311#define GPIO_INT_EDGE_MASK 0x18 312#define GPIO_INT_LEV_MASK 0x1c 313 314#define GPIO_HI_DATA_OUT 0x40 315#define GPIO_HI_DATA_OUT_EN_CTRL 0x44 316#define GPIO_HI_BLINK_EN 0x48 317#define GPIO_HI_DATA_IN_POLAR 0x4c 318#define GPIO_HI_DATA_IN 0x50 319#define GPIO_HI_INT_CAUSE 0x54 320#define GPIO_HI_INT_EDGE_MASK 0x58 321#define GPIO_HI_INT_LEV_MASK 0x5c 322 323#define GPIO(n) (1 << (n)) 324#define MV_GPIO_MAX_NPINS 64 325 326#define MV_GPIO_IN_NONE 0x0 327#define MV_GPIO_IN_POL_LOW (1 << 16) 328#define MV_GPIO_IN_IRQ_EDGE (2 << 16) 329#define MV_GPIO_IN_IRQ_LEVEL (4 << 16) 330#define MV_GPIO_OUT_NONE 0x0 331#define MV_GPIO_OUT_BLINK 0x1 332#define MV_GPIO_OUT_OPEN_DRAIN 0x2 333#define MV_GPIO_OUT_OPEN_SRC 0x4 334 335#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 336#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 337#define IRQ2GPIO(irq) ((irq) - NIRQ) 338 339#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS) 340#define SAMPLE_AT_RESET 0x10 341#elif defined(SOC_MV_KIRKWOOD) 342#define SAMPLE_AT_RESET 0x30 343#elif defined(SOC_MV_FREY) 344#define SAMPLE_AT_RESET 0x100 345#endif 346#if defined(SOC_MV_DISCOVERY) 347#define SAMPLE_AT_RESET_LO 0x30 348#define SAMPLE_AT_RESET_HI 0x34 349#elif defined(SOC_MV_DOVE) 350#define SAMPLE_AT_RESET_LO 0x14 351#define SAMPLE_AT_RESET_HI 0x18 352#elif defined(SOC_MV_ARMADAXP) 353#define SAMPLE_AT_RESET_LO 0x30 354#define SAMPLE_AT_RESET_HI 0x34 355#endif 356 357/* 358 * Clocks 359 */ 360#if defined(SOC_MV_ORION) 361#define TCLK_MASK 0x00000300 362#define TCLK_SHIFT 0x08 363#elif defined(SOC_MV_DISCOVERY) 364#define TCLK_MASK 0x00000180 365#define TCLK_SHIFT 0x07 366#elif defined(SOC_MV_LOKIPLUS) 367#define TCLK_MASK 0x0000F000 368#define TCLK_SHIFT 0x0C 369#endif 370 371#define TCLK_100MHZ 100000000 372#define TCLK_125MHZ 125000000 373#define TCLK_133MHZ 133333333 374#define TCLK_150MHZ 150000000 375#define TCLK_166MHZ 166666667 376#define TCLK_200MHZ 200000000 377#define TCLK_250MHZ 250000000 378#define TCLK_300MHZ 300000000 379#define TCLK_667MHZ 667000000 380 381/* 382 * CPU Cache Configuration 383 */ 384 385#define CPU_CONFIG 0x00000000 386#define CPU_CONFIG_IC_PREF 0x00010000 387#define CPU_CONFIG_DC_PREF 0x00020000 388#define CPU_CONTROL 0x00000004 389#define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */ 390#define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */ 391#define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */ 392#define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */ 393 394/* 395 * PCI Express port control (CPU Control registers) 396 */ 397#define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n))) 398 399/* 400 * Vendor ID 401 */ 402#define PCI_VENDORID_MRVL 0x11AB 403#define PCI_VENDORID_MRVL2 0x1B4B 404 405/* 406 * Chip ID 407 */ 408#define MV_DEV_88F5181 0x5181 409#define MV_DEV_88F5182 0x5182 410#define MV_DEV_88F5281 0x5281 411#define MV_DEV_88F6281 0x6281 412#define MV_DEV_88F6282 0x6282 413#define MV_DEV_88F6781 0x6781 414#define MV_DEV_MV78100_Z0 0x6381 415#define MV_DEV_MV78100 0x7810 416#define MV_DEV_MV78130 0x7813 417#define MV_DEV_MV78160 0x7816 418#define MV_DEV_MV78230 0x7823 419#define MV_DEV_MV78260 0x7826 420#define MV_DEV_MV78460 0x7846 421#define MV_DEV_88RC8180 0x8180 422#define MV_DEV_88RC9480 0x9480 423#define MV_DEV_88RC9580 0x9580 424 425#define MV_DEV_FAMILY_MASK 0xff00 426#define MV_DEV_DISCOVERY 0x7800 427 428/* 429 * Doorbell register control 430 */ 431#define MV_DRBL_PCIE_TO_CPU 0 432#define MV_DRBL_CPU_TO_PCIE 1 433 434#if defined(SOC_MV_FREY) 435#define MV_DRBL_CAUSE(d,u) (0x60 + 0x20 * (d) + 0x8 * (u)) 436#define MV_DRBL_MASK(d,u) (0x60 + 0x20 * (d) + 0x8 * (u) + 0x4) 437#define MV_DRBL_MSG(m,d,u) (0x8 * (u) + 0x20 * (d) + 0x4 * (m)) 438#else 439#define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) 440#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) 441#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) 442#endif 443#endif /* _MVREG_H_ */ 444